diff options
Diffstat (limited to 'arch/mips/kernel/traps.c')
-rw-r--r-- | arch/mips/kernel/traps.c | 26 |
1 files changed, 13 insertions, 13 deletions
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index ac762d8d802d..b3e408b54c24 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c | |||
@@ -627,7 +627,7 @@ asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31) | |||
627 | lose_fpu(1); | 627 | lose_fpu(1); |
628 | 628 | ||
629 | /* Run the emulator */ | 629 | /* Run the emulator */ |
630 | sig = fpu_emulator_cop1Handler (regs, ¤t->thread.fpu, 1); | 630 | sig = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 1); |
631 | 631 | ||
632 | /* | 632 | /* |
633 | * We can't allow the emulated instruction to leave any of | 633 | * We can't allow the emulated instruction to leave any of |
@@ -1165,11 +1165,11 @@ static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs) | |||
1165 | 1165 | ||
1166 | if (cpu_has_veic) { | 1166 | if (cpu_has_veic) { |
1167 | if (board_bind_eic_interrupt) | 1167 | if (board_bind_eic_interrupt) |
1168 | board_bind_eic_interrupt (n, srs); | 1168 | board_bind_eic_interrupt(n, srs); |
1169 | } else if (cpu_has_vint) { | 1169 | } else if (cpu_has_vint) { |
1170 | /* SRSMap is only defined if shadow sets are implemented */ | 1170 | /* SRSMap is only defined if shadow sets are implemented */ |
1171 | if (mips_srs_max() > 1) | 1171 | if (mips_srs_max() > 1) |
1172 | change_c0_srsmap (0xf << n*4, srs << n*4); | 1172 | change_c0_srsmap(0xf << n*4, srs << n*4); |
1173 | } | 1173 | } |
1174 | 1174 | ||
1175 | if (srs == 0) { | 1175 | if (srs == 0) { |
@@ -1198,10 +1198,10 @@ static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs) | |||
1198 | * Sigh... panicing won't help as the console | 1198 | * Sigh... panicing won't help as the console |
1199 | * is probably not configured :( | 1199 | * is probably not configured :( |
1200 | */ | 1200 | */ |
1201 | panic ("VECTORSPACING too small"); | 1201 | panic("VECTORSPACING too small"); |
1202 | } | 1202 | } |
1203 | 1203 | ||
1204 | memcpy (b, &except_vec_vi, handler_len); | 1204 | memcpy(b, &except_vec_vi, handler_len); |
1205 | #ifdef CONFIG_MIPS_MT_SMTC | 1205 | #ifdef CONFIG_MIPS_MT_SMTC |
1206 | BUG_ON(n > 7); /* Vector index %d exceeds SMTC maximum. */ | 1206 | BUG_ON(n > 7); /* Vector index %d exceeds SMTC maximum. */ |
1207 | 1207 | ||
@@ -1370,9 +1370,9 @@ void __init per_cpu_trap_init(void) | |||
1370 | #endif /* CONFIG_MIPS_MT_SMTC */ | 1370 | #endif /* CONFIG_MIPS_MT_SMTC */ |
1371 | 1371 | ||
1372 | if (cpu_has_veic || cpu_has_vint) { | 1372 | if (cpu_has_veic || cpu_has_vint) { |
1373 | write_c0_ebase (ebase); | 1373 | write_c0_ebase(ebase); |
1374 | /* Setting vector spacing enables EI/VI mode */ | 1374 | /* Setting vector spacing enables EI/VI mode */ |
1375 | change_c0_intctl (0x3e0, VECTORSPACING); | 1375 | change_c0_intctl(0x3e0, VECTORSPACING); |
1376 | } | 1376 | } |
1377 | if (cpu_has_divec) { | 1377 | if (cpu_has_divec) { |
1378 | if (cpu_has_mipsmt) { | 1378 | if (cpu_has_mipsmt) { |
@@ -1390,8 +1390,8 @@ void __init per_cpu_trap_init(void) | |||
1390 | * o read IntCtl.IPPCI to determine the performance counter interrupt | 1390 | * o read IntCtl.IPPCI to determine the performance counter interrupt |
1391 | */ | 1391 | */ |
1392 | if (cpu_has_mips_r2) { | 1392 | if (cpu_has_mips_r2) { |
1393 | cp0_compare_irq = (read_c0_intctl () >> 29) & 7; | 1393 | cp0_compare_irq = (read_c0_intctl() >> 29) & 7; |
1394 | cp0_perfcount_irq = (read_c0_intctl () >> 26) & 7; | 1394 | cp0_perfcount_irq = (read_c0_intctl() >> 26) & 7; |
1395 | if (cp0_perfcount_irq == cp0_compare_irq) | 1395 | if (cp0_perfcount_irq == cp0_compare_irq) |
1396 | cp0_perfcount_irq = -1; | 1396 | cp0_perfcount_irq = -1; |
1397 | } else { | 1397 | } else { |
@@ -1429,7 +1429,7 @@ void __init per_cpu_trap_init(void) | |||
1429 | } | 1429 | } |
1430 | 1430 | ||
1431 | /* Install CPU exception handler */ | 1431 | /* Install CPU exception handler */ |
1432 | void __init set_handler (unsigned long offset, void *addr, unsigned long size) | 1432 | void __init set_handler(unsigned long offset, void *addr, unsigned long size) |
1433 | { | 1433 | { |
1434 | memcpy((void *)(ebase + offset), addr, size); | 1434 | memcpy((void *)(ebase + offset), addr, size); |
1435 | flush_icache_range(ebase + offset, ebase + offset + size); | 1435 | flush_icache_range(ebase + offset, ebase + offset + size); |
@@ -1439,7 +1439,7 @@ static char panic_null_cerr[] __initdata = | |||
1439 | "Trying to set NULL cache error exception handler"; | 1439 | "Trying to set NULL cache error exception handler"; |
1440 | 1440 | ||
1441 | /* Install uncached CPU exception handler */ | 1441 | /* Install uncached CPU exception handler */ |
1442 | void __init set_uncached_handler (unsigned long offset, void *addr, unsigned long size) | 1442 | void __init set_uncached_handler(unsigned long offset, void *addr, unsigned long size) |
1443 | { | 1443 | { |
1444 | #ifdef CONFIG_32BIT | 1444 | #ifdef CONFIG_32BIT |
1445 | unsigned long uncached_ebase = KSEG1ADDR(ebase); | 1445 | unsigned long uncached_ebase = KSEG1ADDR(ebase); |
@@ -1470,7 +1470,7 @@ void __init trap_init(void) | |||
1470 | unsigned long i; | 1470 | unsigned long i; |
1471 | 1471 | ||
1472 | if (cpu_has_veic || cpu_has_vint) | 1472 | if (cpu_has_veic || cpu_has_vint) |
1473 | ebase = (unsigned long) alloc_bootmem_low_pages (0x200 + VECTORSPACING*64); | 1473 | ebase = (unsigned long) alloc_bootmem_low_pages(0x200 + VECTORSPACING*64); |
1474 | else | 1474 | else |
1475 | ebase = CAC_BASE; | 1475 | ebase = CAC_BASE; |
1476 | 1476 | ||
@@ -1496,7 +1496,7 @@ void __init trap_init(void) | |||
1496 | * destination. | 1496 | * destination. |
1497 | */ | 1497 | */ |
1498 | if (cpu_has_ejtag && board_ejtag_handler_setup) | 1498 | if (cpu_has_ejtag && board_ejtag_handler_setup) |
1499 | board_ejtag_handler_setup (); | 1499 | board_ejtag_handler_setup(); |
1500 | 1500 | ||
1501 | /* | 1501 | /* |
1502 | * Only some CPUs have the watch exceptions. | 1502 | * Only some CPUs have the watch exceptions. |