diff options
Diffstat (limited to 'arch/mips/kernel/traps.c')
-rw-r--r-- | arch/mips/kernel/traps.c | 12 |
1 files changed, 7 insertions, 5 deletions
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index b2d7041341b8..29fadaccecdd 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c | |||
@@ -1520,7 +1520,9 @@ void __cpuinit per_cpu_trap_init(void) | |||
1520 | #endif /* CONFIG_MIPS_MT_SMTC */ | 1520 | #endif /* CONFIG_MIPS_MT_SMTC */ |
1521 | 1521 | ||
1522 | if (cpu_has_veic || cpu_has_vint) { | 1522 | if (cpu_has_veic || cpu_has_vint) { |
1523 | unsigned long sr = set_c0_status(ST0_BEV); | ||
1523 | write_c0_ebase(ebase); | 1524 | write_c0_ebase(ebase); |
1525 | write_c0_status(sr); | ||
1524 | /* Setting vector spacing enables EI/VI mode */ | 1526 | /* Setting vector spacing enables EI/VI mode */ |
1525 | change_c0_intctl(0x3e0, VECTORSPACING); | 1527 | change_c0_intctl(0x3e0, VECTORSPACING); |
1526 | } | 1528 | } |
@@ -1602,8 +1604,6 @@ void __cpuinit set_uncached_handler(unsigned long offset, void *addr, | |||
1602 | #ifdef CONFIG_64BIT | 1604 | #ifdef CONFIG_64BIT |
1603 | unsigned long uncached_ebase = TO_UNCAC(ebase); | 1605 | unsigned long uncached_ebase = TO_UNCAC(ebase); |
1604 | #endif | 1606 | #endif |
1605 | if (cpu_has_mips_r2) | ||
1606 | uncached_ebase += (read_c0_ebase() & 0x3ffff000); | ||
1607 | 1607 | ||
1608 | if (!addr) | 1608 | if (!addr) |
1609 | panic(panic_null_cerr); | 1609 | panic(panic_null_cerr); |
@@ -1635,9 +1635,11 @@ void __init trap_init(void) | |||
1635 | return; /* Already done */ | 1635 | return; /* Already done */ |
1636 | #endif | 1636 | #endif |
1637 | 1637 | ||
1638 | if (cpu_has_veic || cpu_has_vint) | 1638 | if (cpu_has_veic || cpu_has_vint) { |
1639 | ebase = (unsigned long) alloc_bootmem_low_pages(0x200 + VECTORSPACING*64); | 1639 | unsigned long size = 0x200 + VECTORSPACING*64; |
1640 | else { | 1640 | ebase = (unsigned long) |
1641 | __alloc_bootmem(size, 1 << fls(size), 0); | ||
1642 | } else { | ||
1641 | ebase = CAC_BASE; | 1643 | ebase = CAC_BASE; |
1642 | if (cpu_has_mips_r2) | 1644 | if (cpu_has_mips_r2) |
1643 | ebase += (read_c0_ebase() & 0x3ffff000); | 1645 | ebase += (read_c0_ebase() & 0x3ffff000); |