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Diffstat (limited to 'arch/mips/kernel/traps.c')
-rw-r--r--arch/mips/kernel/traps.c15
1 files changed, 8 insertions, 7 deletions
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index b2d7041341b8..e83da174b533 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -1277,8 +1277,7 @@ static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs)
1277 u32 *w; 1277 u32 *w;
1278 unsigned char *b; 1278 unsigned char *b;
1279 1279
1280 if (!cpu_has_veic && !cpu_has_vint) 1280 BUG_ON(!cpu_has_veic && !cpu_has_vint);
1281 BUG();
1282 1281
1283 if (addr == NULL) { 1282 if (addr == NULL) {
1284 handler = (unsigned long) do_default_vi; 1283 handler = (unsigned long) do_default_vi;
@@ -1520,7 +1519,9 @@ void __cpuinit per_cpu_trap_init(void)
1520#endif /* CONFIG_MIPS_MT_SMTC */ 1519#endif /* CONFIG_MIPS_MT_SMTC */
1521 1520
1522 if (cpu_has_veic || cpu_has_vint) { 1521 if (cpu_has_veic || cpu_has_vint) {
1522 unsigned long sr = set_c0_status(ST0_BEV);
1523 write_c0_ebase(ebase); 1523 write_c0_ebase(ebase);
1524 write_c0_status(sr);
1524 /* Setting vector spacing enables EI/VI mode */ 1525 /* Setting vector spacing enables EI/VI mode */
1525 change_c0_intctl(0x3e0, VECTORSPACING); 1526 change_c0_intctl(0x3e0, VECTORSPACING);
1526 } 1527 }
@@ -1602,8 +1603,6 @@ void __cpuinit set_uncached_handler(unsigned long offset, void *addr,
1602#ifdef CONFIG_64BIT 1603#ifdef CONFIG_64BIT
1603 unsigned long uncached_ebase = TO_UNCAC(ebase); 1604 unsigned long uncached_ebase = TO_UNCAC(ebase);
1604#endif 1605#endif
1605 if (cpu_has_mips_r2)
1606 uncached_ebase += (read_c0_ebase() & 0x3ffff000);
1607 1606
1608 if (!addr) 1607 if (!addr)
1609 panic(panic_null_cerr); 1608 panic(panic_null_cerr);
@@ -1635,9 +1634,11 @@ void __init trap_init(void)
1635 return; /* Already done */ 1634 return; /* Already done */
1636#endif 1635#endif
1637 1636
1638 if (cpu_has_veic || cpu_has_vint) 1637 if (cpu_has_veic || cpu_has_vint) {
1639 ebase = (unsigned long) alloc_bootmem_low_pages(0x200 + VECTORSPACING*64); 1638 unsigned long size = 0x200 + VECTORSPACING*64;
1640 else { 1639 ebase = (unsigned long)
1640 __alloc_bootmem(size, 1 << fls(size), 0);
1641 } else {
1641 ebase = CAC_BASE; 1642 ebase = CAC_BASE;
1642 if (cpu_has_mips_r2) 1643 if (cpu_has_mips_r2)
1643 ebase += (read_c0_ebase() & 0x3ffff000); 1644 ebase += (read_c0_ebase() & 0x3ffff000);