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-rw-r--r--arch/mips/kernel/traps.c17
1 files changed, 11 insertions, 6 deletions
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index cfdaaa4cffc0..2d0c2a277f52 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -15,6 +15,7 @@
15#include <linux/compiler.h> 15#include <linux/compiler.h>
16#include <linux/init.h> 16#include <linux/init.h>
17#include <linux/kernel.h> 17#include <linux/kernel.h>
18#include <linux/module.h>
18#include <linux/mm.h> 19#include <linux/mm.h>
19#include <linux/sched.h> 20#include <linux/sched.h>
20#include <linux/smp.h> 21#include <linux/smp.h>
@@ -91,7 +92,7 @@ void (*board_nmi_handler_setup)(void);
91void (*board_ejtag_handler_setup)(void); 92void (*board_ejtag_handler_setup)(void);
92void (*board_bind_eic_interrupt)(int irq, int regset); 93void (*board_bind_eic_interrupt)(int irq, int regset);
93void (*board_ebase_setup)(void); 94void (*board_ebase_setup)(void);
94 95void __cpuinitdata(*board_cache_error_setup)(void);
95 96
96static void show_raw_backtrace(unsigned long reg29) 97static void show_raw_backtrace(unsigned long reg29)
97{ 98{
@@ -1490,7 +1491,6 @@ void *set_vi_handler(int n, vi_handler_t addr)
1490 return set_vi_srs_handler(n, addr, 0); 1491 return set_vi_srs_handler(n, addr, 0);
1491} 1492}
1492 1493
1493extern void cpu_cache_init(void);
1494extern void tlb_init(void); 1494extern void tlb_init(void);
1495extern void flush_tlb_handlers(void); 1495extern void flush_tlb_handlers(void);
1496 1496
@@ -1517,7 +1517,7 @@ static int __init ulri_disable(char *s)
1517} 1517}
1518__setup("noulri", ulri_disable); 1518__setup("noulri", ulri_disable);
1519 1519
1520void __cpuinit per_cpu_trap_init(void) 1520void __cpuinit per_cpu_trap_init(bool is_boot_cpu)
1521{ 1521{
1522 unsigned int cpu = smp_processor_id(); 1522 unsigned int cpu = smp_processor_id();
1523 unsigned int status_set = ST0_CU0; 1523 unsigned int status_set = ST0_CU0;
@@ -1616,7 +1616,9 @@ void __cpuinit per_cpu_trap_init(void)
1616#ifdef CONFIG_MIPS_MT_SMTC 1616#ifdef CONFIG_MIPS_MT_SMTC
1617 if (bootTC) { 1617 if (bootTC) {
1618#endif /* CONFIG_MIPS_MT_SMTC */ 1618#endif /* CONFIG_MIPS_MT_SMTC */
1619 cpu_cache_init(); 1619 /* Boot CPU's cache setup in setup_arch(). */
1620 if (!is_boot_cpu)
1621 cpu_cache_init();
1620 tlb_init(); 1622 tlb_init();
1621#ifdef CONFIG_MIPS_MT_SMTC 1623#ifdef CONFIG_MIPS_MT_SMTC
1622 } else if (!secondaryTC) { 1624 } else if (!secondaryTC) {
@@ -1632,7 +1634,7 @@ void __cpuinit per_cpu_trap_init(void)
1632} 1634}
1633 1635
1634/* Install CPU exception handler */ 1636/* Install CPU exception handler */
1635void __init set_handler(unsigned long offset, void *addr, unsigned long size) 1637void __cpuinit set_handler(unsigned long offset, void *addr, unsigned long size)
1636{ 1638{
1637 memcpy((void *)(ebase + offset), addr, size); 1639 memcpy((void *)(ebase + offset), addr, size);
1638 local_flush_icache_range(ebase + offset, ebase + offset + size); 1640 local_flush_icache_range(ebase + offset, ebase + offset + size);
@@ -1693,7 +1695,7 @@ void __init trap_init(void)
1693 1695
1694 if (board_ebase_setup) 1696 if (board_ebase_setup)
1695 board_ebase_setup(); 1697 board_ebase_setup();
1696 per_cpu_trap_init(); 1698 per_cpu_trap_init(true);
1697 1699
1698 /* 1700 /*
1699 * Copy the generic exception handlers to their final destination. 1701 * Copy the generic exception handlers to their final destination.
@@ -1797,6 +1799,9 @@ void __init trap_init(void)
1797 1799
1798 set_except_vector(26, handle_dsp); 1800 set_except_vector(26, handle_dsp);
1799 1801
1802 if (board_cache_error_setup)
1803 board_cache_error_setup();
1804
1800 if (cpu_has_vce) 1805 if (cpu_has_vce)
1801 /* Special exception: R4[04]00 uses also the divec space. */ 1806 /* Special exception: R4[04]00 uses also the divec space. */
1802 memcpy((void *)(ebase + 0x180), &except_vec3_r4000, 0x100); 1807 memcpy((void *)(ebase + 0x180), &except_vec3_r4000, 0x100);