diff options
Diffstat (limited to 'arch/mips/kernel/traps.c')
-rw-r--r-- | arch/mips/kernel/traps.c | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index 353056110f2b..f6083c6bfaa4 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c | |||
@@ -47,6 +47,7 @@ | |||
47 | #include <asm/mmu_context.h> | 47 | #include <asm/mmu_context.h> |
48 | #include <asm/types.h> | 48 | #include <asm/types.h> |
49 | #include <asm/stacktrace.h> | 49 | #include <asm/stacktrace.h> |
50 | #include <asm/irq.h> | ||
50 | 51 | ||
51 | extern void check_wait(void); | 52 | extern void check_wait(void); |
52 | extern asmlinkage void r4k_wait(void); | 53 | extern asmlinkage void r4k_wait(void); |
@@ -78,6 +79,10 @@ extern asmlinkage void handle_reserved(void); | |||
78 | extern int fpu_emulator_cop1Handler(struct pt_regs *xcp, | 79 | extern int fpu_emulator_cop1Handler(struct pt_regs *xcp, |
79 | struct mips_fpu_struct *ctx, int has_fpu); | 80 | struct mips_fpu_struct *ctx, int has_fpu); |
80 | 81 | ||
82 | #ifdef CONFIG_CPU_CAVIUM_OCTEON | ||
83 | extern asmlinkage void octeon_cop2_restore(struct octeon_cop2_state *task); | ||
84 | #endif | ||
85 | |||
81 | void (*board_be_init)(void); | 86 | void (*board_be_init)(void); |
82 | int (*board_be_handler)(struct pt_regs *regs, int is_fixup); | 87 | int (*board_be_handler)(struct pt_regs *regs, int is_fixup); |
83 | void (*board_nmi_handler_setup)(void); | 88 | void (*board_nmi_handler_setup)(void); |
@@ -860,6 +865,7 @@ asmlinkage void do_cpu(struct pt_regs *regs) | |||
860 | unsigned int opcode; | 865 | unsigned int opcode; |
861 | unsigned int cpid; | 866 | unsigned int cpid; |
862 | int status; | 867 | int status; |
868 | unsigned long __maybe_unused flags; | ||
863 | 869 | ||
864 | die_if_kernel("do_cpu invoked from kernel context!", regs); | 870 | die_if_kernel("do_cpu invoked from kernel context!", regs); |
865 | 871 | ||
@@ -915,6 +921,17 @@ asmlinkage void do_cpu(struct pt_regs *regs) | |||
915 | return; | 921 | return; |
916 | 922 | ||
917 | case 2: | 923 | case 2: |
924 | #ifdef CONFIG_CPU_CAVIUM_OCTEON | ||
925 | prefetch(¤t->thread.cp2); | ||
926 | local_irq_save(flags); | ||
927 | KSTK_STATUS(current) |= ST0_CU2; | ||
928 | status = read_c0_status(); | ||
929 | write_c0_status(status | ST0_CU2); | ||
930 | octeon_cop2_restore(&(current->thread.cp2)); | ||
931 | write_c0_status(status & ~ST0_CU2); | ||
932 | local_irq_restore(flags); | ||
933 | return; | ||
934 | #endif | ||
918 | case 3: | 935 | case 3: |
919 | break; | 936 | break; |
920 | } | 937 | } |
@@ -1488,6 +1505,10 @@ void __cpuinit per_cpu_trap_init(void) | |||
1488 | write_c0_hwrena(enable); | 1505 | write_c0_hwrena(enable); |
1489 | } | 1506 | } |
1490 | 1507 | ||
1508 | #ifdef CONFIG_CPU_CAVIUM_OCTEON | ||
1509 | write_c0_hwrena(0xc000000f); /* Octeon has register 30 and 31 */ | ||
1510 | #endif | ||
1511 | |||
1491 | #ifdef CONFIG_MIPS_MT_SMTC | 1512 | #ifdef CONFIG_MIPS_MT_SMTC |
1492 | if (!secondaryTC) { | 1513 | if (!secondaryTC) { |
1493 | #endif /* CONFIG_MIPS_MT_SMTC */ | 1514 | #endif /* CONFIG_MIPS_MT_SMTC */ |