1 files changed, 0 insertions, 262 deletions

diff --git a/arch/mips/kernel/time.c b/arch/mips/kernel/time.c
index e4b5e647b142..ea7cfe766a8e 100644
--- a/arch/mips/kernel/time.c
+++ b/arch/mips/kernel/time.c
@@ -72,14 +72,6 @@ int update_persistent_clock(struct timespec now)
         return rtc_mips_set_mmss(now.tv_sec);
 }
 
-/* how many counter cycles in a jiffy */
-static unsigned long cycles_per_jiffy __read_mostly;
-
-/*
- * Null timer ack for systems not needing one (e.g. i8254).
- */
-static void null_timer_ack(void) { /* nothing */ }
-
 /*
  * Null high precision timer functions for systems lacking one.
  */
@@ -89,14 +81,6 @@ static cycle_t null_hpt_read(void)
 }
 
 /*
- * Timer ack for an R4k-compatible timer of a known frequency.
- */
-static void c0_timer_ack(void)
-{
-        write_c0_compare(read_c0_compare());
-}
-
-/*
  * High precision timer functions for a R4k-compatible timer.
  */
 static cycle_t c0_hpt_read(void)
@@ -105,7 +89,6 @@ static cycle_t c0_hpt_read(void)
 }
 
 int (*mips_timer_state)(void);
-void (*mips_timer_ack)(void);
 
 /*
  * local_timer_interrupt() does profiling and process accounting
@@ -135,35 +118,6 @@ int (*perf_irq)(void) = null_perf_irq;
 EXPORT_SYMBOL(perf_irq);
 
 /*
- * Timer interrupt
- */
-int cp0_compare_irq;
-
-/*
- * Performance counter IRQ or -1 if shared with timer
- */
-int cp0_perfcount_irq;
-EXPORT_SYMBOL_GPL(cp0_perfcount_irq);
-
-/*
- * Possibly handle a performance counter interrupt.
- * Return true if the timer interrupt should not be checked
- */
-static inline int handle_perf_irq(int r2)
-{
-        /*
-         * The performance counter overflow interrupt may be shared with the
-         * timer interrupt (cp0_perfcount_irq < 0). If it is and a
-         * performance counter has overflowed (perf_irq() == IRQ_HANDLED)
-         * and we can't reliably determine if a counter interrupt has also
-         * happened (!r2) then don't check for a timer interrupt.
-         */
-        return (cp0_perfcount_irq < 0) &&
-                perf_irq() == IRQ_HANDLED &&
-                !r2;
-}
-
-/*
  * time_init() - it does the following things.
  *
  * 1) plat_time_init() -
@@ -228,84 +182,6 @@ struct clocksource clocksource_mips = {
         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 };
 
-static int mips_next_event(unsigned long delta,
-                           struct clock_event_device *evt)
-{
-        unsigned int cnt;
-        int res;
-
-#ifdef CONFIG_MIPS_MT_SMTC
-        {
-        unsigned long flags, vpflags;
-        local_irq_save(flags);
-        vpflags = dvpe();
-#endif
-        cnt = read_c0_count();
-        cnt += delta;
-        write_c0_compare(cnt);
-        res = ((long)(read_c0_count() - cnt ) > 0) ? -ETIME : 0;
-#ifdef CONFIG_MIPS_MT_SMTC
-        evpe(vpflags);
-        local_irq_restore(flags);
-        }
-#endif
-        return res;
-}
-
-static void mips_set_mode(enum clock_event_mode mode,
-                          struct clock_event_device *evt)
-{
-        /* Nothing to do ...  */
-}
-
-static DEFINE_PER_CPU(struct clock_event_device, mips_clockevent_device);
-static int cp0_timer_irq_installed;
-
-static irqreturn_t timer_interrupt(int irq, void *dev_id)
-{
-        const int r2 = cpu_has_mips_r2;
-        struct clock_event_device *cd;
-        int cpu = smp_processor_id();
-
-        /*
-         * Suckage alert:
-         * Before R2 of the architecture there was no way to see if a
-         * performance counter interrupt was pending, so we have to run
-         * the performance counter interrupt handler anyway.
-         */
-        if (handle_perf_irq(r2))
-                goto out;
-
-        /*
-         * The same applies to performance counter interrupts.  But with the
-         * above we now know that the reason we got here must be a timer
-         * interrupt.  Being the paranoiacs we are we check anyway.
-         */
-        if (!r2 || (read_c0_cause() & (1 << 30))) {
-                c0_timer_ack();
-#ifdef CONFIG_MIPS_MT_SMTC
-                if (cpu_data[cpu].vpe_id)
-                        goto out;
-                cpu = 0;
-#endif
-                cd = &per_cpu(mips_clockevent_device, cpu);
-                cd->event_handler(cd);
-        }
-
-out:
-        return IRQ_HANDLED;
-}
-
-static struct irqaction timer_irqaction = {
-        .handler = timer_interrupt,
-#ifdef CONFIG_MIPS_MT_SMTC
-        .flags = IRQF_DISABLED,
-#else
-        .flags = IRQF_DISABLED | IRQF_PERCPU,
-#endif
-        .name = "timer",
-};
-
 static void __init init_mips_clocksource(void)
 {
         u64 temp;
@@ -345,8 +221,6 @@ static void smtc_set_mode(enum clock_event_mode mode,
 {
 }
 
-int dummycnt[NR_CPUS];
-
 static void mips_broadcast(cpumask_t mask)
 {
         unsigned int cpu;
@@ -387,113 +261,6 @@ static void setup_smtc_dummy_clockevent_device(void)
 }
 #endif
 
-static void mips_event_handler(struct clock_event_device *dev)
-{
-}
-
-/*
- * FIXME: This doesn't hold for the relocated E9000 compare interrupt.
- */
-static int c0_compare_int_pending(void)
-{
-        return (read_c0_cause() >> cp0_compare_irq) & 0x100;
-}
-
-static int c0_compare_int_usable(void)
-{
-        const unsigned int delta = 0x300000;
-        unsigned int cnt;
-
-        /*
-         * IP7 already pending?  Try to clear it by acking the timer.
-         */
-        if (c0_compare_int_pending()) {
-                write_c0_compare(read_c0_compare());
-                irq_disable_hazard();
-                if (c0_compare_int_pending())
-                        return 0;
-        }
-
-        cnt = read_c0_count();
-        cnt += delta;
-        write_c0_compare(cnt);
-
-        while ((long)(read_c0_count() - cnt) <= 0)
-                ;       /* Wait for expiry  */
-
-        if (!c0_compare_int_pending())
-                return 0;
-
-        write_c0_compare(read_c0_compare());
-        irq_disable_hazard();
-        if (c0_compare_int_pending())
-                return 0;
-
-        /*
-         * Feels like a real count / compare timer.
-         */
-        return 1;
-}
-
-void __cpuinit mips_clockevent_init(void)
-{
-        uint64_t mips_freq = mips_hpt_frequency;
-        unsigned int cpu = smp_processor_id();
-        struct clock_event_device *cd;
-        unsigned int irq = MIPS_CPU_IRQ_BASE + 7;
-
-        if (!cpu_has_counter)
-                return;
-
-#ifdef CONFIG_MIPS_MT_SMTC
-        setup_smtc_dummy_clockevent_device();
-
-        /*
-         * On SMTC we only register VPE0's compare interrupt as clockevent
-         * device.
-         */
-        if (cpu)
-                return;
-#endif
-
-        if (!c0_compare_int_usable())
-                return;
-
-        cd = &per_cpu(mips_clockevent_device, cpu);
-
-        cd->name                = "MIPS";
-        cd->features            = CLOCK_EVT_FEAT_ONESHOT;
-
-        /* Calculate the min / max delta */
-        cd->mult        = div_sc((unsigned long) mips_freq, NSEC_PER_SEC, 32);
-        cd->shift               = 32;
-        cd->max_delta_ns        = clockevent_delta2ns(0x7fffffff, cd);
-        cd->min_delta_ns        = clockevent_delta2ns(0x300, cd);
-
-        cd->rating              = 300;
-        cd->irq                 = irq;
-#ifdef CONFIG_MIPS_MT_SMTC
-        cd->cpumask             = CPU_MASK_ALL;
-#else
-        cd->cpumask             = cpumask_of_cpu(cpu);
-#endif
-        cd->set_next_event      = mips_next_event;
-        cd->set_mode            = mips_set_mode;
-        cd->event_handler       = mips_event_handler;
-
-        clockevents_register_device(cd);
-
-        if (!cp0_timer_irq_installed) {
-#ifdef CONFIG_MIPS_MT_SMTC
-#define CPUCTR_IMASKBIT (0x100 << cp0_compare_irq)
-                setup_irq_smtc(irq, &timer_irqaction, CPUCTR_IMASKBIT);
-#else
-                setup_irq(irq, &timer_irqaction);
-#endif /* CONFIG_MIPS_MT_SMTC */
-                cp0_timer_irq_installed = 1;
-        }
-}
-
 void __init time_init(void)
 {
         plat_time_init();
@@ -512,14 +279,6 @@ void __init time_init(void)
                 if (!clocksource_mips.read) {
                         /* No external high precision timer -- use R4k.  */
                         clocksource_mips.read = c0_hpt_read;
-
-                        if (!mips_timer_state) {
-                                /* No external timer interrupt -- use R4k.  */
-                                mips_timer_ack = c0_timer_ack;
-                                /* Calculate cache parameters.  */
-                                cycles_per_jiffy =
-                                        (mips_hpt_frequency + HZ / 2) / HZ;
-                        }
                 }
                 if (!mips_hpt_frequency)
                         mips_hpt_frequency = calibrate_hpt();
@@ -528,29 +287,8 @@ void __init time_init(void)
                 printk("Using %u.%03u MHz high precision timer.\n",
                        ((mips_hpt_frequency + 500) / 1000) / 1000,
                        ((mips_hpt_frequency + 500) / 1000) % 1000);
-
-#ifdef CONFIG_IRQ_CPU
-                setup_irq(MIPS_CPU_IRQ_BASE + 7, &timer_irqaction);
-#endif
         }
 
-        if (!mips_timer_ack)
-                /* No timer interrupt ack (e.g. i8254).  */
-                mips_timer_ack = null_timer_ack;
-
-        /*
-         * Call board specific timer interrupt setup.
-         *
-         * this pointer must be setup in machine setup routine.
-         *
-         * Even if a machine chooses to use a low-level timer interrupt,
-         * it still needs to setup the timer_irqaction.
-         * In that case, it might be better to set timer_irqaction.handler
-         * to be NULL function so that we are sure the high-level code
-         * is not invoked accidentally.
-         */
-        plat_timer_setup(&timer_irqaction);
-
         init_mips_clocksource();
         mips_clockevent_init();
 }