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-rw-r--r--arch/mips/kernel/smp-bmips.c22
1 files changed, 14 insertions, 8 deletions
diff --git a/arch/mips/kernel/smp-bmips.c b/arch/mips/kernel/smp-bmips.c
index c0bb4d59076a..126da74d4c55 100644
--- a/arch/mips/kernel/smp-bmips.c
+++ b/arch/mips/kernel/smp-bmips.c
@@ -66,6 +66,8 @@ static void __init bmips_smp_setup(void)
66 int i, cpu = 1, boot_cpu = 0; 66 int i, cpu = 1, boot_cpu = 0;
67 67
68#if defined(CONFIG_CPU_BMIPS4350) || defined(CONFIG_CPU_BMIPS4380) 68#if defined(CONFIG_CPU_BMIPS4350) || defined(CONFIG_CPU_BMIPS4380)
69 int cpu_hw_intr;
70
69 /* arbitration priority */ 71 /* arbitration priority */
70 clear_c0_brcm_cmt_ctrl(0x30); 72 clear_c0_brcm_cmt_ctrl(0x30);
71 73
@@ -79,15 +81,13 @@ static void __init bmips_smp_setup(void)
79 * MIPS interrupts 0,1 (SW INT 0,1) cross over to the other thread 81 * MIPS interrupts 0,1 (SW INT 0,1) cross over to the other thread
80 * MIPS interrupt 2 (HW INT 0) is the CPU0 L1 controller output 82 * MIPS interrupt 2 (HW INT 0) is the CPU0 L1 controller output
81 * MIPS interrupt 3 (HW INT 1) is the CPU1 L1 controller output 83 * MIPS interrupt 3 (HW INT 1) is the CPU1 L1 controller output
82 *
83 * If booting from TP1, leave the existing CMT interrupt routing
84 * such that TP0 responds to SW1 and TP1 responds to SW0.
85 */ 84 */
86 if (boot_cpu == 0) 85 if (boot_cpu == 0)
87 change_c0_brcm_cmt_intr(0xf8018000, 86 cpu_hw_intr = 0x02;
88 (0x02 << 27) | (0x03 << 15));
89 else 87 else
90 change_c0_brcm_cmt_intr(0xf8018000, (0x1d << 27)); 88 cpu_hw_intr = 0x1d;
89
90 change_c0_brcm_cmt_intr(0xf8018000, (cpu_hw_intr << 27) | (0x03 << 15));
91 91
92 /* single core, 2 threads (2 pipelines) */ 92 /* single core, 2 threads (2 pipelines) */
93 max_cpus = 2; 93 max_cpus = 2;
@@ -202,9 +202,15 @@ static void bmips_init_secondary(void)
202#if defined(CONFIG_CPU_BMIPS4350) || defined(CONFIG_CPU_BMIPS4380) 202#if defined(CONFIG_CPU_BMIPS4350) || defined(CONFIG_CPU_BMIPS4380)
203 void __iomem *cbr = BMIPS_GET_CBR(); 203 void __iomem *cbr = BMIPS_GET_CBR();
204 unsigned long old_vec; 204 unsigned long old_vec;
205 unsigned long relo_vector;
206 int boot_cpu;
207
208 boot_cpu = !!(read_c0_brcm_cmt_local() & (1 << 31));
209 relo_vector = boot_cpu ? BMIPS_RELO_VECTOR_CONTROL_0 :
210 BMIPS_RELO_VECTOR_CONTROL_1;
205 211
206 old_vec = __raw_readl(cbr + BMIPS_RELO_VECTOR_CONTROL_1); 212 old_vec = __raw_readl(cbr + relo_vector);
207 __raw_writel(old_vec & ~0x20000000, cbr + BMIPS_RELO_VECTOR_CONTROL_1); 213 __raw_writel(old_vec & ~0x20000000, cbr + relo_vector);
208 214
209 clear_c0_cause(smp_processor_id() ? C_SW1 : C_SW0); 215 clear_c0_cause(smp_processor_id() ? C_SW1 : C_SW0);
210#elif defined(CONFIG_CPU_BMIPS5000) 216#elif defined(CONFIG_CPU_BMIPS5000)