diff options
Diffstat (limited to 'arch/mips/kernel/perf_event_mipsxx.c')
| -rw-r--r-- | arch/mips/kernel/perf_event_mipsxx.c | 38 |
1 files changed, 0 insertions, 38 deletions
diff --git a/arch/mips/kernel/perf_event_mipsxx.c b/arch/mips/kernel/perf_event_mipsxx.c index b14c14d90fc2..d9c81c5a6c90 100644 --- a/arch/mips/kernel/perf_event_mipsxx.c +++ b/arch/mips/kernel/perf_event_mipsxx.c | |||
| @@ -847,7 +847,6 @@ static const struct mips_perf_event xlp_event_map[PERF_COUNT_HW_MAX] = { | |||
| 847 | [PERF_COUNT_HW_CACHE_MISSES] = { 0x07, CNTR_ALL }, /* PAPI_L1_ICM */ | 847 | [PERF_COUNT_HW_CACHE_MISSES] = { 0x07, CNTR_ALL }, /* PAPI_L1_ICM */ |
| 848 | [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x1b, CNTR_ALL }, /* PAPI_BR_CN */ | 848 | [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x1b, CNTR_ALL }, /* PAPI_BR_CN */ |
| 849 | [PERF_COUNT_HW_BRANCH_MISSES] = { 0x1c, CNTR_ALL }, /* PAPI_BR_MSP */ | 849 | [PERF_COUNT_HW_BRANCH_MISSES] = { 0x1c, CNTR_ALL }, /* PAPI_BR_MSP */ |
| 850 | [PERF_COUNT_HW_BUS_CYCLES] = { UNSUPPORTED_PERF_EVENT_ID }, | ||
| 851 | }; | 850 | }; |
| 852 | 851 | ||
| 853 | /* 24K/34K/1004K cores can share the same cache event map. */ | 852 | /* 24K/34K/1004K cores can share the same cache event map. */ |
| @@ -1115,24 +1114,12 @@ static const struct mips_perf_event xlp_cache_map | |||
| 1115 | [C(RESULT_ACCESS)] = { 0x2f, CNTR_ALL }, /* PAPI_L1_DCW */ | 1114 | [C(RESULT_ACCESS)] = { 0x2f, CNTR_ALL }, /* PAPI_L1_DCW */ |
| 1116 | [C(RESULT_MISS)] = { 0x2e, CNTR_ALL }, /* PAPI_L1_STM */ | 1115 | [C(RESULT_MISS)] = { 0x2e, CNTR_ALL }, /* PAPI_L1_STM */ |
| 1117 | }, | 1116 | }, |
| 1118 | [C(OP_PREFETCH)] = { | ||
| 1119 | [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, | ||
| 1120 | [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, | ||
| 1121 | }, | ||
| 1122 | }, | 1117 | }, |
| 1123 | [C(L1I)] = { | 1118 | [C(L1I)] = { |
| 1124 | [C(OP_READ)] = { | 1119 | [C(OP_READ)] = { |
| 1125 | [C(RESULT_ACCESS)] = { 0x04, CNTR_ALL }, /* PAPI_L1_ICA */ | 1120 | [C(RESULT_ACCESS)] = { 0x04, CNTR_ALL }, /* PAPI_L1_ICA */ |
| 1126 | [C(RESULT_MISS)] = { 0x07, CNTR_ALL }, /* PAPI_L1_ICM */ | 1121 | [C(RESULT_MISS)] = { 0x07, CNTR_ALL }, /* PAPI_L1_ICM */ |
| 1127 | }, | 1122 | }, |
| 1128 | [C(OP_WRITE)] = { | ||
| 1129 | [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, | ||
| 1130 | [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, | ||
| 1131 | }, | ||
| 1132 | [C(OP_PREFETCH)] = { | ||
| 1133 | [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, | ||
| 1134 | [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, | ||
| 1135 | }, | ||
| 1136 | }, | 1123 | }, |
| 1137 | [C(LL)] = { | 1124 | [C(LL)] = { |
| 1138 | [C(OP_READ)] = { | 1125 | [C(OP_READ)] = { |
| @@ -1143,10 +1130,6 @@ static const struct mips_perf_event xlp_cache_map | |||
| 1143 | [C(RESULT_ACCESS)] = { 0x34, CNTR_ALL }, /* PAPI_L2_DCA */ | 1130 | [C(RESULT_ACCESS)] = { 0x34, CNTR_ALL }, /* PAPI_L2_DCA */ |
| 1144 | [C(RESULT_MISS)] = { 0x36, CNTR_ALL }, /* PAPI_L2_DCM */ | 1131 | [C(RESULT_MISS)] = { 0x36, CNTR_ALL }, /* PAPI_L2_DCM */ |
| 1145 | }, | 1132 | }, |
| 1146 | [C(OP_PREFETCH)] = { | ||
| 1147 | [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, | ||
| 1148 | [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, | ||
| 1149 | }, | ||
| 1150 | }, | 1133 | }, |
| 1151 | [C(DTLB)] = { | 1134 | [C(DTLB)] = { |
| 1152 | /* | 1135 | /* |
| @@ -1154,45 +1137,24 @@ static const struct mips_perf_event xlp_cache_map | |||
| 1154 | * read and write. | 1137 | * read and write. |
| 1155 | */ | 1138 | */ |
| 1156 | [C(OP_READ)] = { | 1139 | [C(OP_READ)] = { |
| 1157 | [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, | ||
| 1158 | [C(RESULT_MISS)] = { 0x2d, CNTR_ALL }, /* PAPI_TLB_DM */ | 1140 | [C(RESULT_MISS)] = { 0x2d, CNTR_ALL }, /* PAPI_TLB_DM */ |
| 1159 | }, | 1141 | }, |
| 1160 | [C(OP_WRITE)] = { | 1142 | [C(OP_WRITE)] = { |
| 1161 | [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, | ||
| 1162 | [C(RESULT_MISS)] = { 0x2d, CNTR_ALL }, /* PAPI_TLB_DM */ | 1143 | [C(RESULT_MISS)] = { 0x2d, CNTR_ALL }, /* PAPI_TLB_DM */ |
| 1163 | }, | 1144 | }, |
| 1164 | [C(OP_PREFETCH)] = { | ||
| 1165 | [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, | ||
| 1166 | [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, | ||
| 1167 | }, | ||
| 1168 | }, | 1145 | }, |
| 1169 | [C(ITLB)] = { | 1146 | [C(ITLB)] = { |
| 1170 | [C(OP_READ)] = { | 1147 | [C(OP_READ)] = { |
| 1171 | [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, | ||
| 1172 | [C(RESULT_MISS)] = { 0x08, CNTR_ALL }, /* PAPI_TLB_IM */ | 1148 | [C(RESULT_MISS)] = { 0x08, CNTR_ALL }, /* PAPI_TLB_IM */ |
| 1173 | }, | 1149 | }, |
| 1174 | [C(OP_WRITE)] = { | 1150 | [C(OP_WRITE)] = { |
| 1175 | [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, | ||
| 1176 | [C(RESULT_MISS)] = { 0x08, CNTR_ALL }, /* PAPI_TLB_IM */ | 1151 | [C(RESULT_MISS)] = { 0x08, CNTR_ALL }, /* PAPI_TLB_IM */ |
| 1177 | }, | 1152 | }, |
| 1178 | [C(OP_PREFETCH)] = { | ||
| 1179 | [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, | ||
| 1180 | [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, | ||
| 1181 | }, | ||
| 1182 | }, | 1153 | }, |
| 1183 | [C(BPU)] = { | 1154 | [C(BPU)] = { |
| 1184 | [C(OP_READ)] = { | 1155 | [C(OP_READ)] = { |
| 1185 | [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, | ||
| 1186 | [C(RESULT_MISS)] = { 0x25, CNTR_ALL }, | 1156 | [C(RESULT_MISS)] = { 0x25, CNTR_ALL }, |
| 1187 | }, | 1157 | }, |
| 1188 | [C(OP_WRITE)] = { | ||
| 1189 | [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, | ||
| 1190 | [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, | ||
| 1191 | }, | ||
| 1192 | [C(OP_PREFETCH)] = { | ||
| 1193 | [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, | ||
| 1194 | [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, | ||
| 1195 | }, | ||
| 1196 | }, | 1158 | }, |
| 1197 | }; | 1159 | }; |
| 1198 | 1160 | ||
