diff options
Diffstat (limited to 'arch/mips/kernel/irq-msc01.c')
| -rw-r--r-- | arch/mips/kernel/irq-msc01.c | 38 |
1 files changed, 18 insertions, 20 deletions
diff --git a/arch/mips/kernel/irq-msc01.c b/arch/mips/kernel/irq-msc01.c index 43c00ac0b88d..3f653c7cfbf3 100644 --- a/arch/mips/kernel/irq-msc01.c +++ b/arch/mips/kernel/irq-msc01.c | |||
| @@ -74,7 +74,7 @@ static void disable_msc_irq(unsigned int irq) | |||
| 74 | static void level_mask_and_ack_msc_irq(unsigned int irq) | 74 | static void level_mask_and_ack_msc_irq(unsigned int irq) |
| 75 | { | 75 | { |
| 76 | mask_msc_irq(irq); | 76 | mask_msc_irq(irq); |
| 77 | if (!cpu_has_ei) | 77 | if (!cpu_has_veic) |
| 78 | MSCIC_WRITE(MSC01_IC_EOI, 0); | 78 | MSCIC_WRITE(MSC01_IC_EOI, 0); |
| 79 | } | 79 | } |
| 80 | 80 | ||
| @@ -84,7 +84,7 @@ static void level_mask_and_ack_msc_irq(unsigned int irq) | |||
| 84 | static void edge_mask_and_ack_msc_irq(unsigned int irq) | 84 | static void edge_mask_and_ack_msc_irq(unsigned int irq) |
| 85 | { | 85 | { |
| 86 | mask_msc_irq(irq); | 86 | mask_msc_irq(irq); |
| 87 | if (!cpu_has_ei) | 87 | if (!cpu_has_veic) |
| 88 | MSCIC_WRITE(MSC01_IC_EOI, 0); | 88 | MSCIC_WRITE(MSC01_IC_EOI, 0); |
| 89 | else { | 89 | else { |
| 90 | u32 r; | 90 | u32 r; |
| @@ -129,25 +129,23 @@ msc_bind_eic_interrupt (unsigned int irq, unsigned int set) | |||
| 129 | #define shutdown_msc_irq disable_msc_irq | 129 | #define shutdown_msc_irq disable_msc_irq |
| 130 | 130 | ||
| 131 | struct hw_interrupt_type msc_levelirq_type = { | 131 | struct hw_interrupt_type msc_levelirq_type = { |
| 132 | "SOC-it-Level", | 132 | .typename = "SOC-it-Level", |
| 133 | startup_msc_irq, | 133 | .startup = startup_msc_irq, |
| 134 | shutdown_msc_irq, | 134 | .shutdown = shutdown_msc_irq, |
| 135 | enable_msc_irq, | 135 | .enable = enable_msc_irq, |
| 136 | disable_msc_irq, | 136 | .disable = disable_msc_irq, |
| 137 | level_mask_and_ack_msc_irq, | 137 | .ack = level_mask_and_ack_msc_irq, |
| 138 | end_msc_irq, | 138 | .end = end_msc_irq, |
| 139 | NULL | ||
| 140 | }; | 139 | }; |
| 141 | 140 | ||
| 142 | struct hw_interrupt_type msc_edgeirq_type = { | 141 | struct hw_interrupt_type msc_edgeirq_type = { |
| 143 | "SOC-it-Edge", | 142 | .typename = "SOC-it-Edge", |
| 144 | startup_msc_irq, | 143 | .startup =startup_msc_irq, |
| 145 | shutdown_msc_irq, | 144 | .shutdown = shutdown_msc_irq, |
| 146 | enable_msc_irq, | 145 | .enable = enable_msc_irq, |
| 147 | disable_msc_irq, | 146 | .disable = disable_msc_irq, |
| 148 | edge_mask_and_ack_msc_irq, | 147 | .ack = edge_mask_and_ack_msc_irq, |
| 149 | end_msc_irq, | 148 | .end = end_msc_irq, |
| 150 | NULL | ||
| 151 | }; | 149 | }; |
| 152 | 150 | ||
| 153 | 151 | ||
| @@ -168,14 +166,14 @@ void __init init_msc_irqs(unsigned int base, msc_irqmap_t *imp, int nirq) | |||
| 168 | switch (imp->im_type) { | 166 | switch (imp->im_type) { |
| 169 | case MSC01_IRQ_EDGE: | 167 | case MSC01_IRQ_EDGE: |
| 170 | irq_desc[base+n].handler = &msc_edgeirq_type; | 168 | irq_desc[base+n].handler = &msc_edgeirq_type; |
| 171 | if (cpu_has_ei) | 169 | if (cpu_has_veic) |
| 172 | MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT); | 170 | MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT); |
| 173 | else | 171 | else |
| 174 | MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT | imp->im_lvl); | 172 | MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT | imp->im_lvl); |
| 175 | break; | 173 | break; |
| 176 | case MSC01_IRQ_LEVEL: | 174 | case MSC01_IRQ_LEVEL: |
| 177 | irq_desc[base+n].handler = &msc_levelirq_type; | 175 | irq_desc[base+n].handler = &msc_levelirq_type; |
| 178 | if (cpu_has_ei) | 176 | if (cpu_has_veic) |
| 179 | MSCIC_WRITE(MSC01_IC_SUP+n*8, 0); | 177 | MSCIC_WRITE(MSC01_IC_SUP+n*8, 0); |
| 180 | else | 178 | else |
| 181 | MSCIC_WRITE(MSC01_IC_SUP+n*8, imp->im_lvl); | 179 | MSCIC_WRITE(MSC01_IC_SUP+n*8, imp->im_lvl); |
