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-rw-r--r--arch/mips/kernel/idle.c13
1 files changed, 7 insertions, 6 deletions
diff --git a/arch/mips/kernel/idle.c b/arch/mips/kernel/idle.c
index 3b09b888afa9..0c655deeea4a 100644
--- a/arch/mips/kernel/idle.c
+++ b/arch/mips/kernel/idle.c
@@ -93,26 +93,27 @@ static void rm7k_wait_irqoff(void)
93} 93}
94 94
95/* 95/*
96 * The Au1xxx wait is available only if using 32khz counter or 96 * Au1 'wait' is only useful when the 32kHz counter is used as timer,
97 * external timer source, but specifically not CP0 Counter. 97 * since coreclock (and the cp0 counter) stops upon executing it. Only an
98 * alchemy/common/time.c may override cpu_wait! 98 * interrupt can wake it, so they must be enabled before entering idle modes.
99 */ 99 */
100static void au1k_wait(void) 100static void au1k_wait(void)
101{ 101{
102 unsigned long c0status = read_c0_status() | 1; /* irqs on */
103
102 __asm__( 104 __asm__(
103 " .set mips3 \n" 105 " .set mips3 \n"
104 " cache 0x14, 0(%0) \n" 106 " cache 0x14, 0(%0) \n"
105 " cache 0x14, 32(%0) \n" 107 " cache 0x14, 32(%0) \n"
106 " sync \n" 108 " sync \n"
107 " nop \n" 109 " mtc0 %1, $12 \n" /* wr c0status */
108 " wait \n" 110 " wait \n"
109 " nop \n" 111 " nop \n"
110 " nop \n" 112 " nop \n"
111 " nop \n" 113 " nop \n"
112 " nop \n" 114 " nop \n"
113 " .set mips0 \n" 115 " .set mips0 \n"
114 : : "r" (au1k_wait)); 116 : : "r" (au1k_wait), "r" (c0status));
115 local_irq_enable();
116} 117}
117 118
118static int __initdata nowait; 119static int __initdata nowait;