1 files changed, 39 insertions, 5 deletions

diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S
index e7f6c1b90806..aa18a8b7b380 100644
--- a/arch/mips/kernel/genex.S
+++ b/arch/mips/kernel/genex.S
@@ -82,7 +82,7 @@ NESTED(except_vec3_r4000, 0, sp)
          li     k0, 14<<2
         beq     k1, k0, handle_vcei
 #ifdef CONFIG_64BIT
-        dsll    k1, k1, 1
+         dsll   k1, k1, 1
 #endif
         .set    pop
         PTR_L   k0, exception_handlers(k1)
@@ -90,17 +90,17 @@ NESTED(except_vec3_r4000, 0, sp)
 
         /*
          * Big shit, we now may have two dirty primary cache lines for the same
-         * physical address.  We can savely invalidate the line pointed to by
+         * physical address.  We can safely invalidate the line pointed to by
          * c0_badvaddr because after return from this exception handler the
          * load / store will be re-executed.
          */
 handle_vced:
-        DMFC0   k0, CP0_BADVADDR
+        MFC0    k0, CP0_BADVADDR
         li      k1, -4                                  # Is this ...
         and     k0, k1                                  # ... really needed?
         mtc0    zero, CP0_TAGLO
-        cache   Index_Store_Tag_D,(k0)
-        cache   Hit_Writeback_Inv_SD,(k0)
+        cache   Index_Store_Tag_D, (k0)
+        cache   Hit_Writeback_Inv_SD, (k0)
 #ifdef CONFIG_PROC_FS
         PTR_LA  k0, vced_count
         lw      k1, (k0)
@@ -148,6 +148,38 @@ NESTED(except_vec_ejtag_debug, 0, sp)
         __FINIT
 
 /*
+ * Vectored interrupt handler.
+ * This prototype is copied to ebase + n*IntCtl.VS and patched
+ * to invoke the handler
+ */
+NESTED(except_vec_vi, 0, sp)
+        SAVE_SOME
+        SAVE_AT
+        .set    push
+        .set    noreorder
+EXPORT(except_vec_vi_lui)
+        lui     v0, 0           /* Patched */
+        j       except_vec_vi_handler
+EXPORT(except_vec_vi_ori)
+         ori    v0, 0           /* Patched */
+        .set    pop
+        END(except_vec_vi)
+EXPORT(except_vec_vi_end)
+
+/*
+ * Common Vectored Interrupt code
+ * Complete the register saves and invoke the handler which is passed in $v0
+ */
+NESTED(except_vec_vi_handler, 0, sp)
+        SAVE_TEMP
+        SAVE_STATIC
+        CLI
+        move    a0, sp
+        jalr    v0
+        j       ret_from_irq
+        END(except_vec_vi_handler)
+
+/*
  * EJTAG debug exception handler.
  */
 NESTED(ejtag_debug_handler, PT_SIZE, sp)
@@ -291,6 +323,8 @@ NESTED(nmi_handler, PT_SIZE, sp)
         BUILD_HANDLER mdmx mdmx sti silent              /* #22 */
         BUILD_HANDLER watch watch sti verbose           /* #23 */
         BUILD_HANDLER mcheck mcheck cli verbose         /* #24 */
+        BUILD_HANDLER mt mt sti verbose                 /* #25 */
+        BUILD_HANDLER dsp dsp sti silent                /* #26 */
         BUILD_HANDLER reserved reserved sti verbose     /* others */
 
 #ifdef CONFIG_64BIT