1 files changed, 37 insertions, 3 deletions

diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 94c4a0c0a577..dc49cf30c2db 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -193,6 +193,32 @@ static void set_isa(struct cpuinfo_mips *c, unsigned int isa)
 static char unknown_isa[] = KERN_ERR \
         "Unsupported ISA type, c0.config0: %d.";
 
+static unsigned int calculate_ftlb_probability(struct cpuinfo_mips *c)
+{
+
+        unsigned int probability = c->tlbsize / c->tlbsizevtlb;
+
+        /*
+         * 0 = All TLBWR instructions go to FTLB
+         * 1 = 15:1: For every 16 TBLWR instructions, 15 go to the
+         * FTLB and 1 goes to the VTLB.
+         * 2 = 7:1: As above with 7:1 ratio.
+         * 3 = 3:1: As above with 3:1 ratio.
+         *
+         * Use the linear midpoint as the probability threshold.
+         */
+        if (probability >= 12)
+                return 1;
+        else if (probability >= 6)
+                return 2;
+        else
+                /*
+                 * So FTLB is less than 4 times bigger than VTLB.
+                 * A 3:1 ratio can still be useful though.
+                 */
+                return 3;
+}
+
 static void set_ftlb_enable(struct cpuinfo_mips *c, int enable)
 {
         unsigned int config6;
@@ -203,9 +229,14 @@ static void set_ftlb_enable(struct cpuinfo_mips *c, int enable)
         case CPU_P5600:
                 /* proAptiv & related cores use Config6 to enable the FTLB */
                 config6 = read_c0_config6();
+                /* Clear the old probability value */
+                config6 &= ~(3 << MIPS_CONF6_FTLBP_SHIFT);
                 if (enable)
                         /* Enable FTLB */
-                        write_c0_config6(config6 | MIPS_CONF6_FTLBEN);
+                        write_c0_config6(config6 |
+                                         (calculate_ftlb_probability(c)
+                                          << MIPS_CONF6_FTLBP_SHIFT)
+                                         | MIPS_CONF6_FTLBEN);
                 else
                         /* Disable FTLB */
                         write_c0_config6(config6 &  ~MIPS_CONF6_FTLBEN);
@@ -757,31 +788,34 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
                         c->cputype = CPU_LOONGSON2;
                         __cpu_name[cpu] = "ICT Loongson-2";
                         set_elf_platform(cpu, "loongson2e");
+                        set_isa(c, MIPS_CPU_ISA_III);
                         break;
                 case PRID_REV_LOONGSON2F:
                         c->cputype = CPU_LOONGSON2;
                         __cpu_name[cpu] = "ICT Loongson-2";
                         set_elf_platform(cpu, "loongson2f");
+                        set_isa(c, MIPS_CPU_ISA_III);
                         break;
                 case PRID_REV_LOONGSON3A:
                         c->cputype = CPU_LOONGSON3;
-                        c->writecombine = _CACHE_UNCACHED_ACCELERATED;
                         __cpu_name[cpu] = "ICT Loongson-3";
                         set_elf_platform(cpu, "loongson3a");
+                        set_isa(c, MIPS_CPU_ISA_M64R1);
                         break;
                 case PRID_REV_LOONGSON3B_R1:
                 case PRID_REV_LOONGSON3B_R2:
                         c->cputype = CPU_LOONGSON3;
                         __cpu_name[cpu] = "ICT Loongson-3";
                         set_elf_platform(cpu, "loongson3b");
+                        set_isa(c, MIPS_CPU_ISA_M64R1);
                         break;
                 }
 
-                set_isa(c, MIPS_CPU_ISA_III);
                 c->options = R4K_OPTS |
                              MIPS_CPU_FPU | MIPS_CPU_LLSC |
                              MIPS_CPU_32FPR;
                 c->tlbsize = 64;
+                c->writecombine = _CACHE_UNCACHED_ACCELERATED;
                 break;
         case PRID_IMP_LOONGSON_32:  /* Loongson-1 */
                 decode_configs(c);