1 files changed, 23 insertions, 4 deletions

diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 228ae864c92e..81f0aedbba0f 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -237,6 +237,13 @@ static void set_isa(struct cpuinfo_mips *c, unsigned int isa)
                 c->isa_level |= MIPS_CPU_ISA_II | MIPS_CPU_ISA_III;
                 break;
 
+        /* R6 incompatible with everything else */
+        case MIPS_CPU_ISA_M64R6:
+                c->isa_level |= MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6;
+        case MIPS_CPU_ISA_M32R6:
+                c->isa_level |= MIPS_CPU_ISA_M32R6;
+                /* Break here so we don't add incompatible ISAs */
+                break;
         case MIPS_CPU_ISA_M32R2:
                 c->isa_level |= MIPS_CPU_ISA_M32R2;
         case MIPS_CPU_ISA_M32R1:
@@ -326,6 +333,9 @@ static inline unsigned int decode_config0(struct cpuinfo_mips *c)
                 case 1:
                         set_isa(c, MIPS_CPU_ISA_M32R2);
                         break;
+                case 2:
+                        set_isa(c, MIPS_CPU_ISA_M32R6);
+                        break;
                 default:
                         goto unknown;
                 }
@@ -338,6 +348,9 @@ static inline unsigned int decode_config0(struct cpuinfo_mips *c)
                 case 1:
                         set_isa(c, MIPS_CPU_ISA_M64R2);
                         break;
+                case 2:
+                        set_isa(c, MIPS_CPU_ISA_M64R6);
+                        break;
                 default:
                         goto unknown;
                 }
@@ -501,6 +514,8 @@ static inline unsigned int decode_config5(struct cpuinfo_mips *c)
                 c->options |= MIPS_CPU_EVA;
         if (config5 & MIPS_CONF5_MRP)
                 c->options |= MIPS_CPU_MAAR;
+        if (config5 & MIPS_CONF5_LLB)
+                c->options |= MIPS_CPU_RW_LLB;
 
         return config5 & MIPS_CONF_M;
 }
@@ -543,7 +558,7 @@ static void decode_configs(struct cpuinfo_mips *c)
         }
 
 #ifndef CONFIG_MIPS_CPS
-        if (cpu_has_mips_r2) {
+        if (cpu_has_mips_r2_r6) {
                 c->core = get_ebase_cpunum();
                 if (cpu_has_mipsmt)
                         c->core >>= fls(core_nvpes()) - 1;
@@ -898,6 +913,11 @@ static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
 {
         c->writecombine = _CACHE_UNCACHED_ACCELERATED;
         switch (c->processor_id & PRID_IMP_MASK) {
+        case PRID_IMP_QEMU_GENERIC:
+                c->writecombine = _CACHE_UNCACHED;
+                c->cputype = CPU_QEMU_GENERIC;
+                __cpu_name[cpu] = "MIPS GENERIC QEMU";
+                break;
         case PRID_IMP_4KC:
                 c->cputype = CPU_4KC;
                 c->writecombine = _CACHE_UNCACHED;
@@ -1347,8 +1367,7 @@ void cpu_probe(void)
         if (c->options & MIPS_CPU_FPU) {
                 c->fpu_id = cpu_get_fpu_id();
 
-                if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 |
-                                    MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)) {
+                if (c->isa_level & cpu_has_mips_r) {
                         if (c->fpu_id & MIPS_FPIR_3D)
                                 c->ases |= MIPS_ASE_MIPS3D;
                         if (c->fpu_id & MIPS_FPIR_FREP)
@@ -1356,7 +1375,7 @@ void cpu_probe(void)
                 }
         }
 
-        if (cpu_has_mips_r2) {
+        if (cpu_has_mips_r2_r6) {
                 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
                 /* R2 has Performance Counter Interrupt indicator */
                 c->options |= MIPS_CPU_PCI;