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-rw-r--r--arch/mips/kernel/cpu-probe.c20
1 files changed, 20 insertions, 0 deletions
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 3562b854f2cd..9b6633171a1f 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -187,6 +187,7 @@ void __init check_wait(void)
187 case CPU_BCM6358: 187 case CPU_BCM6358:
188 case CPU_CAVIUM_OCTEON: 188 case CPU_CAVIUM_OCTEON:
189 case CPU_CAVIUM_OCTEON_PLUS: 189 case CPU_CAVIUM_OCTEON_PLUS:
190 case CPU_JZRISC:
190 cpu_wait = r4k_wait; 191 cpu_wait = r4k_wait;
191 break; 192 break;
192 193
@@ -956,6 +957,22 @@ platform:
956 } 957 }
957} 958}
958 959
960static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
961{
962 decode_configs(c);
963 /* JZRISC does not implement the CP0 counter. */
964 c->options &= ~MIPS_CPU_COUNTER;
965 switch (c->processor_id & 0xff00) {
966 case PRID_IMP_JZRISC:
967 c->cputype = CPU_JZRISC;
968 __cpu_name[cpu] = "Ingenic JZRISC";
969 break;
970 default:
971 panic("Unknown Ingenic Processor ID!");
972 break;
973 }
974}
975
959const char *__cpu_name[NR_CPUS]; 976const char *__cpu_name[NR_CPUS];
960const char *__elf_platform; 977const char *__elf_platform;
961 978
@@ -994,6 +1011,9 @@ __cpuinit void cpu_probe(void)
994 case PRID_COMP_CAVIUM: 1011 case PRID_COMP_CAVIUM:
995 cpu_probe_cavium(c, cpu); 1012 cpu_probe_cavium(c, cpu);
996 break; 1013 break;
1014 case PRID_COMP_INGENIC:
1015 cpu_probe_ingenic(c, cpu);
1016 break;
997 } 1017 }
998 1018
999 BUG_ON(!__cpu_name[cpu]); 1019 BUG_ON(!__cpu_name[cpu]);