1 files changed, 30 insertions, 0 deletions

diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index b12eeee0e974..c6b8b074a81a 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -186,9 +186,29 @@ static inline void check_wait(void)
         }
 }
 
+static inline void check_errata(void)
+{
+        struct cpuinfo_mips *c = &current_cpu_data;
+
+        switch (c->cputype) {
+        case CPU_34K:
+                /*
+                 * Erratum "RPS May Cause Incorrect Instruction Execution"
+                 * This code only handles VPE0, any SMP/SMTC/RTOS code
+                 * making use of VPE1 will be responsable for that VPE.
+                 */
+                if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
+                        write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
+                break;
+        default:
+                break;
+        }
+}
+
 void __init check_bugs32(void)
 {
         check_wait();
+        check_errata();
 }
 
 /*
@@ -485,6 +505,14 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
                              MIPS_CPU_LLSC;
                 c->tlbsize = 64;
                 break;
+        case PRID_IMP_LOONGSON2:
+                c->cputype = CPU_LOONGSON2;
+                c->isa_level = MIPS_CPU_ISA_III;
+                c->options = R4K_OPTS |
+                             MIPS_CPU_FPU | MIPS_CPU_LLSC |
+                             MIPS_CPU_32FPR;
+                c->tlbsize = 64;
+                break;
         }
 }
 
@@ -588,6 +616,8 @@ static inline unsigned int decode_config3(struct cpuinfo_mips *c)
                 c->options |= MIPS_CPU_VEIC;
         if (config3 & MIPS_CONF3_MT)
                 c->ases |= MIPS_ASE_MIPSMT;
+        if (config3 & MIPS_CONF3_ULRI)
+                c->options |= MIPS_CPU_ULRI;
 
         return config3 & MIPS_CONF_M;
 }