4 files changed, 107 insertions, 86 deletions

diff --git a/arch/mips/jz4740/Makefile b/arch/mips/jz4740/Makefile
index a604eaeb6c08..a9dff3321251 100644
--- a/arch/mips/jz4740/Makefile
+++ b/arch/mips/jz4740/Makefile
@@ -17,4 +17,4 @@ obj-$(CONFIG_JZ4740_QI_LB60)	+= board-qi_lb60.o
 
 obj-$(CONFIG_PM) += pm.o
 
-EXTRA_CFLAGS += -Werror -Wall
+ccflags-y := -Werror -Wall
diff --git a/arch/mips/jz4740/board-qi_lb60.c b/arch/mips/jz4740/board-qi_lb60.c
index 2c0e107966ad..c3b04be3fb2b 100644
--- a/arch/mips/jz4740/board-qi_lb60.c
+++ b/arch/mips/jz4740/board-qi_lb60.c
@@ -23,6 +23,7 @@
 #include <linux/spi/spi_gpio.h>
 #include <linux/power_supply.h>
 #include <linux/power/jz4740-battery.h>
+#include <linux/power/gpio-charger.h>
 
 #include <asm/mach-jz4740/jz4740_fb.h>
 #include <asm/mach-jz4740/jz4740_mmc.h>
@@ -49,14 +50,14 @@ static bool is_avt2;
 
 /* NAND */
 static struct nand_ecclayout qi_lb60_ecclayout_1gb = {
-/*      .eccbytes = 36,
+        .eccbytes = 36,
         .eccpos = {
                 6,  7,  8,  9,  10, 11, 12, 13,
                 14, 15, 16, 17, 18, 19, 20, 21,
                 22, 23, 24, 25, 26, 27, 28, 29,
                 30, 31, 32, 33, 34, 35, 36, 37,
                 38, 39, 40, 41
-        },*/
+        },
         .oobfree = {
                 { .offset = 2, .length = 4 },
                 { .offset = 42, .length = 22 }
@@ -64,7 +65,7 @@ static struct nand_ecclayout qi_lb60_ecclayout_1gb = {
 };
 
 /* Early prototypes of the QI LB60 had only 1GB of NAND.
- * In order to support these devices aswell the partition and ecc layout is
+ * In order to support these devices as well the partition and ecc layout is
  * initialized depending on the NAND size */
 static struct mtd_partition qi_lb60_partitions_1gb[] = {
         {
@@ -85,7 +86,7 @@ static struct mtd_partition qi_lb60_partitions_1gb[] = {
 };
 
 static struct nand_ecclayout qi_lb60_ecclayout_2gb = {
-/*      .eccbytes = 72,
+        .eccbytes = 72,
         .eccpos = {
                 12, 13, 14, 15, 16, 17, 18, 19,
                 20, 21, 22, 23, 24, 25, 26, 27,
@@ -96,7 +97,7 @@ static struct nand_ecclayout qi_lb60_ecclayout_2gb = {
                 60, 61, 62, 63, 64, 65, 66, 67,
                 68, 69, 70, 71, 72, 73, 74, 75,
                 76, 77, 78, 79, 80, 81, 82, 83
-        },*/
+        },
         .oobfree = {
                 { .offset = 2, .length = 10 },
                 { .offset = 84, .length = 44 },
@@ -396,6 +397,28 @@ static struct platform_device qi_lb60_pwm_beeper = {
         },
 };
 
+/* charger */
+static char *qi_lb60_batteries[] = {
+        "battery",
+};
+
+static struct gpio_charger_platform_data qi_lb60_charger_pdata = {
+        .name = "usb",
+        .type = POWER_SUPPLY_TYPE_USB,
+        .gpio = JZ_GPIO_PORTD(28),
+        .gpio_active_low = 1,
+        .supplied_to = qi_lb60_batteries,
+        .num_supplicants = ARRAY_SIZE(qi_lb60_batteries),
+};
+
+static struct platform_device qi_lb60_charger_device = {
+        .name = "gpio-charger",
+        .dev = {
+                .platform_data = &qi_lb60_charger_pdata,
+        },
+};
+
+
 static struct platform_device *jz_platform_devices[] __initdata = {
         &jz4740_udc_device,
         &jz4740_mmc_device,
@@ -410,12 +433,13 @@ static struct platform_device *jz_platform_devices[] __initdata = {
         &jz4740_adc_device,
         &qi_lb60_gpio_keys,
         &qi_lb60_pwm_beeper,
+        &qi_lb60_charger_device,
 };
 
 static void __init board_gpio_setup(void)
 {
         /* We only need to enable/disable pullup here for pins used in generic
-         * drivers. Everything else is done by the drivers themselfs. */
+         * drivers. Everything else is done by the drivers themselves. */
         jz_gpio_disable_pullup(QI_LB60_GPIO_SD_VCC_EN_N);
         jz_gpio_disable_pullup(QI_LB60_GPIO_SD_CD);
 }
diff --git a/arch/mips/jz4740/gpio.c b/arch/mips/jz4740/gpio.c
index 88e6aeda5bf1..73031f7fc827 100644
--- a/arch/mips/jz4740/gpio.c
+++ b/arch/mips/jz4740/gpio.c
@@ -86,7 +86,6 @@ struct jz_gpio_chip {
         spinlock_t lock;
 
         struct gpio_chip gpio_chip;
-        struct irq_chip irq_chip;
         struct sys_device sysdev;
 };
 
@@ -102,9 +101,9 @@ static inline struct jz_gpio_chip *gpio_chip_to_jz_gpio_chip(struct gpio_chip *g
         return container_of(gpio_chip, struct jz_gpio_chip, gpio_chip);
 }
 
-static inline struct jz_gpio_chip *irq_to_jz_gpio_chip(unsigned int irq)
+static inline struct jz_gpio_chip *irq_to_jz_gpio_chip(struct irq_data *data)
 {
-        return get_irq_chip_data(irq);
+        return irq_data_get_irq_chip_data(data);
 }
 
 static inline void jz_gpio_write_bit(unsigned int gpio, unsigned int reg)
@@ -307,7 +306,7 @@ static void jz_gpio_irq_demux_handler(unsigned int irq, struct irq_desc *desc)
         uint32_t flag;
         unsigned int gpio_irq;
         unsigned int gpio_bank;
-        struct jz_gpio_chip *chip = get_irq_desc_data(desc);
+        struct jz_gpio_chip *chip = irq_desc_get_handler_data(desc);
 
         gpio_bank = JZ4740_IRQ_GPIO0 - irq;
 
@@ -325,62 +324,52 @@ static void jz_gpio_irq_demux_handler(unsigned int irq, struct irq_desc *desc)
         generic_handle_irq(gpio_irq);
 };
 
-static inline void jz_gpio_set_irq_bit(unsigned int irq, unsigned int reg)
+static inline void jz_gpio_set_irq_bit(struct irq_data *data, unsigned int reg)
 {
-        struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(irq);
-        writel(IRQ_TO_BIT(irq), chip->base + reg);
+        struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(data);
+        writel(IRQ_TO_BIT(data->irq), chip->base + reg);
 }
 
-static void jz_gpio_irq_mask(unsigned int irq)
+static void jz_gpio_irq_mask(struct irq_data *data)
 {
-        jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_MASK_SET);
+        jz_gpio_set_irq_bit(data, JZ_REG_GPIO_MASK_SET);
 };
 
-static void jz_gpio_irq_unmask(unsigned int irq)
+static void jz_gpio_irq_unmask(struct irq_data *data)
 {
-        struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(irq);
+        struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(data);
 
-        jz_gpio_check_trigger_both(chip, irq);
+        jz_gpio_check_trigger_both(chip, data->irq);
 
-        jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_MASK_CLEAR);
+        jz_gpio_set_irq_bit(data, JZ_REG_GPIO_MASK_CLEAR);
 };
 
 /* TODO: Check if function is gpio */
-static unsigned int jz_gpio_irq_startup(unsigned int irq)
+static unsigned int jz_gpio_irq_startup(struct irq_data *data)
 {
-        struct irq_desc *desc = irq_to_desc(irq);
-
-        jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_SELECT_SET);
-
-        desc->status &= ~IRQ_MASKED;
-        jz_gpio_irq_unmask(irq);
-
+        jz_gpio_set_irq_bit(data, JZ_REG_GPIO_SELECT_SET);
+        jz_gpio_irq_unmask(data);
         return 0;
 }
 
-static void jz_gpio_irq_shutdown(unsigned int irq)
+static void jz_gpio_irq_shutdown(struct irq_data *data)
 {
-        struct irq_desc *desc = irq_to_desc(irq);
-
-        jz_gpio_irq_mask(irq);
-        desc->status |= IRQ_MASKED;
+        jz_gpio_irq_mask(data);
 
         /* Set direction to input */
-        jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_DIRECTION_CLEAR);
-        jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_SELECT_CLEAR);
+        jz_gpio_set_irq_bit(data, JZ_REG_GPIO_DIRECTION_CLEAR);
+        jz_gpio_set_irq_bit(data, JZ_REG_GPIO_SELECT_CLEAR);
 }
 
-static void jz_gpio_irq_ack(unsigned int irq)
+static void jz_gpio_irq_ack(struct irq_data *data)
 {
-        jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_FLAG_CLEAR);
+        jz_gpio_set_irq_bit(data, JZ_REG_GPIO_FLAG_CLEAR);
 };
 
-static int jz_gpio_irq_set_type(unsigned int irq, unsigned int flow_type)
+static int jz_gpio_irq_set_type(struct irq_data *data, unsigned int flow_type)
 {
-        struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(irq);
-        struct irq_desc *desc = irq_to_desc(irq);
-
-        jz_gpio_irq_mask(irq);
+        struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(data);
+        unsigned int irq = data->irq;
 
         if (flow_type == IRQ_TYPE_EDGE_BOTH) {
                 uint32_t value = readl(chip->base + JZ_REG_GPIO_PIN);
@@ -395,45 +384,54 @@ static int jz_gpio_irq_set_type(unsigned int irq, unsigned int flow_type)
 
         switch (flow_type) {
         case IRQ_TYPE_EDGE_RISING:
-                jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_DIRECTION_SET);
-                jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_TRIGGER_SET);
+                jz_gpio_set_irq_bit(data, JZ_REG_GPIO_DIRECTION_SET);
+                jz_gpio_set_irq_bit(data, JZ_REG_GPIO_TRIGGER_SET);
                 break;
         case IRQ_TYPE_EDGE_FALLING:
-                jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_DIRECTION_CLEAR);
-                jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_TRIGGER_SET);
+                jz_gpio_set_irq_bit(data, JZ_REG_GPIO_DIRECTION_CLEAR);
+                jz_gpio_set_irq_bit(data, JZ_REG_GPIO_TRIGGER_SET);
                 break;
         case IRQ_TYPE_LEVEL_HIGH:
-                jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_DIRECTION_SET);
-                jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_TRIGGER_CLEAR);
+                jz_gpio_set_irq_bit(data, JZ_REG_GPIO_DIRECTION_SET);
+                jz_gpio_set_irq_bit(data, JZ_REG_GPIO_TRIGGER_CLEAR);
                 break;
         case IRQ_TYPE_LEVEL_LOW:
-                jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_DIRECTION_CLEAR);
-                jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_TRIGGER_CLEAR);
+                jz_gpio_set_irq_bit(data, JZ_REG_GPIO_DIRECTION_CLEAR);
+                jz_gpio_set_irq_bit(data, JZ_REG_GPIO_TRIGGER_CLEAR);
                 break;
         default:
                 return -EINVAL;
         }
 
-        if (!(desc->status & IRQ_MASKED))
-                jz_gpio_irq_unmask(irq);
-
         return 0;
 }
 
-static int jz_gpio_irq_set_wake(unsigned int irq, unsigned int on)
+static int jz_gpio_irq_set_wake(struct irq_data *data, unsigned int on)
 {
-        struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(irq);
+        struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(data);
         spin_lock(&chip->lock);
         if (on)
-                chip->wakeup |= IRQ_TO_BIT(irq);
+                chip->wakeup |= IRQ_TO_BIT(data->irq);
         else
-                chip->wakeup &= ~IRQ_TO_BIT(irq);
+                chip->wakeup &= ~IRQ_TO_BIT(data->irq);
         spin_unlock(&chip->lock);
 
-        set_irq_wake(chip->irq, on);
+        irq_set_irq_wake(chip->irq, on);
         return 0;
 }
 
+static struct irq_chip jz_gpio_irq_chip = {
+        .name = "GPIO",
+        .irq_mask = jz_gpio_irq_mask,
+        .irq_unmask = jz_gpio_irq_unmask,
+        .irq_ack = jz_gpio_irq_ack,
+        .irq_startup = jz_gpio_irq_startup,
+        .irq_shutdown = jz_gpio_irq_shutdown,
+        .irq_set_type = jz_gpio_irq_set_type,
+        .irq_set_wake = jz_gpio_irq_set_wake,
+        .flags = IRQCHIP_SET_TYPE_MASKED,
+};
+
 /*
  * This lock class tells lockdep that GPIO irqs are in a different
  * category than their parents, so it won't report false recursion.
@@ -452,16 +450,6 @@ static struct lock_class_key gpio_lock_class;
                 .base = JZ4740_GPIO_BASE_ ## _bank, \
                 .ngpio = JZ4740_GPIO_NUM_ ## _bank, \
         }, \
-        .irq_chip =  { \
-                .name = "GPIO Bank " # _bank, \
-                .mask = jz_gpio_irq_mask, \
-                .unmask = jz_gpio_irq_unmask, \
-                .ack = jz_gpio_irq_ack, \
-                .startup = jz_gpio_irq_startup, \
-                .shutdown = jz_gpio_irq_shutdown, \
-                .set_type = jz_gpio_irq_set_type, \
-                .set_wake = jz_gpio_irq_set_wake, \
-        }, \
 }
 
 static struct jz_gpio_chip jz4740_gpio_chips[] = {
@@ -522,13 +510,14 @@ static int jz4740_gpio_chip_init(struct jz_gpio_chip *chip, unsigned int id)
         gpiochip_add(&chip->gpio_chip);
 
         chip->irq = JZ4740_IRQ_INTC_GPIO(id);
-        set_irq_data(chip->irq, chip);
-        set_irq_chained_handler(chip->irq, jz_gpio_irq_demux_handler);
+        irq_set_handler_data(chip->irq, chip);
+        irq_set_chained_handler(chip->irq, jz_gpio_irq_demux_handler);
 
         for (irq = chip->irq_base; irq < chip->irq_base + chip->gpio_chip.ngpio; ++irq) {
-                lockdep_set_class(&irq_desc[irq].lock, &gpio_lock_class);
-                set_irq_chip_data(irq, chip);
-                set_irq_chip_and_handler(irq, &chip->irq_chip, handle_level_irq);
+                irq_set_lockdep_class(irq, &gpio_lock_class);
+                irq_set_chip_data(irq, chip);
+                irq_set_chip_and_handler(irq, &jz_gpio_irq_chip,
+                                         handle_level_irq);
         }
 
         return 0;
diff --git a/arch/mips/jz4740/irq.c b/arch/mips/jz4740/irq.c
index 7d33ff83580f..d82c0c430e03 100644
--- a/arch/mips/jz4740/irq.c
+++ b/arch/mips/jz4740/irq.c
@@ -43,32 +43,37 @@ static uint32_t jz_intc_saved;
 
 #define IRQ_BIT(x) BIT((x) - JZ4740_IRQ_BASE)
 
-static void intc_irq_unmask(unsigned int irq)
+static inline unsigned long intc_irq_bit(struct irq_data *data)
 {
-        writel(IRQ_BIT(irq), jz_intc_base + JZ_REG_INTC_CLEAR_MASK);
+        return (unsigned long)irq_data_get_irq_chip_data(data);
 }
 
-static void intc_irq_mask(unsigned int irq)
+static void intc_irq_unmask(struct irq_data *data)
 {
-        writel(IRQ_BIT(irq), jz_intc_base + JZ_REG_INTC_SET_MASK);
+        writel(intc_irq_bit(data), jz_intc_base + JZ_REG_INTC_CLEAR_MASK);
 }
 
-static int intc_irq_set_wake(unsigned int irq, unsigned int on)
+static void intc_irq_mask(struct irq_data *data)
+{
+        writel(intc_irq_bit(data), jz_intc_base + JZ_REG_INTC_SET_MASK);
+}
+
+static int intc_irq_set_wake(struct irq_data *data, unsigned int on)
 {
         if (on)
-                jz_intc_wakeup |= IRQ_BIT(irq);
+                jz_intc_wakeup |= intc_irq_bit(data);
         else
-                jz_intc_wakeup &= ~IRQ_BIT(irq);
+                jz_intc_wakeup &= ~intc_irq_bit(data);
 
         return 0;
 }
 
 static struct irq_chip intc_irq_type = {
         .name =         "INTC",
-        .mask =         intc_irq_mask,
-        .mask_ack =     intc_irq_mask,
-        .unmask =       intc_irq_unmask,
-        .set_wake =     intc_irq_set_wake,
+        .irq_mask =     intc_irq_mask,
+        .irq_mask_ack = intc_irq_mask,
+        .irq_unmask =   intc_irq_unmask,
+        .irq_set_wake = intc_irq_set_wake,
 };
 
 static irqreturn_t jz4740_cascade(int irq, void *data)
@@ -95,9 +100,12 @@ void __init arch_init_irq(void)
 
         jz_intc_base = ioremap(JZ4740_INTC_BASE_ADDR, 0x14);
 
+        /* Mask all irqs */
+        writel(0xffffffff, jz_intc_base + JZ_REG_INTC_SET_MASK);
+
         for (i = JZ4740_IRQ_BASE; i < JZ4740_IRQ_BASE + 32; i++) {
-                intc_irq_mask(i);
-                set_irq_chip_and_handler(i, &intc_irq_type, handle_level_irq);
+                irq_set_chip_data(i, (void *)IRQ_BIT(i));
+                irq_set_chip_and_handler(i, &intc_irq_type, handle_level_irq);
         }
 
         setup_irq(2, &jz4740_cascade_action);