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-rw-r--r--arch/mips/jmr3927/common/Makefile5
-rw-r--r--arch/mips/jmr3927/common/prom.c81
-rw-r--r--arch/mips/jmr3927/common/puts.c168
-rw-r--r--arch/mips/jmr3927/common/rtc_ds1742.c165
-rw-r--r--arch/mips/jmr3927/rbhma3100/Makefile9
-rw-r--r--arch/mips/jmr3927/rbhma3100/init.c77
-rw-r--r--arch/mips/jmr3927/rbhma3100/int-handler.S74
-rw-r--r--arch/mips/jmr3927/rbhma3100/irq.c466
-rw-r--r--arch/mips/jmr3927/rbhma3100/kgdb_io.c155
-rw-r--r--arch/mips/jmr3927/rbhma3100/setup.c510
10 files changed, 1710 insertions, 0 deletions
diff --git a/arch/mips/jmr3927/common/Makefile b/arch/mips/jmr3927/common/Makefile
new file mode 100644
index 000000000000..cb09a8eede15
--- /dev/null
+++ b/arch/mips/jmr3927/common/Makefile
@@ -0,0 +1,5 @@
1#
2# Makefile for the common code of TOSHIBA JMR-TX3927 board
3#
4
5obj-y += prom.o puts.o rtc_ds1742.o
diff --git a/arch/mips/jmr3927/common/prom.c b/arch/mips/jmr3927/common/prom.c
new file mode 100644
index 000000000000..5d5838f41d23
--- /dev/null
+++ b/arch/mips/jmr3927/common/prom.c
@@ -0,0 +1,81 @@
1/*
2 * BRIEF MODULE DESCRIPTION
3 * PROM library initialisation code, assuming a version of
4 * pmon is the boot code.
5 *
6 * Copyright 2001 MontaVista Software Inc.
7 * Author: MontaVista Software, Inc.
8 * ahennessy@mvista.com
9 *
10 * Based on arch/mips/au1000/common/prom.c
11 *
12 * This file was derived from Carsten Langgaard's
13 * arch/mips/mips-boards/xx files.
14 *
15 * Carsten Langgaard, carstenl@mips.com
16 * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
17 *
18 * This program is free software; you can redistribute it and/or modify it
19 * under the terms of the GNU General Public License as published by the
20 * Free Software Foundation; either version 2 of the License, or (at your
21 * option) any later version.
22 *
23 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
26 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
29 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
30 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 *
34 * You should have received a copy of the GNU General Public License along
35 * with this program; if not, write to the Free Software Foundation, Inc.,
36 * 675 Mass Ave, Cambridge, MA 02139, USA.
37 */
38#include <linux/kernel.h>
39#include <linux/init.h>
40#include <linux/string.h>
41
42#include <asm/bootinfo.h>
43
44extern int prom_argc;
45extern char **prom_argv, **prom_envp;
46
47typedef struct
48{
49 char *name;
50/* char *val; */
51}t_env_var;
52
53
54char * __init prom_getcmdline(void)
55{
56 return &(arcs_cmdline[0]);
57}
58
59void __init prom_init_cmdline(void)
60{
61 char *cp;
62 int actr;
63
64 actr = 1; /* Always ignore argv[0] */
65
66 cp = &(arcs_cmdline[0]);
67 while(actr < prom_argc) {
68 strcpy(cp, prom_argv[actr]);
69 cp += strlen(prom_argv[actr]);
70 *cp++ = ' ';
71 actr++;
72 }
73 if (cp != &(arcs_cmdline[0])) /* get rid of trailing space */
74 --cp;
75 *cp = '\0';
76}
77
78unsigned long __init prom_free_prom_memory(void)
79{
80 return 0;
81}
diff --git a/arch/mips/jmr3927/common/puts.c b/arch/mips/jmr3927/common/puts.c
new file mode 100644
index 000000000000..1c1cad9cd078
--- /dev/null
+++ b/arch/mips/jmr3927/common/puts.c
@@ -0,0 +1,168 @@
1/*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * Low level uart routines to directly access a TX[34]927 SIO.
5 *
6 * Copyright 2001 MontaVista Software Inc.
7 * Author: MontaVista Software, Inc.
8 * ahennessy@mvista.com or source@mvista.com
9 *
10 * Copyright (C) 2000-2001 Toshiba Corporation
11 *
12 * Based on arch/mips/au1000/common/puts.c
13 *
14 * This program is free software; you can redistribute it and/or modify it
15 * under the terms of the GNU General Public License as published by the
16 * Free Software Foundation; either version 2 of the License, or (at your
17 * option) any later version.
18 *
19 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
20 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
22 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
25 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
28 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 *
30 * You should have received a copy of the GNU General Public License along
31 * with this program; if not, write to the Free Software Foundation, Inc.,
32 * 675 Mass Ave, Cambridge, MA 02139, USA.
33 */
34
35#include <linux/types.h>
36#include <asm/jmr3927/txx927.h>
37#include <asm/jmr3927/tx3927.h>
38#include <asm/jmr3927/jmr3927.h>
39
40#define TIMEOUT 0xffffff
41#define SLOW_DOWN
42
43static const char digits[16] = "0123456789abcdef";
44
45#ifdef SLOW_DOWN
46#define slow_down() { int k; for (k=0; k<10000; k++); }
47#else
48#define slow_down()
49#endif
50
51void
52putch(const unsigned char c)
53{
54 int i = 0;
55
56 do {
57 slow_down();
58 i++;
59 if (i>TIMEOUT) {
60 break;
61 }
62 } while (!(tx3927_sioptr(1)->cisr & TXx927_SICISR_TXALS));
63 tx3927_sioptr(1)->tfifo = c;
64 return;
65}
66
67unsigned char getch(void)
68{
69 int i = 0;
70 int dicr;
71 char c;
72
73 /* diable RX int. */
74 dicr = tx3927_sioptr(1)->dicr;
75 tx3927_sioptr(1)->dicr = 0;
76
77 do {
78 slow_down();
79 i++;
80 if (i>TIMEOUT) {
81 break;
82 }
83 } while (tx3927_sioptr(1)->disr & TXx927_SIDISR_UVALID)
84 ;
85 c = tx3927_sioptr(1)->rfifo;
86
87 /* clear RX int. status */
88 tx3927_sioptr(1)->disr &= ~TXx927_SIDISR_RDIS;
89 /* enable RX int. */
90 tx3927_sioptr(1)->dicr = dicr;
91
92 return c;
93}
94void
95do_jmr3927_led_set(char n)
96{
97 /* and with current leds */
98 jmr3927_led_and_set(n);
99}
100
101void
102puts(unsigned char *cp)
103{
104 int i = 0;
105
106 while (*cp) {
107 do {
108 slow_down();
109 i++;
110 if (i>TIMEOUT) {
111 break;
112 }
113 } while (!(tx3927_sioptr(1)->cisr & TXx927_SICISR_TXALS));
114 tx3927_sioptr(1)->tfifo = *cp++;
115 }
116 putch('\r');
117 putch('\n');
118}
119
120void
121fputs(unsigned char *cp)
122{
123 int i = 0;
124
125 while (*cp) {
126 do {
127 slow_down();
128 i++;
129 if (i>TIMEOUT) {
130 break;
131 }
132 } while (!(tx3927_sioptr(1)->cisr & TXx927_SICISR_TXALS));
133 tx3927_sioptr(1)->tfifo = *cp++;
134 }
135}
136
137
138void
139put64(uint64_t ul)
140{
141 int cnt;
142 unsigned ch;
143
144 cnt = 16; /* 16 nibbles in a 64 bit long */
145 putch('0');
146 putch('x');
147 do {
148 cnt--;
149 ch = (unsigned char)(ul >> cnt * 4) & 0x0F;
150 putch(digits[ch]);
151 } while (cnt > 0);
152}
153
154void
155put32(unsigned u)
156{
157 int cnt;
158 unsigned ch;
159
160 cnt = 8; /* 8 nibbles in a 32 bit long */
161 putch('0');
162 putch('x');
163 do {
164 cnt--;
165 ch = (unsigned char)(u >> cnt * 4) & 0x0F;
166 putch(digits[ch]);
167 } while (cnt > 0);
168}
diff --git a/arch/mips/jmr3927/common/rtc_ds1742.c b/arch/mips/jmr3927/common/rtc_ds1742.c
new file mode 100644
index 000000000000..1ae4318e1358
--- /dev/null
+++ b/arch/mips/jmr3927/common/rtc_ds1742.c
@@ -0,0 +1,165 @@
1/*
2 * Copyright 2001 MontaVista Software Inc.
3 * Author: MontaVista Software, Inc.
4 * ahennessy@mvista.com
5 *
6 * arch/mips/jmr3927/common/rtc_ds1742.c
7 * Based on arch/mips/ddb5xxx/common/rtc_ds1386.c
8 * low-level RTC hookups for s for Dallas 1742 chip.
9 *
10 * Copyright (C) 2000-2001 Toshiba Corporation
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 *
17 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
18 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
20 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
23 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
24 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * You should have received a copy of the GNU General Public License along
29 * with this program; if not, write to the Free Software Foundation, Inc.,
30 * 675 Mass Ave, Cambridge, MA 02139, USA.
31 */
32
33
34/*
35 * This file exports a function, rtc_ds1386_init(), which expects an
36 * uncached base address as the argument. It will set the two function
37 * pointers expected by the MIPS generic timer code.
38 */
39
40#include <linux/bcd.h>
41#include <linux/types.h>
42#include <linux/time.h>
43#include <linux/rtc.h>
44
45#include <asm/time.h>
46#include <asm/addrspace.h>
47
48#include <asm/jmr3927/ds1742rtc.h>
49#include <asm/debug.h>
50
51#define EPOCH 2000
52
53static unsigned long rtc_base;
54
55static unsigned long
56rtc_ds1742_get_time(void)
57{
58 unsigned int year, month, day, hour, minute, second;
59 unsigned int century;
60
61 CMOS_WRITE(RTC_READ, RTC_CONTROL);
62 second = BCD2BIN(CMOS_READ(RTC_SECONDS) & RTC_SECONDS_MASK);
63 minute = BCD2BIN(CMOS_READ(RTC_MINUTES));
64 hour = BCD2BIN(CMOS_READ(RTC_HOURS));
65 day = BCD2BIN(CMOS_READ(RTC_DATE));
66 month = BCD2BIN(CMOS_READ(RTC_MONTH));
67 year = BCD2BIN(CMOS_READ(RTC_YEAR));
68 century = BCD2BIN(CMOS_READ(RTC_CENTURY) & RTC_CENTURY_MASK);
69 CMOS_WRITE(0, RTC_CONTROL);
70
71 year += century * 100;
72
73 return mktime(year, month, day, hour, minute, second);
74}
75extern void to_tm(unsigned long tim, struct rtc_time * tm);
76
77static int
78rtc_ds1742_set_time(unsigned long t)
79{
80 struct rtc_time tm;
81 u8 year, month, day, hour, minute, second;
82 u8 cmos_year, cmos_month, cmos_day, cmos_hour, cmos_minute, cmos_second;
83 int cmos_century;
84
85 CMOS_WRITE(RTC_READ, RTC_CONTROL);
86 cmos_second = (u8)(CMOS_READ(RTC_SECONDS) & RTC_SECONDS_MASK);
87 cmos_minute = (u8)CMOS_READ(RTC_MINUTES);
88 cmos_hour = (u8)CMOS_READ(RTC_HOURS);
89 cmos_day = (u8)CMOS_READ(RTC_DATE);
90 cmos_month = (u8)CMOS_READ(RTC_MONTH);
91 cmos_year = (u8)CMOS_READ(RTC_YEAR);
92 cmos_century = CMOS_READ(RTC_CENTURY) & RTC_CENTURY_MASK;
93
94 CMOS_WRITE(RTC_WRITE, RTC_CONTROL);
95
96 /* convert */
97 to_tm(t, &tm);
98
99 /* check each field one by one */
100 year = BIN2BCD(tm.tm_year - EPOCH);
101 if (year != cmos_year) {
102 CMOS_WRITE(year,RTC_YEAR);
103 }
104
105 month = BIN2BCD(tm.tm_mon);
106 if (month != (cmos_month & 0x1f)) {
107 CMOS_WRITE((month & 0x1f) | (cmos_month & ~0x1f),RTC_MONTH);
108 }
109
110 day = BIN2BCD(tm.tm_mday);
111 if (day != cmos_day) {
112
113 CMOS_WRITE(day, RTC_DATE);
114 }
115
116 if (cmos_hour & 0x40) {
117 /* 12 hour format */
118 hour = 0x40;
119 if (tm.tm_hour > 12) {
120 hour |= 0x20 | (BIN2BCD(hour-12) & 0x1f);
121 } else {
122 hour |= BIN2BCD(tm.tm_hour);
123 }
124 } else {
125 /* 24 hour format */
126 hour = BIN2BCD(tm.tm_hour) & 0x3f;
127 }
128 if (hour != cmos_hour) CMOS_WRITE(hour, RTC_HOURS);
129
130 minute = BIN2BCD(tm.tm_min);
131 if (minute != cmos_minute) {
132 CMOS_WRITE(minute, RTC_MINUTES);
133 }
134
135 second = BIN2BCD(tm.tm_sec);
136 if (second != cmos_second) {
137 CMOS_WRITE(second & RTC_SECONDS_MASK,RTC_SECONDS);
138 }
139
140 /* RTC_CENTURY and RTC_CONTROL share same address... */
141 CMOS_WRITE(cmos_century, RTC_CONTROL);
142
143 return 0;
144}
145
146void
147rtc_ds1742_init(unsigned long base)
148{
149 u8 cmos_second;
150
151 /* remember the base */
152 rtc_base = base;
153 db_assert((rtc_base & 0xe0000000) == KSEG1);
154
155 /* set the function pointers */
156 rtc_get_time = rtc_ds1742_get_time;
157 rtc_set_time = rtc_ds1742_set_time;
158
159 /* clear oscillator stop bit */
160 CMOS_WRITE(RTC_READ, RTC_CONTROL);
161 cmos_second = (u8)(CMOS_READ(RTC_SECONDS) & RTC_SECONDS_MASK);
162 CMOS_WRITE(RTC_WRITE, RTC_CONTROL);
163 CMOS_WRITE(cmos_second, RTC_SECONDS); /* clear msb */
164 CMOS_WRITE(0, RTC_CONTROL);
165}
diff --git a/arch/mips/jmr3927/rbhma3100/Makefile b/arch/mips/jmr3927/rbhma3100/Makefile
new file mode 100644
index 000000000000..75bf418b94c0
--- /dev/null
+++ b/arch/mips/jmr3927/rbhma3100/Makefile
@@ -0,0 +1,9 @@
1#
2# Makefile for TOSHIBA JMR-TX3927 board
3#
4
5obj-y += init.o int-handler.o irq.o setup.o
6obj-$(CONFIG_RUNTIME_DEBUG) += debug.o
7obj-$(CONFIG_KGDB) += kgdb_io.o
8
9EXTRA_AFLAGS := $(CFLAGS)
diff --git a/arch/mips/jmr3927/rbhma3100/init.c b/arch/mips/jmr3927/rbhma3100/init.c
new file mode 100644
index 000000000000..a0674d73962f
--- /dev/null
+++ b/arch/mips/jmr3927/rbhma3100/init.c
@@ -0,0 +1,77 @@
1/*
2 * Copyright 2001 MontaVista Software Inc.
3 * Author: MontaVista Software, Inc.
4 * ahennessy@mvista.com
5 *
6 * arch/mips/jmr3927/common/init.c
7 *
8 * Copyright (C) 2000-2001 Toshiba Corporation
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
17 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
21 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
22 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * You should have received a copy of the GNU General Public License along
27 * with this program; if not, write to the Free Software Foundation, Inc.,
28 * 675 Mass Ave, Cambridge, MA 02139, USA.
29 */
30#include <linux/config.h>
31#include <linux/init.h>
32#include <linux/mm.h>
33#include <linux/sched.h>
34#include <linux/bootmem.h>
35
36#include <asm/addrspace.h>
37#include <asm/bootinfo.h>
38#include <asm/mipsregs.h>
39#include <asm/jmr3927/jmr3927.h>
40
41int prom_argc;
42char **prom_argv, **prom_envp;
43extern void __init prom_init_cmdline(void);
44extern char *prom_getenv(char *envname);
45unsigned long mips_nofpu = 0;
46
47const char *get_system_type(void)
48{
49 return "Toshiba"
50#ifdef CONFIG_TOSHIBA_JMR3927
51 " JMR_TX3927"
52#endif
53 ;
54}
55
56extern void puts(unsigned char *cp);
57
58void __init prom_init(void)
59{
60#ifdef CONFIG_TOSHIBA_JMR3927
61 /* CCFG */
62 if ((tx3927_ccfgptr->ccfg & TX3927_CCFG_TLBOFF) == 0)
63 puts("Warning: TX3927 TLB off\n");
64#endif
65 prom_argc = fw_arg0;
66 prom_argv = (char **) fw_arg1;
67 prom_envp = (char **) fw_arg2;
68
69 mips_machgroup = MACH_GROUP_TOSHIBA;
70
71#ifdef CONFIG_TOSHIBA_JMR3927
72 mips_machtype = MACH_TOSHIBA_JMR3927;
73#endif
74
75 prom_init_cmdline();
76 add_memory_region(0, JMR3927_SDRAM_SIZE, BOOT_MEM_RAM);
77}
diff --git a/arch/mips/jmr3927/rbhma3100/int-handler.S b/arch/mips/jmr3927/rbhma3100/int-handler.S
new file mode 100644
index 000000000000..f85bbf407542
--- /dev/null
+++ b/arch/mips/jmr3927/rbhma3100/int-handler.S
@@ -0,0 +1,74 @@
1/*
2 * Copyright 2001 MontaVista Software Inc.
3 * Author: MontaVista Software, Inc.
4 * ahennessy@mvista.com
5 *
6 * Based on arch/mips/tsdb/kernel/int-handler.S
7 *
8 * Copyright (C) 2000-2001 Toshiba Corporation
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
17 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
21 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
22 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * You should have received a copy of the GNU General Public License along
27 * with this program; if not, write to the Free Software Foundation, Inc.,
28 * 675 Mass Ave, Cambridge, MA 02139, USA.
29 */
30
31#include <asm/asm.h>
32#include <asm/mipsregs.h>
33#include <asm/regdef.h>
34#include <asm/stackframe.h>
35#include <asm/jmr3927/jmr3927.h>
36
37 /* A lot of complication here is taken away because:
38 *
39 * 1) We handle one interrupt and return, sitting in a loop
40 * and moving across all the pending IRQ bits in the cause
41 * register is _NOT_ the answer, the common case is one
42 * pending IRQ so optimize in that direction.
43 *
44 * 2) We need not check against bits in the status register
45 * IRQ mask, that would make this routine slow as hell.
46 *
47 * 3) Linux only thinks in terms of all IRQs on or all IRQs
48 * off, nothing in between like BSD spl() brain-damage.
49 *
50 */
51
52/* Flush write buffer (needed?)
53 * NOTE: TX39xx performs "non-blocking load", so explicitly use the target
54 * register of LBU to flush immediately.
55 */
56#define FLUSH_WB(tmp) \
57 la tmp, JMR3927_IOC_REV_ADDR; \
58 lbu tmp, (tmp); \
59 move tmp, zero;
60
61 .text
62 .set noreorder
63 .set noat
64 .align 5
65 NESTED(jmr3927_IRQ, PT_SIZE, sp)
66 SAVE_ALL
67 CLI
68 .set at
69 jal jmr3927_irc_irqdispatch
70 move a0, sp
71 FLUSH_WB(t0)
72 j ret_from_irq
73 nop
74 END(jmr3927_IRQ)
diff --git a/arch/mips/jmr3927/rbhma3100/irq.c b/arch/mips/jmr3927/rbhma3100/irq.c
new file mode 100644
index 000000000000..b9799b86fc79
--- /dev/null
+++ b/arch/mips/jmr3927/rbhma3100/irq.c
@@ -0,0 +1,466 @@
1/*
2 * Copyright 2001 MontaVista Software Inc.
3 * Author: MontaVista Software, Inc.
4 * ahennessy@mvista.com
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 *
10 * Copyright (C) 2000-2001 Toshiba Corporation
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 *
17 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
18 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
20 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
23 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
24 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * You should have received a copy of the GNU General Public License along
29 * with this program; if not, write to the Free Software Foundation, Inc.,
30 * 675 Mass Ave, Cambridge, MA 02139, USA.
31 */
32#include <linux/config.h>
33#include <linux/init.h>
34
35#include <linux/errno.h>
36#include <linux/irq.h>
37#include <linux/kernel_stat.h>
38#include <linux/signal.h>
39#include <linux/sched.h>
40#include <linux/types.h>
41#include <linux/interrupt.h>
42#include <linux/ioport.h>
43#include <linux/timex.h>
44#include <linux/slab.h>
45#include <linux/random.h>
46#include <linux/smp.h>
47#include <linux/smp_lock.h>
48#include <linux/bitops.h>
49
50#include <asm/io.h>
51#include <asm/mipsregs.h>
52#include <asm/system.h>
53
54#include <asm/ptrace.h>
55#include <asm/processor.h>
56#include <asm/jmr3927/irq.h>
57#include <asm/debug.h>
58#include <asm/jmr3927/jmr3927.h>
59
60#if JMR3927_IRQ_END > NR_IRQS
61#error JMR3927_IRQ_END > NR_IRQS
62#endif
63
64struct tb_irq_space* tb_irq_spaces;
65
66static int jmr3927_irq_base = -1;
67
68#ifdef CONFIG_PCI
69static int jmr3927_gen_iack(void)
70{
71 /* generate ACK cycle */
72#ifdef __BIG_ENDIAN
73 return (tx3927_pcicptr->iiadp >> 24) & 0xff;
74#else
75 return tx3927_pcicptr->iiadp & 0xff;
76#endif
77}
78#endif
79
80extern asmlinkage void jmr3927_IRQ(void);
81
82#define irc_dlevel 0
83#define irc_elevel 1
84
85static unsigned char irc_level[TX3927_NUM_IR] = {
86 5, 5, 5, 5, 5, 5, /* INT[5:0] */
87 7, 7, /* SIO */
88 5, 5, 5, 0, 0, /* DMA, PIO, PCI */
89 6, 6, 6 /* TMR */
90};
91
92static void jmr3927_irq_disable(unsigned int irq_nr);
93static void jmr3927_irq_enable(unsigned int irq_nr);
94
95static DEFINE_SPINLOCK(jmr3927_irq_lock);
96
97static unsigned int jmr3927_irq_startup(unsigned int irq)
98{
99 jmr3927_irq_enable(irq);
100
101 return 0;
102}
103
104#define jmr3927_irq_shutdown jmr3927_irq_disable
105
106static void jmr3927_irq_ack(unsigned int irq)
107{
108 if (irq == JMR3927_IRQ_IRC_TMR0)
109 jmr3927_tmrptr->tisr = 0; /* ack interrupt */
110
111 jmr3927_irq_disable(irq);
112}
113
114static void jmr3927_irq_end(unsigned int irq)
115{
116 jmr3927_irq_enable(irq);
117}
118
119static void jmr3927_irq_disable(unsigned int irq_nr)
120{
121 struct tb_irq_space* sp;
122 unsigned long flags;
123
124 spinlock_irqsave(&jmr3927_irq_lock, flags);
125 for (sp = tb_irq_spaces; sp; sp = sp->next) {
126 if (sp->start_irqno <= irq_nr &&
127 irq_nr < sp->start_irqno + sp->nr_irqs) {
128 if (sp->mask_func)
129 sp->mask_func(irq_nr - sp->start_irqno,
130 sp->space_id);
131 break;
132 }
133 }
134 spinlock_irqrestore(&jmr3927_irq_lock, flags);
135}
136
137static void jmr3927_irq_enable(unsigned int irq_nr)
138{
139 struct tb_irq_space* sp;
140 unsigned long flags;
141
142 spinlock_irqsave(&jmr3927_irq_lock, flags);
143 for (sp = tb_irq_spaces; sp; sp = sp->next) {
144 if (sp->start_irqno <= irq_nr &&
145 irq_nr < sp->start_irqno + sp->nr_irqs) {
146 if (sp->unmask_func)
147 sp->unmask_func(irq_nr - sp->start_irqno,
148 sp->space_id);
149 break;
150 }
151 }
152 spinlock_irqrestore(&jmr3927_irq_lock, flags);
153}
154
155/*
156 * CP0_STATUS is a thread's resource (saved/restored on context switch).
157 * So disable_irq/enable_irq MUST handle IOC/ISAC/IRC registers.
158 */
159static void mask_irq_isac(int irq_nr, int space_id)
160{
161 /* 0: mask */
162 unsigned char imask =
163 jmr3927_isac_reg_in(JMR3927_ISAC_INTM_ADDR);
164 unsigned int bit = 1 << irq_nr;
165 jmr3927_isac_reg_out(imask & ~bit, JMR3927_ISAC_INTM_ADDR);
166 /* flush write buffer */
167 (void)jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR);
168}
169static void unmask_irq_isac(int irq_nr, int space_id)
170{
171 /* 0: mask */
172 unsigned char imask = jmr3927_isac_reg_in(JMR3927_ISAC_INTM_ADDR);
173 unsigned int bit = 1 << irq_nr;
174 jmr3927_isac_reg_out(imask | bit, JMR3927_ISAC_INTM_ADDR);
175 /* flush write buffer */
176 (void)jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR);
177}
178
179static void mask_irq_ioc(int irq_nr, int space_id)
180{
181 /* 0: mask */
182 unsigned char imask = jmr3927_ioc_reg_in(JMR3927_IOC_INTM_ADDR);
183 unsigned int bit = 1 << irq_nr;
184 jmr3927_ioc_reg_out(imask & ~bit, JMR3927_IOC_INTM_ADDR);
185 /* flush write buffer */
186 (void)jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR);
187}
188static void unmask_irq_ioc(int irq_nr, int space_id)
189{
190 /* 0: mask */
191 unsigned char imask = jmr3927_ioc_reg_in(JMR3927_IOC_INTM_ADDR);
192 unsigned int bit = 1 << irq_nr;
193 jmr3927_ioc_reg_out(imask | bit, JMR3927_IOC_INTM_ADDR);
194 /* flush write buffer */
195 (void)jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR);
196}
197
198static void mask_irq_irc(int irq_nr, int space_id)
199{
200 volatile unsigned long *ilrp = &tx3927_ircptr->ilr[irq_nr / 2];
201 if (irq_nr & 1)
202 *ilrp = (*ilrp & 0x00ff) | (irc_dlevel << 8);
203 else
204 *ilrp = (*ilrp & 0xff00) | irc_dlevel;
205 /* update IRCSR */
206 tx3927_ircptr->imr = 0;
207 tx3927_ircptr->imr = irc_elevel;
208}
209static void unmask_irq_irc(int irq_nr, int space_id)
210{
211 volatile unsigned long *ilrp = &tx3927_ircptr->ilr[irq_nr / 2];
212 if (irq_nr & 1)
213 *ilrp = (*ilrp & 0x00ff) | (irc_level[irq_nr] << 8);
214 else
215 *ilrp = (*ilrp & 0xff00) | irc_level[irq_nr];
216 /* update IRCSR */
217 tx3927_ircptr->imr = 0;
218 tx3927_ircptr->imr = irc_elevel;
219}
220
221struct tb_irq_space jmr3927_isac_irqspace = {
222 .next = NULL,
223 .start_irqno = JMR3927_IRQ_ISAC,
224 nr_irqs : JMR3927_NR_IRQ_ISAC,
225 .mask_func = mask_irq_isac,
226 .unmask_func = unmask_irq_isac,
227 .name = "ISAC",
228 .space_id = 0,
229 can_share : 0
230};
231struct tb_irq_space jmr3927_ioc_irqspace = {
232 .next = NULL,
233 .start_irqno = JMR3927_IRQ_IOC,
234 nr_irqs : JMR3927_NR_IRQ_IOC,
235 .mask_func = mask_irq_ioc,
236 .unmask_func = unmask_irq_ioc,
237 .name = "IOC",
238 .space_id = 0,
239 can_share : 1
240};
241struct tb_irq_space jmr3927_irc_irqspace = {
242 .next = NULL,
243 .start_irqno = JMR3927_IRQ_IRC,
244 nr_irqs : JMR3927_NR_IRQ_IRC,
245 .mask_func = mask_irq_irc,
246 .unmask_func = unmask_irq_irc,
247 .name = "on-chip",
248 .space_id = 0,
249 can_share : 0
250};
251
252void jmr3927_spurious(struct pt_regs *regs)
253{
254#ifdef CONFIG_TX_BRANCH_LIKELY_BUG_WORKAROUND
255 tx_branch_likely_bug_fixup(regs);
256#endif
257 printk(KERN_WARNING "spurious interrupt (cause 0x%lx, pc 0x%lx, ra 0x%lx).\n",
258 regs->cp0_cause, regs->cp0_epc, regs->regs[31]);
259}
260
261void jmr3927_irc_irqdispatch(struct pt_regs *regs)
262{
263 int irq;
264
265#ifdef CONFIG_TX_BRANCH_LIKELY_BUG_WORKAROUND
266 tx_branch_likely_bug_fixup(regs);
267#endif
268 if ((regs->cp0_cause & CAUSEF_IP7) == 0) {
269#if 0
270 jmr3927_spurious(regs);
271#endif
272 return;
273 }
274 irq = (regs->cp0_cause >> CAUSEB_IP2) & 0x0f;
275
276 do_IRQ(irq + JMR3927_IRQ_IRC, regs);
277}
278
279static void jmr3927_ioc_interrupt(int irq, void *dev_id, struct pt_regs *regs)
280{
281 unsigned char istat = jmr3927_ioc_reg_in(JMR3927_IOC_INTS2_ADDR);
282 int i;
283
284 for (i = 0; i < JMR3927_NR_IRQ_IOC; i++) {
285 if (istat & (1 << i)) {
286 irq = JMR3927_IRQ_IOC + i;
287 do_IRQ(irq, regs);
288 }
289 }
290}
291
292static struct irqaction ioc_action = {
293 jmr3927_ioc_interrupt, 0, CPU_MASK_NONE, "IOC", NULL, NULL,
294};
295
296static void jmr3927_isac_interrupt(int irq, void *dev_id, struct pt_regs *regs)
297{
298 unsigned char istat = jmr3927_isac_reg_in(JMR3927_ISAC_INTS2_ADDR);
299 int i;
300
301 for (i = 0; i < JMR3927_NR_IRQ_ISAC; i++) {
302 if (istat & (1 << i)) {
303 irq = JMR3927_IRQ_ISAC + i;
304 do_IRQ(irq, regs);
305 }
306 }
307}
308
309static struct irqaction isac_action = {
310 jmr3927_isac_interrupt, 0, CPU_MASK_NONE, "ISAC", NULL, NULL,
311};
312
313
314static void jmr3927_isaerr_interrupt(int irq, void * dev_id, struct pt_regs * regs)
315{
316 printk(KERN_WARNING "ISA error interrupt (irq 0x%x).\n", irq);
317}
318static struct irqaction isaerr_action = {
319 jmr3927_isaerr_interrupt, 0, CPU_MASK_NONE, "ISA error", NULL, NULL,
320};
321
322static void jmr3927_pcierr_interrupt(int irq, void * dev_id, struct pt_regs * regs)
323{
324 printk(KERN_WARNING "PCI error interrupt (irq 0x%x).\n", irq);
325 printk(KERN_WARNING "pcistat:%02x, lbstat:%04lx\n",
326 tx3927_pcicptr->pcistat, tx3927_pcicptr->lbstat);
327}
328static struct irqaction pcierr_action = {
329 jmr3927_pcierr_interrupt, 0, CPU_MASK_NONE, "PCI error", NULL, NULL,
330};
331
332int jmr3927_ether1_irq = 0;
333
334void jmr3927_irq_init(u32 irq_base);
335
336void __init arch_init_irq(void)
337{
338 /* look for io board's presence */
339 int have_isac = jmr3927_have_isac();
340
341 /* Now, interrupt control disabled, */
342 /* all IRC interrupts are masked, */
343 /* all IRC interrupt mode are Low Active. */
344
345 if (have_isac) {
346
347 /* ETHER1 (NE2000 compatible 10M-Ether) parameter setup */
348 /* temporary enable interrupt control */
349 tx3927_ircptr->cer = 1;
350 /* ETHER1 Int. Is High-Active. */
351 if (tx3927_ircptr->ssr & (1 << 0))
352 jmr3927_ether1_irq = JMR3927_IRQ_IRC_INT0;
353#if 0 /* INT3 may be asserted by ether0 (even after reboot...) */
354 else if (tx3927_ircptr->ssr & (1 << 3))
355 jmr3927_ether1_irq = JMR3927_IRQ_IRC_INT3;
356#endif
357 /* disable interrupt control */
358 tx3927_ircptr->cer = 0;
359
360 /* Ether1: High Active */
361 if (jmr3927_ether1_irq) {
362 int ether1_irc = jmr3927_ether1_irq - JMR3927_IRQ_IRC;
363 tx3927_ircptr->cr[ether1_irc / 8] |=
364 TX3927_IRCR_HIGH << ((ether1_irc % 8) * 2);
365 }
366 }
367
368 /* mask all IOC interrupts */
369 jmr3927_ioc_reg_out(0, JMR3927_IOC_INTM_ADDR);
370 /* setup IOC interrupt mode (SOFT:High Active, Others:Low Active) */
371 jmr3927_ioc_reg_out(JMR3927_IOC_INTF_SOFT, JMR3927_IOC_INTP_ADDR);
372
373 if (have_isac) {
374 /* mask all ISAC interrupts */
375 jmr3927_isac_reg_out(0, JMR3927_ISAC_INTM_ADDR);
376 /* setup ISAC interrupt mode (ISAIRQ3,ISAIRQ5:Low Active ???) */
377 jmr3927_isac_reg_out(JMR3927_ISAC_INTF_IRQ3|JMR3927_ISAC_INTF_IRQ5, JMR3927_ISAC_INTP_ADDR);
378 }
379
380 /* clear PCI Soft interrupts */
381 jmr3927_ioc_reg_out(0, JMR3927_IOC_INTS1_ADDR);
382 /* clear PCI Reset interrupts */
383 jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
384
385 /* enable interrupt control */
386 tx3927_ircptr->cer = TX3927_IRCER_ICE;
387 tx3927_ircptr->imr = irc_elevel;
388
389 jmr3927_irq_init(NR_ISA_IRQS);
390
391 set_except_vector(0, jmr3927_IRQ);
392
393 /* setup irq space */
394 add_tb_irq_space(&jmr3927_isac_irqspace);
395 add_tb_irq_space(&jmr3927_ioc_irqspace);
396 add_tb_irq_space(&jmr3927_irc_irqspace);
397
398 /* setup IOC interrupt 1 (PCI, MODEM) */
399 setup_irq(JMR3927_IRQ_IOCINT, &ioc_action);
400
401 if (have_isac) {
402 setup_irq(JMR3927_IRQ_ISACINT, &isac_action);
403 setup_irq(JMR3927_IRQ_ISAC_ISAER, &isaerr_action);
404 }
405
406#ifdef CONFIG_PCI
407 setup_irq(JMR3927_IRQ_IRC_PCI, &pcierr_action);
408#endif
409
410 /* enable all CPU interrupt bits. */
411 set_c0_status(ST0_IM); /* IE bit is still 0. */
412}
413
414static hw_irq_controller jmr3927_irq_controller = {
415 "jmr3927_irq",
416 jmr3927_irq_startup,
417 jmr3927_irq_shutdown,
418 jmr3927_irq_enable,
419 jmr3927_irq_disable,
420 jmr3927_irq_ack,
421 jmr3927_irq_end,
422};
423
424void jmr3927_irq_init(u32 irq_base)
425{
426 u32 i;
427
428 for (i= irq_base; i< irq_base + JMR3927_NR_IRQ_IRC + JMR3927_NR_IRQ_IOC; i++) {
429 irq_desc[i].status = IRQ_DISABLED;
430 irq_desc[i].action = NULL;
431 irq_desc[i].depth = 1;
432 irq_desc[i].handler = &jmr3927_irq_controller;
433 }
434
435 jmr3927_irq_base = irq_base;
436}
437
438#ifdef CONFIG_TX_BRANCH_LIKELY_BUG_WORKAROUND
439static int tx_branch_likely_bug_count = 0;
440static int have_tx_branch_likely_bug = 0;
441void tx_branch_likely_bug_fixup(struct pt_regs *regs)
442{
443 /* TX39/49-BUG: Under this condition, the insn in delay slot
444 of the branch likely insn is executed (not nullified) even
445 the branch condition is false. */
446 if (!have_tx_branch_likely_bug)
447 return;
448 if ((regs->cp0_epc & 0xfff) == 0xffc &&
449 KSEGX(regs->cp0_epc) != KSEG0 &&
450 KSEGX(regs->cp0_epc) != KSEG1) {
451 unsigned int insn = *(unsigned int*)(regs->cp0_epc - 4);
452 /* beql,bnel,blezl,bgtzl */
453 /* bltzl,bgezl,blezall,bgezall */
454 /* bczfl, bcztl */
455 if ((insn & 0xf0000000) == 0x50000000 ||
456 (insn & 0xfc0e0000) == 0x04020000 ||
457 (insn & 0xf3fe0000) == 0x41020000) {
458 regs->cp0_epc -= 4;
459 tx_branch_likely_bug_count++;
460 printk(KERN_INFO
461 "fix branch-likery bug in %s (insn %08x)\n",
462 current->comm, insn);
463 }
464 }
465}
466#endif
diff --git a/arch/mips/jmr3927/rbhma3100/kgdb_io.c b/arch/mips/jmr3927/rbhma3100/kgdb_io.c
new file mode 100644
index 000000000000..269a42deae06
--- /dev/null
+++ b/arch/mips/jmr3927/rbhma3100/kgdb_io.c
@@ -0,0 +1,155 @@
1/*
2 * BRIEF MODULE DESCRIPTION
3 * Low level uart routines to directly access a TX[34]927 SIO.
4 *
5 * Copyright 2001 MontaVista Software Inc.
6 * Author: MontaVista Software, Inc.
7 * ahennessy@mvista.com or source@mvista.com
8 *
9 * Based on arch/mips/ddb5xxx/ddb5477/kgdb_io.c
10 *
11 * Copyright (C) 2000-2001 Toshiba Corporation
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
17 *
18 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
19 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
20 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
21 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
24 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
25 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * You should have received a copy of the GNU General Public License along
30 * with this program; if not, write to the Free Software Foundation, Inc.,
31 * 675 Mass Ave, Cambridge, MA 02139, USA.
32 */
33
34#include <linux/types.h>
35#include <asm/jmr3927/txx927.h>
36#include <asm/jmr3927/tx3927.h>
37#include <asm/jmr3927/jmr3927.h>
38
39#define TIMEOUT 0xffffff
40#define SLOW_DOWN
41
42static const char digits[16] = "0123456789abcdef";
43
44#ifdef SLOW_DOWN
45#define slow_down() { int k; for (k=0; k<10000; k++); }
46#else
47#define slow_down()
48#endif
49
50static int remoteDebugInitialized = 0;
51
52int putDebugChar(unsigned char c)
53{
54 int i = 0;
55
56 if (!remoteDebugInitialized) {
57 remoteDebugInitialized = 1;
58 debugInit(38400);
59 }
60
61 do {
62 slow_down();
63 i++;
64 if (i>TIMEOUT) {
65 break;
66 }
67 } while (!(tx3927_sioptr(0)->cisr & TXx927_SICISR_TXALS));
68 tx3927_sioptr(0)->tfifo = c;
69
70 return 1;
71}
72
73unsigned char getDebugChar(void)
74{
75 int i = 0;
76 int dicr;
77 char c;
78
79 if (!remoteDebugInitialized) {
80 remoteDebugInitialized = 1;
81 debugInit(38400);
82 }
83
84 /* diable RX int. */
85 dicr = tx3927_sioptr(0)->dicr;
86 tx3927_sioptr(0)->dicr = 0;
87
88 do {
89 slow_down();
90 i++;
91 if (i>TIMEOUT) {
92 break;
93 }
94 } while (tx3927_sioptr(0)->disr & TXx927_SIDISR_UVALID)
95 ;
96 c = tx3927_sioptr(0)->rfifo;
97
98 /* clear RX int. status */
99 tx3927_sioptr(0)->disr &= ~TXx927_SIDISR_RDIS;
100 /* enable RX int. */
101 tx3927_sioptr(0)->dicr = dicr;
102
103 return c;
104}
105
106void debugInit(int baud)
107{
108 /*
109 volatile unsigned long lcr;
110 volatile unsigned long dicr;
111 volatile unsigned long disr;
112 volatile unsigned long cisr;
113 volatile unsigned long fcr;
114 volatile unsigned long flcr;
115 volatile unsigned long bgr;
116 volatile unsigned long tfifo;
117 volatile unsigned long rfifo;
118 */
119
120 tx3927_sioptr(0)->lcr = 0x020;
121 tx3927_sioptr(0)->dicr = 0;
122 tx3927_sioptr(0)->disr = 0x4100;
123 tx3927_sioptr(0)->cisr = 0x014;
124 tx3927_sioptr(0)->fcr = 0;
125 tx3927_sioptr(0)->flcr = 0x02;
126 tx3927_sioptr(0)->bgr = ((JMR3927_BASE_BAUD + baud / 2) / baud) |
127 TXx927_SIBGR_BCLK_T0;
128#if 0
129 /*
130 * Reset the UART.
131 */
132 tx3927_sioptr(0)->fcr = TXx927_SIFCR_SWRST;
133 while (tx3927_sioptr(0)->fcr & TXx927_SIFCR_SWRST)
134 ;
135
136 /*
137 * and set the speed of the serial port
138 * (currently hardwired to 9600 8N1
139 */
140
141 tx3927_sioptr(0)->lcr = TXx927_SILCR_UMODE_8BIT |
142 TXx927_SILCR_USBL_1BIT |
143 TXx927_SILCR_SCS_IMCLK_BG;
144 tx3927_sioptr(0)->bgr =
145 ((JMR3927_BASE_BAUD + baud / 2) / baud) |
146 TXx927_SIBGR_BCLK_T0;
147
148 /* HW RTS/CTS control */
149 if (ser->flags & ASYNC_HAVE_CTS_LINE)
150 tx3927_sioptr(0)->flcr = TXx927_SIFLCR_RCS | TXx927_SIFLCR_TES |
151 TXx927_SIFLCR_RTSTL_MAX /* 15 */;
152 /* Enable RX/TX */
153 tx3927_sioptr(0)->flcr &= ~(TXx927_SIFLCR_RSDE | TXx927_SIFLCR_TSDE);
154#endif
155}
diff --git a/arch/mips/jmr3927/rbhma3100/setup.c b/arch/mips/jmr3927/rbhma3100/setup.c
new file mode 100644
index 000000000000..32039bb2f440
--- /dev/null
+++ b/arch/mips/jmr3927/rbhma3100/setup.c
@@ -0,0 +1,510 @@
1/***********************************************************************
2 *
3 * Copyright 2001 MontaVista Software Inc.
4 * Author: MontaVista Software, Inc.
5 * ahennessy@mvista.com
6 *
7 * Based on arch/mips/ddb5xxx/ddb5477/setup.c
8 *
9 * Setup file for JMR3927.
10 *
11 * Copyright (C) 2000-2001 Toshiba Corporation
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
17 *
18 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
19 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
20 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
21 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
24 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
25 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * You should have received a copy of the GNU General Public License along
30 * with this program; if not, write to the Free Software Foundation, Inc.,
31 * 675 Mass Ave, Cambridge, MA 02139, USA.
32 *
33 ***********************************************************************
34 */
35
36#include <linux/config.h>
37#include <linux/init.h>
38#include <linux/kernel.h>
39#include <linux/kdev_t.h>
40#include <linux/types.h>
41#include <linux/sched.h>
42#include <linux/pci.h>
43#include <linux/ide.h>
44#include <linux/ioport.h>
45#include <linux/param.h> /* for HZ */
46#include <linux/delay.h>
47
48#include <asm/addrspace.h>
49#include <asm/time.h>
50#include <asm/bcache.h>
51#include <asm/irq.h>
52#include <asm/reboot.h>
53#include <asm/gdb-stub.h>
54#include <asm/jmr3927/jmr3927.h>
55#include <asm/mipsregs.h>
56#include <asm/traps.h>
57
58/* Tick Timer divider */
59#define JMR3927_TIMER_CCD 0 /* 1/2 */
60#define JMR3927_TIMER_CLK (JMR3927_IMCLK / (2 << JMR3927_TIMER_CCD))
61
62unsigned char led_state = 0xf;
63
64struct {
65 struct resource ram0;
66 struct resource ram1;
67 struct resource pcimem;
68 struct resource iob;
69 struct resource ioc;
70 struct resource pciio;
71 struct resource jmy1394;
72 struct resource rom1;
73 struct resource rom0;
74 struct resource sio0;
75 struct resource sio1;
76} jmr3927_resources = {
77 { "RAM0", 0, 0x01FFFFFF, IORESOURCE_MEM },
78 { "RAM1", 0x02000000, 0x03FFFFFF, IORESOURCE_MEM },
79 { "PCIMEM", 0x08000000, 0x07FFFFFF, IORESOURCE_MEM },
80 { "IOB", 0x10000000, 0x13FFFFFF },
81 { "IOC", 0x14000000, 0x14FFFFFF },
82 { "PCIIO", 0x15000000, 0x15FFFFFF },
83 { "JMY1394", 0x1D000000, 0x1D3FFFFF },
84 { "ROM1", 0x1E000000, 0x1E3FFFFF },
85 { "ROM0", 0x1FC00000, 0x1FFFFFFF },
86 { "SIO0", 0xFFFEF300, 0xFFFEF3FF },
87 { "SIO1", 0xFFFEF400, 0xFFFEF4FF },
88};
89
90/* don't enable - see errata */
91int jmr3927_ccfg_toeon = 0;
92
93static inline void do_reset(void)
94{
95#ifdef CONFIG_TC35815
96 extern void tc35815_killall(void);
97 tc35815_killall();
98#endif
99#if 1 /* Resetting PCI bus */
100 jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
101 jmr3927_ioc_reg_out(JMR3927_IOC_RESET_PCI, JMR3927_IOC_RESET_ADDR);
102 (void)jmr3927_ioc_reg_in(JMR3927_IOC_RESET_ADDR); /* flush WB */
103 mdelay(1);
104 jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
105#endif
106 jmr3927_ioc_reg_out(JMR3927_IOC_RESET_CPU, JMR3927_IOC_RESET_ADDR);
107}
108
109static void jmr3927_machine_restart(char *command)
110{
111 local_irq_disable();
112 puts("Rebooting...");
113 do_reset();
114}
115
116static void jmr3927_machine_halt(void)
117{
118 puts("JMR-TX3927 halted.\n");
119 while (1);
120}
121
122static void jmr3927_machine_power_off(void)
123{
124 puts("JMR-TX3927 halted. Please turn off the power.\n");
125 while (1);
126}
127
128#define USE_RTC_DS1742
129#ifdef USE_RTC_DS1742
130extern void rtc_ds1742_init(unsigned long base);
131#endif
132static void __init jmr3927_time_init(void)
133{
134#ifdef USE_RTC_DS1742
135 if (jmr3927_have_nvram()) {
136 rtc_ds1742_init(JMR3927_IOC_NVRAMB_ADDR);
137 }
138#endif
139}
140
141unsigned long jmr3927_do_gettimeoffset(void);
142extern int setup_irq(unsigned int irq, struct irqaction *irqaction);
143
144static void __init jmr3927_timer_setup(struct irqaction *irq)
145{
146 do_gettimeoffset = jmr3927_do_gettimeoffset;
147
148 jmr3927_tmrptr->cpra = JMR3927_TIMER_CLK / HZ;
149 jmr3927_tmrptr->itmr = TXx927_TMTITMR_TIIE | TXx927_TMTITMR_TZCE;
150 jmr3927_tmrptr->ccdr = JMR3927_TIMER_CCD;
151 jmr3927_tmrptr->tcr =
152 TXx927_TMTCR_TCE | TXx927_TMTCR_CCDE | TXx927_TMTCR_TMODE_ITVL;
153
154 setup_irq(JMR3927_IRQ_TICK, irq);
155}
156
157#define USECS_PER_JIFFY (1000000/HZ)
158
159unsigned long jmr3927_do_gettimeoffset(void)
160{
161 unsigned long count;
162 unsigned long res = 0;
163
164 /* MUST read TRR before TISR. */
165 count = jmr3927_tmrptr->trr;
166
167 if (jmr3927_tmrptr->tisr & TXx927_TMTISR_TIIS) {
168 /* timer interrupt is pending. use Max value. */
169 res = USECS_PER_JIFFY - 1;
170 } else {
171 /* convert to usec */
172 /* res = count / (JMR3927_TIMER_CLK / 1000000); */
173 res = (count << 7) / ((JMR3927_TIMER_CLK << 7) / 1000000);
174
175 /*
176 * Due to possible jiffies inconsistencies, we need to check
177 * the result so that we'll get a timer that is monotonic.
178 */
179 if (res >= USECS_PER_JIFFY)
180 res = USECS_PER_JIFFY-1;
181 }
182
183 return res;
184}
185
186
187//#undef DO_WRITE_THROUGH
188#define DO_WRITE_THROUGH
189#define DO_ENABLE_CACHE
190
191extern char * __init prom_getcmdline(void);
192static void jmr3927_board_init(void);
193extern struct resource pci_io_resource;
194extern struct resource pci_mem_resource;
195
196static void __init jmr3927_setup(void)
197{
198 char *argptr;
199
200 set_io_port_base(JMR3927_PORT_BASE + JMR3927_PCIIO);
201
202 board_time_init = jmr3927_time_init;
203 board_timer_setup = jmr3927_timer_setup;
204
205 _machine_restart = jmr3927_machine_restart;
206 _machine_halt = jmr3927_machine_halt;
207 _machine_power_off = jmr3927_machine_power_off;
208
209 /*
210 * IO/MEM resources.
211 */
212 ioport_resource.start = pci_io_resource.start;
213 ioport_resource.end = pci_io_resource.end;
214 iomem_resource.start = pci_mem_resource.start;
215 iomem_resource.end = pci_mem_resource.end;
216
217 /* Reboot on panic */
218 panic_timeout = 180;
219
220 {
221 unsigned int conf;
222 conf = read_c0_conf();
223 }
224
225#if 1
226 /* cache setup */
227 {
228 unsigned int conf;
229#ifdef DO_ENABLE_CACHE
230 int mips_ic_disable = 0, mips_dc_disable = 0;
231#else
232 int mips_ic_disable = 1, mips_dc_disable = 1;
233#endif
234#ifdef DO_WRITE_THROUGH
235 int mips_config_cwfon = 0;
236 int mips_config_wbon = 0;
237#else
238 int mips_config_cwfon = 1;
239 int mips_config_wbon = 1;
240#endif
241
242 conf = read_c0_conf();
243 conf &= ~(TX39_CONF_ICE | TX39_CONF_DCE | TX39_CONF_WBON | TX39_CONF_CWFON);
244 conf |= mips_ic_disable ? 0 : TX39_CONF_ICE;
245 conf |= mips_dc_disable ? 0 : TX39_CONF_DCE;
246 conf |= mips_config_wbon ? TX39_CONF_WBON : 0;
247 conf |= mips_config_cwfon ? TX39_CONF_CWFON : 0;
248
249 write_c0_conf(conf);
250 write_c0_cache(0);
251 }
252#endif
253
254 /* initialize board */
255 jmr3927_board_init();
256
257 argptr = prom_getcmdline();
258
259 if ((argptr = strstr(argptr, "toeon")) != NULL) {
260 jmr3927_ccfg_toeon = 1;
261 }
262 argptr = prom_getcmdline();
263 if ((argptr = strstr(argptr, "ip=")) == NULL) {
264 argptr = prom_getcmdline();
265 strcat(argptr, " ip=bootp");
266 }
267
268#ifdef CONFIG_TXX927_SERIAL_CONSOLE
269 argptr = prom_getcmdline();
270 if ((argptr = strstr(argptr, "console=")) == NULL) {
271 argptr = prom_getcmdline();
272 strcat(argptr, " console=ttyS1,115200");
273 }
274#endif
275}
276
277early_initcall(jmr3927_setup);
278
279
280static void tx3927_setup(void);
281
282#ifdef CONFIG_PCI
283unsigned long mips_pci_io_base;
284unsigned long mips_pci_io_size;
285unsigned long mips_pci_mem_base;
286unsigned long mips_pci_mem_size;
287/* for legacy I/O, PCI I/O PCI Bus address must be 0 */
288unsigned long mips_pci_io_pciaddr = 0;
289#endif
290
291static void __init jmr3927_board_init(void)
292{
293 char *argptr;
294
295#ifdef CONFIG_PCI
296 mips_pci_io_base = JMR3927_PCIIO;
297 mips_pci_io_size = JMR3927_PCIIO_SIZE;
298 mips_pci_mem_base = JMR3927_PCIMEM;
299 mips_pci_mem_size = JMR3927_PCIMEM_SIZE;
300#endif
301
302 tx3927_setup();
303
304 if (jmr3927_have_isac()) {
305
306#ifdef CONFIG_FB_E1355
307 argptr = prom_getcmdline();
308 if ((argptr = strstr(argptr, "video=")) == NULL) {
309 argptr = prom_getcmdline();
310 strcat(argptr, " video=e1355fb:crt16h");
311 }
312#endif
313
314#ifdef CONFIG_BLK_DEV_IDE
315 /* overrides PCI-IDE */
316#endif
317 }
318
319 /* SIO0 DTR on */
320 jmr3927_ioc_reg_out(0, JMR3927_IOC_DTR_ADDR);
321
322 jmr3927_led_set(0);
323
324
325 if (jmr3927_have_isac())
326 jmr3927_io_led_set(0);
327 printk("JMR-TX3927 (Rev %d) --- IOC(Rev %d) DIPSW:%d,%d,%d,%d\n",
328 jmr3927_ioc_reg_in(JMR3927_IOC_BREV_ADDR) & JMR3927_REV_MASK,
329 jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR) & JMR3927_REV_MASK,
330 jmr3927_dipsw1(), jmr3927_dipsw2(),
331 jmr3927_dipsw3(), jmr3927_dipsw4());
332 if (jmr3927_have_isac())
333 printk("JMI-3927IO2 --- ISAC(Rev %d) DIPSW:%01x\n",
334 jmr3927_isac_reg_in(JMR3927_ISAC_REV_ADDR) & JMR3927_REV_MASK,
335 jmr3927_io_dipsw());
336}
337
338static void __init tx3927_setup(void)
339{
340 int i;
341
342 /* SDRAMC are configured by PROM */
343
344 /* ROMC */
345 tx3927_romcptr->cr[1] = JMR3927_ROMCE1 | 0x00030048;
346 tx3927_romcptr->cr[2] = JMR3927_ROMCE2 | 0x000064c8;
347 tx3927_romcptr->cr[3] = JMR3927_ROMCE3 | 0x0003f698;
348 tx3927_romcptr->cr[5] = JMR3927_ROMCE5 | 0x0000f218;
349
350 /* CCFG */
351 /* enable Timeout BusError */
352 if (jmr3927_ccfg_toeon)
353 tx3927_ccfgptr->ccfg |= TX3927_CCFG_TOE;
354
355 /* clear BusErrorOnWrite flag */
356 tx3927_ccfgptr->ccfg &= ~TX3927_CCFG_BEOW;
357 /* Disable PCI snoop */
358 tx3927_ccfgptr->ccfg &= ~TX3927_CCFG_PSNP;
359
360#ifdef DO_WRITE_THROUGH
361 /* Enable PCI SNOOP - with write through only */
362 tx3927_ccfgptr->ccfg |= TX3927_CCFG_PSNP;
363#endif
364
365 /* Pin selection */
366 tx3927_ccfgptr->pcfg &= ~TX3927_PCFG_SELALL;
367 tx3927_ccfgptr->pcfg |=
368 TX3927_PCFG_SELSIOC(0) | TX3927_PCFG_SELSIO_ALL |
369 (TX3927_PCFG_SELDMA_ALL & ~TX3927_PCFG_SELDMA(1));
370
371 printk("TX3927 -- CRIR:%08lx CCFG:%08lx PCFG:%08lx\n",
372 tx3927_ccfgptr->crir,
373 tx3927_ccfgptr->ccfg, tx3927_ccfgptr->pcfg);
374
375 /* IRC */
376 /* disable interrupt control */
377 tx3927_ircptr->cer = 0;
378 /* mask all IRC interrupts */
379 tx3927_ircptr->imr = 0;
380 for (i = 0; i < TX3927_NUM_IR / 2; i++) {
381 tx3927_ircptr->ilr[i] = 0;
382 }
383 /* setup IRC interrupt mode (Low Active) */
384 for (i = 0; i < TX3927_NUM_IR / 8; i++) {
385 tx3927_ircptr->cr[i] = 0;
386 }
387
388 /* TMR */
389 /* disable all timers */
390 for (i = 0; i < TX3927_NR_TMR; i++) {
391 tx3927_tmrptr(i)->tcr = TXx927_TMTCR_CRE;
392 tx3927_tmrptr(i)->tisr = 0;
393 tx3927_tmrptr(i)->cpra = 0xffffffff;
394 tx3927_tmrptr(i)->itmr = 0;
395 tx3927_tmrptr(i)->ccdr = 0;
396 tx3927_tmrptr(i)->pgmr = 0;
397 }
398
399 /* DMA */
400 tx3927_dmaptr->mcr = 0;
401 for (i = 0; i < sizeof(tx3927_dmaptr->ch) / sizeof(tx3927_dmaptr->ch[0]); i++) {
402 /* reset channel */
403 tx3927_dmaptr->ch[i].ccr = TX3927_DMA_CCR_CHRST;
404 tx3927_dmaptr->ch[i].ccr = 0;
405 }
406 /* enable DMA */
407#ifdef __BIG_ENDIAN
408 tx3927_dmaptr->mcr = TX3927_DMA_MCR_MSTEN;
409#else
410 tx3927_dmaptr->mcr = TX3927_DMA_MCR_MSTEN | TX3927_DMA_MCR_LE;
411#endif
412
413#ifdef CONFIG_PCI
414 /* PCIC */
415 printk("TX3927 PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:",
416 tx3927_pcicptr->did, tx3927_pcicptr->vid,
417 tx3927_pcicptr->rid);
418 if (!(tx3927_ccfgptr->ccfg & TX3927_CCFG_PCIXARB)) {
419 printk("External\n");
420 /* XXX */
421 } else {
422 printk("Internal\n");
423
424 /* Reset PCI Bus */
425 jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
426 udelay(100);
427 jmr3927_ioc_reg_out(JMR3927_IOC_RESET_PCI,
428 JMR3927_IOC_RESET_ADDR);
429 udelay(100);
430 jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
431
432
433 /* Disable External PCI Config. Access */
434 tx3927_pcicptr->lbc = TX3927_PCIC_LBC_EPCAD;
435#ifdef __BIG_ENDIAN
436 tx3927_pcicptr->lbc |= TX3927_PCIC_LBC_IBSE |
437 TX3927_PCIC_LBC_TIBSE |
438 TX3927_PCIC_LBC_TMFBSE | TX3927_PCIC_LBC_MSDSE;
439#endif
440 /* LB->PCI mappings */
441 tx3927_pcicptr->iomas = ~(mips_pci_io_size - 1);
442 tx3927_pcicptr->ilbioma = mips_pci_io_base;
443 tx3927_pcicptr->ipbioma = mips_pci_io_pciaddr;
444 tx3927_pcicptr->mmas = ~(mips_pci_mem_size - 1);
445 tx3927_pcicptr->ilbmma = mips_pci_mem_base;
446 tx3927_pcicptr->ipbmma = mips_pci_mem_base;
447 /* PCI->LB mappings */
448 tx3927_pcicptr->iobas = 0xffffffff;
449 tx3927_pcicptr->ioba = 0;
450 tx3927_pcicptr->tlbioma = 0;
451 tx3927_pcicptr->mbas = ~(mips_pci_mem_size - 1);
452 tx3927_pcicptr->mba = 0;
453 tx3927_pcicptr->tlbmma = 0;
454#ifndef JMR3927_INIT_INDIRECT_PCI
455 /* Enable Direct mapping Address Space Decoder */
456 tx3927_pcicptr->lbc |= TX3927_PCIC_LBC_ILMDE | TX3927_PCIC_LBC_ILIDE;
457#endif
458
459 /* Clear All Local Bus Status */
460 tx3927_pcicptr->lbstat = TX3927_PCIC_LBIM_ALL;
461 /* Enable All Local Bus Interrupts */
462 tx3927_pcicptr->lbim = TX3927_PCIC_LBIM_ALL;
463 /* Clear All PCI Status Error */
464 tx3927_pcicptr->pcistat = TX3927_PCIC_PCISTATIM_ALL;
465 /* Enable All PCI Status Error Interrupts */
466 tx3927_pcicptr->pcistatim = TX3927_PCIC_PCISTATIM_ALL;
467
468 /* PCIC Int => IRC IRQ10 */
469 tx3927_pcicptr->il = TX3927_IR_PCI;
470#if 1
471 /* Target Control (per errata) */
472 tx3927_pcicptr->tc = TX3927_PCIC_TC_OF8E | TX3927_PCIC_TC_IF8E;
473#endif
474
475 /* Enable Bus Arbiter */
476#if 0
477 tx3927_pcicptr->req_trace = 0x73737373;
478#endif
479 tx3927_pcicptr->pbapmc = TX3927_PCIC_PBAPMC_PBAEN;
480
481 tx3927_pcicptr->pcicmd = PCI_COMMAND_MASTER |
482 PCI_COMMAND_MEMORY |
483#if 1
484 PCI_COMMAND_IO |
485#endif
486 PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
487 }
488#endif /* CONFIG_PCI */
489
490 /* PIO */
491 /* PIO[15:12] connected to LEDs */
492 tx3927_pioptr->dir = 0x0000f000;
493 tx3927_pioptr->maskcpu = 0;
494 tx3927_pioptr->maskext = 0;
495 {
496 unsigned int conf;
497
498 conf = read_c0_conf();
499 if (!(conf & TX39_CONF_ICE))
500 printk("TX3927 I-Cache disabled.\n");
501 if (!(conf & TX39_CONF_DCE))
502 printk("TX3927 D-Cache disabled.\n");
503 else if (!(conf & TX39_CONF_WBON))
504 printk("TX3927 D-Cache WriteThrough.\n");
505 else if (!(conf & TX39_CONF_CWFON))
506 printk("TX3927 D-Cache WriteBack.\n");
507 else
508 printk("TX3927 D-Cache WriteBack (CWF) .\n");
509 }
510}
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