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-rw-r--r--arch/mips/jmr3927/rbhma3100/Makefile2
-rw-r--r--arch/mips/jmr3927/rbhma3100/int-handler.S74
-rw-r--r--arch/mips/jmr3927/rbhma3100/irq.c6
3 files changed, 2 insertions, 80 deletions
diff --git a/arch/mips/jmr3927/rbhma3100/Makefile b/arch/mips/jmr3927/rbhma3100/Makefile
index 75bf418b94c0..baf5077813c1 100644
--- a/arch/mips/jmr3927/rbhma3100/Makefile
+++ b/arch/mips/jmr3927/rbhma3100/Makefile
@@ -2,7 +2,7 @@
2# Makefile for TOSHIBA JMR-TX3927 board 2# Makefile for TOSHIBA JMR-TX3927 board
3# 3#
4 4
5obj-y += init.o int-handler.o irq.o setup.o 5obj-y += init.o irq.o setup.o
6obj-$(CONFIG_RUNTIME_DEBUG) += debug.o 6obj-$(CONFIG_RUNTIME_DEBUG) += debug.o
7obj-$(CONFIG_KGDB) += kgdb_io.o 7obj-$(CONFIG_KGDB) += kgdb_io.o
8 8
diff --git a/arch/mips/jmr3927/rbhma3100/int-handler.S b/arch/mips/jmr3927/rbhma3100/int-handler.S
deleted file mode 100644
index f85bbf407542..000000000000
--- a/arch/mips/jmr3927/rbhma3100/int-handler.S
+++ /dev/null
@@ -1,74 +0,0 @@
1/*
2 * Copyright 2001 MontaVista Software Inc.
3 * Author: MontaVista Software, Inc.
4 * ahennessy@mvista.com
5 *
6 * Based on arch/mips/tsdb/kernel/int-handler.S
7 *
8 * Copyright (C) 2000-2001 Toshiba Corporation
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
17 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
21 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
22 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * You should have received a copy of the GNU General Public License along
27 * with this program; if not, write to the Free Software Foundation, Inc.,
28 * 675 Mass Ave, Cambridge, MA 02139, USA.
29 */
30
31#include <asm/asm.h>
32#include <asm/mipsregs.h>
33#include <asm/regdef.h>
34#include <asm/stackframe.h>
35#include <asm/jmr3927/jmr3927.h>
36
37 /* A lot of complication here is taken away because:
38 *
39 * 1) We handle one interrupt and return, sitting in a loop
40 * and moving across all the pending IRQ bits in the cause
41 * register is _NOT_ the answer, the common case is one
42 * pending IRQ so optimize in that direction.
43 *
44 * 2) We need not check against bits in the status register
45 * IRQ mask, that would make this routine slow as hell.
46 *
47 * 3) Linux only thinks in terms of all IRQs on or all IRQs
48 * off, nothing in between like BSD spl() brain-damage.
49 *
50 */
51
52/* Flush write buffer (needed?)
53 * NOTE: TX39xx performs "non-blocking load", so explicitly use the target
54 * register of LBU to flush immediately.
55 */
56#define FLUSH_WB(tmp) \
57 la tmp, JMR3927_IOC_REV_ADDR; \
58 lbu tmp, (tmp); \
59 move tmp, zero;
60
61 .text
62 .set noreorder
63 .set noat
64 .align 5
65 NESTED(jmr3927_IRQ, PT_SIZE, sp)
66 SAVE_ALL
67 CLI
68 .set at
69 jal jmr3927_irc_irqdispatch
70 move a0, sp
71 FLUSH_WB(t0)
72 j ret_from_irq
73 nop
74 END(jmr3927_IRQ)
diff --git a/arch/mips/jmr3927/rbhma3100/irq.c b/arch/mips/jmr3927/rbhma3100/irq.c
index 2810727f1d4e..11304d1354f4 100644
--- a/arch/mips/jmr3927/rbhma3100/irq.c
+++ b/arch/mips/jmr3927/rbhma3100/irq.c
@@ -77,8 +77,6 @@ static int jmr3927_gen_iack(void)
77} 77}
78#endif 78#endif
79 79
80extern asmlinkage void jmr3927_IRQ(void);
81
82#define irc_dlevel 0 80#define irc_dlevel 0
83#define irc_elevel 1 81#define irc_elevel 1
84 82
@@ -262,7 +260,7 @@ void jmr3927_spurious(struct pt_regs *regs)
262 regs->cp0_cause, regs->cp0_epc, regs->regs[31]); 260 regs->cp0_cause, regs->cp0_epc, regs->regs[31]);
263} 261}
264 262
265void jmr3927_irc_irqdispatch(struct pt_regs *regs) 263asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
266{ 264{
267 int irq; 265 int irq;
268 266
@@ -398,8 +396,6 @@ void __init arch_init_irq(void)
398 396
399 jmr3927_irq_init(NR_ISA_IRQS); 397 jmr3927_irq_init(NR_ISA_IRQS);
400 398
401 set_except_vector(0, jmr3927_IRQ);
402
403 /* setup irq space */ 399 /* setup irq space */
404 add_tb_irq_space(&jmr3927_isac_irqspace); 400 add_tb_irq_space(&jmr3927_isac_irqspace);
405 add_tb_irq_space(&jmr3927_ioc_irqspace); 401 add_tb_irq_space(&jmr3927_ioc_irqspace);