diff options
Diffstat (limited to 'arch/mips/jmr3927/rbhma3100/setup.c')
-rw-r--r-- | arch/mips/jmr3927/rbhma3100/setup.c | 157 |
1 files changed, 20 insertions, 137 deletions
diff --git a/arch/mips/jmr3927/rbhma3100/setup.c b/arch/mips/jmr3927/rbhma3100/setup.c index fc523bda068f..d1ef2895d564 100644 --- a/arch/mips/jmr3927/rbhma3100/setup.c +++ b/arch/mips/jmr3927/rbhma3100/setup.c | |||
@@ -54,87 +54,18 @@ | |||
54 | 54 | ||
55 | #include <asm/addrspace.h> | 55 | #include <asm/addrspace.h> |
56 | #include <asm/time.h> | 56 | #include <asm/time.h> |
57 | #include <asm/bcache.h> | ||
58 | #include <asm/irq.h> | ||
59 | #include <asm/reboot.h> | 57 | #include <asm/reboot.h> |
60 | #include <asm/gdb-stub.h> | ||
61 | #include <asm/jmr3927/jmr3927.h> | 58 | #include <asm/jmr3927/jmr3927.h> |
62 | #include <asm/mipsregs.h> | 59 | #include <asm/mipsregs.h> |
63 | #include <asm/traps.h> | ||
64 | 60 | ||
65 | extern void puts(unsigned char *cp); | 61 | extern void puts(const char *cp); |
66 | 62 | ||
67 | /* Tick Timer divider */ | 63 | /* Tick Timer divider */ |
68 | #define JMR3927_TIMER_CCD 0 /* 1/2 */ | 64 | #define JMR3927_TIMER_CCD 0 /* 1/2 */ |
69 | #define JMR3927_TIMER_CLK (JMR3927_IMCLK / (2 << JMR3927_TIMER_CCD)) | 65 | #define JMR3927_TIMER_CLK (JMR3927_IMCLK / (2 << JMR3927_TIMER_CCD)) |
70 | 66 | ||
71 | unsigned char led_state = 0xf; | ||
72 | |||
73 | struct { | ||
74 | struct resource ram0; | ||
75 | struct resource ram1; | ||
76 | struct resource pcimem; | ||
77 | struct resource iob; | ||
78 | struct resource ioc; | ||
79 | struct resource pciio; | ||
80 | struct resource jmy1394; | ||
81 | struct resource rom1; | ||
82 | struct resource rom0; | ||
83 | struct resource sio0; | ||
84 | struct resource sio1; | ||
85 | } jmr3927_resources = { | ||
86 | { | ||
87 | .start = 0, | ||
88 | .end = 0x01FFFFFF, | ||
89 | .name = "RAM0", | ||
90 | .flags = IORESOURCE_MEM | ||
91 | }, { | ||
92 | .start = 0x02000000, | ||
93 | .end = 0x03FFFFFF, | ||
94 | .name = "RAM1", | ||
95 | .flags = IORESOURCE_MEM | ||
96 | }, { | ||
97 | .start = 0x08000000, | ||
98 | .end = 0x07FFFFFF, | ||
99 | .name = "PCIMEM", | ||
100 | .flags = IORESOURCE_MEM | ||
101 | }, { | ||
102 | .start = 0x10000000, | ||
103 | .end = 0x13FFFFFF, | ||
104 | .name = "IOB" | ||
105 | }, { | ||
106 | .start = 0x14000000, | ||
107 | .end = 0x14FFFFFF, | ||
108 | .name = "IOC" | ||
109 | }, { | ||
110 | .start = 0x15000000, | ||
111 | .end = 0x15FFFFFF, | ||
112 | .name = "PCIIO" | ||
113 | }, { | ||
114 | .start = 0x1D000000, | ||
115 | .end = 0x1D3FFFFF, | ||
116 | .name = "JMY1394" | ||
117 | }, { | ||
118 | .start = 0x1E000000, | ||
119 | .end = 0x1E3FFFFF, | ||
120 | .name = "ROM1" | ||
121 | }, { | ||
122 | .start = 0x1FC00000, | ||
123 | .end = 0x1FFFFFFF, | ||
124 | .name = "ROM0" | ||
125 | }, { | ||
126 | .start = 0xFFFEF300, | ||
127 | .end = 0xFFFEF3FF, | ||
128 | .name = "SIO0" | ||
129 | }, { | ||
130 | .start = 0xFFFEF400, | ||
131 | .end = 0xFFFEF4FF, | ||
132 | .name = "SIO1" | ||
133 | }, | ||
134 | }; | ||
135 | |||
136 | /* don't enable - see errata */ | 67 | /* don't enable - see errata */ |
137 | int jmr3927_ccfg_toeon = 0; | 68 | static int jmr3927_ccfg_toeon; |
138 | 69 | ||
139 | static inline void do_reset(void) | 70 | static inline void do_reset(void) |
140 | { | 71 | { |
@@ -173,9 +104,15 @@ static cycle_t jmr3927_hpt_read(void) | |||
173 | return jiffies * (JMR3927_TIMER_CLK / HZ) + jmr3927_tmrptr->trr; | 104 | return jiffies * (JMR3927_TIMER_CLK / HZ) + jmr3927_tmrptr->trr; |
174 | } | 105 | } |
175 | 106 | ||
107 | static void jmr3927_timer_ack(void) | ||
108 | { | ||
109 | jmr3927_tmrptr->tisr = 0; /* ack interrupt */ | ||
110 | } | ||
111 | |||
176 | static void __init jmr3927_time_init(void) | 112 | static void __init jmr3927_time_init(void) |
177 | { | 113 | { |
178 | clocksource_mips.read = jmr3927_hpt_read; | 114 | clocksource_mips.read = jmr3927_hpt_read; |
115 | mips_timer_ack = jmr3927_timer_ack; | ||
179 | mips_hpt_frequency = JMR3927_TIMER_CLK; | 116 | mips_hpt_frequency = JMR3927_TIMER_CLK; |
180 | } | 117 | } |
181 | 118 | ||
@@ -190,9 +127,6 @@ void __init plat_timer_setup(struct irqaction *irq) | |||
190 | setup_irq(JMR3927_IRQ_TICK, irq); | 127 | setup_irq(JMR3927_IRQ_TICK, irq); |
191 | } | 128 | } |
192 | 129 | ||
193 | #define USECS_PER_JIFFY (1000000/HZ) | ||
194 | |||
195 | //#undef DO_WRITE_THROUGH | ||
196 | #define DO_WRITE_THROUGH | 130 | #define DO_WRITE_THROUGH |
197 | #define DO_ENABLE_CACHE | 131 | #define DO_ENABLE_CACHE |
198 | 132 | ||
@@ -224,12 +158,6 @@ void __init plat_mem_setup(void) | |||
224 | /* Reboot on panic */ | 158 | /* Reboot on panic */ |
225 | panic_timeout = 180; | 159 | panic_timeout = 180; |
226 | 160 | ||
227 | { | ||
228 | unsigned int conf; | ||
229 | conf = read_c0_conf(); | ||
230 | } | ||
231 | |||
232 | #if 1 | ||
233 | /* cache setup */ | 161 | /* cache setup */ |
234 | { | 162 | { |
235 | unsigned int conf; | 163 | unsigned int conf; |
@@ -256,16 +184,14 @@ void __init plat_mem_setup(void) | |||
256 | write_c0_conf(conf); | 184 | write_c0_conf(conf); |
257 | write_c0_cache(0); | 185 | write_c0_cache(0); |
258 | } | 186 | } |
259 | #endif | ||
260 | 187 | ||
261 | /* initialize board */ | 188 | /* initialize board */ |
262 | jmr3927_board_init(); | 189 | jmr3927_board_init(); |
263 | 190 | ||
264 | argptr = prom_getcmdline(); | 191 | argptr = prom_getcmdline(); |
265 | 192 | ||
266 | if ((argptr = strstr(argptr, "toeon")) != NULL) { | 193 | if ((argptr = strstr(argptr, "toeon")) != NULL) |
267 | jmr3927_ccfg_toeon = 1; | 194 | jmr3927_ccfg_toeon = 1; |
268 | } | ||
269 | argptr = prom_getcmdline(); | 195 | argptr = prom_getcmdline(); |
270 | if ((argptr = strstr(argptr, "ip=")) == NULL) { | 196 | if ((argptr = strstr(argptr, "ip=")) == NULL) { |
271 | argptr = prom_getcmdline(); | 197 | argptr = prom_getcmdline(); |
@@ -281,7 +207,7 @@ void __init plat_mem_setup(void) | |||
281 | memset(&req, 0, sizeof(req)); | 207 | memset(&req, 0, sizeof(req)); |
282 | req.line = i; | 208 | req.line = i; |
283 | req.iotype = UPIO_MEM; | 209 | req.iotype = UPIO_MEM; |
284 | req.membase = (char *)TX3927_SIO_REG(i); | 210 | req.membase = (unsigned char __iomem *)TX3927_SIO_REG(i); |
285 | req.mapbase = TX3927_SIO_REG(i); | 211 | req.mapbase = TX3927_SIO_REG(i); |
286 | req.irq = i == 0 ? | 212 | req.irq = i == 0 ? |
287 | JMR3927_IRQ_IRC_SIO0 : JMR3927_IRQ_IRC_SIO1; | 213 | JMR3927_IRQ_IRC_SIO0 : JMR3927_IRQ_IRC_SIO1; |
@@ -303,65 +229,33 @@ void __init plat_mem_setup(void) | |||
303 | 229 | ||
304 | static void tx3927_setup(void); | 230 | static void tx3927_setup(void); |
305 | 231 | ||
306 | #ifdef CONFIG_PCI | ||
307 | unsigned long mips_pci_io_base; | ||
308 | unsigned long mips_pci_io_size; | ||
309 | unsigned long mips_pci_mem_base; | ||
310 | unsigned long mips_pci_mem_size; | ||
311 | /* for legacy I/O, PCI I/O PCI Bus address must be 0 */ | ||
312 | unsigned long mips_pci_io_pciaddr = 0; | ||
313 | #endif | ||
314 | |||
315 | static void __init jmr3927_board_init(void) | 232 | static void __init jmr3927_board_init(void) |
316 | { | 233 | { |
317 | char *argptr; | ||
318 | |||
319 | #ifdef CONFIG_PCI | ||
320 | mips_pci_io_base = JMR3927_PCIIO; | ||
321 | mips_pci_io_size = JMR3927_PCIIO_SIZE; | ||
322 | mips_pci_mem_base = JMR3927_PCIMEM; | ||
323 | mips_pci_mem_size = JMR3927_PCIMEM_SIZE; | ||
324 | #endif | ||
325 | |||
326 | tx3927_setup(); | 234 | tx3927_setup(); |
327 | 235 | ||
328 | if (jmr3927_have_isac()) { | ||
329 | |||
330 | #ifdef CONFIG_FB_E1355 | ||
331 | argptr = prom_getcmdline(); | ||
332 | if ((argptr = strstr(argptr, "video=")) == NULL) { | ||
333 | argptr = prom_getcmdline(); | ||
334 | strcat(argptr, " video=e1355fb:crt16h"); | ||
335 | } | ||
336 | #endif | ||
337 | |||
338 | #ifdef CONFIG_BLK_DEV_IDE | ||
339 | /* overrides PCI-IDE */ | ||
340 | #endif | ||
341 | } | ||
342 | |||
343 | /* SIO0 DTR on */ | 236 | /* SIO0 DTR on */ |
344 | jmr3927_ioc_reg_out(0, JMR3927_IOC_DTR_ADDR); | 237 | jmr3927_ioc_reg_out(0, JMR3927_IOC_DTR_ADDR); |
345 | 238 | ||
346 | jmr3927_led_set(0); | 239 | jmr3927_led_set(0); |
347 | 240 | ||
348 | |||
349 | if (jmr3927_have_isac()) | ||
350 | jmr3927_io_led_set(0); | ||
351 | printk("JMR-TX3927 (Rev %d) --- IOC(Rev %d) DIPSW:%d,%d,%d,%d\n", | 241 | printk("JMR-TX3927 (Rev %d) --- IOC(Rev %d) DIPSW:%d,%d,%d,%d\n", |
352 | jmr3927_ioc_reg_in(JMR3927_IOC_BREV_ADDR) & JMR3927_REV_MASK, | 242 | jmr3927_ioc_reg_in(JMR3927_IOC_BREV_ADDR) & JMR3927_REV_MASK, |
353 | jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR) & JMR3927_REV_MASK, | 243 | jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR) & JMR3927_REV_MASK, |
354 | jmr3927_dipsw1(), jmr3927_dipsw2(), | 244 | jmr3927_dipsw1(), jmr3927_dipsw2(), |
355 | jmr3927_dipsw3(), jmr3927_dipsw4()); | 245 | jmr3927_dipsw3(), jmr3927_dipsw4()); |
356 | if (jmr3927_have_isac()) | ||
357 | printk("JMI-3927IO2 --- ISAC(Rev %d) DIPSW:%01x\n", | ||
358 | jmr3927_isac_reg_in(JMR3927_ISAC_REV_ADDR) & JMR3927_REV_MASK, | ||
359 | jmr3927_io_dipsw()); | ||
360 | } | 246 | } |
361 | 247 | ||
362 | void __init tx3927_setup(void) | 248 | static void __init tx3927_setup(void) |
363 | { | 249 | { |
364 | int i; | 250 | int i; |
251 | #ifdef CONFIG_PCI | ||
252 | unsigned long mips_pci_io_base = JMR3927_PCIIO; | ||
253 | unsigned long mips_pci_io_size = JMR3927_PCIIO_SIZE; | ||
254 | unsigned long mips_pci_mem_base = JMR3927_PCIMEM; | ||
255 | unsigned long mips_pci_mem_size = JMR3927_PCIMEM_SIZE; | ||
256 | /* for legacy I/O, PCI I/O PCI Bus address must be 0 */ | ||
257 | unsigned long mips_pci_io_pciaddr = 0; | ||
258 | #endif | ||
365 | 259 | ||
366 | /* SDRAMC are configured by PROM */ | 260 | /* SDRAMC are configured by PROM */ |
367 | 261 | ||
@@ -475,10 +369,8 @@ void __init tx3927_setup(void) | |||
475 | tx3927_pcicptr->mbas = ~(mips_pci_mem_size - 1); | 369 | tx3927_pcicptr->mbas = ~(mips_pci_mem_size - 1); |
476 | tx3927_pcicptr->mba = 0; | 370 | tx3927_pcicptr->mba = 0; |
477 | tx3927_pcicptr->tlbmma = 0; | 371 | tx3927_pcicptr->tlbmma = 0; |
478 | #ifndef JMR3927_INIT_INDIRECT_PCI | ||
479 | /* Enable Direct mapping Address Space Decoder */ | 372 | /* Enable Direct mapping Address Space Decoder */ |
480 | tx3927_pcicptr->lbc |= TX3927_PCIC_LBC_ILMDE | TX3927_PCIC_LBC_ILIDE; | 373 | tx3927_pcicptr->lbc |= TX3927_PCIC_LBC_ILMDE | TX3927_PCIC_LBC_ILIDE; |
481 | #endif | ||
482 | 374 | ||
483 | /* Clear All Local Bus Status */ | 375 | /* Clear All Local Bus Status */ |
484 | tx3927_pcicptr->lbstat = TX3927_PCIC_LBIM_ALL; | 376 | tx3927_pcicptr->lbstat = TX3927_PCIC_LBIM_ALL; |
@@ -491,22 +383,15 @@ void __init tx3927_setup(void) | |||
491 | 383 | ||
492 | /* PCIC Int => IRC IRQ10 */ | 384 | /* PCIC Int => IRC IRQ10 */ |
493 | tx3927_pcicptr->il = TX3927_IR_PCI; | 385 | tx3927_pcicptr->il = TX3927_IR_PCI; |
494 | #if 1 | ||
495 | /* Target Control (per errata) */ | 386 | /* Target Control (per errata) */ |
496 | tx3927_pcicptr->tc = TX3927_PCIC_TC_OF8E | TX3927_PCIC_TC_IF8E; | 387 | tx3927_pcicptr->tc = TX3927_PCIC_TC_OF8E | TX3927_PCIC_TC_IF8E; |
497 | #endif | ||
498 | 388 | ||
499 | /* Enable Bus Arbiter */ | 389 | /* Enable Bus Arbiter */ |
500 | #if 0 | ||
501 | tx3927_pcicptr->req_trace = 0x73737373; | ||
502 | #endif | ||
503 | tx3927_pcicptr->pbapmc = TX3927_PCIC_PBAPMC_PBAEN; | 390 | tx3927_pcicptr->pbapmc = TX3927_PCIC_PBAPMC_PBAEN; |
504 | 391 | ||
505 | tx3927_pcicptr->pcicmd = PCI_COMMAND_MASTER | | 392 | tx3927_pcicptr->pcicmd = PCI_COMMAND_MASTER | |
506 | PCI_COMMAND_MEMORY | | 393 | PCI_COMMAND_MEMORY | |
507 | #if 1 | ||
508 | PCI_COMMAND_IO | | 394 | PCI_COMMAND_IO | |
509 | #endif | ||
510 | PCI_COMMAND_PARITY | PCI_COMMAND_SERR; | 395 | PCI_COMMAND_PARITY | PCI_COMMAND_SERR; |
511 | } | 396 | } |
512 | #endif /* CONFIG_PCI */ | 397 | #endif /* CONFIG_PCI */ |
@@ -555,8 +440,6 @@ static int __init jmr3927_rtc_init(void) | |||
555 | .flags = IORESOURCE_MEM, | 440 | .flags = IORESOURCE_MEM, |
556 | }; | 441 | }; |
557 | struct platform_device *dev; | 442 | struct platform_device *dev; |
558 | if (!jmr3927_have_nvram()) | ||
559 | return -ENODEV; | ||
560 | dev = platform_device_register_simple("ds1742", -1, &res, 1); | 443 | dev = platform_device_register_simple("ds1742", -1, &res, 1); |
561 | return IS_ERR(dev) ? PTR_ERR(dev) : 0; | 444 | return IS_ERR(dev) ? PTR_ERR(dev) : 0; |
562 | } | 445 | } |