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-rw-r--r--arch/mips/jmr3927/rbhma3100/setup.c196
1 files changed, 48 insertions, 148 deletions
diff --git a/arch/mips/jmr3927/rbhma3100/setup.c b/arch/mips/jmr3927/rbhma3100/setup.c
index 7ca3d6d07b34..d1ef2895d564 100644
--- a/arch/mips/jmr3927/rbhma3100/setup.c
+++ b/arch/mips/jmr3927/rbhma3100/setup.c
@@ -45,6 +45,7 @@
45#include <linux/param.h> /* for HZ */ 45#include <linux/param.h> /* for HZ */
46#include <linux/delay.h> 46#include <linux/delay.h>
47#include <linux/pm.h> 47#include <linux/pm.h>
48#include <linux/platform_device.h>
48#ifdef CONFIG_SERIAL_TXX9 49#ifdef CONFIG_SERIAL_TXX9
49#include <linux/tty.h> 50#include <linux/tty.h>
50#include <linux/serial.h> 51#include <linux/serial.h>
@@ -53,94 +54,21 @@
53 54
54#include <asm/addrspace.h> 55#include <asm/addrspace.h>
55#include <asm/time.h> 56#include <asm/time.h>
56#include <asm/bcache.h>
57#include <asm/irq.h>
58#include <asm/reboot.h> 57#include <asm/reboot.h>
59#include <asm/gdb-stub.h>
60#include <asm/jmr3927/jmr3927.h> 58#include <asm/jmr3927/jmr3927.h>
61#include <asm/mipsregs.h> 59#include <asm/mipsregs.h>
62#include <asm/traps.h>
63 60
64extern void puts(unsigned char *cp); 61extern void puts(const char *cp);
65 62
66/* Tick Timer divider */ 63/* Tick Timer divider */
67#define JMR3927_TIMER_CCD 0 /* 1/2 */ 64#define JMR3927_TIMER_CCD 0 /* 1/2 */
68#define JMR3927_TIMER_CLK (JMR3927_IMCLK / (2 << JMR3927_TIMER_CCD)) 65#define JMR3927_TIMER_CLK (JMR3927_IMCLK / (2 << JMR3927_TIMER_CCD))
69 66
70unsigned char led_state = 0xf;
71
72struct {
73 struct resource ram0;
74 struct resource ram1;
75 struct resource pcimem;
76 struct resource iob;
77 struct resource ioc;
78 struct resource pciio;
79 struct resource jmy1394;
80 struct resource rom1;
81 struct resource rom0;
82 struct resource sio0;
83 struct resource sio1;
84} jmr3927_resources = {
85 {
86 .start = 0,
87 .end = 0x01FFFFFF,
88 .name = "RAM0",
89 .flags = IORESOURCE_MEM
90 }, {
91 .start = 0x02000000,
92 .end = 0x03FFFFFF,
93 .name = "RAM1",
94 .flags = IORESOURCE_MEM
95 }, {
96 .start = 0x08000000,
97 .end = 0x07FFFFFF,
98 .name = "PCIMEM",
99 .flags = IORESOURCE_MEM
100 }, {
101 .start = 0x10000000,
102 .end = 0x13FFFFFF,
103 .name = "IOB"
104 }, {
105 .start = 0x14000000,
106 .end = 0x14FFFFFF,
107 .name = "IOC"
108 }, {
109 .start = 0x15000000,
110 .end = 0x15FFFFFF,
111 .name = "PCIIO"
112 }, {
113 .start = 0x1D000000,
114 .end = 0x1D3FFFFF,
115 .name = "JMY1394"
116 }, {
117 .start = 0x1E000000,
118 .end = 0x1E3FFFFF,
119 .name = "ROM1"
120 }, {
121 .start = 0x1FC00000,
122 .end = 0x1FFFFFFF,
123 .name = "ROM0"
124 }, {
125 .start = 0xFFFEF300,
126 .end = 0xFFFEF3FF,
127 .name = "SIO0"
128 }, {
129 .start = 0xFFFEF400,
130 .end = 0xFFFEF4FF,
131 .name = "SIO1"
132 },
133};
134
135/* don't enable - see errata */ 67/* don't enable - see errata */
136int jmr3927_ccfg_toeon = 0; 68static int jmr3927_ccfg_toeon;
137 69
138static inline void do_reset(void) 70static inline void do_reset(void)
139{ 71{
140#ifdef CONFIG_TC35815
141 extern void tc35815_killall(void);
142 tc35815_killall();
143#endif
144#if 1 /* Resetting PCI bus */ 72#if 1 /* Resetting PCI bus */
145 jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR); 73 jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
146 jmr3927_ioc_reg_out(JMR3927_IOC_RESET_PCI, JMR3927_IOC_RESET_ADDR); 74 jmr3927_ioc_reg_out(JMR3927_IOC_RESET_PCI, JMR3927_IOC_RESET_ADDR);
@@ -176,19 +104,16 @@ static cycle_t jmr3927_hpt_read(void)
176 return jiffies * (JMR3927_TIMER_CLK / HZ) + jmr3927_tmrptr->trr; 104 return jiffies * (JMR3927_TIMER_CLK / HZ) + jmr3927_tmrptr->trr;
177} 105}
178 106
179#define USE_RTC_DS1742 107static void jmr3927_timer_ack(void)
180#ifdef USE_RTC_DS1742 108{
181extern void rtc_ds1742_init(unsigned long base); 109 jmr3927_tmrptr->tisr = 0; /* ack interrupt */
182#endif 110}
111
183static void __init jmr3927_time_init(void) 112static void __init jmr3927_time_init(void)
184{ 113{
185 clocksource_mips.read = jmr3927_hpt_read; 114 clocksource_mips.read = jmr3927_hpt_read;
115 mips_timer_ack = jmr3927_timer_ack;
186 mips_hpt_frequency = JMR3927_TIMER_CLK; 116 mips_hpt_frequency = JMR3927_TIMER_CLK;
187#ifdef USE_RTC_DS1742
188 if (jmr3927_have_nvram()) {
189 rtc_ds1742_init(JMR3927_IOC_NVRAMB_ADDR);
190 }
191#endif
192} 117}
193 118
194void __init plat_timer_setup(struct irqaction *irq) 119void __init plat_timer_setup(struct irqaction *irq)
@@ -202,9 +127,6 @@ void __init plat_timer_setup(struct irqaction *irq)
202 setup_irq(JMR3927_IRQ_TICK, irq); 127 setup_irq(JMR3927_IRQ_TICK, irq);
203} 128}
204 129
205#define USECS_PER_JIFFY (1000000/HZ)
206
207//#undef DO_WRITE_THROUGH
208#define DO_WRITE_THROUGH 130#define DO_WRITE_THROUGH
209#define DO_ENABLE_CACHE 131#define DO_ENABLE_CACHE
210 132
@@ -236,12 +158,6 @@ void __init plat_mem_setup(void)
236 /* Reboot on panic */ 158 /* Reboot on panic */
237 panic_timeout = 180; 159 panic_timeout = 180;
238 160
239 {
240 unsigned int conf;
241 conf = read_c0_conf();
242 }
243
244#if 1
245 /* cache setup */ 161 /* cache setup */
246 { 162 {
247 unsigned int conf; 163 unsigned int conf;
@@ -268,16 +184,14 @@ void __init plat_mem_setup(void)
268 write_c0_conf(conf); 184 write_c0_conf(conf);
269 write_c0_cache(0); 185 write_c0_cache(0);
270 } 186 }
271#endif
272 187
273 /* initialize board */ 188 /* initialize board */
274 jmr3927_board_init(); 189 jmr3927_board_init();
275 190
276 argptr = prom_getcmdline(); 191 argptr = prom_getcmdline();
277 192
278 if ((argptr = strstr(argptr, "toeon")) != NULL) { 193 if ((argptr = strstr(argptr, "toeon")) != NULL)
279 jmr3927_ccfg_toeon = 1; 194 jmr3927_ccfg_toeon = 1;
280 }
281 argptr = prom_getcmdline(); 195 argptr = prom_getcmdline();
282 if ((argptr = strstr(argptr, "ip=")) == NULL) { 196 if ((argptr = strstr(argptr, "ip=")) == NULL) {
283 argptr = prom_getcmdline(); 197 argptr = prom_getcmdline();
@@ -293,7 +207,7 @@ void __init plat_mem_setup(void)
293 memset(&req, 0, sizeof(req)); 207 memset(&req, 0, sizeof(req));
294 req.line = i; 208 req.line = i;
295 req.iotype = UPIO_MEM; 209 req.iotype = UPIO_MEM;
296 req.membase = (char *)TX3927_SIO_REG(i); 210 req.membase = (unsigned char __iomem *)TX3927_SIO_REG(i);
297 req.mapbase = TX3927_SIO_REG(i); 211 req.mapbase = TX3927_SIO_REG(i);
298 req.irq = i == 0 ? 212 req.irq = i == 0 ?
299 JMR3927_IRQ_IRC_SIO0 : JMR3927_IRQ_IRC_SIO1; 213 JMR3927_IRQ_IRC_SIO0 : JMR3927_IRQ_IRC_SIO1;
@@ -315,65 +229,33 @@ void __init plat_mem_setup(void)
315 229
316static void tx3927_setup(void); 230static void tx3927_setup(void);
317 231
318#ifdef CONFIG_PCI
319unsigned long mips_pci_io_base;
320unsigned long mips_pci_io_size;
321unsigned long mips_pci_mem_base;
322unsigned long mips_pci_mem_size;
323/* for legacy I/O, PCI I/O PCI Bus address must be 0 */
324unsigned long mips_pci_io_pciaddr = 0;
325#endif
326
327static void __init jmr3927_board_init(void) 232static void __init jmr3927_board_init(void)
328{ 233{
329 char *argptr;
330
331#ifdef CONFIG_PCI
332 mips_pci_io_base = JMR3927_PCIIO;
333 mips_pci_io_size = JMR3927_PCIIO_SIZE;
334 mips_pci_mem_base = JMR3927_PCIMEM;
335 mips_pci_mem_size = JMR3927_PCIMEM_SIZE;
336#endif
337
338 tx3927_setup(); 234 tx3927_setup();
339 235
340 if (jmr3927_have_isac()) {
341
342#ifdef CONFIG_FB_E1355
343 argptr = prom_getcmdline();
344 if ((argptr = strstr(argptr, "video=")) == NULL) {
345 argptr = prom_getcmdline();
346 strcat(argptr, " video=e1355fb:crt16h");
347 }
348#endif
349
350#ifdef CONFIG_BLK_DEV_IDE
351 /* overrides PCI-IDE */
352#endif
353 }
354
355 /* SIO0 DTR on */ 236 /* SIO0 DTR on */
356 jmr3927_ioc_reg_out(0, JMR3927_IOC_DTR_ADDR); 237 jmr3927_ioc_reg_out(0, JMR3927_IOC_DTR_ADDR);
357 238
358 jmr3927_led_set(0); 239 jmr3927_led_set(0);
359 240
360
361 if (jmr3927_have_isac())
362 jmr3927_io_led_set(0);
363 printk("JMR-TX3927 (Rev %d) --- IOC(Rev %d) DIPSW:%d,%d,%d,%d\n", 241 printk("JMR-TX3927 (Rev %d) --- IOC(Rev %d) DIPSW:%d,%d,%d,%d\n",
364 jmr3927_ioc_reg_in(JMR3927_IOC_BREV_ADDR) & JMR3927_REV_MASK, 242 jmr3927_ioc_reg_in(JMR3927_IOC_BREV_ADDR) & JMR3927_REV_MASK,
365 jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR) & JMR3927_REV_MASK, 243 jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR) & JMR3927_REV_MASK,
366 jmr3927_dipsw1(), jmr3927_dipsw2(), 244 jmr3927_dipsw1(), jmr3927_dipsw2(),
367 jmr3927_dipsw3(), jmr3927_dipsw4()); 245 jmr3927_dipsw3(), jmr3927_dipsw4());
368 if (jmr3927_have_isac())
369 printk("JMI-3927IO2 --- ISAC(Rev %d) DIPSW:%01x\n",
370 jmr3927_isac_reg_in(JMR3927_ISAC_REV_ADDR) & JMR3927_REV_MASK,
371 jmr3927_io_dipsw());
372} 246}
373 247
374void __init tx3927_setup(void) 248static void __init tx3927_setup(void)
375{ 249{
376 int i; 250 int i;
251#ifdef CONFIG_PCI
252 unsigned long mips_pci_io_base = JMR3927_PCIIO;
253 unsigned long mips_pci_io_size = JMR3927_PCIIO_SIZE;
254 unsigned long mips_pci_mem_base = JMR3927_PCIMEM;
255 unsigned long mips_pci_mem_size = JMR3927_PCIMEM_SIZE;
256 /* for legacy I/O, PCI I/O PCI Bus address must be 0 */
257 unsigned long mips_pci_io_pciaddr = 0;
258#endif
377 259
378 /* SDRAMC are configured by PROM */ 260 /* SDRAMC are configured by PROM */
379 261
@@ -487,10 +369,8 @@ void __init tx3927_setup(void)
487 tx3927_pcicptr->mbas = ~(mips_pci_mem_size - 1); 369 tx3927_pcicptr->mbas = ~(mips_pci_mem_size - 1);
488 tx3927_pcicptr->mba = 0; 370 tx3927_pcicptr->mba = 0;
489 tx3927_pcicptr->tlbmma = 0; 371 tx3927_pcicptr->tlbmma = 0;
490#ifndef JMR3927_INIT_INDIRECT_PCI
491 /* Enable Direct mapping Address Space Decoder */ 372 /* Enable Direct mapping Address Space Decoder */
492 tx3927_pcicptr->lbc |= TX3927_PCIC_LBC_ILMDE | TX3927_PCIC_LBC_ILIDE; 373 tx3927_pcicptr->lbc |= TX3927_PCIC_LBC_ILMDE | TX3927_PCIC_LBC_ILIDE;
493#endif
494 374
495 /* Clear All Local Bus Status */ 375 /* Clear All Local Bus Status */
496 tx3927_pcicptr->lbstat = TX3927_PCIC_LBIM_ALL; 376 tx3927_pcicptr->lbstat = TX3927_PCIC_LBIM_ALL;
@@ -503,22 +383,15 @@ void __init tx3927_setup(void)
503 383
504 /* PCIC Int => IRC IRQ10 */ 384 /* PCIC Int => IRC IRQ10 */
505 tx3927_pcicptr->il = TX3927_IR_PCI; 385 tx3927_pcicptr->il = TX3927_IR_PCI;
506#if 1
507 /* Target Control (per errata) */ 386 /* Target Control (per errata) */
508 tx3927_pcicptr->tc = TX3927_PCIC_TC_OF8E | TX3927_PCIC_TC_IF8E; 387 tx3927_pcicptr->tc = TX3927_PCIC_TC_OF8E | TX3927_PCIC_TC_IF8E;
509#endif
510 388
511 /* Enable Bus Arbiter */ 389 /* Enable Bus Arbiter */
512#if 0
513 tx3927_pcicptr->req_trace = 0x73737373;
514#endif
515 tx3927_pcicptr->pbapmc = TX3927_PCIC_PBAPMC_PBAEN; 390 tx3927_pcicptr->pbapmc = TX3927_PCIC_PBAPMC_PBAEN;
516 391
517 tx3927_pcicptr->pcicmd = PCI_COMMAND_MASTER | 392 tx3927_pcicptr->pcicmd = PCI_COMMAND_MASTER |
518 PCI_COMMAND_MEMORY | 393 PCI_COMMAND_MEMORY |
519#if 1
520 PCI_COMMAND_IO | 394 PCI_COMMAND_IO |
521#endif
522 PCI_COMMAND_PARITY | PCI_COMMAND_SERR; 395 PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
523 } 396 }
524#endif /* CONFIG_PCI */ 397#endif /* CONFIG_PCI */
@@ -544,3 +417,30 @@ void __init tx3927_setup(void)
544 printk("TX3927 D-Cache WriteBack (CWF) .\n"); 417 printk("TX3927 D-Cache WriteBack (CWF) .\n");
545 } 418 }
546} 419}
420
421/* This trick makes rtc-ds1742 driver usable as is. */
422unsigned long __swizzle_addr_b(unsigned long port)
423{
424 if ((port & 0xffff0000) != JMR3927_IOC_NVRAMB_ADDR)
425 return port;
426 port = (port & 0xffff0000) | (port & 0x7fff << 1);
427#ifdef __BIG_ENDIAN
428 return port;
429#else
430 return port | 1;
431#endif
432}
433EXPORT_SYMBOL(__swizzle_addr_b);
434
435static int __init jmr3927_rtc_init(void)
436{
437 struct resource res = {
438 .start = JMR3927_IOC_NVRAMB_ADDR - IO_BASE,
439 .end = JMR3927_IOC_NVRAMB_ADDR - IO_BASE + 0x800 - 1,
440 .flags = IORESOURCE_MEM,
441 };
442 struct platform_device *dev;
443 dev = platform_device_register_simple("ds1742", -1, &res, 1);
444 return IS_ERR(dev) ? PTR_ERR(dev) : 0;
445}
446device_initcall(jmr3927_rtc_init);