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Diffstat (limited to 'arch/mips/jmr3927/rbhma3100/irq.c')
-rw-r--r--arch/mips/jmr3927/rbhma3100/irq.c48
1 files changed, 3 insertions, 45 deletions
diff --git a/arch/mips/jmr3927/rbhma3100/irq.c b/arch/mips/jmr3927/rbhma3100/irq.c
index 1187b44a3dd4..d9efe692e551 100644
--- a/arch/mips/jmr3927/rbhma3100/irq.c
+++ b/arch/mips/jmr3927/rbhma3100/irq.c
@@ -45,9 +45,6 @@
45#error JMR3927_IRQ_END > NR_IRQS 45#error JMR3927_IRQ_END > NR_IRQS
46#endif 46#endif
47 47
48#define irc_dlevel 0
49#define irc_elevel 1
50
51static unsigned char irc_level[TX3927_NUM_IR] = { 48static unsigned char irc_level[TX3927_NUM_IR] = {
52 5, 5, 5, 5, 5, 5, /* INT[5:0] */ 49 5, 5, 5, 5, 5, 5, /* INT[5:0] */
53 7, 7, /* SIO */ 50 7, 7, /* SIO */
@@ -80,34 +77,6 @@ static void unmask_irq_ioc(unsigned int irq)
80 (void)jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR); 77 (void)jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR);
81} 78}
82 79
83static void mask_irq_irc(unsigned int irq)
84{
85 unsigned int irq_nr = irq - JMR3927_IRQ_IRC;
86 volatile unsigned long *ilrp = &tx3927_ircptr->ilr[irq_nr / 2];
87 if (irq_nr & 1)
88 *ilrp = (*ilrp & 0x00ff) | (irc_dlevel << 8);
89 else
90 *ilrp = (*ilrp & 0xff00) | irc_dlevel;
91 /* update IRCSR */
92 tx3927_ircptr->imr = 0;
93 tx3927_ircptr->imr = irc_elevel;
94 /* flush write buffer */
95 (void)tx3927_ircptr->ssr;
96}
97
98static void unmask_irq_irc(unsigned int irq)
99{
100 unsigned int irq_nr = irq - JMR3927_IRQ_IRC;
101 volatile unsigned long *ilrp = &tx3927_ircptr->ilr[irq_nr / 2];
102 if (irq_nr & 1)
103 *ilrp = (*ilrp & 0x00ff) | (irc_level[irq_nr] << 8);
104 else
105 *ilrp = (*ilrp & 0xff00) | irc_level[irq_nr];
106 /* update IRCSR */
107 tx3927_ircptr->imr = 0;
108 tx3927_ircptr->imr = irc_elevel;
109}
110
111asmlinkage void plat_irq_dispatch(void) 80asmlinkage void plat_irq_dispatch(void)
112{ 81{
113 unsigned long cp0_cause = read_c0_cause(); 82 unsigned long cp0_cause = read_c0_cause();
@@ -168,10 +137,6 @@ void __init arch_init_irq(void)
168 /* clear PCI Reset interrupts */ 137 /* clear PCI Reset interrupts */
169 jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR); 138 jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
170 139
171 /* enable interrupt control */
172 tx3927_ircptr->cer = TX3927_IRCER_ICE;
173 tx3927_ircptr->imr = irc_elevel;
174
175 jmr3927_irq_init(); 140 jmr3927_irq_init();
176 141
177 /* setup IOC interrupt 1 (PCI, MODEM) */ 142 /* setup IOC interrupt 1 (PCI, MODEM) */
@@ -193,20 +158,13 @@ static struct irq_chip jmr3927_irq_ioc = {
193 .unmask = unmask_irq_ioc, 158 .unmask = unmask_irq_ioc,
194}; 159};
195 160
196static struct irq_chip jmr3927_irq_irc = {
197 .name = "jmr3927_irc",
198 .ack = mask_irq_irc,
199 .mask = mask_irq_irc,
200 .mask_ack = mask_irq_irc,
201 .unmask = unmask_irq_irc,
202};
203
204static void __init jmr3927_irq_init(void) 161static void __init jmr3927_irq_init(void)
205{ 162{
206 u32 i; 163 u32 i;
207 164
208 for (i = JMR3927_IRQ_IRC; i < JMR3927_IRQ_IRC + JMR3927_NR_IRQ_IRC; i++) 165 txx9_irq_init(TX3927_IRC_REG);
209 set_irq_chip_and_handler(i, &jmr3927_irq_irc, handle_level_irq); 166 for (i = 0; i < TXx9_MAX_IR; i++)
167 txx9_irq_set_pri(i, irc_level[i]);
210 for (i = JMR3927_IRQ_IOC; i < JMR3927_IRQ_IOC + JMR3927_NR_IRQ_IOC; i++) 168 for (i = JMR3927_IRQ_IOC; i < JMR3927_IRQ_IOC + JMR3927_NR_IRQ_IOC; i++)
211 set_irq_chip_and_handler(i, &jmr3927_irq_ioc, handle_level_irq); 169 set_irq_chip_and_handler(i, &jmr3927_irq_ioc, handle_level_irq);
212} 170}