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-rw-r--r--arch/mips/ite-boards/generic/Makefile15
-rw-r--r--arch/mips/ite-boards/generic/dbg_io.c125
-rw-r--r--arch/mips/ite-boards/generic/int-handler.S63
-rw-r--r--arch/mips/ite-boards/generic/irq.c304
-rw-r--r--arch/mips/ite-boards/generic/it8172_cir.c171
-rw-r--r--arch/mips/ite-boards/generic/it8172_setup.c309
-rw-r--r--arch/mips/ite-boards/generic/lpc.c144
-rw-r--r--arch/mips/ite-boards/generic/pmon_prom.c136
-rw-r--r--arch/mips/ite-boards/generic/puts.c139
-rw-r--r--arch/mips/ite-boards/generic/reset.c60
-rw-r--r--arch/mips/ite-boards/generic/time.c247
-rw-r--r--arch/mips/ite-boards/ivr/Makefile10
-rw-r--r--arch/mips/ite-boards/ivr/README3
-rw-r--r--arch/mips/ite-boards/ivr/init.c84
-rw-r--r--arch/mips/ite-boards/qed-4n-s01b/Makefile10
-rw-r--r--arch/mips/ite-boards/qed-4n-s01b/README2
-rw-r--r--arch/mips/ite-boards/qed-4n-s01b/init.c85
17 files changed, 1907 insertions, 0 deletions
diff --git a/arch/mips/ite-boards/generic/Makefile b/arch/mips/ite-boards/generic/Makefile
new file mode 100644
index 000000000000..0e7853f43983
--- /dev/null
+++ b/arch/mips/ite-boards/generic/Makefile
@@ -0,0 +1,15 @@
1#
2# Copyright 2000 MontaVista Software Inc.
3# Author: MontaVista Software, Inc.
4# ppopov@mvista.com or source@mvista.com
5#
6# Makefile for the ITE 8172 (qed-4n-s01b) board, generic files.
7#
8
9obj-y += it8172_setup.o irq.o int-handler.o pmon_prom.o \
10 time.o lpc.o puts.o reset.o
11
12obj-$(CONFIG_IT8172_CIR)+= it8172_cir.o
13obj-$(CONFIG_KGDB) += dbg_io.o
14
15EXTRA_AFLAGS := $(CFLAGS)
diff --git a/arch/mips/ite-boards/generic/dbg_io.c b/arch/mips/ite-boards/generic/dbg_io.c
new file mode 100644
index 000000000000..c4f8530fd07e
--- /dev/null
+++ b/arch/mips/ite-boards/generic/dbg_io.c
@@ -0,0 +1,125 @@
1
2#include <linux/config.h>
3
4#ifdef CONFIG_KGDB
5
6/* --- CONFIG --- */
7
8/* we need uint32 uint8 */
9/* #include "types.h" */
10typedef unsigned char uint8;
11typedef unsigned int uint32;
12
13/* --- END OF CONFIG --- */
14
15#define UART16550_BAUD_2400 2400
16#define UART16550_BAUD_4800 4800
17#define UART16550_BAUD_9600 9600
18#define UART16550_BAUD_19200 19200
19#define UART16550_BAUD_38400 38400
20#define UART16550_BAUD_57600 57600
21#define UART16550_BAUD_115200 115200
22
23#define UART16550_PARITY_NONE 0
24#define UART16550_PARITY_ODD 0x08
25#define UART16550_PARITY_EVEN 0x18
26#define UART16550_PARITY_MARK 0x28
27#define UART16550_PARITY_SPACE 0x38
28
29#define UART16550_DATA_5BIT 0x0
30#define UART16550_DATA_6BIT 0x1
31#define UART16550_DATA_7BIT 0x2
32#define UART16550_DATA_8BIT 0x3
33
34#define UART16550_STOP_1BIT 0x0
35#define UART16550_STOP_2BIT 0x4
36
37/* ----------------------------------------------------- */
38
39/* === CONFIG === */
40
41/* [stevel] we use the IT8712 serial port for kgdb */
42#define DEBUG_BASE 0xB40003F8 /* 8712 serial port 1 base address */
43#define MAX_BAUD 115200
44
45/* === END OF CONFIG === */
46
47/* register offset */
48#define OFS_RCV_BUFFER 0
49#define OFS_TRANS_HOLD 0
50#define OFS_SEND_BUFFER 0
51#define OFS_INTR_ENABLE 1
52#define OFS_INTR_ID 2
53#define OFS_DATA_FORMAT 3
54#define OFS_LINE_CONTROL 3
55#define OFS_MODEM_CONTROL 4
56#define OFS_RS232_OUTPUT 4
57#define OFS_LINE_STATUS 5
58#define OFS_MODEM_STATUS 6
59#define OFS_RS232_INPUT 6
60#define OFS_SCRATCH_PAD 7
61
62#define OFS_DIVISOR_LSB 0
63#define OFS_DIVISOR_MSB 1
64
65
66/* memory-mapped read/write of the port */
67#define UART16550_READ(y) (*((volatile uint8*)(DEBUG_BASE + y)))
68#define UART16550_WRITE(y,z) ((*((volatile uint8*)(DEBUG_BASE + y))) = z)
69
70void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop)
71{
72 /* disable interrupts */
73 UART16550_WRITE(OFS_INTR_ENABLE, 0);
74
75 /* set up buad rate */
76 {
77 uint32 divisor;
78
79 /* set DIAB bit */
80 UART16550_WRITE(OFS_LINE_CONTROL, 0x80);
81
82 /* set divisor */
83 divisor = MAX_BAUD / baud;
84 UART16550_WRITE(OFS_DIVISOR_LSB, divisor & 0xff);
85 UART16550_WRITE(OFS_DIVISOR_MSB, (divisor & 0xff00) >> 8);
86
87 /* clear DIAB bit */
88 UART16550_WRITE(OFS_LINE_CONTROL, 0x0);
89 }
90
91 /* set data format */
92 UART16550_WRITE(OFS_DATA_FORMAT, data | parity | stop);
93}
94
95static int remoteDebugInitialized = 0;
96
97uint8 getDebugChar(void)
98{
99 if (!remoteDebugInitialized) {
100 remoteDebugInitialized = 1;
101 debugInit(UART16550_BAUD_115200,
102 UART16550_DATA_8BIT,
103 UART16550_PARITY_NONE, UART16550_STOP_1BIT);
104 }
105
106 while ((UART16550_READ(OFS_LINE_STATUS) & 0x1) == 0);
107 return UART16550_READ(OFS_RCV_BUFFER);
108}
109
110
111int putDebugChar(uint8 byte)
112{
113 if (!remoteDebugInitialized) {
114 remoteDebugInitialized = 1;
115 debugInit(UART16550_BAUD_115200,
116 UART16550_DATA_8BIT,
117 UART16550_PARITY_NONE, UART16550_STOP_1BIT);
118 }
119
120 while ((UART16550_READ(OFS_LINE_STATUS) & 0x20) == 0);
121 UART16550_WRITE(OFS_SEND_BUFFER, byte);
122 return 1;
123}
124
125#endif
diff --git a/arch/mips/ite-boards/generic/int-handler.S b/arch/mips/ite-boards/generic/int-handler.S
new file mode 100644
index 000000000000..d190d8add9cb
--- /dev/null
+++ b/arch/mips/ite-boards/generic/int-handler.S
@@ -0,0 +1,63 @@
1#include <asm/asm.h>
2#include <asm/mipsregs.h>
3#include <asm/regdef.h>
4#include <asm/stackframe.h>
5
6 .text
7 .set macro
8 .set noat
9 .align 5
10
11NESTED(it8172_IRQ, PT_SIZE, sp)
12 SAVE_ALL
13 CLI # Important: mark KERNEL mode !
14
15 /* We're working with 'reorder' set at this point. */
16 /*
17 * Get pending interrupts
18 */
19
20 mfc0 t0,CP0_CAUSE # get pending interrupts
21 mfc0 t1,CP0_STATUS # get enabled interrupts
22 and t0,t1 # isolate allowed ones
23
24 andi t0,0xff00 # isolate pending bits
25 beqz t0, 3f # spurious interrupt
26
27 andi a0, t0, CAUSEF_IP7
28 beq a0, zero, 1f
29
30 li a0, 127 # MIPS_CPU_TIMER_IRQ = (NR_IRQS-1)
31 move a1, sp
32 jal ll_timer_interrupt
33 j ret_from_irq
34 nop
35
361:
37 andi a0, t0, CAUSEF_IP2 # the only int we expect at this time
38 beq a0, zero, 3f
39 move a0,sp
40 jal it8172_hw0_irqdispatch
41
42 mfc0 t0,CP0_STATUS # disable interrupts
43 ori t0,1
44 xori t0,1
45 mtc0 t0,CP0_STATUS
46 nop
47 nop
48 nop
49
50 la a1, ret_from_irq
51 jr a1
52 nop
53
543:
55 move a0, sp
56 jal mips_spurious_interrupt
57 nop
58 la a1, ret_from_irq
59 jr a1
60 nop
61
62END(it8172_IRQ)
63
diff --git a/arch/mips/ite-boards/generic/irq.c b/arch/mips/ite-boards/generic/irq.c
new file mode 100644
index 000000000000..cb71b9024d6f
--- /dev/null
+++ b/arch/mips/ite-boards/generic/irq.c
@@ -0,0 +1,304 @@
1/*
2 * BRIEF MODULE DESCRIPTION
3 * ITE 8172G interrupt/setup routines.
4 *
5 * Copyright 2000,2001 MontaVista Software Inc.
6 * Author: MontaVista Software, Inc.
7 * ppopov@mvista.com or source@mvista.com
8 *
9 * Part of this file was derived from Carsten Langgaard's
10 * arch/mips/mips-boards/atlas/atlas_int.c.
11 *
12 * Carsten Langgaard, carstenl@mips.com
13 * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
14 *
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
19 *
20 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
21 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
23 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
26 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
27 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 *
31 * You should have received a copy of the GNU General Public License along
32 * with this program; if not, write to the Free Software Foundation, Inc.,
33 * 675 Mass Ave, Cambridge, MA 02139, USA.
34 */
35#include <linux/errno.h>
36#include <linux/init.h>
37#include <linux/irq.h>
38#include <linux/kernel_stat.h>
39#include <linux/module.h>
40#include <linux/signal.h>
41#include <linux/sched.h>
42#include <linux/types.h>
43#include <linux/interrupt.h>
44#include <linux/ioport.h>
45#include <linux/timex.h>
46#include <linux/slab.h>
47#include <linux/random.h>
48#include <linux/serial_reg.h>
49#include <linux/bitops.h>
50
51#include <asm/bootinfo.h>
52#include <asm/io.h>
53#include <asm/mipsregs.h>
54#include <asm/system.h>
55#include <asm/it8172/it8172.h>
56#include <asm/it8172/it8172_int.h>
57#include <asm/it8172/it8172_dbg.h>
58
59/* revisit */
60#define EXT_IRQ0_TO_IP 2 /* IP 2 */
61#define EXT_IRQ5_TO_IP 7 /* IP 7 */
62
63#define ALLINTS_NOTIMER (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4)
64
65void disable_it8172_irq(unsigned int irq_nr);
66void enable_it8172_irq(unsigned int irq_nr);
67
68extern void set_debug_traps(void);
69extern void mips_timer_interrupt(int irq, struct pt_regs *regs);
70extern asmlinkage void it8172_IRQ(void);
71
72struct it8172_intc_regs volatile *it8172_hw0_icregs =
73 (struct it8172_intc_regs volatile *)(KSEG1ADDR(IT8172_PCI_IO_BASE + IT_INTC_BASE));
74
75static void disable_it8172_irq(unsigned int irq_nr)
76{
77 if ( (irq_nr >= IT8172_LPC_IRQ_BASE) && (irq_nr <= IT8172_SERIRQ_15)) {
78 /* LPC interrupt */
79 it8172_hw0_icregs->lpc_mask |=
80 (1 << (irq_nr - IT8172_LPC_IRQ_BASE));
81 } else if ( (irq_nr >= IT8172_LB_IRQ_BASE) && (irq_nr <= IT8172_IOCHK_IRQ)) {
82 /* Local Bus interrupt */
83 it8172_hw0_icregs->lb_mask |=
84 (1 << (irq_nr - IT8172_LB_IRQ_BASE));
85 } else if ( (irq_nr >= IT8172_PCI_DEV_IRQ_BASE) && (irq_nr <= IT8172_DMA_IRQ)) {
86 /* PCI and other interrupts */
87 it8172_hw0_icregs->pci_mask |=
88 (1 << (irq_nr - IT8172_PCI_DEV_IRQ_BASE));
89 } else if ( (irq_nr >= IT8172_NMI_IRQ_BASE) && (irq_nr <= IT8172_POWER_NMI_IRQ)) {
90 /* NMI interrupts */
91 it8172_hw0_icregs->nmi_mask |=
92 (1 << (irq_nr - IT8172_NMI_IRQ_BASE));
93 } else {
94 panic("disable_it8172_irq: bad irq %d", irq_nr);
95 }
96}
97
98static void enable_it8172_irq(unsigned int irq_nr)
99{
100 if ( (irq_nr >= IT8172_LPC_IRQ_BASE) && (irq_nr <= IT8172_SERIRQ_15)) {
101 /* LPC interrupt */
102 it8172_hw0_icregs->lpc_mask &=
103 ~(1 << (irq_nr - IT8172_LPC_IRQ_BASE));
104 }
105 else if ( (irq_nr >= IT8172_LB_IRQ_BASE) && (irq_nr <= IT8172_IOCHK_IRQ)) {
106 /* Local Bus interrupt */
107 it8172_hw0_icregs->lb_mask &=
108 ~(1 << (irq_nr - IT8172_LB_IRQ_BASE));
109 }
110 else if ( (irq_nr >= IT8172_PCI_DEV_IRQ_BASE) && (irq_nr <= IT8172_DMA_IRQ)) {
111 /* PCI and other interrupts */
112 it8172_hw0_icregs->pci_mask &=
113 ~(1 << (irq_nr - IT8172_PCI_DEV_IRQ_BASE));
114 }
115 else if ( (irq_nr >= IT8172_NMI_IRQ_BASE) && (irq_nr <= IT8172_POWER_NMI_IRQ)) {
116 /* NMI interrupts */
117 it8172_hw0_icregs->nmi_mask &=
118 ~(1 << (irq_nr - IT8172_NMI_IRQ_BASE));
119 }
120 else {
121 panic("enable_it8172_irq: bad irq %d", irq_nr);
122 }
123}
124
125static unsigned int startup_ite_irq(unsigned int irq)
126{
127 enable_it8172_irq(irq);
128 return 0;
129}
130
131#define shutdown_ite_irq disable_it8172_irq
132#define mask_and_ack_ite_irq disable_it8172_irq
133
134static void end_ite_irq(unsigned int irq)
135{
136 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
137 enable_it8172_irq(irq);
138}
139
140static struct hw_interrupt_type it8172_irq_type = {
141 "ITE8172",
142 startup_ite_irq,
143 shutdown_ite_irq,
144 enable_it8172_irq,
145 disable_it8172_irq,
146 mask_and_ack_ite_irq,
147 end_ite_irq,
148 NULL
149};
150
151
152static void enable_none(unsigned int irq) { }
153static unsigned int startup_none(unsigned int irq) { return 0; }
154static void disable_none(unsigned int irq) { }
155static void ack_none(unsigned int irq) { }
156
157/* startup is the same as "enable", shutdown is same as "disable" */
158#define shutdown_none disable_none
159#define end_none enable_none
160
161static struct hw_interrupt_type cp0_irq_type = {
162 "CP0 Count",
163 startup_none,
164 shutdown_none,
165 enable_none,
166 disable_none,
167 ack_none,
168 end_none
169};
170
171void enable_cpu_timer(void)
172{
173 unsigned long flags;
174
175 local_irq_save(flags);
176 set_c0_status(0x100 << EXT_IRQ5_TO_IP);
177 local_irq_restore(flags);
178}
179
180void __init arch_init_irq(void)
181{
182 int i;
183 unsigned long flags;
184
185 memset(irq_desc, 0, sizeof(irq_desc));
186 set_except_vector(0, it8172_IRQ);
187
188 /* mask all interrupts */
189 it8172_hw0_icregs->lb_mask = 0xffff;
190 it8172_hw0_icregs->lpc_mask = 0xffff;
191 it8172_hw0_icregs->pci_mask = 0xffff;
192 it8172_hw0_icregs->nmi_mask = 0xffff;
193
194 /* make all interrupts level triggered */
195 it8172_hw0_icregs->lb_trigger = 0;
196 it8172_hw0_icregs->lpc_trigger = 0;
197 it8172_hw0_icregs->pci_trigger = 0;
198 it8172_hw0_icregs->nmi_trigger = 0;
199
200 /* active level setting */
201 /* uart, keyboard, and mouse are active high */
202 it8172_hw0_icregs->lpc_level = (0x10 | 0x2 | 0x1000);
203 it8172_hw0_icregs->lb_level |= 0x20;
204
205 /* keyboard and mouse are edge triggered */
206 it8172_hw0_icregs->lpc_trigger |= (0x2 | 0x1000);
207
208
209#if 0
210 // Enable this piece of code to make internal USB interrupt
211 // edge triggered.
212 it8172_hw0_icregs->pci_trigger |=
213 (1 << (IT8172_USB_IRQ - IT8172_PCI_DEV_IRQ_BASE));
214 it8172_hw0_icregs->pci_level &=
215 ~(1 << (IT8172_USB_IRQ - IT8172_PCI_DEV_IRQ_BASE));
216#endif
217
218 for (i = 0; i <= IT8172_LAST_IRQ; i++) {
219 irq_desc[i].handler = &it8172_irq_type;
220 spin_lock_init(&irq_desc[i].lock);
221 }
222 irq_desc[MIPS_CPU_TIMER_IRQ].handler = &cp0_irq_type;
223 set_c0_status(ALLINTS_NOTIMER);
224}
225
226void mips_spurious_interrupt(struct pt_regs *regs)
227{
228#if 1
229 return;
230#else
231 unsigned long status, cause;
232
233 printk("got spurious interrupt\n");
234 status = read_c0_status();
235 cause = read_c0_cause();
236 printk("status %x cause %x\n", status, cause);
237 printk("epc %x badvaddr %x \n", regs->cp0_epc, regs->cp0_badvaddr);
238#endif
239}
240
241void it8172_hw0_irqdispatch(struct pt_regs *regs)
242{
243 int irq;
244 unsigned short intstatus = 0, status = 0;
245
246 intstatus = it8172_hw0_icregs->intstatus;
247 if (intstatus & 0x8) {
248 panic("Got NMI interrupt");
249 } else if (intstatus & 0x4) {
250 /* PCI interrupt */
251 irq = 0;
252 status |= it8172_hw0_icregs->pci_req;
253 while (!(status & 0x1)) {
254 irq++;
255 status >>= 1;
256 }
257 irq += IT8172_PCI_DEV_IRQ_BASE;
258 } else if (intstatus & 0x1) {
259 /* Local Bus interrupt */
260 irq = 0;
261 status |= it8172_hw0_icregs->lb_req;
262 while (!(status & 0x1)) {
263 irq++;
264 status >>= 1;
265 }
266 irq += IT8172_LB_IRQ_BASE;
267 } else if (intstatus & 0x2) {
268 /* LPC interrupt */
269 /* Since some lpc interrupts are edge triggered,
270 * we could lose an interrupt this way because
271 * we acknowledge all ints at onces. Revisit.
272 */
273 status |= it8172_hw0_icregs->lpc_req;
274 it8172_hw0_icregs->lpc_req = 0; /* acknowledge ints */
275 irq = 0;
276 while (!(status & 0x1)) {
277 irq++;
278 status >>= 1;
279 }
280 irq += IT8172_LPC_IRQ_BASE;
281 } else
282 return;
283
284 do_IRQ(irq, regs);
285}
286
287void show_pending_irqs(void)
288{
289 fputs("intstatus: ");
290 put32(it8172_hw0_icregs->intstatus);
291 puts("");
292
293 fputs("pci_req: ");
294 put32(it8172_hw0_icregs->pci_req);
295 puts("");
296
297 fputs("lb_req: ");
298 put32(it8172_hw0_icregs->lb_req);
299 puts("");
300
301 fputs("lpc_req: ");
302 put32(it8172_hw0_icregs->lpc_req);
303 puts("");
304}
diff --git a/arch/mips/ite-boards/generic/it8172_cir.c b/arch/mips/ite-boards/generic/it8172_cir.c
new file mode 100644
index 000000000000..19deb153d005
--- /dev/null
+++ b/arch/mips/ite-boards/generic/it8172_cir.c
@@ -0,0 +1,171 @@
1/*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * IT8172 Consumer IR port generic routines.
5 *
6 * Copyright 2001 MontaVista Software Inc.
7 * Author: MontaVista Software, Inc.
8 * ppopov@mvista.com or source@mvista.com
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
17 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
21 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
22 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * You should have received a copy of the GNU General Public License along
27 * with this program; if not, write to the Free Software Foundation, Inc.,
28 * 675 Mass Ave, Cambridge, MA 02139, USA.
29 */
30
31#include <linux/config.h>
32
33#ifdef CONFIG_IT8172_CIR
34
35#include <linux/types.h>
36#include <linux/pci.h>
37#include <linux/kernel.h>
38#include <linux/init.h>
39
40#include <asm/it8172/it8172.h>
41#include <asm/it8172/it8172_cir.h>
42
43
44volatile struct it8172_cir_regs *cir_regs[NUM_CIR_PORTS] = {
45 (volatile struct it8172_cir_regs *)(KSEG1ADDR(IT8172_PCI_IO_BASE + IT_CIR0_BASE)),
46 (volatile struct it8172_cir_regs *)(KSEG1ADDR(IT8172_PCI_IO_BASE + IT_CIR1_BASE))};
47
48
49/*
50 * Initialize Consumer IR Port.
51 */
52int cir_port_init(struct cir_port *cir)
53{
54 int port = cir->port;
55 unsigned char data;
56
57 /* set baud rate */
58 cir_regs[port]->bdlr = cir->baud_rate & 0xff;
59 cir_regs[port]->bdhr = (cir->baud_rate >> 8) & 0xff;
60
61 /* set receiver control register */
62 cir_regs[port]->rcr = (CIR_SET_RDWOS(cir->rdwos) | CIR_SET_RXDCR(cir->rxdcr));
63
64 /* set carrier frequency register */
65 cir_regs[port]->cfr = (CIR_SET_CF(cir->cfq) | CIR_SET_HS(cir->hcfs));
66
67 /* set fifo threshold */
68 data = cir_regs[port]->mstcr & 0xf3;
69 data |= CIR_SET_FIFO_TL(cir->fifo_tl);
70 cir_regs[port]->mstcr = data;
71
72 clear_fifo(cir);
73 enable_receiver(cir);
74 disable_rx_demodulation(cir);
75
76 set_rx_active(cir);
77 int_enable(cir);
78 rx_int_enable(cir);
79
80 return 0;
81}
82
83
84void clear_fifo(struct cir_port *cir)
85{
86 cir_regs[cir->port]->mstcr |= CIR_FIFO_CLEAR;
87}
88
89void enable_receiver(struct cir_port *cir)
90{
91 cir_regs[cir->port]->rcr |= CIR_RXEN;
92}
93
94void disable_receiver(struct cir_port *cir)
95{
96 cir_regs[cir->port]->rcr &= ~CIR_RXEN;
97}
98
99void enable_rx_demodulation(struct cir_port *cir)
100{
101 cir_regs[cir->port]->rcr |= CIR_RXEND;
102}
103
104void disable_rx_demodulation(struct cir_port *cir)
105{
106 cir_regs[cir->port]->rcr &= ~CIR_RXEND;
107}
108
109void set_rx_active(struct cir_port *cir)
110{
111 cir_regs[cir->port]->rcr |= CIR_RXACT;
112}
113
114void int_enable(struct cir_port *cir)
115{
116 cir_regs[cir->port]->ier |= CIR_IEC;
117}
118
119void rx_int_enable(struct cir_port *cir)
120{
121 cir_regs[cir->port]->ier |= CIR_RDAIE;
122}
123
124void dump_regs(struct cir_port *cir)
125{
126 printk("mstcr %x ier %x iir %x cfr %x rcr %x tcr %x tfsr %x rfsr %x\n",
127 cir_regs[cir->port]->mstcr,
128 cir_regs[cir->port]->ier,
129 cir_regs[cir->port]->iir,
130 cir_regs[cir->port]->cfr,
131 cir_regs[cir->port]->rcr,
132 cir_regs[cir->port]->tcr,
133 cir_regs[cir->port]->tfsr,
134 cir_regs[cir->port]->rfsr);
135
136 while (cir_regs[cir->port]->iir & CIR_RDAI) {
137 printk("data %x\n", cir_regs[cir->port]->dr);
138 }
139}
140
141void dump_reg_addr(struct cir_port *cir)
142{
143 printk("dr %x mstcr %x ier %x iir %x cfr %x rcr %x tcr %x bdlr %x bdhr %x tfsr %x rfsr %x\n",
144 (unsigned)&cir_regs[cir->port]->dr,
145 (unsigned)&cir_regs[cir->port]->mstcr,
146 (unsigned)&cir_regs[cir->port]->ier,
147 (unsigned)&cir_regs[cir->port]->iir,
148 (unsigned)&cir_regs[cir->port]->cfr,
149 (unsigned)&cir_regs[cir->port]->rcr,
150 (unsigned)&cir_regs[cir->port]->tcr,
151 (unsigned)&cir_regs[cir->port]->bdlr,
152 (unsigned)&cir_regs[cir->port]->bdhr,
153 (unsigned)&cir_regs[cir->port]->tfsr,
154 (unsigned)&cir_regs[cir->port]->rfsr);
155}
156
157int cir_get_rx_count(struct cir_port *cir)
158{
159 return cir_regs[cir->port]->rfsr & CIR_RXFBC_MASK;
160}
161
162char cir_read_data(struct cir_port *cir)
163{
164 return cir_regs[cir->port]->dr;
165}
166
167char get_int_status(struct cir_port *cir)
168{
169 return cir_regs[cir->port]->iir;
170}
171#endif
diff --git a/arch/mips/ite-boards/generic/it8172_setup.c b/arch/mips/ite-boards/generic/it8172_setup.c
new file mode 100644
index 000000000000..d808a67294b8
--- /dev/null
+++ b/arch/mips/ite-boards/generic/it8172_setup.c
@@ -0,0 +1,309 @@
1/*
2 * BRIEF MODULE DESCRIPTION
3 * IT8172/QED5231 board setup.
4 *
5 * Copyright 2000 MontaVista Software Inc.
6 * Author: MontaVista Software, Inc.
7 * ppopov@mvista.com or source@mvista.com
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
15 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
17 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
20 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
21 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 *
25 * You should have received a copy of the GNU General Public License along
26 * with this program; if not, write to the Free Software Foundation, Inc.,
27 * 675 Mass Ave, Cambridge, MA 02139, USA.
28 */
29#include <linux/config.h>
30#include <linux/init.h>
31#include <linux/sched.h>
32#include <linux/ioport.h>
33#include <linux/serial_reg.h>
34#include <linux/major.h>
35#include <linux/kdev_t.h>
36#include <linux/root_dev.h>
37
38#include <asm/cpu.h>
39#include <asm/time.h>
40#include <asm/io.h>
41#include <asm/bootinfo.h>
42#include <asm/irq.h>
43#include <asm/mipsregs.h>
44#include <asm/reboot.h>
45#include <asm/traps.h>
46#include <asm/it8172/it8172.h>
47#include <asm/it8712.h>
48
49extern struct resource ioport_resource;
50#ifdef CONFIG_SERIO_I8042
51int init_8712_keyboard(void);
52#endif
53
54extern int SearchIT8712(void);
55extern void InitLPCInterface(void);
56extern char * __init prom_getcmdline(void);
57extern void it8172_restart(char *command);
58extern void it8172_halt(void);
59extern void it8172_power_off(void);
60
61extern void (*board_time_init)(void);
62extern void (*board_timer_setup)(struct irqaction *irq);
63extern void it8172_time_init(void);
64extern void it8172_timer_setup(struct irqaction *irq);
65
66#ifdef CONFIG_IT8172_REVC
67struct {
68 struct resource ram;
69 struct resource pci_mem;
70 struct resource pci_io;
71 struct resource flash;
72 struct resource boot;
73} it8172_resources = {
74 { "RAM", 0, 0, IORESOURCE_MEM }, /* to be initted */
75 { "PCI Mem", 0x10000000, 0x13FFFFFF, IORESOURCE_MEM },
76 { "PCI I/O", 0x14000000, 0x17FFFFFF },
77 { "Flash", 0x08000000, 0x0CFFFFFF },
78 { "Boot ROM", 0x1FC00000, 0x1FFFFFFF }
79};
80#else
81struct {
82 struct resource ram;
83 struct resource pci_mem0;
84 struct resource pci_mem1;
85 struct resource pci_io;
86 struct resource pci_mem2;
87 struct resource pci_mem3;
88 struct resource flash;
89 struct resource boot;
90} it8172_resources = {
91 { "RAM", 0, 0, IORESOURCE_MEM }, /* to be initted */
92 { "PCI Mem0", 0x0C000000, 0x0FFFFFFF, IORESOURCE_MEM },
93 { "PCI Mem1", 0x10000000, 0x13FFFFFF, IORESOURCE_MEM },
94 { "PCI I/O", 0x14000000, 0x17FFFFFF },
95 { "PCI Mem2", 0x1A000000, 0x1BFFFFFF, IORESOURCE_MEM },
96 { "PCI Mem3", 0x1C000000, 0x1FBFFFFF, IORESOURCE_MEM },
97 { "Flash", 0x08000000, 0x0CFFFFFF },
98 { "Boot ROM", 0x1FC00000, 0x1FFFFFFF }
99};
100#endif
101
102
103void __init it8172_init_ram_resource(unsigned long memsize)
104{
105 it8172_resources.ram.end = memsize;
106}
107
108static void __init it8172_setup(void)
109{
110 unsigned short dsr;
111 char *argptr;
112
113 argptr = prom_getcmdline();
114#ifdef CONFIG_SERIAL_CONSOLE
115 if ((argptr = strstr(argptr, "console=")) == NULL) {
116 argptr = prom_getcmdline();
117 strcat(argptr, " console=ttyS0,115200");
118 }
119#endif
120
121 clear_c0_status(ST0_FR);
122
123 board_time_init = it8172_time_init;
124 board_timer_setup = it8172_timer_setup;
125
126 _machine_restart = it8172_restart;
127 _machine_halt = it8172_halt;
128 _machine_power_off = it8172_power_off;
129
130 /*
131 * IO/MEM resources.
132 *
133 * revisit this area.
134 */
135 set_io_port_base(KSEG1);
136 ioport_resource.start = it8172_resources.pci_io.start;
137 ioport_resource.end = it8172_resources.pci_io.end;
138#ifdef CONFIG_IT8172_REVC
139 iomem_resource.start = it8172_resources.pci_mem.start;
140 iomem_resource.end = it8172_resources.pci_mem.end;
141#else
142 iomem_resource.start = it8172_resources.pci_mem0.start;
143 iomem_resource.end = it8172_resources.pci_mem3.end;
144#endif
145
146#ifdef CONFIG_BLK_DEV_INITRD
147 ROOT_DEV = Root_RAM0;
148#endif
149
150 /*
151 * Pull enabled devices out of standby
152 */
153 IT_IO_READ16(IT_PM_DSR, dsr);
154
155 /*
156 * Fixme: This breaks when these drivers are modules!!!
157 */
158#ifdef CONFIG_SOUND_IT8172
159 dsr &= ~IT_PM_DSR_ACSB;
160#else
161 dsr |= IT_PM_DSR_ACSB;
162#endif
163#ifdef CONFIG_BLK_DEV_IT8172
164 dsr &= ~IT_PM_DSR_IDESB;
165#else
166 dsr |= IT_PM_DSR_IDESB;
167#endif
168 IT_IO_WRITE16(IT_PM_DSR, dsr);
169
170 InitLPCInterface();
171
172#ifdef CONFIG_MIPS_ITE8172
173 if (SearchIT8712()) {
174 printk("Found IT8712 Super IO\n");
175 /* enable IT8712 serial port */
176 LPCSetConfig(LDN_SERIAL1, 0x30, 0x01); /* enable */
177 LPCSetConfig(LDN_SERIAL1, 0x23, 0x01); /* clock selection */
178#ifdef CONFIG_SERIO_I8042
179 if (init_8712_keyboard()) {
180 printk("Unable to initialize keyboard\n");
181 LPCSetConfig(LDN_KEYBOARD, 0x30, 0x0); /* disable keyboard */
182 } else {
183 LPCSetConfig(LDN_KEYBOARD, 0x30, 0x1); /* enable keyboard */
184 LPCSetConfig(LDN_KEYBOARD, 0xf0, 0x2);
185 LPCSetConfig(LDN_KEYBOARD, 0x71, 0x3);
186
187 LPCSetConfig(LDN_MOUSE, 0x30, 0x1); /* enable mouse */
188
189 LPCSetConfig(0x4, 0x30, 0x1);
190 LPCSetConfig(0x4, 0xf4, LPCGetConfig(0x4, 0xf4) | 0x80);
191
192 if ((LPCGetConfig(LDN_KEYBOARD, 0x30) == 0) ||
193 (LPCGetConfig(LDN_MOUSE, 0x30) == 0))
194 printk("Error: keyboard or mouse not enabled\n");
195
196 }
197#endif
198 }
199 else {
200 printk("IT8712 Super IO not found\n");
201 }
202#endif
203
204#ifdef CONFIG_IT8172_CIR
205 {
206 unsigned long data;
207 //printk("Enabling CIR0\n");
208 IT_IO_READ16(IT_PM_DSR, data);
209 data &= ~IT_PM_DSR_CIR0SB;
210 IT_IO_WRITE16(IT_PM_DSR, data);
211 //printk("DSR register: %x\n", (unsigned)IT_IO_READ16(IT_PM_DSR, data));
212 }
213#endif
214#ifdef CONFIG_IT8172_SCR0
215 {
216 unsigned i;
217 /* Enable Smart Card Reader 0 */
218 /* First power it up */
219 IT_IO_READ16(IT_PM_DSR, i);
220 i &= ~IT_PM_DSR_SCR0SB;
221 IT_IO_WRITE16(IT_PM_DSR, i);
222 /* Then initialize its registers */
223 outb(( IT_SCR_SFR_GATE_UART_OFF << IT_SCR_SFR_GATE_UART_BIT
224 |IT_SCR_SFR_FET_CHARGE_213_US << IT_SCR_SFR_FET_CHARGE_BIT
225 |IT_SCR_SFR_CARD_FREQ_3_5_MHZ << IT_SCR_SFR_CARD_FREQ_BIT
226 |IT_SCR_SFR_FET_ACTIVE_INVERT << IT_SCR_SFR_FET_ACTIVE_BIT
227 |IT_SCR_SFR_ENABLE_ON << IT_SCR_SFR_ENABLE_BIT),
228 IT8172_PCI_IO_BASE + IT_SCR0_BASE + IT_SCR_SFR);
229 outb(IT_SCR_SCDR_RESET_MODE_ASYNC << IT_SCR_SCDR_RESET_MODE_BIT,
230 IT8172_PCI_IO_BASE + IT_SCR0_BASE + IT_SCR_SCDR);
231 }
232#endif /* CONFIG_IT8172_SCR0 */
233#ifdef CONFIG_IT8172_SCR1
234 {
235 unsigned i;
236 /* Enable Smart Card Reader 1 */
237 /* First power it up */
238 IT_IO_READ16(IT_PM_DSR, i);
239 i &= ~IT_PM_DSR_SCR1SB;
240 IT_IO_WRITE16(IT_PM_DSR, i);
241 /* Then initialize its registers */
242 outb(( IT_SCR_SFR_GATE_UART_OFF << IT_SCR_SFR_GATE_UART_BIT
243 |IT_SCR_SFR_FET_CHARGE_213_US << IT_SCR_SFR_FET_CHARGE_BIT
244 |IT_SCR_SFR_CARD_FREQ_3_5_MHZ << IT_SCR_SFR_CARD_FREQ_BIT
245 |IT_SCR_SFR_FET_ACTIVE_INVERT << IT_SCR_SFR_FET_ACTIVE_BIT
246 |IT_SCR_SFR_ENABLE_ON << IT_SCR_SFR_ENABLE_BIT),
247 IT8172_PCI_IO_BASE + IT_SCR1_BASE + IT_SCR_SFR);
248 outb(IT_SCR_SCDR_RESET_MODE_ASYNC << IT_SCR_SCDR_RESET_MODE_BIT,
249 IT8172_PCI_IO_BASE + IT_SCR1_BASE + IT_SCR_SCDR);
250 }
251#endif /* CONFIG_IT8172_SCR1 */
252}
253
254early_initcall(it8172_setup);
255
256#ifdef CONFIG_SERIO_I8042
257/*
258 * According to the ITE Special BIOS Note for waking up the
259 * keyboard controller...
260 */
261static int init_8712_keyboard(void)
262{
263 unsigned int cmd_port = 0x14000064;
264 unsigned int data_port = 0x14000060;
265 ^^^^^^^^^^^
266 Somebody here doesn't grok the concept of io ports.
267
268 unsigned char data;
269 int i;
270
271 outb(0xaa, cmd_port); /* send self-test cmd */
272 i = 0;
273 while (!(inb(cmd_port) & 0x1)) { /* wait output buffer full */
274 i++;
275 if (i > 0xffffff)
276 return 1;
277 }
278
279 data = inb(data_port);
280 outb(0xcb, cmd_port); /* set ps2 mode */
281 while (inb(cmd_port) & 0x2) { /* wait while input buffer full */
282 i++;
283 if (i > 0xffffff)
284 return 1;
285 }
286 outb(0x01, data_port);
287 while (inb(cmd_port) & 0x2) { /* wait while input buffer full */
288 i++;
289 if (i > 0xffffff)
290 return 1;
291 }
292
293 outb(0x60, cmd_port); /* write 8042 command byte */
294 while (inb(cmd_port) & 0x2) { /* wait while input buffer full */
295 i++;
296 if (i > 0xffffff)
297 return 1;
298 }
299 outb(0x45, data_port); /* at interface, keyboard enabled, system flag */
300 while (inb(cmd_port) & 0x2) { /* wait while input buffer full */
301 i++;
302 if (i > 0xffffff)
303 return 1;
304 }
305
306 outb(0xae, cmd_port); /* enable interface */
307 return 0;
308}
309#endif
diff --git a/arch/mips/ite-boards/generic/lpc.c b/arch/mips/ite-boards/generic/lpc.c
new file mode 100644
index 000000000000..cc7584fbef8a
--- /dev/null
+++ b/arch/mips/ite-boards/generic/lpc.c
@@ -0,0 +1,144 @@
1/*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * ITE Semi IT8712 Super I/O functions.
5 *
6 * Copyright 2001 MontaVista Software Inc.
7 * Author: MontaVista Software, Inc.
8 * ppopov@mvista.com or source@mvista.com
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
17 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
21 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
22 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * You should have received a copy of the GNU General Public License along
27 * with this program; if not, write to the Free Software Foundation, Inc.,
28 * 675 Mass Ave, Cambridge, MA 02139, USA.
29 */
30
31#include <asm/io.h>
32#include <asm/types.h>
33#include <asm/it8712.h>
34#include <asm/it8172/it8172.h>
35
36#ifndef TRUE
37#define TRUE 1
38#endif
39
40#ifndef FALSE
41#define FALSE 0
42#endif
43
44void LPCEnterMBPnP(void)
45{
46 int i;
47 unsigned char key[4] = {0x87, 0x01, 0x55, 0x55};
48
49 for (i = 0; i<4; i++)
50 outb(key[i], LPC_KEY_ADDR);
51
52}
53
54void LPCExitMBPnP(void)
55{
56 outb(0x02, LPC_KEY_ADDR);
57 outb(0x02, LPC_DATA_ADDR);
58}
59
60void LPCSetConfig(char LdnNumber, char Index, char data)
61{
62 LPCEnterMBPnP(); // Enter IT8712 MB PnP mode
63 outb(0x07, LPC_KEY_ADDR);
64 outb(LdnNumber, LPC_DATA_ADDR);
65 outb(Index, LPC_KEY_ADDR);
66 outb(data, LPC_DATA_ADDR);
67 LPCExitMBPnP();
68}
69
70char LPCGetConfig(char LdnNumber, char Index)
71{
72 char rtn;
73
74 LPCEnterMBPnP(); // Enter IT8712 MB PnP mode
75 outb(0x07, LPC_KEY_ADDR);
76 outb(LdnNumber, LPC_DATA_ADDR);
77 outb(Index, LPC_KEY_ADDR);
78 rtn = inb(LPC_DATA_ADDR);
79 LPCExitMBPnP();
80 return rtn;
81}
82
83int SearchIT8712(void)
84{
85 unsigned char Id1, Id2;
86 unsigned short Id;
87
88 LPCEnterMBPnP();
89 outb(0x20, LPC_KEY_ADDR); /* chip id byte 1 */
90 Id1 = inb(LPC_DATA_ADDR);
91 outb(0x21, LPC_KEY_ADDR); /* chip id byte 2 */
92 Id2 = inb(LPC_DATA_ADDR);
93 Id = (Id1 << 8) | Id2;
94 LPCExitMBPnP();
95 if (Id == 0x8712)
96 return TRUE;
97 else
98 return FALSE;
99}
100
101void InitLPCInterface(void)
102{
103 unsigned char bus, dev_fn;
104 unsigned long data;
105
106 bus = 0;
107 dev_fn = 1<<3 | 4;
108
109
110 /* pci cmd, SERR# Enable */
111 IT_WRITE(IT_CONFADDR,
112 (bus << IT_BUSNUM_SHF) |
113 (dev_fn << IT_FUNCNUM_SHF) |
114 ((0x4 / 4) << IT_REGNUM_SHF));
115 IT_READ(IT_CONFDATA, data);
116 data |= 0x0100;
117 IT_WRITE(IT_CONFADDR,
118 (bus << IT_BUSNUM_SHF) |
119 (dev_fn << IT_FUNCNUM_SHF) |
120 ((0x4 / 4) << IT_REGNUM_SHF));
121 IT_WRITE(IT_CONFDATA, data);
122
123 /* setup serial irq control register */
124 IT_WRITE(IT_CONFADDR,
125 (bus << IT_BUSNUM_SHF) |
126 (dev_fn << IT_FUNCNUM_SHF) |
127 ((0x48 / 4) << IT_REGNUM_SHF));
128 IT_READ(IT_CONFDATA, data);
129 data = (data & 0xffff00ff) | 0xc400;
130 IT_WRITE(IT_CONFADDR,
131 (bus << IT_BUSNUM_SHF) |
132 (dev_fn << IT_FUNCNUM_SHF) |
133 ((0x48 / 4) << IT_REGNUM_SHF));
134 IT_WRITE(IT_CONFDATA, data);
135
136
137 /* Enable I/O Space Subtractive Decode */
138 /* default 0x4C is 0x3f220000 */
139 IT_WRITE(IT_CONFADDR,
140 (bus << IT_BUSNUM_SHF) |
141 (dev_fn << IT_FUNCNUM_SHF) |
142 ((0x4C / 4) << IT_REGNUM_SHF));
143 IT_WRITE(IT_CONFDATA, 0x3f2200f3);
144}
diff --git a/arch/mips/ite-boards/generic/pmon_prom.c b/arch/mips/ite-boards/generic/pmon_prom.c
new file mode 100644
index 000000000000..6e505af0cc08
--- /dev/null
+++ b/arch/mips/ite-boards/generic/pmon_prom.c
@@ -0,0 +1,136 @@
1/*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * PROM library initialisation code, assuming a version of
5 * pmon is the boot code.
6 *
7 * Copyright 2000 MontaVista Software Inc.
8 * Author: MontaVista Software, Inc.
9 * ppopov@mvista.com or source@mvista.com
10 *
11 * This file was derived from Carsten Langgaard's
12 * arch/mips/mips-boards/xx files.
13 *
14 * Carsten Langgaard, carstenl@mips.com
15 * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
16 *
17 * This program is free software; you can redistribute it and/or modify it
18 * under the terms of the GNU General Public License as published by the
19 * Free Software Foundation; either version 2 of the License, or (at your
20 * option) any later version.
21 *
22 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 * You should have received a copy of the GNU General Public License along
34 * with this program; if not, write to the Free Software Foundation, Inc.,
35 * 675 Mass Ave, Cambridge, MA 02139, USA.
36 */
37
38#include <linux/config.h>
39#include <linux/kernel.h>
40#include <linux/init.h>
41#include <linux/string.h>
42
43#include <asm/bootinfo.h>
44
45extern int prom_argc;
46extern char **prom_argv, **prom_envp;
47
48typedef struct
49{
50 char *name;
51/* char *val; */
52}t_env_var;
53
54
55char * __init prom_getcmdline(void)
56{
57 return &(arcs_cmdline[0]);
58}
59
60void __init prom_init_cmdline(void)
61{
62 char *cp;
63 int actr;
64
65 actr = 1; /* Always ignore argv[0] */
66
67 cp = &(arcs_cmdline[0]);
68 while(actr < prom_argc) {
69 strcpy(cp, prom_argv[actr]);
70 cp += strlen(prom_argv[actr]);
71 *cp++ = ' ';
72 actr++;
73 }
74 if (cp != &(arcs_cmdline[0])) /* get rid of trailing space */
75 --cp;
76 *cp = '\0';
77
78}
79
80
81char *prom_getenv(char *envname)
82{
83 /*
84 * Return a pointer to the given environment variable.
85 * Environment variables are stored in the form of "memsize=64".
86 */
87
88 t_env_var *env = (t_env_var *)prom_envp;
89 int i;
90
91 i = strlen(envname);
92
93 while(env->name) {
94 if(strncmp(envname, env->name, i) == 0) {
95 return(env->name + strlen(envname) + 1);
96 }
97 env++;
98 }
99 return(NULL);
100}
101
102static inline unsigned char str2hexnum(unsigned char c)
103{
104 if(c >= '0' && c <= '9')
105 return c - '0';
106 if(c >= 'a' && c <= 'f')
107 return c - 'a' + 10;
108 return 0; /* foo */
109}
110
111unsigned long __init prom_free_prom_memory(void)
112{
113 return 0;
114}
115
116unsigned long __init prom_get_memsize(void)
117{
118 char *memsize_str;
119 unsigned int memsize;
120
121 memsize_str = prom_getenv("memsize");
122 if (!memsize_str) {
123#ifdef CONFIG_MIPS_ITE8172
124 memsize = 32;
125#elif defined(CONFIG_MIPS_IVR)
126 memsize = 64;
127#else
128 memsize = 8;
129#endif
130 printk("memsize unknown: setting to %dMB\n", memsize);
131 } else {
132 printk("memsize: %s\n", memsize_str);
133 memsize = simple_strtol(memsize_str, NULL, 0);
134 }
135 return memsize;
136}
diff --git a/arch/mips/ite-boards/generic/puts.c b/arch/mips/ite-boards/generic/puts.c
new file mode 100644
index 000000000000..20b02df6b414
--- /dev/null
+++ b/arch/mips/ite-boards/generic/puts.c
@@ -0,0 +1,139 @@
1/*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * Low level uart routines to directly access a 16550 uart.
5 *
6 * Copyright 2000,2001 MontaVista Software Inc.
7 * Author: MontaVista Software, Inc.
8 * ppopov@mvista.com or source@mvista.com
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
17 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
21 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
22 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * You should have received a copy of the GNU General Public License along
27 * with this program; if not, write to the Free Software Foundation, Inc.,
28 * 675 Mass Ave, Cambridge, MA 02139, USA.
29 */
30
31#include <linux/types.h>
32
33#define SERIAL_BASE 0xB4011800 /* it8172 */
34#define SER_CMD 5
35#define SER_DATA 0x00
36#define TX_BUSY 0x20
37
38#define TIMEOUT 0xffff
39#undef SLOW_DOWN
40
41static const char digits[16] = "0123456789abcdef";
42static volatile unsigned char *const com1 = (unsigned char *) SERIAL_BASE;
43
44
45#ifdef SLOW_DOWN
46static inline void slow_down()
47{
48 int k;
49 for (k = 0; k < 10000; k++);
50}
51#else
52#define slow_down()
53#endif
54
55void putch(const unsigned char c)
56{
57 unsigned char ch;
58 int i = 0;
59
60 do {
61 ch = com1[SER_CMD];
62 slow_down();
63 i++;
64 if (i > TIMEOUT) {
65 break;
66 }
67 } while (0 == (ch & TX_BUSY));
68 com1[SER_DATA] = c;
69}
70
71void puts(unsigned char *cp)
72{
73 unsigned char ch;
74 int i = 0;
75
76 while (*cp) {
77 do {
78 ch = com1[SER_CMD];
79 slow_down();
80 i++;
81 if (i > TIMEOUT) {
82 break;
83 }
84 } while (0 == (ch & TX_BUSY));
85 com1[SER_DATA] = *cp++;
86 }
87 putch('\r');
88 putch('\n');
89}
90
91void fputs(unsigned char *cp)
92{
93 unsigned char ch;
94 int i = 0;
95
96 while (*cp) {
97
98 do {
99 ch = com1[SER_CMD];
100 slow_down();
101 i++;
102 if (i > TIMEOUT) {
103 break;
104 }
105 } while (0 == (ch & TX_BUSY));
106 com1[SER_DATA] = *cp++;
107 }
108}
109
110
111void put64(uint64_t ul)
112{
113 int cnt;
114 unsigned ch;
115
116 cnt = 16; /* 16 nibbles in a 64 bit long */
117 putch('0');
118 putch('x');
119 do {
120 cnt--;
121 ch = (unsigned char) (ul >> cnt * 4) & 0x0F;
122 putch(digits[ch]);
123 } while (cnt > 0);
124}
125
126void put32(unsigned u)
127{
128 int cnt;
129 unsigned ch;
130
131 cnt = 8; /* 8 nibbles in a 32 bit long */
132 putch('0');
133 putch('x');
134 do {
135 cnt--;
136 ch = (unsigned char) (u >> cnt * 4) & 0x0F;
137 putch(digits[ch]);
138 } while (cnt > 0);
139}
diff --git a/arch/mips/ite-boards/generic/reset.c b/arch/mips/ite-boards/generic/reset.c
new file mode 100644
index 000000000000..03bd5ba8c913
--- /dev/null
+++ b/arch/mips/ite-boards/generic/reset.c
@@ -0,0 +1,60 @@
1/*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * ITE 8172 reset routines.
5 *
6 * Copyright 2001 MontaVista Software Inc.
7 * Author: MontaVista Software, Inc.
8 * ppopov@mvista.com or source@mvista.com
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
17 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
21 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
22 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * You should have received a copy of the GNU General Public License along
27 * with this program; if not, write to the Free Software Foundation, Inc.,
28 * 675 Mass Ave, Cambridge, MA 02139, USA.
29 */
30
31#include <linux/sched.h>
32#include <linux/mm.h>
33#include <asm/cacheflush.h>
34#include <asm/io.h>
35#include <asm/processor.h>
36#include <asm/reboot.h>
37#include <asm/system.h>
38
39void it8172_restart()
40{
41 set_c0_status(ST0_BEV | ST0_ERL);
42 change_c0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
43 flush_cache_all();
44 write_c0_wired(0);
45 __asm__ __volatile__("jr\t%0"::"r"(0xbfc00000));
46}
47
48void it8172_halt(void)
49{
50 printk(KERN_NOTICE "\n** You can safely turn off the power\n");
51 while (1)
52 __asm__(".set\tmips3\n\t"
53 "wait\n\t"
54 ".set\tmips0");
55}
56
57void it8172_power_off(void)
58{
59 it8172_halt();
60}
diff --git a/arch/mips/ite-boards/generic/time.c b/arch/mips/ite-boards/generic/time.c
new file mode 100644
index 000000000000..30a6c0d5fc50
--- /dev/null
+++ b/arch/mips/ite-boards/generic/time.c
@@ -0,0 +1,247 @@
1/*
2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
4 *
5 * Copyright (C) 2003 MontaVista Software Inc.
6 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
7 *
8 * ########################################################################
9 *
10 * This program is free software; you can distribute it and/or modify it
11 * under the terms of the GNU General Public License (Version 2) as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 * for more details.
18 *
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, write to the Free Software Foundation, Inc.,
21 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
22 *
23 * ########################################################################
24 *
25 * Setting up the clock on the MIPS boards.
26 */
27#include <linux/init.h>
28#include <linux/kernel_stat.h>
29#include <linux/sched.h>
30#include <linux/time.h>
31#include <linux/spinlock.h>
32
33#include <asm/time.h>
34#include <asm/mipsregs.h>
35#include <asm/ptrace.h>
36#include <asm/it8172/it8172.h>
37#include <asm/it8172/it8172_int.h>
38#include <asm/debug.h>
39
40#define IT8172_RTC_ADR_REG (IT8172_PCI_IO_BASE + IT_RTC_BASE)
41#define IT8172_RTC_DAT_REG (IT8172_RTC_ADR_REG + 1)
42#define IT8172_RTC_CENTURY_REG (IT8172_PCI_IO_BASE + IT_RTC_CENTURY)
43
44static volatile char *rtc_adr_reg = (char*)KSEG1ADDR(IT8172_RTC_ADR_REG);
45static volatile char *rtc_dat_reg = (char*)KSEG1ADDR(IT8172_RTC_DAT_REG);
46static volatile char *rtc_century_reg = (char*)KSEG1ADDR(IT8172_RTC_CENTURY_REG);
47
48unsigned char it8172_rtc_read_data(unsigned long addr)
49{
50 unsigned char retval;
51
52 *rtc_adr_reg = addr;
53 retval = *rtc_dat_reg;
54 return retval;
55}
56
57void it8172_rtc_write_data(unsigned char data, unsigned long addr)
58{
59 *rtc_adr_reg = addr;
60 *rtc_dat_reg = data;
61}
62
63#undef CMOS_READ
64#undef CMOS_WRITE
65#define CMOS_READ(addr) it8172_rtc_read_data(addr)
66#define CMOS_WRITE(data, addr) it8172_rtc_write_data(data, addr)
67
68static unsigned char saved_control; /* remember rtc control reg */
69static inline int rtc_24h(void) { return saved_control & RTC_24H; }
70static inline int rtc_dm_binary(void) { return saved_control & RTC_DM_BINARY; }
71
72static inline unsigned char
73bin_to_hw(unsigned char c)
74{
75 if (rtc_dm_binary())
76 return c;
77 else
78 return ((c/10) << 4) + (c%10);
79}
80
81static inline unsigned char
82hw_to_bin(unsigned char c)
83{
84 if (rtc_dm_binary())
85 return c;
86 else
87 return (c>>4)*10 + (c &0xf);
88}
89
90/* 0x80 bit indicates pm in 12-hour format */
91static inline unsigned char
92hour_bin_to_hw(unsigned char c)
93{
94 if (rtc_24h())
95 return bin_to_hw(c);
96 if (c >= 12)
97 return 0x80 | bin_to_hw((c==12)?12:c-12); /* 12 is 12pm */
98 else
99 return bin_to_hw((c==0)?12:c); /* 0 is 12 AM, not 0 am */
100}
101
102static inline unsigned char
103hour_hw_to_bin(unsigned char c)
104{
105 unsigned char tmp = hw_to_bin(c&0x3f);
106 if (rtc_24h())
107 return tmp;
108 if (c & 0x80)
109 return (tmp==12)?12:tmp+12; /* 12pm is 12, not 24 */
110 else
111 return (tmp==12)?0:tmp; /* 12am is 0 */
112}
113
114static unsigned long r4k_offset; /* Amount to increment compare reg each time */
115static unsigned long r4k_cur; /* What counter should be at next timer irq */
116extern unsigned int mips_hpt_frequency;
117
118/*
119 * Figure out the r4k offset, the amount to increment the compare
120 * register for each time tick.
121 * Use the RTC to calculate offset.
122 */
123static unsigned long __init cal_r4koff(void)
124{
125 unsigned int flags;
126
127 local_irq_save(flags);
128
129 /* Start counter exactly on falling edge of update flag */
130 while (CMOS_READ(RTC_REG_A) & RTC_UIP);
131 while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
132
133 /* Start r4k counter. */
134 write_c0_count(0);
135
136 /* Read counter exactly on falling edge of update flag */
137 while (CMOS_READ(RTC_REG_A) & RTC_UIP);
138 while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
139
140 mips_hpt_frequency = read_c0_count();
141
142 /* restore interrupts */
143 local_irq_restore(flags);
144
145 return (mips_hpt_frequency / HZ);
146}
147
148static unsigned long
149it8172_rtc_get_time(void)
150{
151 unsigned int year, mon, day, hour, min, sec;
152 unsigned int flags;
153
154 /* avoid update-in-progress. */
155 for (;;) {
156 local_irq_save(flags);
157 if (! (CMOS_READ(RTC_REG_A) & RTC_UIP))
158 break;
159 /* don't hold intr closed all the time */
160 local_irq_restore(flags);
161 }
162
163 /* Read regs. */
164 sec = hw_to_bin(CMOS_READ(RTC_SECONDS));
165 min = hw_to_bin(CMOS_READ(RTC_MINUTES));
166 hour = hour_hw_to_bin(CMOS_READ(RTC_HOURS));
167 day = hw_to_bin(CMOS_READ(RTC_DAY_OF_MONTH));
168 mon = hw_to_bin(CMOS_READ(RTC_MONTH));
169 year = hw_to_bin(CMOS_READ(RTC_YEAR)) +
170 hw_to_bin(*rtc_century_reg) * 100;
171
172 /* restore interrupts */
173 local_irq_restore(flags);
174
175 return mktime(year, mon, day, hour, min, sec);
176}
177
178static int
179it8172_rtc_set_time(unsigned long t)
180{
181 struct rtc_time tm;
182 unsigned int flags;
183
184 /* convert */
185 to_tm(t, &tm);
186
187 /* avoid update-in-progress. */
188 for (;;) {
189 local_irq_save(flags);
190 if (! (CMOS_READ(RTC_REG_A) & RTC_UIP))
191 break;
192 /* don't hold intr closed all the time */
193 local_irq_restore(flags);
194 }
195
196 *rtc_century_reg = bin_to_hw(tm.tm_year/100);
197 CMOS_WRITE(bin_to_hw(tm.tm_sec), RTC_SECONDS);
198 CMOS_WRITE(bin_to_hw(tm.tm_min), RTC_MINUTES);
199 CMOS_WRITE(hour_bin_to_hw(tm.tm_hour), RTC_HOURS);
200 CMOS_WRITE(bin_to_hw(tm.tm_mday), RTC_DAY_OF_MONTH);
201 CMOS_WRITE(bin_to_hw(tm.tm_mon+1), RTC_MONTH); /* tm_mon starts from 0 */
202 CMOS_WRITE(bin_to_hw(tm.tm_year%100), RTC_YEAR);
203
204 /* restore interrupts */
205 local_irq_restore(flags);
206
207 return 0;
208}
209
210void __init it8172_time_init(void)
211{
212 unsigned int est_freq, flags;
213
214 local_irq_save(flags);
215
216 saved_control = CMOS_READ(RTC_CONTROL);
217
218 printk("calculating r4koff... ");
219 r4k_offset = cal_r4koff();
220 printk("%08lx(%d)\n", r4k_offset, (int) r4k_offset);
221
222 est_freq = 2*r4k_offset*HZ;
223 est_freq += 5000; /* round */
224 est_freq -= est_freq%10000;
225 printk("CPU frequency %d.%02d MHz\n", est_freq/1000000,
226 (est_freq%1000000)*100/1000000);
227
228 local_irq_restore(flags);
229
230 rtc_get_time = it8172_rtc_get_time;
231 rtc_set_time = it8172_rtc_set_time;
232}
233
234#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
235void __init it8172_timer_setup(struct irqaction *irq)
236{
237 puts("timer_setup\n");
238 put32(NR_IRQS);
239 puts("");
240 /* we are using the cpu counter for timer interrupts */
241 setup_irq(MIPS_CPU_TIMER_IRQ, irq);
242
243 /* to generate the first timer interrupt */
244 r4k_cur = (read_c0_count() + r4k_offset);
245 write_c0_compare(r4k_cur);
246 set_c0_status(ALLINTS);
247}
diff --git a/arch/mips/ite-boards/ivr/Makefile b/arch/mips/ite-boards/ivr/Makefile
new file mode 100644
index 000000000000..e4fa6042b472
--- /dev/null
+++ b/arch/mips/ite-boards/ivr/Makefile
@@ -0,0 +1,10 @@
1#
2# Copyright 2000 MontaVista Software Inc.
3# Author: MontaVista Software, Inc.
4# ppopov@mvista.com or source@mvista.com
5#
6# Makefile for the Globespan IVR board,
7# board-specific files.
8#
9
10obj-y += init.o
diff --git a/arch/mips/ite-boards/ivr/README b/arch/mips/ite-boards/ivr/README
new file mode 100644
index 000000000000..aa7d8db855bb
--- /dev/null
+++ b/arch/mips/ite-boards/ivr/README
@@ -0,0 +1,3 @@
1This is not really a board made by ITE Semi, but it's very
2similar to the ITE QED-4N-S01B board. The IVR board is made
3by Globespan and it's a reference board for the PVR chip.
diff --git a/arch/mips/ite-boards/ivr/init.c b/arch/mips/ite-boards/ivr/init.c
new file mode 100644
index 000000000000..ea4e1935fec5
--- /dev/null
+++ b/arch/mips/ite-boards/ivr/init.c
@@ -0,0 +1,84 @@
1/*
2 * BRIEF MODULE DESCRIPTION
3 * IVR board setup.
4 *
5 * Copyright 2000 MontaVista Software Inc.
6 * Author: MontaVista Software, Inc.
7 * ppopov@mvista.com or source@mvista.com
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
15 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
17 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
20 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
21 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 *
25 * You should have received a copy of the GNU General Public License along
26 * with this program; if not, write to the Free Software Foundation, Inc.,
27 * 675 Mass Ave, Cambridge, MA 02139, USA.
28 */
29#include <linux/init.h>
30#include <linux/mm.h>
31#include <linux/sched.h>
32#include <linux/bootmem.h>
33#include <asm/addrspace.h>
34#include <asm/bootinfo.h>
35#include <linux/string.h>
36#include <linux/kernel.h>
37#include <asm/it8172/it8172.h>
38#include <asm/it8172/it8172_dbg.h>
39
40int prom_argc;
41char **prom_argv, **prom_envp;
42
43extern char _end;
44extern void __init prom_init_cmdline(void);
45extern unsigned long __init prom_get_memsize(void);
46extern void __init it8172_init_ram_resource(unsigned long memsize);
47
48#define PFN_UP(x) (((x) + PAGE_SIZE-1) >> PAGE_SHIFT)
49#define PFN_ALIGN(x) (((unsigned long)(x) + (PAGE_SIZE - 1)) & PAGE_MASK)
50
51const char *get_system_type(void)
52{
53 return "Globespan IVR";
54}
55
56void __init prom_init(void)
57{
58 unsigned long mem_size;
59 unsigned long pcicr;
60
61 prom_argc = fw_arg0;
62 prom_argv = (char **) fw_arg1;
63 prom_envp = (int *) fw_arg3;
64
65 mips_machgroup = MACH_GROUP_GLOBESPAN;
66 mips_machtype = MACH_IVR; /* Globespan's iTVC15 reference board */
67
68 prom_init_cmdline();
69
70 /* pmon does not set memsize */
71 mem_size = prom_get_memsize();
72 mem_size = mem_size << 20;
73
74 /*
75 * make the entire physical memory visible to pci bus masters
76 */
77 IT_READ(IT_MC_PCICR, pcicr);
78 pcicr &= ~0x1f;
79 pcicr |= (mem_size - 1) >> 22;
80 IT_WRITE(IT_MC_PCICR, pcicr);
81
82 it8172_init_ram_resource(mem_size);
83 add_memory_region(0, mem_size, BOOT_MEM_RAM);
84}
diff --git a/arch/mips/ite-boards/qed-4n-s01b/Makefile b/arch/mips/ite-boards/qed-4n-s01b/Makefile
new file mode 100644
index 000000000000..bb9972ad9c45
--- /dev/null
+++ b/arch/mips/ite-boards/qed-4n-s01b/Makefile
@@ -0,0 +1,10 @@
1#
2# Copyright 2000 MontaVista Software Inc.
3# Author: MontaVista Software, Inc.
4# ppopov@mvista.com or source@mvista.com
5#
6# Makefile for the ITE 8172 (qed-4n-s01b) board, board
7# specific files.
8#
9
10obj-y := init.o
diff --git a/arch/mips/ite-boards/qed-4n-s01b/README b/arch/mips/ite-boards/qed-4n-s01b/README
new file mode 100644
index 000000000000..fb4b5197e800
--- /dev/null
+++ b/arch/mips/ite-boards/qed-4n-s01b/README
@@ -0,0 +1,2 @@
1This is an ITE (www.iteusa.com) eval board for the ITE 8172G
2system controller, with a QED 5231 CPU.
diff --git a/arch/mips/ite-boards/qed-4n-s01b/init.c b/arch/mips/ite-boards/qed-4n-s01b/init.c
new file mode 100644
index 000000000000..56dca7e0c21d
--- /dev/null
+++ b/arch/mips/ite-boards/qed-4n-s01b/init.c
@@ -0,0 +1,85 @@
1/*
2 * BRIEF MODULE DESCRIPTION
3 * IT8172/QED5231 board setup.
4 *
5 * Copyright 2000 MontaVista Software Inc.
6 * Author: MontaVista Software, Inc.
7 * ppopov@mvista.com or source@mvista.com
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
15 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
17 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
20 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
21 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 *
25 * You should have received a copy of the GNU General Public License along
26 * with this program; if not, write to the Free Software Foundation, Inc.,
27 * 675 Mass Ave, Cambridge, MA 02139, USA.
28 */
29#include <linux/init.h>
30#include <linux/mm.h>
31#include <linux/sched.h>
32#include <linux/bootmem.h>
33#include <asm/addrspace.h>
34#include <asm/bootinfo.h>
35#include <linux/string.h>
36#include <linux/kernel.h>
37#include <asm/it8172/it8172.h>
38#include <asm/it8172/it8172_dbg.h>
39
40int prom_argc;
41char **prom_argv, **prom_envp;
42
43extern char _end;
44extern void __init prom_init_cmdline(void);
45extern unsigned long __init prom_get_memsize(void);
46extern void __init it8172_init_ram_resource(unsigned long memsize);
47
48#define PFN_UP(x) (((x) + PAGE_SIZE-1) >> PAGE_SHIFT)
49#define PFN_ALIGN(x) (((unsigned long)(x) + (PAGE_SIZE - 1)) & PAGE_MASK)
50
51const char *get_system_type(void)
52{
53 return "ITE QED-4N-S01B";
54}
55
56void __init prom_init(void)
57{
58 unsigned long mem_size;
59 unsigned long pcicr;
60
61 prom_argc = fw_arg0;
62 prom_argv = (char **) fw_arg1;
63 prom_envp = (int *) fw_arg3;
64
65 mips_machgroup = MACH_GROUP_ITE;
66 mips_machtype = MACH_QED_4N_S01B; /* ITE board name/number */
67
68 prom_init_cmdline();
69 mem_size = prom_get_memsize();
70
71 printk("Memory size: %dMB\n", (unsigned)mem_size);
72
73 mem_size <<= 20; /* MB */
74
75 /*
76 * make the entire physical memory visible to pci bus masters
77 */
78 IT_READ(IT_MC_PCICR, pcicr);
79 pcicr &= ~0x1f;
80 pcicr |= (mem_size - 1) >> 22;
81 IT_WRITE(IT_MC_PCICR, pcicr);
82
83 it8172_init_ram_resource(mem_size);
84 add_memory_region(0, mem_size, BOOT_MEM_RAM);
85}
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-22 19:10:01 -0500