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-rw-r--r--arch/mips/ite-boards/Kconfig8
-rw-r--r--arch/mips/ite-boards/generic/Makefile15
-rw-r--r--arch/mips/ite-boards/generic/dbg_io.c124
-rw-r--r--arch/mips/ite-boards/generic/irq.c308
-rw-r--r--arch/mips/ite-boards/generic/it8172_cir.c170
-rw-r--r--arch/mips/ite-boards/generic/it8172_setup.c352
-rw-r--r--arch/mips/ite-boards/generic/lpc.c144
-rw-r--r--arch/mips/ite-boards/generic/pmon_prom.c135
-rw-r--r--arch/mips/ite-boards/generic/puts.c139
-rw-r--r--arch/mips/ite-boards/generic/reset.c60
-rw-r--r--arch/mips/ite-boards/generic/time.c249
-rw-r--r--arch/mips/ite-boards/ivr/Makefile10
-rw-r--r--arch/mips/ite-boards/ivr/README3
-rw-r--r--arch/mips/ite-boards/ivr/init.c81
-rw-r--r--arch/mips/ite-boards/qed-4n-s01b/Makefile10
-rw-r--r--arch/mips/ite-boards/qed-4n-s01b/README2
-rw-r--r--arch/mips/ite-boards/qed-4n-s01b/init.c82
17 files changed, 0 insertions, 1892 deletions
diff --git a/arch/mips/ite-boards/Kconfig b/arch/mips/ite-boards/Kconfig
deleted file mode 100644
index a6d59ad8f846..000000000000
--- a/arch/mips/ite-boards/Kconfig
+++ /dev/null
@@ -1,8 +0,0 @@
1config IT8172_REVC
2 bool "Support for older IT8172 (Rev C)"
3 depends on MIPS_ITE8172
4 help
5 Say Y here to support the older, Revision C version of the Integrated
6 Technology Express, Inc. ITE8172 SBC. Vendor page at
7 <http://www.ite.com.tw/ia/brief_it8172bsp.htm>; picture of the
8 board at <http://www.mvista.com/partners/semiconductor/ite.html>.
diff --git a/arch/mips/ite-boards/generic/Makefile b/arch/mips/ite-boards/generic/Makefile
deleted file mode 100644
index 63431538d0ec..000000000000
--- a/arch/mips/ite-boards/generic/Makefile
+++ /dev/null
@@ -1,15 +0,0 @@
1#
2# Copyright 2000 MontaVista Software Inc.
3# Author: MontaVista Software, Inc.
4# ppopov@mvista.com or source@mvista.com
5#
6# Makefile for the ITE 8172 (qed-4n-s01b) board, generic files.
7#
8
9obj-y += it8172_setup.o irq.o pmon_prom.o \
10 time.o lpc.o puts.o reset.o
11
12obj-$(CONFIG_IT8172_CIR)+= it8172_cir.o
13obj-$(CONFIG_KGDB) += dbg_io.o
14
15EXTRA_AFLAGS := $(CFLAGS)
diff --git a/arch/mips/ite-boards/generic/dbg_io.c b/arch/mips/ite-boards/generic/dbg_io.c
deleted file mode 100644
index 8e9cd8a9670a..000000000000
--- a/arch/mips/ite-boards/generic/dbg_io.c
+++ /dev/null
@@ -1,124 +0,0 @@
1
2
3#ifdef CONFIG_KGDB
4
5/* --- CONFIG --- */
6
7/* we need uint32 uint8 */
8/* #include "types.h" */
9typedef unsigned char uint8;
10typedef unsigned int uint32;
11
12/* --- END OF CONFIG --- */
13
14#define UART16550_BAUD_2400 2400
15#define UART16550_BAUD_4800 4800
16#define UART16550_BAUD_9600 9600
17#define UART16550_BAUD_19200 19200
18#define UART16550_BAUD_38400 38400
19#define UART16550_BAUD_57600 57600
20#define UART16550_BAUD_115200 115200
21
22#define UART16550_PARITY_NONE 0
23#define UART16550_PARITY_ODD 0x08
24#define UART16550_PARITY_EVEN 0x18
25#define UART16550_PARITY_MARK 0x28
26#define UART16550_PARITY_SPACE 0x38
27
28#define UART16550_DATA_5BIT 0x0
29#define UART16550_DATA_6BIT 0x1
30#define UART16550_DATA_7BIT 0x2
31#define UART16550_DATA_8BIT 0x3
32
33#define UART16550_STOP_1BIT 0x0
34#define UART16550_STOP_2BIT 0x4
35
36/* ----------------------------------------------------- */
37
38/* === CONFIG === */
39
40/* [stevel] we use the IT8712 serial port for kgdb */
41#define DEBUG_BASE 0xB40003F8 /* 8712 serial port 1 base address */
42#define MAX_BAUD 115200
43
44/* === END OF CONFIG === */
45
46/* register offset */
47#define OFS_RCV_BUFFER 0
48#define OFS_TRANS_HOLD 0
49#define OFS_SEND_BUFFER 0
50#define OFS_INTR_ENABLE 1
51#define OFS_INTR_ID 2
52#define OFS_DATA_FORMAT 3
53#define OFS_LINE_CONTROL 3
54#define OFS_MODEM_CONTROL 4
55#define OFS_RS232_OUTPUT 4
56#define OFS_LINE_STATUS 5
57#define OFS_MODEM_STATUS 6
58#define OFS_RS232_INPUT 6
59#define OFS_SCRATCH_PAD 7
60
61#define OFS_DIVISOR_LSB 0
62#define OFS_DIVISOR_MSB 1
63
64
65/* memory-mapped read/write of the port */
66#define UART16550_READ(y) (*((volatile uint8*)(DEBUG_BASE + y)))
67#define UART16550_WRITE(y,z) ((*((volatile uint8*)(DEBUG_BASE + y))) = z)
68
69void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop)
70{
71 /* disable interrupts */
72 UART16550_WRITE(OFS_INTR_ENABLE, 0);
73
74 /* set up baud rate */
75 {
76 uint32 divisor;
77
78 /* set DIAB bit */
79 UART16550_WRITE(OFS_LINE_CONTROL, 0x80);
80
81 /* set divisor */
82 divisor = MAX_BAUD / baud;
83 UART16550_WRITE(OFS_DIVISOR_LSB, divisor & 0xff);
84 UART16550_WRITE(OFS_DIVISOR_MSB, (divisor & 0xff00) >> 8);
85
86 /* clear DIAB bit */
87 UART16550_WRITE(OFS_LINE_CONTROL, 0x0);
88 }
89
90 /* set data format */
91 UART16550_WRITE(OFS_DATA_FORMAT, data | parity | stop);
92}
93
94static int remoteDebugInitialized = 0;
95
96uint8 getDebugChar(void)
97{
98 if (!remoteDebugInitialized) {
99 remoteDebugInitialized = 1;
100 debugInit(UART16550_BAUD_115200,
101 UART16550_DATA_8BIT,
102 UART16550_PARITY_NONE, UART16550_STOP_1BIT);
103 }
104
105 while ((UART16550_READ(OFS_LINE_STATUS) & 0x1) == 0);
106 return UART16550_READ(OFS_RCV_BUFFER);
107}
108
109
110int putDebugChar(uint8 byte)
111{
112 if (!remoteDebugInitialized) {
113 remoteDebugInitialized = 1;
114 debugInit(UART16550_BAUD_115200,
115 UART16550_DATA_8BIT,
116 UART16550_PARITY_NONE, UART16550_STOP_1BIT);
117 }
118
119 while ((UART16550_READ(OFS_LINE_STATUS) & 0x20) == 0);
120 UART16550_WRITE(OFS_SEND_BUFFER, byte);
121 return 1;
122}
123
124#endif
diff --git a/arch/mips/ite-boards/generic/irq.c b/arch/mips/ite-boards/generic/irq.c
deleted file mode 100644
index cb59ca4f76f0..000000000000
--- a/arch/mips/ite-boards/generic/irq.c
+++ /dev/null
@@ -1,308 +0,0 @@
1/*
2 * BRIEF MODULE DESCRIPTION
3 * ITE 8172G interrupt/setup routines.
4 *
5 * Copyright 2000,2001 MontaVista Software Inc.
6 * Author: MontaVista Software, Inc.
7 * ppopov@mvista.com or source@mvista.com
8 *
9 * Part of this file was derived from Carsten Langgaard's
10 * arch/mips/mips-boards/atlas/atlas_int.c.
11 *
12 * Carsten Langgaard, carstenl@mips.com
13 * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
14 *
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
19 *
20 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
21 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
23 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
26 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
27 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 *
31 * You should have received a copy of the GNU General Public License along
32 * with this program; if not, write to the Free Software Foundation, Inc.,
33 * 675 Mass Ave, Cambridge, MA 02139, USA.
34 */
35#include <linux/errno.h>
36#include <linux/init.h>
37#include <linux/irq.h>
38#include <linux/kernel_stat.h>
39#include <linux/module.h>
40#include <linux/signal.h>
41#include <linux/sched.h>
42#include <linux/types.h>
43#include <linux/interrupt.h>
44#include <linux/ioport.h>
45#include <linux/timex.h>
46#include <linux/slab.h>
47#include <linux/random.h>
48#include <linux/serial_reg.h>
49#include <linux/bitops.h>
50
51#include <asm/bootinfo.h>
52#include <asm/io.h>
53#include <asm/mipsregs.h>
54#include <asm/system.h>
55#include <asm/it8172/it8172.h>
56#include <asm/it8172/it8172_int.h>
57#include <asm/it8172/it8172_dbg.h>
58
59/* revisit */
60#define EXT_IRQ0_TO_IP 2 /* IP 2 */
61#define EXT_IRQ5_TO_IP 7 /* IP 7 */
62
63#define ALLINTS_NOTIMER (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4)
64
65extern void set_debug_traps(void);
66extern void mips_timer_interrupt(int irq, struct pt_regs *regs);
67
68struct it8172_intc_regs volatile *it8172_hw0_icregs =
69 (struct it8172_intc_regs volatile *)(KSEG1ADDR(IT8172_PCI_IO_BASE + IT_INTC_BASE));
70
71static void disable_it8172_irq(unsigned int irq_nr)
72{
73 if ( (irq_nr >= IT8172_LPC_IRQ_BASE) && (irq_nr <= IT8172_SERIRQ_15)) {
74 /* LPC interrupt */
75 it8172_hw0_icregs->lpc_mask |=
76 (1 << (irq_nr - IT8172_LPC_IRQ_BASE));
77 } else if ( (irq_nr >= IT8172_LB_IRQ_BASE) && (irq_nr <= IT8172_IOCHK_IRQ)) {
78 /* Local Bus interrupt */
79 it8172_hw0_icregs->lb_mask |=
80 (1 << (irq_nr - IT8172_LB_IRQ_BASE));
81 } else if ( (irq_nr >= IT8172_PCI_DEV_IRQ_BASE) && (irq_nr <= IT8172_DMA_IRQ)) {
82 /* PCI and other interrupts */
83 it8172_hw0_icregs->pci_mask |=
84 (1 << (irq_nr - IT8172_PCI_DEV_IRQ_BASE));
85 } else if ( (irq_nr >= IT8172_NMI_IRQ_BASE) && (irq_nr <= IT8172_POWER_NMI_IRQ)) {
86 /* NMI interrupts */
87 it8172_hw0_icregs->nmi_mask |=
88 (1 << (irq_nr - IT8172_NMI_IRQ_BASE));
89 } else {
90 panic("disable_it8172_irq: bad irq %d", irq_nr);
91 }
92}
93
94static void enable_it8172_irq(unsigned int irq_nr)
95{
96 if ( (irq_nr >= IT8172_LPC_IRQ_BASE) && (irq_nr <= IT8172_SERIRQ_15)) {
97 /* LPC interrupt */
98 it8172_hw0_icregs->lpc_mask &=
99 ~(1 << (irq_nr - IT8172_LPC_IRQ_BASE));
100 }
101 else if ( (irq_nr >= IT8172_LB_IRQ_BASE) && (irq_nr <= IT8172_IOCHK_IRQ)) {
102 /* Local Bus interrupt */
103 it8172_hw0_icregs->lb_mask &=
104 ~(1 << (irq_nr - IT8172_LB_IRQ_BASE));
105 }
106 else if ( (irq_nr >= IT8172_PCI_DEV_IRQ_BASE) && (irq_nr <= IT8172_DMA_IRQ)) {
107 /* PCI and other interrupts */
108 it8172_hw0_icregs->pci_mask &=
109 ~(1 << (irq_nr - IT8172_PCI_DEV_IRQ_BASE));
110 }
111 else if ( (irq_nr >= IT8172_NMI_IRQ_BASE) && (irq_nr <= IT8172_POWER_NMI_IRQ)) {
112 /* NMI interrupts */
113 it8172_hw0_icregs->nmi_mask &=
114 ~(1 << (irq_nr - IT8172_NMI_IRQ_BASE));
115 }
116 else {
117 panic("enable_it8172_irq: bad irq %d", irq_nr);
118 }
119}
120
121static unsigned int startup_ite_irq(unsigned int irq)
122{
123 enable_it8172_irq(irq);
124 return 0;
125}
126
127#define shutdown_ite_irq disable_it8172_irq
128#define mask_and_ack_ite_irq disable_it8172_irq
129
130static void end_ite_irq(unsigned int irq)
131{
132 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
133 enable_it8172_irq(irq);
134}
135
136static struct irq_chip it8172_irq_type = {
137 .typename = "ITE8172",
138 .startup = startup_ite_irq,
139 .shutdown = shutdown_ite_irq,
140 .enable = enable_it8172_irq,
141 .disable = disable_it8172_irq,
142 .ack = mask_and_ack_ite_irq,
143 .end = end_ite_irq,
144};
145
146
147static void enable_none(unsigned int irq) { }
148static unsigned int startup_none(unsigned int irq) { return 0; }
149static void disable_none(unsigned int irq) { }
150static void ack_none(unsigned int irq) { }
151
152/* startup is the same as "enable", shutdown is same as "disable" */
153#define shutdown_none disable_none
154#define end_none enable_none
155
156static struct irq_chip cp0_irq_type = {
157 .typename = "CP0 Count",
158 .startup = startup_none,
159 .shutdown = shutdown_none,
160 .enable = enable_none,
161 .disable = disable_none,
162 .ack = ack_none,
163 .end = end_none
164};
165
166void enable_cpu_timer(void)
167{
168 unsigned long flags;
169
170 local_irq_save(flags);
171 set_c0_status(0x100 << EXT_IRQ5_TO_IP);
172 local_irq_restore(flags);
173}
174
175void __init arch_init_irq(void)
176{
177 int i;
178 unsigned long flags;
179
180 /* mask all interrupts */
181 it8172_hw0_icregs->lb_mask = 0xffff;
182 it8172_hw0_icregs->lpc_mask = 0xffff;
183 it8172_hw0_icregs->pci_mask = 0xffff;
184 it8172_hw0_icregs->nmi_mask = 0xffff;
185
186 /* make all interrupts level triggered */
187 it8172_hw0_icregs->lb_trigger = 0;
188 it8172_hw0_icregs->lpc_trigger = 0;
189 it8172_hw0_icregs->pci_trigger = 0;
190 it8172_hw0_icregs->nmi_trigger = 0;
191
192 /* active level setting */
193 /* uart, keyboard, and mouse are active high */
194 it8172_hw0_icregs->lpc_level = (0x10 | 0x2 | 0x1000);
195 it8172_hw0_icregs->lb_level |= 0x20;
196
197 /* keyboard and mouse are edge triggered */
198 it8172_hw0_icregs->lpc_trigger |= (0x2 | 0x1000);
199
200
201#if 0
202 // Enable this piece of code to make internal USB interrupt
203 // edge triggered.
204 it8172_hw0_icregs->pci_trigger |=
205 (1 << (IT8172_USB_IRQ - IT8172_PCI_DEV_IRQ_BASE));
206 it8172_hw0_icregs->pci_level &=
207 ~(1 << (IT8172_USB_IRQ - IT8172_PCI_DEV_IRQ_BASE));
208#endif
209
210 for (i = 0; i <= IT8172_LAST_IRQ; i++) {
211 irq_desc[i].chip = &it8172_irq_type;
212 spin_lock_init(&irq_desc[i].lock);
213 }
214 irq_desc[MIPS_CPU_TIMER_IRQ].chip = &cp0_irq_type;
215 set_c0_status(ALLINTS_NOTIMER);
216}
217
218void mips_spurious_interrupt(struct pt_regs *regs)
219{
220#if 1
221 return;
222#else
223 unsigned long status, cause;
224
225 printk("got spurious interrupt\n");
226 status = read_c0_status();
227 cause = read_c0_cause();
228 printk("status %x cause %x\n", status, cause);
229 printk("epc %x badvaddr %x \n", regs->cp0_epc, regs->cp0_badvaddr);
230#endif
231}
232
233void it8172_hw0_irqdispatch(struct pt_regs *regs)
234{
235 int irq;
236 unsigned short intstatus = 0, status = 0;
237
238 intstatus = it8172_hw0_icregs->intstatus;
239 if (intstatus & 0x8) {
240 panic("Got NMI interrupt");
241 } else if (intstatus & 0x4) {
242 /* PCI interrupt */
243 irq = 0;
244 status |= it8172_hw0_icregs->pci_req;
245 while (!(status & 0x1)) {
246 irq++;
247 status >>= 1;
248 }
249 irq += IT8172_PCI_DEV_IRQ_BASE;
250 } else if (intstatus & 0x1) {
251 /* Local Bus interrupt */
252 irq = 0;
253 status |= it8172_hw0_icregs->lb_req;
254 while (!(status & 0x1)) {
255 irq++;
256 status >>= 1;
257 }
258 irq += IT8172_LB_IRQ_BASE;
259 } else if (intstatus & 0x2) {
260 /* LPC interrupt */
261 /* Since some lpc interrupts are edge triggered,
262 * we could lose an interrupt this way because
263 * we acknowledge all ints at onces. Revisit.
264 */
265 status |= it8172_hw0_icregs->lpc_req;
266 it8172_hw0_icregs->lpc_req = 0; /* acknowledge ints */
267 irq = 0;
268 while (!(status & 0x1)) {
269 irq++;
270 status >>= 1;
271 }
272 irq += IT8172_LPC_IRQ_BASE;
273 } else
274 return;
275
276 do_IRQ(irq, regs);
277}
278
279asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
280{
281 unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
282
283 if (!pending)
284 mips_spurious_interrupt(regs);
285 else if (pending & CAUSEF_IP7)
286 ll_timer_interrupt(127, regs);
287 else if (pending & CAUSEF_IP2)
288 it8172_hw0_irqdispatch(regs);
289}
290
291void show_pending_irqs(void)
292{
293 fputs("intstatus: ");
294 put32(it8172_hw0_icregs->intstatus);
295 puts("");
296
297 fputs("pci_req: ");
298 put32(it8172_hw0_icregs->pci_req);
299 puts("");
300
301 fputs("lb_req: ");
302 put32(it8172_hw0_icregs->lb_req);
303 puts("");
304
305 fputs("lpc_req: ");
306 put32(it8172_hw0_icregs->lpc_req);
307 puts("");
308}
diff --git a/arch/mips/ite-boards/generic/it8172_cir.c b/arch/mips/ite-boards/generic/it8172_cir.c
deleted file mode 100644
index bfc25adcfec6..000000000000
--- a/arch/mips/ite-boards/generic/it8172_cir.c
+++ /dev/null
@@ -1,170 +0,0 @@
1/*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * IT8172 Consumer IR port generic routines.
5 *
6 * Copyright 2001 MontaVista Software Inc.
7 * Author: MontaVista Software, Inc.
8 * ppopov@mvista.com or source@mvista.com
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
17 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
21 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
22 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * You should have received a copy of the GNU General Public License along
27 * with this program; if not, write to the Free Software Foundation, Inc.,
28 * 675 Mass Ave, Cambridge, MA 02139, USA.
29 */
30
31
32#ifdef CONFIG_IT8172_CIR
33
34#include <linux/types.h>
35#include <linux/pci.h>
36#include <linux/kernel.h>
37#include <linux/init.h>
38
39#include <asm/it8172/it8172.h>
40#include <asm/it8172/it8172_cir.h>
41
42
43volatile struct it8172_cir_regs *cir_regs[NUM_CIR_PORTS] = {
44 (volatile struct it8172_cir_regs *)(KSEG1ADDR(IT8172_PCI_IO_BASE + IT_CIR0_BASE)),
45 (volatile struct it8172_cir_regs *)(KSEG1ADDR(IT8172_PCI_IO_BASE + IT_CIR1_BASE))};
46
47
48/*
49 * Initialize Consumer IR Port.
50 */
51int cir_port_init(struct cir_port *cir)
52{
53 int port = cir->port;
54 unsigned char data;
55
56 /* set baud rate */
57 cir_regs[port]->bdlr = cir->baud_rate & 0xff;
58 cir_regs[port]->bdhr = (cir->baud_rate >> 8) & 0xff;
59
60 /* set receiver control register */
61 cir_regs[port]->rcr = (CIR_SET_RDWOS(cir->rdwos) | CIR_SET_RXDCR(cir->rxdcr));
62
63 /* set carrier frequency register */
64 cir_regs[port]->cfr = (CIR_SET_CF(cir->cfq) | CIR_SET_HS(cir->hcfs));
65
66 /* set fifo threshold */
67 data = cir_regs[port]->mstcr & 0xf3;
68 data |= CIR_SET_FIFO_TL(cir->fifo_tl);
69 cir_regs[port]->mstcr = data;
70
71 clear_fifo(cir);
72 enable_receiver(cir);
73 disable_rx_demodulation(cir);
74
75 set_rx_active(cir);
76 int_enable(cir);
77 rx_int_enable(cir);
78
79 return 0;
80}
81
82
83void clear_fifo(struct cir_port *cir)
84{
85 cir_regs[cir->port]->mstcr |= CIR_FIFO_CLEAR;
86}
87
88void enable_receiver(struct cir_port *cir)
89{
90 cir_regs[cir->port]->rcr |= CIR_RXEN;
91}
92
93void disable_receiver(struct cir_port *cir)
94{
95 cir_regs[cir->port]->rcr &= ~CIR_RXEN;
96}
97
98void enable_rx_demodulation(struct cir_port *cir)
99{
100 cir_regs[cir->port]->rcr |= CIR_RXEND;
101}
102
103void disable_rx_demodulation(struct cir_port *cir)
104{
105 cir_regs[cir->port]->rcr &= ~CIR_RXEND;
106}
107
108void set_rx_active(struct cir_port *cir)
109{
110 cir_regs[cir->port]->rcr |= CIR_RXACT;
111}
112
113void int_enable(struct cir_port *cir)
114{
115 cir_regs[cir->port]->ier |= CIR_IEC;
116}
117
118void rx_int_enable(struct cir_port *cir)
119{
120 cir_regs[cir->port]->ier |= CIR_RDAIE;
121}
122
123void dump_regs(struct cir_port *cir)
124{
125 printk("mstcr %x ier %x iir %x cfr %x rcr %x tcr %x tfsr %x rfsr %x\n",
126 cir_regs[cir->port]->mstcr,
127 cir_regs[cir->port]->ier,
128 cir_regs[cir->port]->iir,
129 cir_regs[cir->port]->cfr,
130 cir_regs[cir->port]->rcr,
131 cir_regs[cir->port]->tcr,
132 cir_regs[cir->port]->tfsr,
133 cir_regs[cir->port]->rfsr);
134
135 while (cir_regs[cir->port]->iir & CIR_RDAI) {
136 printk("data %x\n", cir_regs[cir->port]->dr);
137 }
138}
139
140void dump_reg_addr(struct cir_port *cir)
141{
142 printk("dr %x mstcr %x ier %x iir %x cfr %x rcr %x tcr %x bdlr %x bdhr %x tfsr %x rfsr %x\n",
143 (unsigned)&cir_regs[cir->port]->dr,
144 (unsigned)&cir_regs[cir->port]->mstcr,
145 (unsigned)&cir_regs[cir->port]->ier,
146 (unsigned)&cir_regs[cir->port]->iir,
147 (unsigned)&cir_regs[cir->port]->cfr,
148 (unsigned)&cir_regs[cir->port]->rcr,
149 (unsigned)&cir_regs[cir->port]->tcr,
150 (unsigned)&cir_regs[cir->port]->bdlr,
151 (unsigned)&cir_regs[cir->port]->bdhr,
152 (unsigned)&cir_regs[cir->port]->tfsr,
153 (unsigned)&cir_regs[cir->port]->rfsr);
154}
155
156int cir_get_rx_count(struct cir_port *cir)
157{
158 return cir_regs[cir->port]->rfsr & CIR_RXFBC_MASK;
159}
160
161char cir_read_data(struct cir_port *cir)
162{
163 return cir_regs[cir->port]->dr;
164}
165
166char get_int_status(struct cir_port *cir)
167{
168 return cir_regs[cir->port]->iir;
169}
170#endif
diff --git a/arch/mips/ite-boards/generic/it8172_setup.c b/arch/mips/ite-boards/generic/it8172_setup.c
deleted file mode 100644
index 07faf3cacff2..000000000000
--- a/arch/mips/ite-boards/generic/it8172_setup.c
+++ /dev/null
@@ -1,352 +0,0 @@
1/*
2 * BRIEF MODULE DESCRIPTION
3 * IT8172/QED5231 board setup.
4 *
5 * Copyright 2000 MontaVista Software Inc.
6 * Author: MontaVista Software, Inc.
7 * ppopov@mvista.com or source@mvista.com
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
15 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
17 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
20 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
21 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 *
25 * You should have received a copy of the GNU General Public License along
26 * with this program; if not, write to the Free Software Foundation, Inc.,
27 * 675 Mass Ave, Cambridge, MA 02139, USA.
28 */
29#include <linux/init.h>
30#include <linux/sched.h>
31#include <linux/ioport.h>
32#include <linux/irq.h>
33#include <linux/serial_reg.h>
34#include <linux/major.h>
35#include <linux/kdev_t.h>
36#include <linux/root_dev.h>
37#include <linux/pm.h>
38
39#include <asm/cpu.h>
40#include <asm/time.h>
41#include <asm/io.h>
42#include <asm/bootinfo.h>
43#include <asm/irq.h>
44#include <asm/mipsregs.h>
45#include <asm/reboot.h>
46#include <asm/traps.h>
47#include <asm/it8172/it8172.h>
48#include <asm/it8712.h>
49
50extern struct resource ioport_resource;
51#ifdef CONFIG_SERIO_I8042
52int init_8712_keyboard(void);
53#endif
54
55extern int SearchIT8712(void);
56extern void InitLPCInterface(void);
57extern char * __init prom_getcmdline(void);
58extern void it8172_restart(char *command);
59extern void it8172_halt(void);
60extern void it8172_power_off(void);
61
62extern void it8172_time_init(void);
63
64#ifdef CONFIG_IT8172_REVC
65struct {
66 struct resource ram;
67 struct resource pci_mem;
68 struct resource pci_io;
69 struct resource flash;
70 struct resource boot;
71} it8172_resources = {
72 {
73 .start = 0, /* to be initted */
74 .end = 0,
75 .name = "RAM",
76 .flags = IORESOURCE_MEM
77 }, {
78 .start = 0x10000000,
79 .end = 0x13FFFFFF,
80 .name = "PCI Mem",
81 .flags = IORESOURCE_MEM
82 }, {
83 .start = 0x14000000,
84 .end = 0x17FFFFFF
85 .name = "PCI I/O",
86 }, {
87 .start = 0x08000000,
88 .end = 0x0CFFFFFF
89 .name = "Flash",
90 }, {
91 .start = 0x1FC00000,
92 .end = 0x1FFFFFFF
93 .name = "Boot ROM",
94 }
95};
96#else
97struct {
98 struct resource ram;
99 struct resource pci_mem0;
100 struct resource pci_mem1;
101 struct resource pci_io;
102 struct resource pci_mem2;
103 struct resource pci_mem3;
104 struct resource flash;
105 struct resource boot;
106} it8172_resources = {
107 {
108 .start = 0, /* to be initted */
109 .end = 0,
110 .name = "RAM",
111 .flags = IORESOURCE_MEM
112 }, {
113 .start = 0x0C000000,
114 .end = 0x0FFFFFFF,
115 .name = "PCI Mem0",
116 .flags = IORESOURCE_MEM
117 }, {
118 .start = 0x10000000,
119 .end = 0x13FFFFFF,
120 .name = "PCI Mem1",
121 .flags = IORESOURCE_MEM
122 }, {
123 .start = 0x14000000,
124 .end = 0x17FFFFFF
125 .name = "PCI I/O",
126 }, {
127 .start = 0x1A000000,
128 .end = 0x1BFFFFFF,
129 .name = "PCI Mem2",
130 .flags = IORESOURCE_MEM
131 }, {
132 .start = 0x1C000000,
133 .end = 0x1FBFFFFF,
134 .name = "PCI Mem3",
135 .flags = IORESOURCE_MEM
136 }, {
137 .start = 0x08000000,
138 .end = 0x0CFFFFFF
139 .name = "Flash",
140 }, {
141 .start = 0x1FC00000,
142 .end = 0x1FFFFFFF
143 .name = "Boot ROM",
144 }
145};
146#endif
147
148
149void __init it8172_init_ram_resource(unsigned long memsize)
150{
151 it8172_resources.ram.end = memsize;
152}
153
154void __init plat_mem_setup(void)
155{
156 unsigned short dsr;
157 char *argptr;
158
159 argptr = prom_getcmdline();
160#ifdef CONFIG_SERIAL_CONSOLE
161 if ((argptr = strstr(argptr, "console=")) == NULL) {
162 argptr = prom_getcmdline();
163 strcat(argptr, " console=ttyS0,115200");
164 }
165#endif
166
167 clear_c0_status(ST0_FR);
168
169 board_time_init = it8172_time_init;
170
171 _machine_restart = it8172_restart;
172 _machine_halt = it8172_halt;
173 pm_power_off = it8172_power_off;
174
175 /*
176 * IO/MEM resources.
177 *
178 * revisit this area.
179 */
180 set_io_port_base(KSEG1);
181 ioport_resource.start = it8172_resources.pci_io.start;
182 ioport_resource.end = it8172_resources.pci_io.end;
183#ifdef CONFIG_IT8172_REVC
184 iomem_resource.start = it8172_resources.pci_mem.start;
185 iomem_resource.end = it8172_resources.pci_mem.end;
186#else
187 iomem_resource.start = it8172_resources.pci_mem0.start;
188 iomem_resource.end = it8172_resources.pci_mem3.end;
189#endif
190
191#ifdef CONFIG_BLK_DEV_INITRD
192 ROOT_DEV = Root_RAM0;
193#endif
194
195 /*
196 * Pull enabled devices out of standby
197 */
198 IT_IO_READ16(IT_PM_DSR, dsr);
199
200 /*
201 * Fixme: This breaks when these drivers are modules!!!
202 */
203#ifdef CONFIG_SOUND_IT8172
204 dsr &= ~IT_PM_DSR_ACSB;
205#else
206 dsr |= IT_PM_DSR_ACSB;
207#endif
208#ifdef CONFIG_BLK_DEV_IT8172
209 dsr &= ~IT_PM_DSR_IDESB;
210#else
211 dsr |= IT_PM_DSR_IDESB;
212#endif
213 IT_IO_WRITE16(IT_PM_DSR, dsr);
214
215 InitLPCInterface();
216
217#ifdef CONFIG_MIPS_ITE8172
218 if (SearchIT8712()) {
219 printk("Found IT8712 Super IO\n");
220 /* enable IT8712 serial port */
221 LPCSetConfig(LDN_SERIAL1, 0x30, 0x01); /* enable */
222 LPCSetConfig(LDN_SERIAL1, 0x23, 0x01); /* clock selection */
223#ifdef CONFIG_SERIO_I8042
224 if (init_8712_keyboard()) {
225 printk("Unable to initialize keyboard\n");
226 LPCSetConfig(LDN_KEYBOARD, 0x30, 0x0); /* disable keyboard */
227 } else {
228 LPCSetConfig(LDN_KEYBOARD, 0x30, 0x1); /* enable keyboard */
229 LPCSetConfig(LDN_KEYBOARD, 0xf0, 0x2);
230 LPCSetConfig(LDN_KEYBOARD, 0x71, 0x3);
231
232 LPCSetConfig(LDN_MOUSE, 0x30, 0x1); /* enable mouse */
233
234 LPCSetConfig(0x4, 0x30, 0x1);
235 LPCSetConfig(0x4, 0xf4, LPCGetConfig(0x4, 0xf4) | 0x80);
236
237 if ((LPCGetConfig(LDN_KEYBOARD, 0x30) == 0) ||
238 (LPCGetConfig(LDN_MOUSE, 0x30) == 0))
239 printk("Error: keyboard or mouse not enabled\n");
240
241 }
242#endif
243 }
244 else {
245 printk("IT8712 Super IO not found\n");
246 }
247#endif
248
249#ifdef CONFIG_IT8172_CIR
250 {
251 unsigned long data;
252 //printk("Enabling CIR0\n");
253 IT_IO_READ16(IT_PM_DSR, data);
254 data &= ~IT_PM_DSR_CIR0SB;
255 IT_IO_WRITE16(IT_PM_DSR, data);
256 //printk("DSR register: %x\n", (unsigned)IT_IO_READ16(IT_PM_DSR, data));
257 }
258#endif
259#ifdef CONFIG_IT8172_SCR0
260 {
261 unsigned i;
262 /* Enable Smart Card Reader 0 */
263 /* First power it up */
264 IT_IO_READ16(IT_PM_DSR, i);
265 i &= ~IT_PM_DSR_SCR0SB;
266 IT_IO_WRITE16(IT_PM_DSR, i);
267 /* Then initialize its registers */
268 outb(( IT_SCR_SFR_GATE_UART_OFF << IT_SCR_SFR_GATE_UART_BIT
269 |IT_SCR_SFR_FET_CHARGE_213_US << IT_SCR_SFR_FET_CHARGE_BIT
270 |IT_SCR_SFR_CARD_FREQ_3_5_MHZ << IT_SCR_SFR_CARD_FREQ_BIT
271 |IT_SCR_SFR_FET_ACTIVE_INVERT << IT_SCR_SFR_FET_ACTIVE_BIT
272 |IT_SCR_SFR_ENABLE_ON << IT_SCR_SFR_ENABLE_BIT),
273 IT8172_PCI_IO_BASE + IT_SCR0_BASE + IT_SCR_SFR);
274 outb(IT_SCR_SCDR_RESET_MODE_ASYNC << IT_SCR_SCDR_RESET_MODE_BIT,
275 IT8172_PCI_IO_BASE + IT_SCR0_BASE + IT_SCR_SCDR);
276 }
277#endif /* CONFIG_IT8172_SCR0 */
278#ifdef CONFIG_IT8172_SCR1
279 {
280 unsigned i;
281 /* Enable Smart Card Reader 1 */
282 /* First power it up */
283 IT_IO_READ16(IT_PM_DSR, i);
284 i &= ~IT_PM_DSR_SCR1SB;
285 IT_IO_WRITE16(IT_PM_DSR, i);
286 /* Then initialize its registers */
287 outb(( IT_SCR_SFR_GATE_UART_OFF << IT_SCR_SFR_GATE_UART_BIT
288 |IT_SCR_SFR_FET_CHARGE_213_US << IT_SCR_SFR_FET_CHARGE_BIT
289 |IT_SCR_SFR_CARD_FREQ_3_5_MHZ << IT_SCR_SFR_CARD_FREQ_BIT
290 |IT_SCR_SFR_FET_ACTIVE_INVERT << IT_SCR_SFR_FET_ACTIVE_BIT
291 |IT_SCR_SFR_ENABLE_ON << IT_SCR_SFR_ENABLE_BIT),
292 IT8172_PCI_IO_BASE + IT_SCR1_BASE + IT_SCR_SFR);
293 outb(IT_SCR_SCDR_RESET_MODE_ASYNC << IT_SCR_SCDR_RESET_MODE_BIT,
294 IT8172_PCI_IO_BASE + IT_SCR1_BASE + IT_SCR_SCDR);
295 }
296#endif /* CONFIG_IT8172_SCR1 */
297}
298
299#ifdef CONFIG_SERIO_I8042
300/*
301 * According to the ITE Special BIOS Note for waking up the
302 * keyboard controller...
303 */
304static int init_8712_keyboard(void)
305{
306 unsigned int cmd_port = 0x14000064;
307 unsigned int data_port = 0x14000060;
308 ^^^^^^^^^^^
309 Somebody here doesn't grok the concept of io ports.
310
311 unsigned char data;
312 int i;
313
314 outb(0xaa, cmd_port); /* send self-test cmd */
315 i = 0;
316 while (!(inb(cmd_port) & 0x1)) { /* wait output buffer full */
317 i++;
318 if (i > 0xffffff)
319 return 1;
320 }
321
322 data = inb(data_port);
323 outb(0xcb, cmd_port); /* set ps2 mode */
324 while (inb(cmd_port) & 0x2) { /* wait while input buffer full */
325 i++;
326 if (i > 0xffffff)
327 return 1;
328 }
329 outb(0x01, data_port);
330 while (inb(cmd_port) & 0x2) { /* wait while input buffer full */
331 i++;
332 if (i > 0xffffff)
333 return 1;
334 }
335
336 outb(0x60, cmd_port); /* write 8042 command byte */
337 while (inb(cmd_port) & 0x2) { /* wait while input buffer full */
338 i++;
339 if (i > 0xffffff)
340 return 1;
341 }
342 outb(0x45, data_port); /* at interface, keyboard enabled, system flag */
343 while (inb(cmd_port) & 0x2) { /* wait while input buffer full */
344 i++;
345 if (i > 0xffffff)
346 return 1;
347 }
348
349 outb(0xae, cmd_port); /* enable interface */
350 return 0;
351}
352#endif
diff --git a/arch/mips/ite-boards/generic/lpc.c b/arch/mips/ite-boards/generic/lpc.c
deleted file mode 100644
index cc7584fbef8a..000000000000
--- a/arch/mips/ite-boards/generic/lpc.c
+++ /dev/null
@@ -1,144 +0,0 @@
1/*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * ITE Semi IT8712 Super I/O functions.
5 *
6 * Copyright 2001 MontaVista Software Inc.
7 * Author: MontaVista Software, Inc.
8 * ppopov@mvista.com or source@mvista.com
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
17 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
21 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
22 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * You should have received a copy of the GNU General Public License along
27 * with this program; if not, write to the Free Software Foundation, Inc.,
28 * 675 Mass Ave, Cambridge, MA 02139, USA.
29 */
30
31#include <asm/io.h>
32#include <asm/types.h>
33#include <asm/it8712.h>
34#include <asm/it8172/it8172.h>
35
36#ifndef TRUE
37#define TRUE 1
38#endif
39
40#ifndef FALSE
41#define FALSE 0
42#endif
43
44void LPCEnterMBPnP(void)
45{
46 int i;
47 unsigned char key[4] = {0x87, 0x01, 0x55, 0x55};
48
49 for (i = 0; i<4; i++)
50 outb(key[i], LPC_KEY_ADDR);
51
52}
53
54void LPCExitMBPnP(void)
55{
56 outb(0x02, LPC_KEY_ADDR);
57 outb(0x02, LPC_DATA_ADDR);
58}
59
60void LPCSetConfig(char LdnNumber, char Index, char data)
61{
62 LPCEnterMBPnP(); // Enter IT8712 MB PnP mode
63 outb(0x07, LPC_KEY_ADDR);
64 outb(LdnNumber, LPC_DATA_ADDR);
65 outb(Index, LPC_KEY_ADDR);
66 outb(data, LPC_DATA_ADDR);
67 LPCExitMBPnP();
68}
69
70char LPCGetConfig(char LdnNumber, char Index)
71{
72 char rtn;
73
74 LPCEnterMBPnP(); // Enter IT8712 MB PnP mode
75 outb(0x07, LPC_KEY_ADDR);
76 outb(LdnNumber, LPC_DATA_ADDR);
77 outb(Index, LPC_KEY_ADDR);
78 rtn = inb(LPC_DATA_ADDR);
79 LPCExitMBPnP();
80 return rtn;
81}
82
83int SearchIT8712(void)
84{
85 unsigned char Id1, Id2;
86 unsigned short Id;
87
88 LPCEnterMBPnP();
89 outb(0x20, LPC_KEY_ADDR); /* chip id byte 1 */
90 Id1 = inb(LPC_DATA_ADDR);
91 outb(0x21, LPC_KEY_ADDR); /* chip id byte 2 */
92 Id2 = inb(LPC_DATA_ADDR);
93 Id = (Id1 << 8) | Id2;
94 LPCExitMBPnP();
95 if (Id == 0x8712)
96 return TRUE;
97 else
98 return FALSE;
99}
100
101void InitLPCInterface(void)
102{
103 unsigned char bus, dev_fn;
104 unsigned long data;
105
106 bus = 0;
107 dev_fn = 1<<3 | 4;
108
109
110 /* pci cmd, SERR# Enable */
111 IT_WRITE(IT_CONFADDR,
112 (bus << IT_BUSNUM_SHF) |
113 (dev_fn << IT_FUNCNUM_SHF) |
114 ((0x4 / 4) << IT_REGNUM_SHF));
115 IT_READ(IT_CONFDATA, data);
116 data |= 0x0100;
117 IT_WRITE(IT_CONFADDR,
118 (bus << IT_BUSNUM_SHF) |
119 (dev_fn << IT_FUNCNUM_SHF) |
120 ((0x4 / 4) << IT_REGNUM_SHF));
121 IT_WRITE(IT_CONFDATA, data);
122
123 /* setup serial irq control register */
124 IT_WRITE(IT_CONFADDR,
125 (bus << IT_BUSNUM_SHF) |
126 (dev_fn << IT_FUNCNUM_SHF) |
127 ((0x48 / 4) << IT_REGNUM_SHF));
128 IT_READ(IT_CONFDATA, data);
129 data = (data & 0xffff00ff) | 0xc400;
130 IT_WRITE(IT_CONFADDR,
131 (bus << IT_BUSNUM_SHF) |
132 (dev_fn << IT_FUNCNUM_SHF) |
133 ((0x48 / 4) << IT_REGNUM_SHF));
134 IT_WRITE(IT_CONFDATA, data);
135
136
137 /* Enable I/O Space Subtractive Decode */
138 /* default 0x4C is 0x3f220000 */
139 IT_WRITE(IT_CONFADDR,
140 (bus << IT_BUSNUM_SHF) |
141 (dev_fn << IT_FUNCNUM_SHF) |
142 ((0x4C / 4) << IT_REGNUM_SHF));
143 IT_WRITE(IT_CONFDATA, 0x3f2200f3);
144}
diff --git a/arch/mips/ite-boards/generic/pmon_prom.c b/arch/mips/ite-boards/generic/pmon_prom.c
deleted file mode 100644
index 7d0a79be34d8..000000000000
--- a/arch/mips/ite-boards/generic/pmon_prom.c
+++ /dev/null
@@ -1,135 +0,0 @@
1/*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * PROM library initialisation code, assuming a version of
5 * pmon is the boot code.
6 *
7 * Copyright 2000 MontaVista Software Inc.
8 * Author: MontaVista Software, Inc.
9 * ppopov@mvista.com or source@mvista.com
10 *
11 * This file was derived from Carsten Langgaard's
12 * arch/mips/mips-boards/xx files.
13 *
14 * Carsten Langgaard, carstenl@mips.com
15 * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
16 *
17 * This program is free software; you can redistribute it and/or modify it
18 * under the terms of the GNU General Public License as published by the
19 * Free Software Foundation; either version 2 of the License, or (at your
20 * option) any later version.
21 *
22 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 * You should have received a copy of the GNU General Public License along
34 * with this program; if not, write to the Free Software Foundation, Inc.,
35 * 675 Mass Ave, Cambridge, MA 02139, USA.
36 */
37
38#include <linux/kernel.h>
39#include <linux/init.h>
40#include <linux/string.h>
41
42#include <asm/bootinfo.h>
43
44extern int prom_argc;
45extern char **prom_argv, **prom_envp;
46
47typedef struct
48{
49 char *name;
50/* char *val; */
51}t_env_var;
52
53
54char * __init prom_getcmdline(void)
55{
56 return &(arcs_cmdline[0]);
57}
58
59void __init prom_init_cmdline(void)
60{
61 char *cp;
62 int actr;
63
64 actr = 1; /* Always ignore argv[0] */
65
66 cp = &(arcs_cmdline[0]);
67 while(actr < prom_argc) {
68 strcpy(cp, prom_argv[actr]);
69 cp += strlen(prom_argv[actr]);
70 *cp++ = ' ';
71 actr++;
72 }
73 if (cp != &(arcs_cmdline[0])) /* get rid of trailing space */
74 --cp;
75 *cp = '\0';
76
77}
78
79
80char *prom_getenv(char *envname)
81{
82 /*
83 * Return a pointer to the given environment variable.
84 * Environment variables are stored in the form of "memsize=64".
85 */
86
87 t_env_var *env = (t_env_var *)prom_envp;
88 int i;
89
90 i = strlen(envname);
91
92 while(env->name) {
93 if(strncmp(envname, env->name, i) == 0) {
94 return(env->name + strlen(envname) + 1);
95 }
96 env++;
97 }
98 return(NULL);
99}
100
101static inline unsigned char str2hexnum(unsigned char c)
102{
103 if(c >= '0' && c <= '9')
104 return c - '0';
105 if(c >= 'a' && c <= 'f')
106 return c - 'a' + 10;
107 return 0; /* foo */
108}
109
110unsigned long __init prom_free_prom_memory(void)
111{
112 return 0;
113}
114
115unsigned long __init prom_get_memsize(void)
116{
117 char *memsize_str;
118 unsigned int memsize;
119
120 memsize_str = prom_getenv("memsize");
121 if (!memsize_str) {
122#ifdef CONFIG_MIPS_ITE8172
123 memsize = 32;
124#elif defined(CONFIG_MIPS_IVR)
125 memsize = 64;
126#else
127 memsize = 8;
128#endif
129 printk("memsize unknown: setting to %dMB\n", memsize);
130 } else {
131 printk("memsize: %s\n", memsize_str);
132 memsize = simple_strtol(memsize_str, NULL, 0);
133 }
134 return memsize;
135}
diff --git a/arch/mips/ite-boards/generic/puts.c b/arch/mips/ite-boards/generic/puts.c
deleted file mode 100644
index 20b02df6b414..000000000000
--- a/arch/mips/ite-boards/generic/puts.c
+++ /dev/null
@@ -1,139 +0,0 @@
1/*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * Low level uart routines to directly access a 16550 uart.
5 *
6 * Copyright 2000,2001 MontaVista Software Inc.
7 * Author: MontaVista Software, Inc.
8 * ppopov@mvista.com or source@mvista.com
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
17 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
21 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
22 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * You should have received a copy of the GNU General Public License along
27 * with this program; if not, write to the Free Software Foundation, Inc.,
28 * 675 Mass Ave, Cambridge, MA 02139, USA.
29 */
30
31#include <linux/types.h>
32
33#define SERIAL_BASE 0xB4011800 /* it8172 */
34#define SER_CMD 5
35#define SER_DATA 0x00
36#define TX_BUSY 0x20
37
38#define TIMEOUT 0xffff
39#undef SLOW_DOWN
40
41static const char digits[16] = "0123456789abcdef";
42static volatile unsigned char *const com1 = (unsigned char *) SERIAL_BASE;
43
44
45#ifdef SLOW_DOWN
46static inline void slow_down()
47{
48 int k;
49 for (k = 0; k < 10000; k++);
50}
51#else
52#define slow_down()
53#endif
54
55void putch(const unsigned char c)
56{
57 unsigned char ch;
58 int i = 0;
59
60 do {
61 ch = com1[SER_CMD];
62 slow_down();
63 i++;
64 if (i > TIMEOUT) {
65 break;
66 }
67 } while (0 == (ch & TX_BUSY));
68 com1[SER_DATA] = c;
69}
70
71void puts(unsigned char *cp)
72{
73 unsigned char ch;
74 int i = 0;
75
76 while (*cp) {
77 do {
78 ch = com1[SER_CMD];
79 slow_down();
80 i++;
81 if (i > TIMEOUT) {
82 break;
83 }
84 } while (0 == (ch & TX_BUSY));
85 com1[SER_DATA] = *cp++;
86 }
87 putch('\r');
88 putch('\n');
89}
90
91void fputs(unsigned char *cp)
92{
93 unsigned char ch;
94 int i = 0;
95
96 while (*cp) {
97
98 do {
99 ch = com1[SER_CMD];
100 slow_down();
101 i++;
102 if (i > TIMEOUT) {
103 break;
104 }
105 } while (0 == (ch & TX_BUSY));
106 com1[SER_DATA] = *cp++;
107 }
108}
109
110
111void put64(uint64_t ul)
112{
113 int cnt;
114 unsigned ch;
115
116 cnt = 16; /* 16 nibbles in a 64 bit long */
117 putch('0');
118 putch('x');
119 do {
120 cnt--;
121 ch = (unsigned char) (ul >> cnt * 4) & 0x0F;
122 putch(digits[ch]);
123 } while (cnt > 0);
124}
125
126void put32(unsigned u)
127{
128 int cnt;
129 unsigned ch;
130
131 cnt = 8; /* 8 nibbles in a 32 bit long */
132 putch('0');
133 putch('x');
134 do {
135 cnt--;
136 ch = (unsigned char) (u >> cnt * 4) & 0x0F;
137 putch(digits[ch]);
138 } while (cnt > 0);
139}
diff --git a/arch/mips/ite-boards/generic/reset.c b/arch/mips/ite-boards/generic/reset.c
deleted file mode 100644
index 03bd5ba8c913..000000000000
--- a/arch/mips/ite-boards/generic/reset.c
+++ /dev/null
@@ -1,60 +0,0 @@
1/*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * ITE 8172 reset routines.
5 *
6 * Copyright 2001 MontaVista Software Inc.
7 * Author: MontaVista Software, Inc.
8 * ppopov@mvista.com or source@mvista.com
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
17 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
21 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
22 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * You should have received a copy of the GNU General Public License along
27 * with this program; if not, write to the Free Software Foundation, Inc.,
28 * 675 Mass Ave, Cambridge, MA 02139, USA.
29 */
30
31#include <linux/sched.h>
32#include <linux/mm.h>
33#include <asm/cacheflush.h>
34#include <asm/io.h>
35#include <asm/processor.h>
36#include <asm/reboot.h>
37#include <asm/system.h>
38
39void it8172_restart()
40{
41 set_c0_status(ST0_BEV | ST0_ERL);
42 change_c0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
43 flush_cache_all();
44 write_c0_wired(0);
45 __asm__ __volatile__("jr\t%0"::"r"(0xbfc00000));
46}
47
48void it8172_halt(void)
49{
50 printk(KERN_NOTICE "\n** You can safely turn off the power\n");
51 while (1)
52 __asm__(".set\tmips3\n\t"
53 "wait\n\t"
54 ".set\tmips0");
55}
56
57void it8172_power_off(void)
58{
59 it8172_halt();
60}
diff --git a/arch/mips/ite-boards/generic/time.c b/arch/mips/ite-boards/generic/time.c
deleted file mode 100644
index 3dc55569ff7f..000000000000
--- a/arch/mips/ite-boards/generic/time.c
+++ /dev/null
@@ -1,249 +0,0 @@
1/*
2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
4 *
5 * Copyright (C) 2003 MontaVista Software Inc.
6 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
7 *
8 * ########################################################################
9 *
10 * This program is free software; you can distribute it and/or modify it
11 * under the terms of the GNU General Public License (Version 2) as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 * for more details.
18 *
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, write to the Free Software Foundation, Inc.,
21 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
22 *
23 * ########################################################################
24 *
25 * Setting up the clock on the MIPS boards.
26 */
27#include <linux/init.h>
28#include <linux/kernel_stat.h>
29#include <linux/sched.h>
30#include <linux/time.h>
31#include <linux/spinlock.h>
32#include <linux/mc146818rtc.h>
33
34#include <asm/time.h>
35#include <asm/mipsregs.h>
36#include <asm/ptrace.h>
37#include <asm/it8172/it8172.h>
38#include <asm/it8172/it8172_int.h>
39#include <asm/debug.h>
40
41#define IT8172_RTC_ADR_REG (IT8172_PCI_IO_BASE + IT_RTC_BASE)
42#define IT8172_RTC_DAT_REG (IT8172_RTC_ADR_REG + 1)
43#define IT8172_RTC_CENTURY_REG (IT8172_PCI_IO_BASE + IT_RTC_CENTURY)
44
45static volatile char *rtc_adr_reg = (char*)KSEG1ADDR(IT8172_RTC_ADR_REG);
46static volatile char *rtc_dat_reg = (char*)KSEG1ADDR(IT8172_RTC_DAT_REG);
47static volatile char *rtc_century_reg = (char*)KSEG1ADDR(IT8172_RTC_CENTURY_REG);
48
49unsigned char it8172_rtc_read_data(unsigned long addr)
50{
51 unsigned char retval;
52
53 *rtc_adr_reg = addr;
54 retval = *rtc_dat_reg;
55 return retval;
56}
57
58void it8172_rtc_write_data(unsigned char data, unsigned long addr)
59{
60 *rtc_adr_reg = addr;
61 *rtc_dat_reg = data;
62}
63
64#undef CMOS_READ
65#undef CMOS_WRITE
66#define CMOS_READ(addr) it8172_rtc_read_data(addr)
67#define CMOS_WRITE(data, addr) it8172_rtc_write_data(data, addr)
68
69static unsigned char saved_control; /* remember rtc control reg */
70static inline int rtc_24h(void) { return saved_control & RTC_24H; }
71static inline int rtc_dm_binary(void) { return saved_control & RTC_DM_BINARY; }
72
73static inline unsigned char
74bin_to_hw(unsigned char c)
75{
76 if (rtc_dm_binary())
77 return c;
78 else
79 return ((c/10) << 4) + (c%10);
80}
81
82static inline unsigned char
83hw_to_bin(unsigned char c)
84{
85 if (rtc_dm_binary())
86 return c;
87 else
88 return (c>>4)*10 + (c &0xf);
89}
90
91/* 0x80 bit indicates pm in 12-hour format */
92static inline unsigned char
93hour_bin_to_hw(unsigned char c)
94{
95 if (rtc_24h())
96 return bin_to_hw(c);
97 if (c >= 12)
98 return 0x80 | bin_to_hw((c==12)?12:c-12); /* 12 is 12pm */
99 else
100 return bin_to_hw((c==0)?12:c); /* 0 is 12 AM, not 0 am */
101}
102
103static inline unsigned char
104hour_hw_to_bin(unsigned char c)
105{
106 unsigned char tmp = hw_to_bin(c&0x3f);
107 if (rtc_24h())
108 return tmp;
109 if (c & 0x80)
110 return (tmp==12)?12:tmp+12; /* 12pm is 12, not 24 */
111 else
112 return (tmp==12)?0:tmp; /* 12am is 0 */
113}
114
115static unsigned long r4k_offset; /* Amount to increment compare reg each time */
116static unsigned long r4k_cur; /* What counter should be at next timer irq */
117extern unsigned int mips_hpt_frequency;
118
119/*
120 * Figure out the r4k offset, the amount to increment the compare
121 * register for each time tick.
122 * Use the RTC to calculate offset.
123 */
124static unsigned long __init cal_r4koff(void)
125{
126 unsigned int flags;
127
128 local_irq_save(flags);
129
130 /* Start counter exactly on falling edge of update flag */
131 while (CMOS_READ(RTC_REG_A) & RTC_UIP);
132 while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
133
134 /* Start r4k counter. */
135 write_c0_count(0);
136
137 /* Read counter exactly on falling edge of update flag */
138 while (CMOS_READ(RTC_REG_A) & RTC_UIP);
139 while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
140
141 mips_hpt_frequency = read_c0_count();
142
143 /* restore interrupts */
144 local_irq_restore(flags);
145
146 return (mips_hpt_frequency / HZ);
147}
148
149static unsigned long
150it8172_rtc_get_time(void)
151{
152 unsigned int year, mon, day, hour, min, sec;
153 unsigned int flags;
154
155 /* avoid update-in-progress. */
156 for (;;) {
157 local_irq_save(flags);
158 if (! (CMOS_READ(RTC_REG_A) & RTC_UIP))
159 break;
160 /* don't hold intr closed all the time */
161 local_irq_restore(flags);
162 }
163
164 /* Read regs. */
165 sec = hw_to_bin(CMOS_READ(RTC_SECONDS));
166 min = hw_to_bin(CMOS_READ(RTC_MINUTES));
167 hour = hour_hw_to_bin(CMOS_READ(RTC_HOURS));
168 day = hw_to_bin(CMOS_READ(RTC_DAY_OF_MONTH));
169 mon = hw_to_bin(CMOS_READ(RTC_MONTH));
170 year = hw_to_bin(CMOS_READ(RTC_YEAR)) +
171 hw_to_bin(*rtc_century_reg) * 100;
172
173 /* restore interrupts */
174 local_irq_restore(flags);
175
176 return mktime(year, mon, day, hour, min, sec);
177}
178
179static int
180it8172_rtc_set_time(unsigned long t)
181{
182 struct rtc_time tm;
183 unsigned int flags;
184
185 /* convert */
186 to_tm(t, &tm);
187
188 /* avoid update-in-progress. */
189 for (;;) {
190 local_irq_save(flags);
191 if (! (CMOS_READ(RTC_REG_A) & RTC_UIP))
192 break;
193 /* don't hold intr closed all the time */
194 local_irq_restore(flags);
195 }
196
197 *rtc_century_reg = bin_to_hw(tm.tm_year/100);
198 CMOS_WRITE(bin_to_hw(tm.tm_sec), RTC_SECONDS);
199 CMOS_WRITE(bin_to_hw(tm.tm_min), RTC_MINUTES);
200 CMOS_WRITE(hour_bin_to_hw(tm.tm_hour), RTC_HOURS);
201 CMOS_WRITE(bin_to_hw(tm.tm_mday), RTC_DAY_OF_MONTH);
202 CMOS_WRITE(bin_to_hw(tm.tm_mon+1), RTC_MONTH); /* tm_mon starts from 0 */
203 CMOS_WRITE(bin_to_hw(tm.tm_year%100), RTC_YEAR);
204
205 /* restore interrupts */
206 local_irq_restore(flags);
207
208 return 0;
209}
210
211void __init it8172_time_init(void)
212{
213 unsigned int est_freq, flags;
214
215 local_irq_save(flags);
216
217 saved_control = CMOS_READ(RTC_CONTROL);
218
219 printk("calculating r4koff... ");
220 r4k_offset = cal_r4koff();
221 printk("%08lx(%d)\n", r4k_offset, (int) r4k_offset);
222
223 est_freq = 2*r4k_offset*HZ;
224 est_freq += 5000; /* round */
225 est_freq -= est_freq%10000;
226 printk("CPU frequency %d.%02d MHz\n", est_freq/1000000,
227 (est_freq%1000000)*100/1000000);
228
229 local_irq_restore(flags);
230
231 rtc_mips_get_time = it8172_rtc_get_time;
232 rtc_mips_set_time = it8172_rtc_set_time;
233}
234
235#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
236
237void __init plat_timer_setup(struct irqaction *irq)
238{
239 puts("timer_setup\n");
240 put32(NR_IRQS);
241 puts("");
242 /* we are using the cpu counter for timer interrupts */
243 setup_irq(MIPS_CPU_TIMER_IRQ, irq);
244
245 /* to generate the first timer interrupt */
246 r4k_cur = (read_c0_count() + r4k_offset);
247 write_c0_compare(r4k_cur);
248 set_c0_status(ALLINTS);
249}
diff --git a/arch/mips/ite-boards/ivr/Makefile b/arch/mips/ite-boards/ivr/Makefile
deleted file mode 100644
index e4fa6042b472..000000000000
--- a/arch/mips/ite-boards/ivr/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
1#
2# Copyright 2000 MontaVista Software Inc.
3# Author: MontaVista Software, Inc.
4# ppopov@mvista.com or source@mvista.com
5#
6# Makefile for the Globespan IVR board,
7# board-specific files.
8#
9
10obj-y += init.o
diff --git a/arch/mips/ite-boards/ivr/README b/arch/mips/ite-boards/ivr/README
deleted file mode 100644
index aa7d8db855bb..000000000000
--- a/arch/mips/ite-boards/ivr/README
+++ /dev/null
@@ -1,3 +0,0 @@
1This is not really a board made by ITE Semi, but it's very
2similar to the ITE QED-4N-S01B board. The IVR board is made
3by Globespan and it's a reference board for the PVR chip.
diff --git a/arch/mips/ite-boards/ivr/init.c b/arch/mips/ite-boards/ivr/init.c
deleted file mode 100644
index 05cf9218c432..000000000000
--- a/arch/mips/ite-boards/ivr/init.c
+++ /dev/null
@@ -1,81 +0,0 @@
1/*
2 * BRIEF MODULE DESCRIPTION
3 * IVR board setup.
4 *
5 * Copyright 2000 MontaVista Software Inc.
6 * Author: MontaVista Software, Inc.
7 * ppopov@mvista.com or source@mvista.com
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
15 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
17 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
20 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
21 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 *
25 * You should have received a copy of the GNU General Public License along
26 * with this program; if not, write to the Free Software Foundation, Inc.,
27 * 675 Mass Ave, Cambridge, MA 02139, USA.
28 */
29#include <linux/init.h>
30#include <linux/mm.h>
31#include <linux/sched.h>
32#include <linux/bootmem.h>
33#include <asm/addrspace.h>
34#include <asm/bootinfo.h>
35#include <linux/string.h>
36#include <linux/kernel.h>
37#include <asm/sections.h>
38#include <asm/it8172/it8172.h>
39#include <asm/it8172/it8172_dbg.h>
40
41int prom_argc;
42char **prom_argv, **prom_envp;
43
44extern void __init prom_init_cmdline(void);
45extern unsigned long __init prom_get_memsize(void);
46extern void __init it8172_init_ram_resource(unsigned long memsize);
47
48const char *get_system_type(void)
49{
50 return "Globespan IVR";
51}
52
53void __init prom_init(void)
54{
55 unsigned long mem_size;
56 unsigned long pcicr;
57
58 prom_argc = fw_arg0;
59 prom_argv = (char **) fw_arg1;
60 prom_envp = (int *) fw_arg3;
61
62 mips_machgroup = MACH_GROUP_GLOBESPAN;
63 mips_machtype = MACH_IVR; /* Globespan's iTVC15 reference board */
64
65 prom_init_cmdline();
66
67 /* pmon does not set memsize */
68 mem_size = prom_get_memsize();
69 mem_size = mem_size << 20;
70
71 /*
72 * make the entire physical memory visible to pci bus masters
73 */
74 IT_READ(IT_MC_PCICR, pcicr);
75 pcicr &= ~0x1f;
76 pcicr |= (mem_size - 1) >> 22;
77 IT_WRITE(IT_MC_PCICR, pcicr);
78
79 it8172_init_ram_resource(mem_size);
80 add_memory_region(0, mem_size, BOOT_MEM_RAM);
81}
diff --git a/arch/mips/ite-boards/qed-4n-s01b/Makefile b/arch/mips/ite-boards/qed-4n-s01b/Makefile
deleted file mode 100644
index bb9972ad9c45..000000000000
--- a/arch/mips/ite-boards/qed-4n-s01b/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
1#
2# Copyright 2000 MontaVista Software Inc.
3# Author: MontaVista Software, Inc.
4# ppopov@mvista.com or source@mvista.com
5#
6# Makefile for the ITE 8172 (qed-4n-s01b) board, board
7# specific files.
8#
9
10obj-y := init.o
diff --git a/arch/mips/ite-boards/qed-4n-s01b/README b/arch/mips/ite-boards/qed-4n-s01b/README
deleted file mode 100644
index fb4b5197e800..000000000000
--- a/arch/mips/ite-boards/qed-4n-s01b/README
+++ /dev/null
@@ -1,2 +0,0 @@
1This is an ITE (www.iteusa.com) eval board for the ITE 8172G
2system controller, with a QED 5231 CPU.
diff --git a/arch/mips/ite-boards/qed-4n-s01b/init.c b/arch/mips/ite-boards/qed-4n-s01b/init.c
deleted file mode 100644
index ea2a754cafe5..000000000000
--- a/arch/mips/ite-boards/qed-4n-s01b/init.c
+++ /dev/null
@@ -1,82 +0,0 @@
1/*
2 * BRIEF MODULE DESCRIPTION
3 * IT8172/QED5231 board setup.
4 *
5 * Copyright 2000 MontaVista Software Inc.
6 * Author: MontaVista Software, Inc.
7 * ppopov@mvista.com or source@mvista.com
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
15 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
17 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
20 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
21 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 *
25 * You should have received a copy of the GNU General Public License along
26 * with this program; if not, write to the Free Software Foundation, Inc.,
27 * 675 Mass Ave, Cambridge, MA 02139, USA.
28 */
29#include <linux/init.h>
30#include <linux/mm.h>
31#include <linux/sched.h>
32#include <linux/bootmem.h>
33#include <asm/addrspace.h>
34#include <asm/bootinfo.h>
35#include <linux/string.h>
36#include <linux/kernel.h>
37#include <asm/sections.h>
38#include <asm/it8172/it8172.h>
39#include <asm/it8172/it8172_dbg.h>
40
41int prom_argc;
42char **prom_argv, **prom_envp;
43
44extern void __init prom_init_cmdline(void);
45extern unsigned long __init prom_get_memsize(void);
46extern void __init it8172_init_ram_resource(unsigned long memsize);
47
48const char *get_system_type(void)
49{
50 return "ITE QED-4N-S01B";
51}
52
53void __init prom_init(void)
54{
55 unsigned long mem_size;
56 unsigned long pcicr;
57
58 prom_argc = fw_arg0;
59 prom_argv = (char **) fw_arg1;
60 prom_envp = (int *) fw_arg3;
61
62 mips_machgroup = MACH_GROUP_ITE;
63 mips_machtype = MACH_QED_4N_S01B; /* ITE board name/number */
64
65 prom_init_cmdline();
66 mem_size = prom_get_memsize();
67
68 printk("Memory size: %dMB\n", (unsigned)mem_size);
69
70 mem_size <<= 20; /* MB */
71
72 /*
73 * make the entire physical memory visible to pci bus masters
74 */
75 IT_READ(IT_MC_PCICR, pcicr);
76 pcicr &= ~0x1f;
77 pcicr |= (mem_size - 1) >> 22;
78 IT_WRITE(IT_MC_PCICR, pcicr);
79
80 it8172_init_ram_resource(mem_size);
81 add_memory_region(0, mem_size, BOOT_MEM_RAM);
82}
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-05 00:24:51 -0500