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-rw-r--r--arch/mips/ite-boards/generic/it8172_setup.c352
1 files changed, 0 insertions, 352 deletions
diff --git a/arch/mips/ite-boards/generic/it8172_setup.c b/arch/mips/ite-boards/generic/it8172_setup.c
deleted file mode 100644
index 07faf3cacff2..000000000000
--- a/arch/mips/ite-boards/generic/it8172_setup.c
+++ /dev/null
@@ -1,352 +0,0 @@
1/*
2 * BRIEF MODULE DESCRIPTION
3 * IT8172/QED5231 board setup.
4 *
5 * Copyright 2000 MontaVista Software Inc.
6 * Author: MontaVista Software, Inc.
7 * ppopov@mvista.com or source@mvista.com
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
15 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
17 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
20 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
21 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 *
25 * You should have received a copy of the GNU General Public License along
26 * with this program; if not, write to the Free Software Foundation, Inc.,
27 * 675 Mass Ave, Cambridge, MA 02139, USA.
28 */
29#include <linux/init.h>
30#include <linux/sched.h>
31#include <linux/ioport.h>
32#include <linux/irq.h>
33#include <linux/serial_reg.h>
34#include <linux/major.h>
35#include <linux/kdev_t.h>
36#include <linux/root_dev.h>
37#include <linux/pm.h>
38
39#include <asm/cpu.h>
40#include <asm/time.h>
41#include <asm/io.h>
42#include <asm/bootinfo.h>
43#include <asm/irq.h>
44#include <asm/mipsregs.h>
45#include <asm/reboot.h>
46#include <asm/traps.h>
47#include <asm/it8172/it8172.h>
48#include <asm/it8712.h>
49
50extern struct resource ioport_resource;
51#ifdef CONFIG_SERIO_I8042
52int init_8712_keyboard(void);
53#endif
54
55extern int SearchIT8712(void);
56extern void InitLPCInterface(void);
57extern char * __init prom_getcmdline(void);
58extern void it8172_restart(char *command);
59extern void it8172_halt(void);
60extern void it8172_power_off(void);
61
62extern void it8172_time_init(void);
63
64#ifdef CONFIG_IT8172_REVC
65struct {
66 struct resource ram;
67 struct resource pci_mem;
68 struct resource pci_io;
69 struct resource flash;
70 struct resource boot;
71} it8172_resources = {
72 {
73 .start = 0, /* to be initted */
74 .end = 0,
75 .name = "RAM",
76 .flags = IORESOURCE_MEM
77 }, {
78 .start = 0x10000000,
79 .end = 0x13FFFFFF,
80 .name = "PCI Mem",
81 .flags = IORESOURCE_MEM
82 }, {
83 .start = 0x14000000,
84 .end = 0x17FFFFFF
85 .name = "PCI I/O",
86 }, {
87 .start = 0x08000000,
88 .end = 0x0CFFFFFF
89 .name = "Flash",
90 }, {
91 .start = 0x1FC00000,
92 .end = 0x1FFFFFFF
93 .name = "Boot ROM",
94 }
95};
96#else
97struct {
98 struct resource ram;
99 struct resource pci_mem0;
100 struct resource pci_mem1;
101 struct resource pci_io;
102 struct resource pci_mem2;
103 struct resource pci_mem3;
104 struct resource flash;
105 struct resource boot;
106} it8172_resources = {
107 {
108 .start = 0, /* to be initted */
109 .end = 0,
110 .name = "RAM",
111 .flags = IORESOURCE_MEM
112 }, {
113 .start = 0x0C000000,
114 .end = 0x0FFFFFFF,
115 .name = "PCI Mem0",
116 .flags = IORESOURCE_MEM
117 }, {
118 .start = 0x10000000,
119 .end = 0x13FFFFFF,
120 .name = "PCI Mem1",
121 .flags = IORESOURCE_MEM
122 }, {
123 .start = 0x14000000,
124 .end = 0x17FFFFFF
125 .name = "PCI I/O",
126 }, {
127 .start = 0x1A000000,
128 .end = 0x1BFFFFFF,
129 .name = "PCI Mem2",
130 .flags = IORESOURCE_MEM
131 }, {
132 .start = 0x1C000000,
133 .end = 0x1FBFFFFF,
134 .name = "PCI Mem3",
135 .flags = IORESOURCE_MEM
136 }, {
137 .start = 0x08000000,
138 .end = 0x0CFFFFFF
139 .name = "Flash",
140 }, {
141 .start = 0x1FC00000,
142 .end = 0x1FFFFFFF
143 .name = "Boot ROM",
144 }
145};
146#endif
147
148
149void __init it8172_init_ram_resource(unsigned long memsize)
150{
151 it8172_resources.ram.end = memsize;
152}
153
154void __init plat_mem_setup(void)
155{
156 unsigned short dsr;
157 char *argptr;
158
159 argptr = prom_getcmdline();
160#ifdef CONFIG_SERIAL_CONSOLE
161 if ((argptr = strstr(argptr, "console=")) == NULL) {
162 argptr = prom_getcmdline();
163 strcat(argptr, " console=ttyS0,115200");
164 }
165#endif
166
167 clear_c0_status(ST0_FR);
168
169 board_time_init = it8172_time_init;
170
171 _machine_restart = it8172_restart;
172 _machine_halt = it8172_halt;
173 pm_power_off = it8172_power_off;
174
175 /*
176 * IO/MEM resources.
177 *
178 * revisit this area.
179 */
180 set_io_port_base(KSEG1);
181 ioport_resource.start = it8172_resources.pci_io.start;
182 ioport_resource.end = it8172_resources.pci_io.end;
183#ifdef CONFIG_IT8172_REVC
184 iomem_resource.start = it8172_resources.pci_mem.start;
185 iomem_resource.end = it8172_resources.pci_mem.end;
186#else
187 iomem_resource.start = it8172_resources.pci_mem0.start;
188 iomem_resource.end = it8172_resources.pci_mem3.end;
189#endif
190
191#ifdef CONFIG_BLK_DEV_INITRD
192 ROOT_DEV = Root_RAM0;
193#endif
194
195 /*
196 * Pull enabled devices out of standby
197 */
198 IT_IO_READ16(IT_PM_DSR, dsr);
199
200 /*
201 * Fixme: This breaks when these drivers are modules!!!
202 */
203#ifdef CONFIG_SOUND_IT8172
204 dsr &= ~IT_PM_DSR_ACSB;
205#else
206 dsr |= IT_PM_DSR_ACSB;
207#endif
208#ifdef CONFIG_BLK_DEV_IT8172
209 dsr &= ~IT_PM_DSR_IDESB;
210#else
211 dsr |= IT_PM_DSR_IDESB;
212#endif
213 IT_IO_WRITE16(IT_PM_DSR, dsr);
214
215 InitLPCInterface();
216
217#ifdef CONFIG_MIPS_ITE8172
218 if (SearchIT8712()) {
219 printk("Found IT8712 Super IO\n");
220 /* enable IT8712 serial port */
221 LPCSetConfig(LDN_SERIAL1, 0x30, 0x01); /* enable */
222 LPCSetConfig(LDN_SERIAL1, 0x23, 0x01); /* clock selection */
223#ifdef CONFIG_SERIO_I8042
224 if (init_8712_keyboard()) {
225 printk("Unable to initialize keyboard\n");
226 LPCSetConfig(LDN_KEYBOARD, 0x30, 0x0); /* disable keyboard */
227 } else {
228 LPCSetConfig(LDN_KEYBOARD, 0x30, 0x1); /* enable keyboard */
229 LPCSetConfig(LDN_KEYBOARD, 0xf0, 0x2);
230 LPCSetConfig(LDN_KEYBOARD, 0x71, 0x3);
231
232 LPCSetConfig(LDN_MOUSE, 0x30, 0x1); /* enable mouse */
233
234 LPCSetConfig(0x4, 0x30, 0x1);
235 LPCSetConfig(0x4, 0xf4, LPCGetConfig(0x4, 0xf4) | 0x80);
236
237 if ((LPCGetConfig(LDN_KEYBOARD, 0x30) == 0) ||
238 (LPCGetConfig(LDN_MOUSE, 0x30) == 0))
239 printk("Error: keyboard or mouse not enabled\n");
240
241 }
242#endif
243 }
244 else {
245 printk("IT8712 Super IO not found\n");
246 }
247#endif
248
249#ifdef CONFIG_IT8172_CIR
250 {
251 unsigned long data;
252 //printk("Enabling CIR0\n");
253 IT_IO_READ16(IT_PM_DSR, data);
254 data &= ~IT_PM_DSR_CIR0SB;
255 IT_IO_WRITE16(IT_PM_DSR, data);
256 //printk("DSR register: %x\n", (unsigned)IT_IO_READ16(IT_PM_DSR, data));
257 }
258#endif
259#ifdef CONFIG_IT8172_SCR0
260 {
261 unsigned i;
262 /* Enable Smart Card Reader 0 */
263 /* First power it up */
264 IT_IO_READ16(IT_PM_DSR, i);
265 i &= ~IT_PM_DSR_SCR0SB;
266 IT_IO_WRITE16(IT_PM_DSR, i);
267 /* Then initialize its registers */
268 outb(( IT_SCR_SFR_GATE_UART_OFF << IT_SCR_SFR_GATE_UART_BIT
269 |IT_SCR_SFR_FET_CHARGE_213_US << IT_SCR_SFR_FET_CHARGE_BIT
270 |IT_SCR_SFR_CARD_FREQ_3_5_MHZ << IT_SCR_SFR_CARD_FREQ_BIT
271 |IT_SCR_SFR_FET_ACTIVE_INVERT << IT_SCR_SFR_FET_ACTIVE_BIT
272 |IT_SCR_SFR_ENABLE_ON << IT_SCR_SFR_ENABLE_BIT),
273 IT8172_PCI_IO_BASE + IT_SCR0_BASE + IT_SCR_SFR);
274 outb(IT_SCR_SCDR_RESET_MODE_ASYNC << IT_SCR_SCDR_RESET_MODE_BIT,
275 IT8172_PCI_IO_BASE + IT_SCR0_BASE + IT_SCR_SCDR);
276 }
277#endif /* CONFIG_IT8172_SCR0 */
278#ifdef CONFIG_IT8172_SCR1
279 {
280 unsigned i;
281 /* Enable Smart Card Reader 1 */
282 /* First power it up */
283 IT_IO_READ16(IT_PM_DSR, i);
284 i &= ~IT_PM_DSR_SCR1SB;
285 IT_IO_WRITE16(IT_PM_DSR, i);
286 /* Then initialize its registers */
287 outb(( IT_SCR_SFR_GATE_UART_OFF << IT_SCR_SFR_GATE_UART_BIT
288 |IT_SCR_SFR_FET_CHARGE_213_US << IT_SCR_SFR_FET_CHARGE_BIT
289 |IT_SCR_SFR_CARD_FREQ_3_5_MHZ << IT_SCR_SFR_CARD_FREQ_BIT
290 |IT_SCR_SFR_FET_ACTIVE_INVERT << IT_SCR_SFR_FET_ACTIVE_BIT
291 |IT_SCR_SFR_ENABLE_ON << IT_SCR_SFR_ENABLE_BIT),
292 IT8172_PCI_IO_BASE + IT_SCR1_BASE + IT_SCR_SFR);
293 outb(IT_SCR_SCDR_RESET_MODE_ASYNC << IT_SCR_SCDR_RESET_MODE_BIT,
294 IT8172_PCI_IO_BASE + IT_SCR1_BASE + IT_SCR_SCDR);
295 }
296#endif /* CONFIG_IT8172_SCR1 */
297}
298
299#ifdef CONFIG_SERIO_I8042
300/*
301 * According to the ITE Special BIOS Note for waking up the
302 * keyboard controller...
303 */
304static int init_8712_keyboard(void)
305{
306 unsigned int cmd_port = 0x14000064;
307 unsigned int data_port = 0x14000060;
308 ^^^^^^^^^^^
309 Somebody here doesn't grok the concept of io ports.
310
311 unsigned char data;
312 int i;
313
314 outb(0xaa, cmd_port); /* send self-test cmd */
315 i = 0;
316 while (!(inb(cmd_port) & 0x1)) { /* wait output buffer full */
317 i++;
318 if (i > 0xffffff)
319 return 1;
320 }
321
322 data = inb(data_port);
323 outb(0xcb, cmd_port); /* set ps2 mode */
324 while (inb(cmd_port) & 0x2) { /* wait while input buffer full */
325 i++;
326 if (i > 0xffffff)
327 return 1;
328 }
329 outb(0x01, data_port);
330 while (inb(cmd_port) & 0x2) { /* wait while input buffer full */
331 i++;
332 if (i > 0xffffff)
333 return 1;
334 }
335
336 outb(0x60, cmd_port); /* write 8042 command byte */
337 while (inb(cmd_port) & 0x2) { /* wait while input buffer full */
338 i++;
339 if (i > 0xffffff)
340 return 1;
341 }
342 outb(0x45, data_port); /* at interface, keyboard enabled, system flag */
343 while (inb(cmd_port) & 0x2) { /* wait while input buffer full */
344 i++;
345 if (i > 0xffffff)
346 return 1;
347 }
348
349 outb(0xae, cmd_port); /* enable interface */
350 return 0;
351}
352#endif
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