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-rw-r--r--arch/mips/include/asm/atomic.h374
-rw-r--r--arch/mips/include/asm/bitops.h35
-rw-r--r--arch/mips/include/asm/bmips.h1
-rw-r--r--arch/mips/include/asm/bootinfo.h13
-rw-r--r--arch/mips/include/asm/clock.h3
-rw-r--r--arch/mips/include/asm/cmpxchg.h27
-rw-r--r--arch/mips/include/asm/compiler.h8
-rw-r--r--arch/mips/include/asm/cpu-features.h4
-rw-r--r--arch/mips/include/asm/cpu.h2
-rw-r--r--arch/mips/include/asm/edac.h6
-rw-r--r--arch/mips/include/asm/elf.h74
-rw-r--r--arch/mips/include/asm/fpu.h49
-rw-r--r--arch/mips/include/asm/futex.h27
-rw-r--r--arch/mips/include/asm/gic.h384
-rw-r--r--arch/mips/include/asm/hpet.h73
-rw-r--r--arch/mips/include/asm/io.h8
-rw-r--r--arch/mips/include/asm/irq.h3
-rw-r--r--arch/mips/include/asm/irq_cpu.h4
-rw-r--r--arch/mips/include/asm/mach-ath25/ath25_platform.h73
-rw-r--r--arch/mips/include/asm/mach-ath25/cpu-feature-overrides.h64
-rw-r--r--arch/mips/include/asm/mach-ath25/dma-coherence.h82
-rw-r--r--arch/mips/include/asm/mach-ath25/gpio.h16
-rw-r--r--arch/mips/include/asm/mach-ath25/war.h25
-rw-r--r--arch/mips/include/asm/mach-au1x00/ioremap.h10
-rw-r--r--arch/mips/include/asm/mach-bcm3384/dma-coherence.h48
-rw-r--r--arch/mips/include/asm/mach-bcm3384/war.h24
-rw-r--r--arch/mips/include/asm/mach-bcm47xx/bcm47xx_nvram.h36
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/ioremap.h6
-rw-r--r--arch/mips/include/asm/mach-generic/ioremap.h4
-rw-r--r--arch/mips/include/asm/mach-generic/irq.h6
-rw-r--r--arch/mips/include/asm/mach-lantiq/lantiq.h2
-rw-r--r--arch/mips/include/asm/mach-loongson/boot_param.h49
-rw-r--r--arch/mips/include/asm/mach-loongson/dma-coherence.h6
-rw-r--r--arch/mips/include/asm/mach-loongson/irq.h3
-rw-r--r--arch/mips/include/asm/mach-loongson/loongson.h2
-rw-r--r--arch/mips/include/asm/mach-loongson/loongson_hwmon.h55
-rw-r--r--arch/mips/include/asm/mach-loongson/machine.h2
-rw-r--r--arch/mips/include/asm/mach-loongson/topology.h2
-rw-r--r--arch/mips/include/asm/mach-loongson/workarounds.h7
-rw-r--r--arch/mips/include/asm/mach-loongson1/cpufreq.h23
-rw-r--r--arch/mips/include/asm/mach-loongson1/loongson1.h8
-rw-r--r--arch/mips/include/asm/mach-loongson1/platform.h10
-rw-r--r--arch/mips/include/asm/mach-loongson1/regs-clk.h23
-rw-r--r--arch/mips/include/asm/mach-loongson1/regs-mux.h67
-rw-r--r--arch/mips/include/asm/mach-loongson1/regs-pwm.h29
-rw-r--r--arch/mips/include/asm/mach-loongson1/regs-wdt.h11
-rw-r--r--arch/mips/include/asm/mach-malta/irq.h1
-rw-r--r--arch/mips/include/asm/mach-pmcs-msp71xx/msp_regops.h25
-rw-r--r--arch/mips/include/asm/mach-ralink/mt7620.h64
-rw-r--r--arch/mips/include/asm/mach-ralink/pinmux.h55
-rw-r--r--arch/mips/include/asm/mach-ralink/ralink_regs.h7
-rw-r--r--arch/mips/include/asm/mach-ralink/rt305x.h35
-rw-r--r--arch/mips/include/asm/mach-ralink/rt3883.h16
-rw-r--r--arch/mips/include/asm/mach-sead3/irq.h1
-rw-r--r--arch/mips/include/asm/mach-tx39xx/ioremap.h4
-rw-r--r--arch/mips/include/asm/mach-tx49xx/ioremap.h4
-rw-r--r--arch/mips/include/asm/mips-boards/maltaint.h24
-rw-r--r--arch/mips/include/asm/mips-boards/sead3int.h15
-rw-r--r--arch/mips/include/asm/mips-cm.h2
-rw-r--r--arch/mips/include/asm/mips-cpc.h4
-rw-r--r--arch/mips/include/asm/mipsregs.h43
-rw-r--r--arch/mips/include/asm/octeon/cvmx-cmd-queue.h4
-rw-r--r--arch/mips/include/asm/octeon/cvmx-pow.h69
-rw-r--r--arch/mips/include/asm/octeon/cvmx.h63
-rw-r--r--arch/mips/include/asm/octeon/octeon-feature.h52
-rw-r--r--arch/mips/include/asm/octeon/octeon-model.h3
-rw-r--r--arch/mips/include/asm/paccess.h2
-rw-r--r--arch/mips/include/asm/page.h2
-rw-r--r--arch/mips/include/asm/pci.h2
-rw-r--r--arch/mips/include/asm/pgtable-32.h104
-rw-r--r--arch/mips/include/asm/pgtable-bits.h36
-rw-r--r--arch/mips/include/asm/pgtable.h18
-rw-r--r--arch/mips/include/asm/prom.h1
-rw-r--r--arch/mips/include/asm/r4kcache.h59
-rw-r--r--arch/mips/include/asm/spinlock.h50
-rw-r--r--arch/mips/include/asm/thread_info.h2
-rw-r--r--arch/mips/include/asm/time.h6
-rw-r--r--arch/mips/include/asm/types.h18
-rw-r--r--arch/mips/include/asm/uaccess.h27
-rw-r--r--arch/mips/include/asm/uasm.h2
-rw-r--r--arch/mips/include/uapi/asm/inst.h7
81 files changed, 1451 insertions, 1164 deletions
diff --git a/arch/mips/include/asm/atomic.h b/arch/mips/include/asm/atomic.h
index 6dd6bfc607e9..857da84cfc92 100644
--- a/arch/mips/include/asm/atomic.h
+++ b/arch/mips/include/asm/atomic.h
@@ -17,6 +17,7 @@
17#include <linux/irqflags.h> 17#include <linux/irqflags.h>
18#include <linux/types.h> 18#include <linux/types.h>
19#include <asm/barrier.h> 19#include <asm/barrier.h>
20#include <asm/compiler.h>
20#include <asm/cpu-features.h> 21#include <asm/cpu-features.h>
21#include <asm/cmpxchg.h> 22#include <asm/cmpxchg.h>
22#include <asm/war.h> 23#include <asm/war.h>
@@ -40,95 +41,97 @@
40 */ 41 */
41#define atomic_set(v, i) ((v)->counter = (i)) 42#define atomic_set(v, i) ((v)->counter = (i))
42 43
43#define ATOMIC_OP(op, c_op, asm_op) \ 44#define ATOMIC_OP(op, c_op, asm_op) \
44static __inline__ void atomic_##op(int i, atomic_t * v) \ 45static __inline__ void atomic_##op(int i, atomic_t * v) \
45{ \ 46{ \
46 if (kernel_uses_llsc && R10000_LLSC_WAR) { \ 47 if (kernel_uses_llsc && R10000_LLSC_WAR) { \
47 int temp; \ 48 int temp; \
48 \ 49 \
49 __asm__ __volatile__( \ 50 __asm__ __volatile__( \
50 " .set arch=r4000 \n" \ 51 " .set arch=r4000 \n" \
51 "1: ll %0, %1 # atomic_" #op " \n" \ 52 "1: ll %0, %1 # atomic_" #op " \n" \
52 " " #asm_op " %0, %2 \n" \ 53 " " #asm_op " %0, %2 \n" \
53 " sc %0, %1 \n" \ 54 " sc %0, %1 \n" \
54 " beqzl %0, 1b \n" \ 55 " beqzl %0, 1b \n" \
55 " .set mips0 \n" \ 56 " .set mips0 \n" \
56 : "=&r" (temp), "+m" (v->counter) \ 57 : "=&r" (temp), "+" GCC_OFF12_ASM() (v->counter) \
57 : "Ir" (i)); \ 58 : "Ir" (i)); \
58 } else if (kernel_uses_llsc) { \ 59 } else if (kernel_uses_llsc) { \
59 int temp; \ 60 int temp; \
60 \ 61 \
61 do { \ 62 do { \
62 __asm__ __volatile__( \ 63 __asm__ __volatile__( \
63 " .set arch=r4000 \n" \ 64 " .set arch=r4000 \n" \
64 " ll %0, %1 # atomic_" #op "\n" \ 65 " ll %0, %1 # atomic_" #op "\n" \
65 " " #asm_op " %0, %2 \n" \ 66 " " #asm_op " %0, %2 \n" \
66 " sc %0, %1 \n" \ 67 " sc %0, %1 \n" \
67 " .set mips0 \n" \ 68 " .set mips0 \n" \
68 : "=&r" (temp), "+m" (v->counter) \ 69 : "=&r" (temp), "+" GCC_OFF12_ASM() (v->counter) \
69 : "Ir" (i)); \ 70 : "Ir" (i)); \
70 } while (unlikely(!temp)); \ 71 } while (unlikely(!temp)); \
71 } else { \ 72 } else { \
72 unsigned long flags; \ 73 unsigned long flags; \
73 \ 74 \
74 raw_local_irq_save(flags); \ 75 raw_local_irq_save(flags); \
75 v->counter c_op i; \ 76 v->counter c_op i; \
76 raw_local_irq_restore(flags); \ 77 raw_local_irq_restore(flags); \
77 } \ 78 } \
78} \
79
80#define ATOMIC_OP_RETURN(op, c_op, asm_op) \
81static __inline__ int atomic_##op##_return(int i, atomic_t * v) \
82{ \
83 int result; \
84 \
85 smp_mb__before_llsc(); \
86 \
87 if (kernel_uses_llsc && R10000_LLSC_WAR) { \
88 int temp; \
89 \
90 __asm__ __volatile__( \
91 " .set arch=r4000 \n" \
92 "1: ll %1, %2 # atomic_" #op "_return \n" \
93 " " #asm_op " %0, %1, %3 \n" \
94 " sc %0, %2 \n" \
95 " beqzl %0, 1b \n" \
96 " " #asm_op " %0, %1, %3 \n" \
97 " .set mips0 \n" \
98 : "=&r" (result), "=&r" (temp), "+m" (v->counter) \
99 : "Ir" (i)); \
100 } else if (kernel_uses_llsc) { \
101 int temp; \
102 \
103 do { \
104 __asm__ __volatile__( \
105 " .set arch=r4000 \n" \
106 " ll %1, %2 # atomic_" #op "_return \n" \
107 " " #asm_op " %0, %1, %3 \n" \
108 " sc %0, %2 \n" \
109 " .set mips0 \n" \
110 : "=&r" (result), "=&r" (temp), "+m" (v->counter) \
111 : "Ir" (i)); \
112 } while (unlikely(!result)); \
113 \
114 result = temp; result c_op i; \
115 } else { \
116 unsigned long flags; \
117 \
118 raw_local_irq_save(flags); \
119 result = v->counter; \
120 result c_op i; \
121 v->counter = result; \
122 raw_local_irq_restore(flags); \
123 } \
124 \
125 smp_llsc_mb(); \
126 \
127 return result; \
128} 79}
129 80
130#define ATOMIC_OPS(op, c_op, asm_op) \ 81#define ATOMIC_OP_RETURN(op, c_op, asm_op) \
131 ATOMIC_OP(op, c_op, asm_op) \ 82static __inline__ int atomic_##op##_return(int i, atomic_t * v) \
83{ \
84 int result; \
85 \
86 smp_mb__before_llsc(); \
87 \
88 if (kernel_uses_llsc && R10000_LLSC_WAR) { \
89 int temp; \
90 \
91 __asm__ __volatile__( \
92 " .set arch=r4000 \n" \
93 "1: ll %1, %2 # atomic_" #op "_return \n" \
94 " " #asm_op " %0, %1, %3 \n" \
95 " sc %0, %2 \n" \
96 " beqzl %0, 1b \n" \
97 " " #asm_op " %0, %1, %3 \n" \
98 " .set mips0 \n" \
99 : "=&r" (result), "=&r" (temp), \
100 "+" GCC_OFF12_ASM() (v->counter) \
101 : "Ir" (i)); \
102 } else if (kernel_uses_llsc) { \
103 int temp; \
104 \
105 do { \
106 __asm__ __volatile__( \
107 " .set arch=r4000 \n" \
108 " ll %1, %2 # atomic_" #op "_return \n" \
109 " " #asm_op " %0, %1, %3 \n" \
110 " sc %0, %2 \n" \
111 " .set mips0 \n" \
112 : "=&r" (result), "=&r" (temp), \
113 "+" GCC_OFF12_ASM() (v->counter) \
114 : "Ir" (i)); \
115 } while (unlikely(!result)); \
116 \
117 result = temp; result c_op i; \
118 } else { \
119 unsigned long flags; \
120 \
121 raw_local_irq_save(flags); \
122 result = v->counter; \
123 result c_op i; \
124 v->counter = result; \
125 raw_local_irq_restore(flags); \
126 } \
127 \
128 smp_llsc_mb(); \
129 \
130 return result; \
131}
132
133#define ATOMIC_OPS(op, c_op, asm_op) \
134 ATOMIC_OP(op, c_op, asm_op) \
132 ATOMIC_OP_RETURN(op, c_op, asm_op) 135 ATOMIC_OP_RETURN(op, c_op, asm_op)
133 136
134ATOMIC_OPS(add, +=, addu) 137ATOMIC_OPS(add, +=, addu)
@@ -167,8 +170,9 @@ static __inline__ int atomic_sub_if_positive(int i, atomic_t * v)
167 " .set reorder \n" 170 " .set reorder \n"
168 "1: \n" 171 "1: \n"
169 " .set mips0 \n" 172 " .set mips0 \n"
170 : "=&r" (result), "=&r" (temp), "+m" (v->counter) 173 : "=&r" (result), "=&r" (temp),
171 : "Ir" (i), "m" (v->counter) 174 "+" GCC_OFF12_ASM() (v->counter)
175 : "Ir" (i), GCC_OFF12_ASM() (v->counter)
172 : "memory"); 176 : "memory");
173 } else if (kernel_uses_llsc) { 177 } else if (kernel_uses_llsc) {
174 int temp; 178 int temp;
@@ -185,7 +189,8 @@ static __inline__ int atomic_sub_if_positive(int i, atomic_t * v)
185 " .set reorder \n" 189 " .set reorder \n"
186 "1: \n" 190 "1: \n"
187 " .set mips0 \n" 191 " .set mips0 \n"
188 : "=&r" (result), "=&r" (temp), "+m" (v->counter) 192 : "=&r" (result), "=&r" (temp),
193 "+" GCC_OFF12_ASM() (v->counter)
189 : "Ir" (i)); 194 : "Ir" (i));
190 } else { 195 } else {
191 unsigned long flags; 196 unsigned long flags;
@@ -315,96 +320,98 @@ static __inline__ int __atomic_add_unless(atomic_t *v, int a, int u)
315 */ 320 */
316#define atomic64_set(v, i) ((v)->counter = (i)) 321#define atomic64_set(v, i) ((v)->counter = (i))
317 322
318#define ATOMIC64_OP(op, c_op, asm_op) \ 323#define ATOMIC64_OP(op, c_op, asm_op) \
319static __inline__ void atomic64_##op(long i, atomic64_t * v) \ 324static __inline__ void atomic64_##op(long i, atomic64_t * v) \
320{ \ 325{ \
321 if (kernel_uses_llsc && R10000_LLSC_WAR) { \ 326 if (kernel_uses_llsc && R10000_LLSC_WAR) { \
322 long temp; \ 327 long temp; \
323 \ 328 \
324 __asm__ __volatile__( \ 329 __asm__ __volatile__( \
325 " .set arch=r4000 \n" \ 330 " .set arch=r4000 \n" \
326 "1: lld %0, %1 # atomic64_" #op " \n" \ 331 "1: lld %0, %1 # atomic64_" #op " \n" \
327 " " #asm_op " %0, %2 \n" \ 332 " " #asm_op " %0, %2 \n" \
328 " scd %0, %1 \n" \ 333 " scd %0, %1 \n" \
329 " beqzl %0, 1b \n" \ 334 " beqzl %0, 1b \n" \
330 " .set mips0 \n" \ 335 " .set mips0 \n" \
331 : "=&r" (temp), "+m" (v->counter) \ 336 : "=&r" (temp), "+" GCC_OFF12_ASM() (v->counter) \
332 : "Ir" (i)); \ 337 : "Ir" (i)); \
333 } else if (kernel_uses_llsc) { \ 338 } else if (kernel_uses_llsc) { \
334 long temp; \ 339 long temp; \
335 \ 340 \
336 do { \ 341 do { \
337 __asm__ __volatile__( \ 342 __asm__ __volatile__( \
338 " .set arch=r4000 \n" \ 343 " .set arch=r4000 \n" \
339 " lld %0, %1 # atomic64_" #op "\n" \ 344 " lld %0, %1 # atomic64_" #op "\n" \
340 " " #asm_op " %0, %2 \n" \ 345 " " #asm_op " %0, %2 \n" \
341 " scd %0, %1 \n" \ 346 " scd %0, %1 \n" \
342 " .set mips0 \n" \ 347 " .set mips0 \n" \
343 : "=&r" (temp), "+m" (v->counter) \ 348 : "=&r" (temp), "+" GCC_OFF12_ASM() (v->counter) \
344 : "Ir" (i)); \ 349 : "Ir" (i)); \
345 } while (unlikely(!temp)); \ 350 } while (unlikely(!temp)); \
346 } else { \ 351 } else { \
347 unsigned long flags; \ 352 unsigned long flags; \
348 \ 353 \
349 raw_local_irq_save(flags); \ 354 raw_local_irq_save(flags); \
350 v->counter c_op i; \ 355 v->counter c_op i; \
351 raw_local_irq_restore(flags); \ 356 raw_local_irq_restore(flags); \
352 } \ 357 } \
353} \ 358}
354 359
355#define ATOMIC64_OP_RETURN(op, c_op, asm_op) \ 360#define ATOMIC64_OP_RETURN(op, c_op, asm_op) \
356static __inline__ long atomic64_##op##_return(long i, atomic64_t * v) \ 361static __inline__ long atomic64_##op##_return(long i, atomic64_t * v) \
357{ \ 362{ \
358 long result; \ 363 long result; \
359 \ 364 \
360 smp_mb__before_llsc(); \ 365 smp_mb__before_llsc(); \
361 \ 366 \
362 if (kernel_uses_llsc && R10000_LLSC_WAR) { \ 367 if (kernel_uses_llsc && R10000_LLSC_WAR) { \
363 long temp; \ 368 long temp; \
364 \ 369 \
365 __asm__ __volatile__( \ 370 __asm__ __volatile__( \
366 " .set arch=r4000 \n" \ 371 " .set arch=r4000 \n" \
367 "1: lld %1, %2 # atomic64_" #op "_return\n" \ 372 "1: lld %1, %2 # atomic64_" #op "_return\n" \
368 " " #asm_op " %0, %1, %3 \n" \ 373 " " #asm_op " %0, %1, %3 \n" \
369 " scd %0, %2 \n" \ 374 " scd %0, %2 \n" \
370 " beqzl %0, 1b \n" \ 375 " beqzl %0, 1b \n" \
371 " " #asm_op " %0, %1, %3 \n" \ 376 " " #asm_op " %0, %1, %3 \n" \
372 " .set mips0 \n" \ 377 " .set mips0 \n" \
373 : "=&r" (result), "=&r" (temp), "+m" (v->counter) \ 378 : "=&r" (result), "=&r" (temp), \
374 : "Ir" (i)); \ 379 "+" GCC_OFF12_ASM() (v->counter) \
375 } else if (kernel_uses_llsc) { \ 380 : "Ir" (i)); \
376 long temp; \ 381 } else if (kernel_uses_llsc) { \
377 \ 382 long temp; \
378 do { \ 383 \
379 __asm__ __volatile__( \ 384 do { \
380 " .set arch=r4000 \n" \ 385 __asm__ __volatile__( \
381 " lld %1, %2 # atomic64_" #op "_return\n" \ 386 " .set arch=r4000 \n" \
382 " " #asm_op " %0, %1, %3 \n" \ 387 " lld %1, %2 # atomic64_" #op "_return\n" \
383 " scd %0, %2 \n" \ 388 " " #asm_op " %0, %1, %3 \n" \
384 " .set mips0 \n" \ 389 " scd %0, %2 \n" \
385 : "=&r" (result), "=&r" (temp), "=m" (v->counter) \ 390 " .set mips0 \n" \
386 : "Ir" (i), "m" (v->counter) \ 391 : "=&r" (result), "=&r" (temp), \
387 : "memory"); \ 392 "=" GCC_OFF12_ASM() (v->counter) \
388 } while (unlikely(!result)); \ 393 : "Ir" (i), GCC_OFF12_ASM() (v->counter) \
389 \ 394 : "memory"); \
390 result = temp; result c_op i; \ 395 } while (unlikely(!result)); \
391 } else { \ 396 \
392 unsigned long flags; \ 397 result = temp; result c_op i; \
393 \ 398 } else { \
394 raw_local_irq_save(flags); \ 399 unsigned long flags; \
395 result = v->counter; \ 400 \
396 result c_op i; \ 401 raw_local_irq_save(flags); \
397 v->counter = result; \ 402 result = v->counter; \
398 raw_local_irq_restore(flags); \ 403 result c_op i; \
399 } \ 404 v->counter = result; \
400 \ 405 raw_local_irq_restore(flags); \
401 smp_llsc_mb(); \ 406 } \
402 \ 407 \
403 return result; \ 408 smp_llsc_mb(); \
409 \
410 return result; \
404} 411}
405 412
406#define ATOMIC64_OPS(op, c_op, asm_op) \ 413#define ATOMIC64_OPS(op, c_op, asm_op) \
407 ATOMIC64_OP(op, c_op, asm_op) \ 414 ATOMIC64_OP(op, c_op, asm_op) \
408 ATOMIC64_OP_RETURN(op, c_op, asm_op) 415 ATOMIC64_OP_RETURN(op, c_op, asm_op)
409 416
410ATOMIC64_OPS(add, +=, daddu) 417ATOMIC64_OPS(add, +=, daddu)
@@ -415,7 +422,8 @@ ATOMIC64_OPS(sub, -=, dsubu)
415#undef ATOMIC64_OP 422#undef ATOMIC64_OP
416 423
417/* 424/*
418 * atomic64_sub_if_positive - conditionally subtract integer from atomic variable 425 * atomic64_sub_if_positive - conditionally subtract integer from atomic
426 * variable
419 * @i: integer value to subtract 427 * @i: integer value to subtract
420 * @v: pointer of type atomic64_t 428 * @v: pointer of type atomic64_t
421 * 429 *
@@ -443,8 +451,9 @@ static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v)
443 " .set reorder \n" 451 " .set reorder \n"
444 "1: \n" 452 "1: \n"
445 " .set mips0 \n" 453 " .set mips0 \n"
446 : "=&r" (result), "=&r" (temp), "=m" (v->counter) 454 : "=&r" (result), "=&r" (temp),
447 : "Ir" (i), "m" (v->counter) 455 "=" GCC_OFF12_ASM() (v->counter)
456 : "Ir" (i), GCC_OFF12_ASM() (v->counter)
448 : "memory"); 457 : "memory");
449 } else if (kernel_uses_llsc) { 458 } else if (kernel_uses_llsc) {
450 long temp; 459 long temp;
@@ -461,7 +470,8 @@ static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v)
461 " .set reorder \n" 470 " .set reorder \n"
462 "1: \n" 471 "1: \n"
463 " .set mips0 \n" 472 " .set mips0 \n"
464 : "=&r" (result), "=&r" (temp), "+m" (v->counter) 473 : "=&r" (result), "=&r" (temp),
474 "+" GCC_OFF12_ASM() (v->counter)
465 : "Ir" (i)); 475 : "Ir" (i));
466 } else { 476 } else {
467 unsigned long flags; 477 unsigned long flags;
diff --git a/arch/mips/include/asm/bitops.h b/arch/mips/include/asm/bitops.h
index bae6b0fa8ab5..6663bcca9d0c 100644
--- a/arch/mips/include/asm/bitops.h
+++ b/arch/mips/include/asm/bitops.h
@@ -17,6 +17,7 @@
17#include <linux/types.h> 17#include <linux/types.h>
18#include <asm/barrier.h> 18#include <asm/barrier.h>
19#include <asm/byteorder.h> /* sigh ... */ 19#include <asm/byteorder.h> /* sigh ... */
20#include <asm/compiler.h>
20#include <asm/cpu-features.h> 21#include <asm/cpu-features.h>
21#include <asm/sgidefs.h> 22#include <asm/sgidefs.h>
22#include <asm/war.h> 23#include <asm/war.h>
@@ -78,8 +79,8 @@ static inline void set_bit(unsigned long nr, volatile unsigned long *addr)
78 " " __SC "%0, %1 \n" 79 " " __SC "%0, %1 \n"
79 " beqzl %0, 1b \n" 80 " beqzl %0, 1b \n"
80 " .set mips0 \n" 81 " .set mips0 \n"
81 : "=&r" (temp), "=m" (*m) 82 : "=&r" (temp), "=" GCC_OFF12_ASM() (*m)
82 : "ir" (1UL << bit), "m" (*m)); 83 : "ir" (1UL << bit), GCC_OFF12_ASM() (*m));
83#ifdef CONFIG_CPU_MIPSR2 84#ifdef CONFIG_CPU_MIPSR2
84 } else if (kernel_uses_llsc && __builtin_constant_p(bit)) { 85 } else if (kernel_uses_llsc && __builtin_constant_p(bit)) {
85 do { 86 do {
@@ -87,7 +88,7 @@ static inline void set_bit(unsigned long nr, volatile unsigned long *addr)
87 " " __LL "%0, %1 # set_bit \n" 88 " " __LL "%0, %1 # set_bit \n"
88 " " __INS "%0, %3, %2, 1 \n" 89 " " __INS "%0, %3, %2, 1 \n"
89 " " __SC "%0, %1 \n" 90 " " __SC "%0, %1 \n"
90 : "=&r" (temp), "+m" (*m) 91 : "=&r" (temp), "+" GCC_OFF12_ASM() (*m)
91 : "ir" (bit), "r" (~0)); 92 : "ir" (bit), "r" (~0));
92 } while (unlikely(!temp)); 93 } while (unlikely(!temp));
93#endif /* CONFIG_CPU_MIPSR2 */ 94#endif /* CONFIG_CPU_MIPSR2 */
@@ -99,7 +100,7 @@ static inline void set_bit(unsigned long nr, volatile unsigned long *addr)
99 " or %0, %2 \n" 100 " or %0, %2 \n"
100 " " __SC "%0, %1 \n" 101 " " __SC "%0, %1 \n"
101 " .set mips0 \n" 102 " .set mips0 \n"
102 : "=&r" (temp), "+m" (*m) 103 : "=&r" (temp), "+" GCC_OFF12_ASM() (*m)
103 : "ir" (1UL << bit)); 104 : "ir" (1UL << bit));
104 } while (unlikely(!temp)); 105 } while (unlikely(!temp));
105 } else 106 } else
@@ -130,7 +131,7 @@ static inline void clear_bit(unsigned long nr, volatile unsigned long *addr)
130 " " __SC "%0, %1 \n" 131 " " __SC "%0, %1 \n"
131 " beqzl %0, 1b \n" 132 " beqzl %0, 1b \n"
132 " .set mips0 \n" 133 " .set mips0 \n"
133 : "=&r" (temp), "+m" (*m) 134 : "=&r" (temp), "+" GCC_OFF12_ASM() (*m)
134 : "ir" (~(1UL << bit))); 135 : "ir" (~(1UL << bit)));
135#ifdef CONFIG_CPU_MIPSR2 136#ifdef CONFIG_CPU_MIPSR2
136 } else if (kernel_uses_llsc && __builtin_constant_p(bit)) { 137 } else if (kernel_uses_llsc && __builtin_constant_p(bit)) {
@@ -139,7 +140,7 @@ static inline void clear_bit(unsigned long nr, volatile unsigned long *addr)
139 " " __LL "%0, %1 # clear_bit \n" 140 " " __LL "%0, %1 # clear_bit \n"
140 " " __INS "%0, $0, %2, 1 \n" 141 " " __INS "%0, $0, %2, 1 \n"
141 " " __SC "%0, %1 \n" 142 " " __SC "%0, %1 \n"
142 : "=&r" (temp), "+m" (*m) 143 : "=&r" (temp), "+" GCC_OFF12_ASM() (*m)
143 : "ir" (bit)); 144 : "ir" (bit));
144 } while (unlikely(!temp)); 145 } while (unlikely(!temp));
145#endif /* CONFIG_CPU_MIPSR2 */ 146#endif /* CONFIG_CPU_MIPSR2 */
@@ -151,7 +152,7 @@ static inline void clear_bit(unsigned long nr, volatile unsigned long *addr)
151 " and %0, %2 \n" 152 " and %0, %2 \n"
152 " " __SC "%0, %1 \n" 153 " " __SC "%0, %1 \n"
153 " .set mips0 \n" 154 " .set mips0 \n"
154 : "=&r" (temp), "+m" (*m) 155 : "=&r" (temp), "+" GCC_OFF12_ASM() (*m)
155 : "ir" (~(1UL << bit))); 156 : "ir" (~(1UL << bit)));
156 } while (unlikely(!temp)); 157 } while (unlikely(!temp));
157 } else 158 } else
@@ -196,7 +197,7 @@ static inline void change_bit(unsigned long nr, volatile unsigned long *addr)
196 " " __SC "%0, %1 \n" 197 " " __SC "%0, %1 \n"
197 " beqzl %0, 1b \n" 198 " beqzl %0, 1b \n"
198 " .set mips0 \n" 199 " .set mips0 \n"
199 : "=&r" (temp), "+m" (*m) 200 : "=&r" (temp), "+" GCC_OFF12_ASM() (*m)
200 : "ir" (1UL << bit)); 201 : "ir" (1UL << bit));
201 } else if (kernel_uses_llsc) { 202 } else if (kernel_uses_llsc) {
202 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); 203 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
@@ -209,7 +210,7 @@ static inline void change_bit(unsigned long nr, volatile unsigned long *addr)
209 " xor %0, %2 \n" 210 " xor %0, %2 \n"
210 " " __SC "%0, %1 \n" 211 " " __SC "%0, %1 \n"
211 " .set mips0 \n" 212 " .set mips0 \n"
212 : "=&r" (temp), "+m" (*m) 213 : "=&r" (temp), "+" GCC_OFF12_ASM() (*m)
213 : "ir" (1UL << bit)); 214 : "ir" (1UL << bit));
214 } while (unlikely(!temp)); 215 } while (unlikely(!temp));
215 } else 216 } else
@@ -244,7 +245,7 @@ static inline int test_and_set_bit(unsigned long nr,
244 " beqzl %2, 1b \n" 245 " beqzl %2, 1b \n"
245 " and %2, %0, %3 \n" 246 " and %2, %0, %3 \n"
246 " .set mips0 \n" 247 " .set mips0 \n"
247 : "=&r" (temp), "+m" (*m), "=&r" (res) 248 : "=&r" (temp), "+" GCC_OFF12_ASM() (*m), "=&r" (res)
248 : "r" (1UL << bit) 249 : "r" (1UL << bit)
249 : "memory"); 250 : "memory");
250 } else if (kernel_uses_llsc) { 251 } else if (kernel_uses_llsc) {
@@ -258,7 +259,7 @@ static inline int test_and_set_bit(unsigned long nr,
258 " or %2, %0, %3 \n" 259 " or %2, %0, %3 \n"
259 " " __SC "%2, %1 \n" 260 " " __SC "%2, %1 \n"
260 " .set mips0 \n" 261 " .set mips0 \n"
261 : "=&r" (temp), "+m" (*m), "=&r" (res) 262 : "=&r" (temp), "+" GCC_OFF12_ASM() (*m), "=&r" (res)
262 : "r" (1UL << bit) 263 : "r" (1UL << bit)
263 : "memory"); 264 : "memory");
264 } while (unlikely(!res)); 265 } while (unlikely(!res));
@@ -312,7 +313,7 @@ static inline int test_and_set_bit_lock(unsigned long nr,
312 " or %2, %0, %3 \n" 313 " or %2, %0, %3 \n"
313 " " __SC "%2, %1 \n" 314 " " __SC "%2, %1 \n"
314 " .set mips0 \n" 315 " .set mips0 \n"
315 : "=&r" (temp), "+m" (*m), "=&r" (res) 316 : "=&r" (temp), "+" GCC_OFF12_ASM() (*m), "=&r" (res)
316 : "r" (1UL << bit) 317 : "r" (1UL << bit)
317 : "memory"); 318 : "memory");
318 } while (unlikely(!res)); 319 } while (unlikely(!res));
@@ -354,7 +355,7 @@ static inline int test_and_clear_bit(unsigned long nr,
354 " beqzl %2, 1b \n" 355 " beqzl %2, 1b \n"
355 " and %2, %0, %3 \n" 356 " and %2, %0, %3 \n"
356 " .set mips0 \n" 357 " .set mips0 \n"
357 : "=&r" (temp), "+m" (*m), "=&r" (res) 358 : "=&r" (temp), "+" GCC_OFF12_ASM() (*m), "=&r" (res)
358 : "r" (1UL << bit) 359 : "r" (1UL << bit)
359 : "memory"); 360 : "memory");
360#ifdef CONFIG_CPU_MIPSR2 361#ifdef CONFIG_CPU_MIPSR2
@@ -368,7 +369,7 @@ static inline int test_and_clear_bit(unsigned long nr,
368 " " __EXT "%2, %0, %3, 1 \n" 369 " " __EXT "%2, %0, %3, 1 \n"
369 " " __INS "%0, $0, %3, 1 \n" 370 " " __INS "%0, $0, %3, 1 \n"
370 " " __SC "%0, %1 \n" 371 " " __SC "%0, %1 \n"
371 : "=&r" (temp), "+m" (*m), "=&r" (res) 372 : "=&r" (temp), "+" GCC_OFF12_ASM() (*m), "=&r" (res)
372 : "ir" (bit) 373 : "ir" (bit)
373 : "memory"); 374 : "memory");
374 } while (unlikely(!temp)); 375 } while (unlikely(!temp));
@@ -385,7 +386,7 @@ static inline int test_and_clear_bit(unsigned long nr,
385 " xor %2, %3 \n" 386 " xor %2, %3 \n"
386 " " __SC "%2, %1 \n" 387 " " __SC "%2, %1 \n"
387 " .set mips0 \n" 388 " .set mips0 \n"
388 : "=&r" (temp), "+m" (*m), "=&r" (res) 389 : "=&r" (temp), "+" GCC_OFF12_ASM() (*m), "=&r" (res)
389 : "r" (1UL << bit) 390 : "r" (1UL << bit)
390 : "memory"); 391 : "memory");
391 } while (unlikely(!res)); 392 } while (unlikely(!res));
@@ -427,7 +428,7 @@ static inline int test_and_change_bit(unsigned long nr,
427 " beqzl %2, 1b \n" 428 " beqzl %2, 1b \n"
428 " and %2, %0, %3 \n" 429 " and %2, %0, %3 \n"
429 " .set mips0 \n" 430 " .set mips0 \n"
430 : "=&r" (temp), "+m" (*m), "=&r" (res) 431 : "=&r" (temp), "+" GCC_OFF12_ASM() (*m), "=&r" (res)
431 : "r" (1UL << bit) 432 : "r" (1UL << bit)
432 : "memory"); 433 : "memory");
433 } else if (kernel_uses_llsc) { 434 } else if (kernel_uses_llsc) {
@@ -441,7 +442,7 @@ static inline int test_and_change_bit(unsigned long nr,
441 " xor %2, %0, %3 \n" 442 " xor %2, %0, %3 \n"
442 " " __SC "\t%2, %1 \n" 443 " " __SC "\t%2, %1 \n"
443 " .set mips0 \n" 444 " .set mips0 \n"
444 : "=&r" (temp), "+m" (*m), "=&r" (res) 445 : "=&r" (temp), "+" GCC_OFF12_ASM() (*m), "=&r" (res)
445 : "r" (1UL << bit) 446 : "r" (1UL << bit)
446 : "memory"); 447 : "memory");
447 } while (unlikely(!res)); 448 } while (unlikely(!res));
diff --git a/arch/mips/include/asm/bmips.h b/arch/mips/include/asm/bmips.h
index cbaccebf5065..30939b02e3ff 100644
--- a/arch/mips/include/asm/bmips.h
+++ b/arch/mips/include/asm/bmips.h
@@ -84,6 +84,7 @@ extern char bmips_smp_int_vec_end;
84extern int bmips_smp_enabled; 84extern int bmips_smp_enabled;
85extern int bmips_cpu_offset; 85extern int bmips_cpu_offset;
86extern cpumask_t bmips_booted_mask; 86extern cpumask_t bmips_booted_mask;
87extern unsigned long bmips_tp1_irqs;
87 88
88extern void bmips_ebase_setup(void); 89extern void bmips_ebase_setup(void);
89extern asmlinkage void plat_wired_tlb_setup(void); 90extern asmlinkage void plat_wired_tlb_setup(void);
diff --git a/arch/mips/include/asm/bootinfo.h b/arch/mips/include/asm/bootinfo.h
index 1f7ca8b00404..b603804caac5 100644
--- a/arch/mips/include/asm/bootinfo.h
+++ b/arch/mips/include/asm/bootinfo.h
@@ -70,10 +70,7 @@ enum loongson_machine_type {
70 MACH_DEXXON_GDIUM2F10, 70 MACH_DEXXON_GDIUM2F10,
71 MACH_LEMOTE_NAS, 71 MACH_LEMOTE_NAS,
72 MACH_LEMOTE_LL2F, 72 MACH_LEMOTE_LL2F,
73 MACH_LEMOTE_A1004, 73 MACH_LOONGSON_GENERIC,
74 MACH_LEMOTE_A1101,
75 MACH_LEMOTE_A1201,
76 MACH_LEMOTE_A1205,
77 MACH_LOONGSON_END 74 MACH_LOONGSON_END
78}; 75};
79 76
@@ -101,16 +98,16 @@ extern unsigned long mips_machtype;
101struct boot_mem_map { 98struct boot_mem_map {
102 int nr_map; 99 int nr_map;
103 struct boot_mem_map_entry { 100 struct boot_mem_map_entry {
104 phys_t addr; /* start of memory segment */ 101 phys_addr_t addr; /* start of memory segment */
105 phys_t size; /* size of memory segment */ 102 phys_addr_t size; /* size of memory segment */
106 long type; /* type of memory segment */ 103 long type; /* type of memory segment */
107 } map[BOOT_MEM_MAP_MAX]; 104 } map[BOOT_MEM_MAP_MAX];
108}; 105};
109 106
110extern struct boot_mem_map boot_mem_map; 107extern struct boot_mem_map boot_mem_map;
111 108
112extern void add_memory_region(phys_t start, phys_t size, long type); 109extern void add_memory_region(phys_addr_t start, phys_addr_t size, long type);
113extern void detect_memory_region(phys_t start, phys_t sz_min, phys_t sz_max); 110extern void detect_memory_region(phys_addr_t start, phys_addr_t sz_min, phys_addr_t sz_max);
114 111
115extern void prom_init(void); 112extern void prom_init(void);
116extern void prom_free_prom_memory(void); 113extern void prom_free_prom_memory(void);
diff --git a/arch/mips/include/asm/clock.h b/arch/mips/include/asm/clock.h
index 778e32d817bc..4809c29a4890 100644
--- a/arch/mips/include/asm/clock.h
+++ b/arch/mips/include/asm/clock.h
@@ -35,9 +35,6 @@ struct clk {
35#define CLK_ALWAYS_ENABLED (1 << 0) 35#define CLK_ALWAYS_ENABLED (1 << 0)
36#define CLK_RATE_PROPAGATES (1 << 1) 36#define CLK_RATE_PROPAGATES (1 << 1)
37 37
38/* Should be defined by processor-specific code */
39void arch_init_clk_ops(struct clk_ops **, int type);
40
41int clk_init(void); 38int clk_init(void);
42 39
43int __clk_enable(struct clk *); 40int __clk_enable(struct clk *);
diff --git a/arch/mips/include/asm/cmpxchg.h b/arch/mips/include/asm/cmpxchg.h
index eefcaa363a87..28b1edf19501 100644
--- a/arch/mips/include/asm/cmpxchg.h
+++ b/arch/mips/include/asm/cmpxchg.h
@@ -10,6 +10,7 @@
10 10
11#include <linux/bug.h> 11#include <linux/bug.h>
12#include <linux/irqflags.h> 12#include <linux/irqflags.h>
13#include <asm/compiler.h>
13#include <asm/war.h> 14#include <asm/war.h>
14 15
15static inline unsigned long __xchg_u32(volatile int * m, unsigned int val) 16static inline unsigned long __xchg_u32(volatile int * m, unsigned int val)
@@ -30,8 +31,8 @@ static inline unsigned long __xchg_u32(volatile int * m, unsigned int val)
30 " sc %2, %1 \n" 31 " sc %2, %1 \n"
31 " beqzl %2, 1b \n" 32 " beqzl %2, 1b \n"
32 " .set mips0 \n" 33 " .set mips0 \n"
33 : "=&r" (retval), "=m" (*m), "=&r" (dummy) 34 : "=&r" (retval), "=" GCC_OFF12_ASM() (*m), "=&r" (dummy)
34 : "R" (*m), "Jr" (val) 35 : GCC_OFF12_ASM() (*m), "Jr" (val)
35 : "memory"); 36 : "memory");
36 } else if (kernel_uses_llsc) { 37 } else if (kernel_uses_llsc) {
37 unsigned long dummy; 38 unsigned long dummy;
@@ -45,8 +46,9 @@ static inline unsigned long __xchg_u32(volatile int * m, unsigned int val)
45 " .set arch=r4000 \n" 46 " .set arch=r4000 \n"
46 " sc %2, %1 \n" 47 " sc %2, %1 \n"
47 " .set mips0 \n" 48 " .set mips0 \n"
48 : "=&r" (retval), "=m" (*m), "=&r" (dummy) 49 : "=&r" (retval), "=" GCC_OFF12_ASM() (*m),
49 : "R" (*m), "Jr" (val) 50 "=&r" (dummy)
51 : GCC_OFF12_ASM() (*m), "Jr" (val)
50 : "memory"); 52 : "memory");
51 } while (unlikely(!dummy)); 53 } while (unlikely(!dummy));
52 } else { 54 } else {
@@ -80,8 +82,8 @@ static inline __u64 __xchg_u64(volatile __u64 * m, __u64 val)
80 " scd %2, %1 \n" 82 " scd %2, %1 \n"
81 " beqzl %2, 1b \n" 83 " beqzl %2, 1b \n"
82 " .set mips0 \n" 84 " .set mips0 \n"
83 : "=&r" (retval), "=m" (*m), "=&r" (dummy) 85 : "=&r" (retval), "=" GCC_OFF12_ASM() (*m), "=&r" (dummy)
84 : "R" (*m), "Jr" (val) 86 : GCC_OFF12_ASM() (*m), "Jr" (val)
85 : "memory"); 87 : "memory");
86 } else if (kernel_uses_llsc) { 88 } else if (kernel_uses_llsc) {
87 unsigned long dummy; 89 unsigned long dummy;
@@ -93,8 +95,9 @@ static inline __u64 __xchg_u64(volatile __u64 * m, __u64 val)
93 " move %2, %z4 \n" 95 " move %2, %z4 \n"
94 " scd %2, %1 \n" 96 " scd %2, %1 \n"
95 " .set mips0 \n" 97 " .set mips0 \n"
96 : "=&r" (retval), "=m" (*m), "=&r" (dummy) 98 : "=&r" (retval), "=" GCC_OFF12_ASM() (*m),
97 : "R" (*m), "Jr" (val) 99 "=&r" (dummy)
100 : GCC_OFF12_ASM() (*m), "Jr" (val)
98 : "memory"); 101 : "memory");
99 } while (unlikely(!dummy)); 102 } while (unlikely(!dummy));
100 } else { 103 } else {
@@ -155,8 +158,8 @@ static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int siz
155 " beqzl $1, 1b \n" \ 158 " beqzl $1, 1b \n" \
156 "2: \n" \ 159 "2: \n" \
157 " .set pop \n" \ 160 " .set pop \n" \
158 : "=&r" (__ret), "=R" (*m) \ 161 : "=&r" (__ret), "=" GCC_OFF12_ASM() (*m) \
159 : "R" (*m), "Jr" (old), "Jr" (new) \ 162 : GCC_OFF12_ASM() (*m), "Jr" (old), "Jr" (new) \
160 : "memory"); \ 163 : "memory"); \
161 } else if (kernel_uses_llsc) { \ 164 } else if (kernel_uses_llsc) { \
162 __asm__ __volatile__( \ 165 __asm__ __volatile__( \
@@ -172,8 +175,8 @@ static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int siz
172 " beqz $1, 1b \n" \ 175 " beqz $1, 1b \n" \
173 " .set pop \n" \ 176 " .set pop \n" \
174 "2: \n" \ 177 "2: \n" \
175 : "=&r" (__ret), "=R" (*m) \ 178 : "=&r" (__ret), "=" GCC_OFF12_ASM() (*m) \
176 : "R" (*m), "Jr" (old), "Jr" (new) \ 179 : GCC_OFF12_ASM() (*m), "Jr" (old), "Jr" (new) \
177 : "memory"); \ 180 : "memory"); \
178 } else { \ 181 } else { \
179 unsigned long __flags; \ 182 unsigned long __flags; \
diff --git a/arch/mips/include/asm/compiler.h b/arch/mips/include/asm/compiler.h
index 71f5c5cfc58a..c73815e0123a 100644
--- a/arch/mips/include/asm/compiler.h
+++ b/arch/mips/include/asm/compiler.h
@@ -16,4 +16,12 @@
16#define GCC_REG_ACCUM "accum" 16#define GCC_REG_ACCUM "accum"
17#endif 17#endif
18 18
19#ifndef CONFIG_CPU_MICROMIPS
20#define GCC_OFF12_ASM() "R"
21#elif __GNUC__ > 4 || (__GNUC__ == 4 && __GNUC_MINOR__ >= 9)
22#define GCC_OFF12_ASM() "ZC"
23#else
24#error "microMIPS compilation unsupported with GCC older than 4.9"
25#endif
26
19#endif /* _ASM_COMPILER_H */ 27#endif /* _ASM_COMPILER_H */
diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
index 3325f3eb248c..2897cfafcaf0 100644
--- a/arch/mips/include/asm/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
@@ -344,4 +344,8 @@
344# define cpu_has_msa 0 344# define cpu_has_msa 0
345#endif 345#endif
346 346
347#ifndef cpu_has_fre
348# define cpu_has_fre (cpu_data[0].options & MIPS_CPU_FRE)
349#endif
350
347#endif /* __ASM_CPU_FEATURES_H */ 351#endif /* __ASM_CPU_FEATURES_H */
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index dfdc77ed1839..33866fce4d63 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -142,6 +142,7 @@
142#define PRID_IMP_BMIPS3300_BUG 0x0000 142#define PRID_IMP_BMIPS3300_BUG 0x0000
143#define PRID_IMP_BMIPS43XX 0xa000 143#define PRID_IMP_BMIPS43XX 0xa000
144#define PRID_IMP_BMIPS5000 0x5a00 144#define PRID_IMP_BMIPS5000 0x5a00
145#define PRID_IMP_BMIPS5200 0x5b00
145 146
146#define PRID_REV_BMIPS4380_LO 0x0040 147#define PRID_REV_BMIPS4380_LO 0x0040
147#define PRID_REV_BMIPS4380_HI 0x006f 148#define PRID_REV_BMIPS4380_HI 0x006f
@@ -368,6 +369,7 @@ enum cpu_type_enum {
368#define MIPS_CPU_HTW 0x100000000ull /* CPU support Hardware Page Table Walker */ 369#define MIPS_CPU_HTW 0x100000000ull /* CPU support Hardware Page Table Walker */
369#define MIPS_CPU_RIXIEX 0x200000000ull /* CPU has unique exception codes for {Read, Execute}-Inhibit exceptions */ 370#define MIPS_CPU_RIXIEX 0x200000000ull /* CPU has unique exception codes for {Read, Execute}-Inhibit exceptions */
370#define MIPS_CPU_MAAR 0x400000000ull /* MAAR(I) registers are present */ 371#define MIPS_CPU_MAAR 0x400000000ull /* MAAR(I) registers are present */
372#define MIPS_CPU_FRE 0x800000000ull /* FRE & UFE bits implemented */
371 373
372/* 374/*
373 * CPU ASE encodings 375 * CPU ASE encodings
diff --git a/arch/mips/include/asm/edac.h b/arch/mips/include/asm/edac.h
index 4da0c1fe30d9..ae6fedcb0060 100644
--- a/arch/mips/include/asm/edac.h
+++ b/arch/mips/include/asm/edac.h
@@ -1,6 +1,8 @@
1#ifndef ASM_EDAC_H 1#ifndef ASM_EDAC_H
2#define ASM_EDAC_H 2#define ASM_EDAC_H
3 3
4#include <asm/compiler.h>
5
4/* ECC atomic, DMA, SMP and interrupt safe scrub function */ 6/* ECC atomic, DMA, SMP and interrupt safe scrub function */
5 7
6static inline void atomic_scrub(void *va, u32 size) 8static inline void atomic_scrub(void *va, u32 size)
@@ -24,8 +26,8 @@ static inline void atomic_scrub(void *va, u32 size)
24 " sc %0, %1 \n" 26 " sc %0, %1 \n"
25 " beqz %0, 1b \n" 27 " beqz %0, 1b \n"
26 " .set mips0 \n" 28 " .set mips0 \n"
27 : "=&r" (temp), "=m" (*virt_addr) 29 : "=&r" (temp), "=" GCC_OFF12_ASM() (*virt_addr)
28 : "m" (*virt_addr)); 30 : GCC_OFF12_ASM() (*virt_addr));
29 31
30 virt_addr++; 32 virt_addr++;
31 } 33 }
diff --git a/arch/mips/include/asm/elf.h b/arch/mips/include/asm/elf.h
index 1d38fe0edd2d..eb4d95de619c 100644
--- a/arch/mips/include/asm/elf.h
+++ b/arch/mips/include/asm/elf.h
@@ -8,6 +8,8 @@
8#ifndef _ASM_ELF_H 8#ifndef _ASM_ELF_H
9#define _ASM_ELF_H 9#define _ASM_ELF_H
10 10
11#include <linux/fs.h>
12#include <uapi/linux/elf.h>
11 13
12/* ELF header e_flags defines. */ 14/* ELF header e_flags defines. */
13/* MIPS architecture level. */ 15/* MIPS architecture level. */
@@ -28,6 +30,7 @@
28#define PT_MIPS_REGINFO 0x70000000 30#define PT_MIPS_REGINFO 0x70000000
29#define PT_MIPS_RTPROC 0x70000001 31#define PT_MIPS_RTPROC 0x70000001
30#define PT_MIPS_OPTIONS 0x70000002 32#define PT_MIPS_OPTIONS 0x70000002
33#define PT_MIPS_ABIFLAGS 0x70000003
31 34
32/* Flags in the e_flags field of the header */ 35/* Flags in the e_flags field of the header */
33#define EF_MIPS_NOREORDER 0x00000001 36#define EF_MIPS_NOREORDER 0x00000001
@@ -174,6 +177,30 @@ typedef elf_greg_t elf_gregset_t[ELF_NGREG];
174typedef double elf_fpreg_t; 177typedef double elf_fpreg_t;
175typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG]; 178typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];
176 179
180struct mips_elf_abiflags_v0 {
181 uint16_t version; /* Version of flags structure */
182 uint8_t isa_level; /* The level of the ISA: 1-5, 32, 64 */
183 uint8_t isa_rev; /* The revision of ISA: 0 for MIPS V and below,
184 1-n otherwise */
185 uint8_t gpr_size; /* The size of general purpose registers */
186 uint8_t cpr1_size; /* The size of co-processor 1 registers */
187 uint8_t cpr2_size; /* The size of co-processor 2 registers */
188 uint8_t fp_abi; /* The floating-point ABI */
189 uint32_t isa_ext; /* Mask of processor-specific extensions */
190 uint32_t ases; /* Mask of ASEs used */
191 uint32_t flags1; /* Mask of general flags */
192 uint32_t flags2;
193};
194
195#define MIPS_ABI_FP_ANY 0 /* FP ABI doesn't matter */
196#define MIPS_ABI_FP_DOUBLE 1 /* -mdouble-float */
197#define MIPS_ABI_FP_SINGLE 2 /* -msingle-float */
198#define MIPS_ABI_FP_SOFT 3 /* -msoft-float */
199#define MIPS_ABI_FP_OLD_64 4 /* -mips32r2 -mfp64 */
200#define MIPS_ABI_FP_XX 5 /* -mfpxx */
201#define MIPS_ABI_FP_64 6 /* -mips32r2 -mfp64 */
202#define MIPS_ABI_FP_64A 7 /* -mips32r2 -mfp64 -mno-odd-spreg */
203
177#ifdef CONFIG_32BIT 204#ifdef CONFIG_32BIT
178 205
179/* 206/*
@@ -262,16 +289,13 @@ extern struct mips_abi mips_abi_n32;
262 289
263#ifdef CONFIG_32BIT 290#ifdef CONFIG_32BIT
264 291
265#define SET_PERSONALITY(ex) \ 292#define SET_PERSONALITY2(ex, state) \
266do { \ 293do { \
267 if ((ex).e_flags & EF_MIPS_FP64) \
268 clear_thread_flag(TIF_32BIT_FPREGS); \
269 else \
270 set_thread_flag(TIF_32BIT_FPREGS); \
271 \
272 if (personality(current->personality) != PER_LINUX) \ 294 if (personality(current->personality) != PER_LINUX) \
273 set_personality(PER_LINUX); \ 295 set_personality(PER_LINUX); \
274 \ 296 \
297 mips_set_personality_fp(state); \
298 \
275 current->thread.abi = &mips_abi; \ 299 current->thread.abi = &mips_abi; \
276} while (0) 300} while (0)
277 301
@@ -291,44 +315,44 @@ do { \
291#endif 315#endif
292 316
293#ifdef CONFIG_MIPS32_O32 317#ifdef CONFIG_MIPS32_O32
294#define __SET_PERSONALITY32_O32(ex) \ 318#define __SET_PERSONALITY32_O32(ex, state) \
295 do { \ 319 do { \
296 set_thread_flag(TIF_32BIT_REGS); \ 320 set_thread_flag(TIF_32BIT_REGS); \
297 set_thread_flag(TIF_32BIT_ADDR); \ 321 set_thread_flag(TIF_32BIT_ADDR); \
298 \ 322 \
299 if (!((ex).e_flags & EF_MIPS_FP64)) \ 323 mips_set_personality_fp(state); \
300 set_thread_flag(TIF_32BIT_FPREGS); \
301 \ 324 \
302 current->thread.abi = &mips_abi_32; \ 325 current->thread.abi = &mips_abi_32; \
303 } while (0) 326 } while (0)
304#else 327#else
305#define __SET_PERSONALITY32_O32(ex) \ 328#define __SET_PERSONALITY32_O32(ex, state) \
306 do { } while (0) 329 do { } while (0)
307#endif 330#endif
308 331
309#ifdef CONFIG_MIPS32_COMPAT 332#ifdef CONFIG_MIPS32_COMPAT
310#define __SET_PERSONALITY32(ex) \ 333#define __SET_PERSONALITY32(ex, state) \
311do { \ 334do { \
312 if ((((ex).e_flags & EF_MIPS_ABI2) != 0) && \ 335 if ((((ex).e_flags & EF_MIPS_ABI2) != 0) && \
313 ((ex).e_flags & EF_MIPS_ABI) == 0) \ 336 ((ex).e_flags & EF_MIPS_ABI) == 0) \
314 __SET_PERSONALITY32_N32(); \ 337 __SET_PERSONALITY32_N32(); \
315 else \ 338 else \
316 __SET_PERSONALITY32_O32(ex); \ 339 __SET_PERSONALITY32_O32(ex, state); \
317} while (0) 340} while (0)
318#else 341#else
319#define __SET_PERSONALITY32(ex) do { } while (0) 342#define __SET_PERSONALITY32(ex, state) do { } while (0)
320#endif 343#endif
321 344
322#define SET_PERSONALITY(ex) \ 345#define SET_PERSONALITY2(ex, state) \
323do { \ 346do { \
324 unsigned int p; \ 347 unsigned int p; \
325 \ 348 \
326 clear_thread_flag(TIF_32BIT_REGS); \ 349 clear_thread_flag(TIF_32BIT_REGS); \
327 clear_thread_flag(TIF_32BIT_FPREGS); \ 350 clear_thread_flag(TIF_32BIT_FPREGS); \
351 clear_thread_flag(TIF_HYBRID_FPREGS); \
328 clear_thread_flag(TIF_32BIT_ADDR); \ 352 clear_thread_flag(TIF_32BIT_ADDR); \
329 \ 353 \
330 if ((ex).e_ident[EI_CLASS] == ELFCLASS32) \ 354 if ((ex).e_ident[EI_CLASS] == ELFCLASS32) \
331 __SET_PERSONALITY32(ex); \ 355 __SET_PERSONALITY32(ex, state); \
332 else \ 356 else \
333 current->thread.abi = &mips_abi; \ 357 current->thread.abi = &mips_abi; \
334 \ 358 \
@@ -390,4 +414,24 @@ struct mm_struct;
390extern unsigned long arch_randomize_brk(struct mm_struct *mm); 414extern unsigned long arch_randomize_brk(struct mm_struct *mm);
391#define arch_randomize_brk arch_randomize_brk 415#define arch_randomize_brk arch_randomize_brk
392 416
417struct arch_elf_state {
418 int fp_abi;
419 int interp_fp_abi;
420 int overall_abi;
421};
422
423#define INIT_ARCH_ELF_STATE { \
424 .fp_abi = -1, \
425 .interp_fp_abi = -1, \
426 .overall_abi = -1, \
427}
428
429extern int arch_elf_pt_proc(void *ehdr, void *phdr, struct file *elf,
430 bool is_interp, struct arch_elf_state *state);
431
432extern int arch_check_elf(void *ehdr, bool has_interpreter,
433 struct arch_elf_state *state);
434
435extern void mips_set_personality_fp(struct arch_elf_state *state);
436
393#endif /* _ASM_ELF_H */ 437#endif /* _ASM_ELF_H */
diff --git a/arch/mips/include/asm/fpu.h b/arch/mips/include/asm/fpu.h
index dd562414cd5e..994d21939676 100644
--- a/arch/mips/include/asm/fpu.h
+++ b/arch/mips/include/asm/fpu.h
@@ -36,14 +36,16 @@ extern void _restore_fp(struct task_struct *);
36 36
37/* 37/*
38 * This enum specifies a mode in which we want the FPU to operate, for cores 38 * This enum specifies a mode in which we want the FPU to operate, for cores
39 * which implement the Status.FR bit. Note that FPU_32BIT & FPU_64BIT 39 * which implement the Status.FR bit. Note that the bottom bit of the value
40 * purposefully have the values 0 & 1 respectively, so that an integer value 40 * purposefully matches the desired value of the Status.FR bit.
41 * of Status.FR can be trivially casted to the corresponding enum fpu_mode.
42 */ 41 */
43enum fpu_mode { 42enum fpu_mode {
44 FPU_32BIT = 0, /* FR = 0 */ 43 FPU_32BIT = 0, /* FR = 0 */
45 FPU_64BIT, /* FR = 1 */ 44 FPU_64BIT, /* FR = 1, FRE = 0 */
46 FPU_AS_IS, 45 FPU_AS_IS,
46 FPU_HYBRID, /* FR = 1, FRE = 1 */
47
48#define FPU_FR_MASK 0x1
47}; 49};
48 50
49static inline int __enable_fpu(enum fpu_mode mode) 51static inline int __enable_fpu(enum fpu_mode mode)
@@ -57,6 +59,14 @@ static inline int __enable_fpu(enum fpu_mode mode)
57 enable_fpu_hazard(); 59 enable_fpu_hazard();
58 return 0; 60 return 0;
59 61
62 case FPU_HYBRID:
63 if (!cpu_has_fre)
64 return SIGFPE;
65
66 /* set FRE */
67 write_c0_config5(read_c0_config5() | MIPS_CONF5_FRE);
68 goto fr_common;
69
60 case FPU_64BIT: 70 case FPU_64BIT:
61#if !(defined(CONFIG_CPU_MIPS32_R2) || defined(CONFIG_64BIT)) 71#if !(defined(CONFIG_CPU_MIPS32_R2) || defined(CONFIG_64BIT))
62 /* we only have a 32-bit FPU */ 72 /* we only have a 32-bit FPU */
@@ -64,8 +74,11 @@ static inline int __enable_fpu(enum fpu_mode mode)
64#endif 74#endif
65 /* fall through */ 75 /* fall through */
66 case FPU_32BIT: 76 case FPU_32BIT:
77 /* clear FRE */
78 write_c0_config5(read_c0_config5() & ~MIPS_CONF5_FRE);
79fr_common:
67 /* set CU1 & change FR appropriately */ 80 /* set CU1 & change FR appropriately */
68 fr = (int)mode; 81 fr = (int)mode & FPU_FR_MASK;
69 change_c0_status(ST0_CU1 | ST0_FR, ST0_CU1 | (fr ? ST0_FR : 0)); 82 change_c0_status(ST0_CU1 | ST0_FR, ST0_CU1 | (fr ? ST0_FR : 0));
70 enable_fpu_hazard(); 83 enable_fpu_hazard();
71 84
@@ -102,13 +115,17 @@ static inline int __own_fpu(void)
102 enum fpu_mode mode; 115 enum fpu_mode mode;
103 int ret; 116 int ret;
104 117
105 mode = !test_thread_flag(TIF_32BIT_FPREGS); 118 if (test_thread_flag(TIF_HYBRID_FPREGS))
119 mode = FPU_HYBRID;
120 else
121 mode = !test_thread_flag(TIF_32BIT_FPREGS);
122
106 ret = __enable_fpu(mode); 123 ret = __enable_fpu(mode);
107 if (ret) 124 if (ret)
108 return ret; 125 return ret;
109 126
110 KSTK_STATUS(current) |= ST0_CU1; 127 KSTK_STATUS(current) |= ST0_CU1;
111 if (mode == FPU_64BIT) 128 if (mode == FPU_64BIT || mode == FPU_HYBRID)
112 KSTK_STATUS(current) |= ST0_FR; 129 KSTK_STATUS(current) |= ST0_FR;
113 else /* mode == FPU_32BIT */ 130 else /* mode == FPU_32BIT */
114 KSTK_STATUS(current) &= ~ST0_FR; 131 KSTK_STATUS(current) &= ~ST0_FR;
@@ -166,8 +183,24 @@ static inline int init_fpu(void)
166 183
167 if (cpu_has_fpu) { 184 if (cpu_has_fpu) {
168 ret = __own_fpu(); 185 ret = __own_fpu();
169 if (!ret) 186 if (!ret) {
187 unsigned int config5 = read_c0_config5();
188
189 /*
190 * Ensure FRE is clear whilst running _init_fpu, since
191 * single precision FP instructions are used. If FRE
192 * was set then we'll just end up initialising all 32
193 * 64b registers.
194 */
195 write_c0_config5(config5 & ~MIPS_CONF5_FRE);
196 enable_fpu_hazard();
197
170 _init_fpu(); 198 _init_fpu();
199
200 /* Restore FRE */
201 write_c0_config5(config5);
202 enable_fpu_hazard();
203 }
171 } else 204 } else
172 fpu_emulator_init_fpu(); 205 fpu_emulator_init_fpu();
173 206
diff --git a/arch/mips/include/asm/futex.h b/arch/mips/include/asm/futex.h
index 194cda0396a3..ef9987a61d88 100644
--- a/arch/mips/include/asm/futex.h
+++ b/arch/mips/include/asm/futex.h
@@ -14,6 +14,7 @@
14#include <linux/uaccess.h> 14#include <linux/uaccess.h>
15#include <asm/asm-eva.h> 15#include <asm/asm-eva.h>
16#include <asm/barrier.h> 16#include <asm/barrier.h>
17#include <asm/compiler.h>
17#include <asm/errno.h> 18#include <asm/errno.h>
18#include <asm/war.h> 19#include <asm/war.h>
19 20
@@ -32,6 +33,7 @@
32 " beqzl $1, 1b \n" \ 33 " beqzl $1, 1b \n" \
33 __WEAK_LLSC_MB \ 34 __WEAK_LLSC_MB \
34 "3: \n" \ 35 "3: \n" \
36 " .insn \n" \
35 " .set pop \n" \ 37 " .set pop \n" \
36 " .set mips0 \n" \ 38 " .set mips0 \n" \
37 " .section .fixup,\"ax\" \n" \ 39 " .section .fixup,\"ax\" \n" \
@@ -42,8 +44,10 @@
42 " "__UA_ADDR "\t1b, 4b \n" \ 44 " "__UA_ADDR "\t1b, 4b \n" \
43 " "__UA_ADDR "\t2b, 4b \n" \ 45 " "__UA_ADDR "\t2b, 4b \n" \
44 " .previous \n" \ 46 " .previous \n" \
45 : "=r" (ret), "=&r" (oldval), "=R" (*uaddr) \ 47 : "=r" (ret), "=&r" (oldval), \
46 : "0" (0), "R" (*uaddr), "Jr" (oparg), "i" (-EFAULT) \ 48 "=" GCC_OFF12_ASM() (*uaddr) \
49 : "0" (0), GCC_OFF12_ASM() (*uaddr), "Jr" (oparg), \
50 "i" (-EFAULT) \
47 : "memory"); \ 51 : "memory"); \
48 } else if (cpu_has_llsc) { \ 52 } else if (cpu_has_llsc) { \
49 __asm__ __volatile__( \ 53 __asm__ __volatile__( \
@@ -58,6 +62,7 @@
58 " beqz $1, 1b \n" \ 62 " beqz $1, 1b \n" \
59 __WEAK_LLSC_MB \ 63 __WEAK_LLSC_MB \
60 "3: \n" \ 64 "3: \n" \
65 " .insn \n" \
61 " .set pop \n" \ 66 " .set pop \n" \
62 " .set mips0 \n" \ 67 " .set mips0 \n" \
63 " .section .fixup,\"ax\" \n" \ 68 " .section .fixup,\"ax\" \n" \
@@ -68,8 +73,10 @@
68 " "__UA_ADDR "\t1b, 4b \n" \ 73 " "__UA_ADDR "\t1b, 4b \n" \
69 " "__UA_ADDR "\t2b, 4b \n" \ 74 " "__UA_ADDR "\t2b, 4b \n" \
70 " .previous \n" \ 75 " .previous \n" \
71 : "=r" (ret), "=&r" (oldval), "=R" (*uaddr) \ 76 : "=r" (ret), "=&r" (oldval), \
72 : "0" (0), "R" (*uaddr), "Jr" (oparg), "i" (-EFAULT) \ 77 "=" GCC_OFF12_ASM() (*uaddr) \
78 : "0" (0), GCC_OFF12_ASM() (*uaddr), "Jr" (oparg), \
79 "i" (-EFAULT) \
73 : "memory"); \ 80 : "memory"); \
74 } else \ 81 } else \
75 ret = -ENOSYS; \ 82 ret = -ENOSYS; \
@@ -157,6 +164,7 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
157 " beqzl $1, 1b \n" 164 " beqzl $1, 1b \n"
158 __WEAK_LLSC_MB 165 __WEAK_LLSC_MB
159 "3: \n" 166 "3: \n"
167 " .insn \n"
160 " .set pop \n" 168 " .set pop \n"
161 " .section .fixup,\"ax\" \n" 169 " .section .fixup,\"ax\" \n"
162 "4: li %0, %6 \n" 170 "4: li %0, %6 \n"
@@ -166,8 +174,9 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
166 " "__UA_ADDR "\t1b, 4b \n" 174 " "__UA_ADDR "\t1b, 4b \n"
167 " "__UA_ADDR "\t2b, 4b \n" 175 " "__UA_ADDR "\t2b, 4b \n"
168 " .previous \n" 176 " .previous \n"
169 : "+r" (ret), "=&r" (val), "=R" (*uaddr) 177 : "+r" (ret), "=&r" (val), "=" GCC_OFF12_ASM() (*uaddr)
170 : "R" (*uaddr), "Jr" (oldval), "Jr" (newval), "i" (-EFAULT) 178 : GCC_OFF12_ASM() (*uaddr), "Jr" (oldval), "Jr" (newval),
179 "i" (-EFAULT)
171 : "memory"); 180 : "memory");
172 } else if (cpu_has_llsc) { 181 } else if (cpu_has_llsc) {
173 __asm__ __volatile__( 182 __asm__ __volatile__(
@@ -184,6 +193,7 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
184 " beqz $1, 1b \n" 193 " beqz $1, 1b \n"
185 __WEAK_LLSC_MB 194 __WEAK_LLSC_MB
186 "3: \n" 195 "3: \n"
196 " .insn \n"
187 " .set pop \n" 197 " .set pop \n"
188 " .section .fixup,\"ax\" \n" 198 " .section .fixup,\"ax\" \n"
189 "4: li %0, %6 \n" 199 "4: li %0, %6 \n"
@@ -193,8 +203,9 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
193 " "__UA_ADDR "\t1b, 4b \n" 203 " "__UA_ADDR "\t1b, 4b \n"
194 " "__UA_ADDR "\t2b, 4b \n" 204 " "__UA_ADDR "\t2b, 4b \n"
195 " .previous \n" 205 " .previous \n"
196 : "+r" (ret), "=&r" (val), "=R" (*uaddr) 206 : "+r" (ret), "=&r" (val), "=" GCC_OFF12_ASM() (*uaddr)
197 : "R" (*uaddr), "Jr" (oldval), "Jr" (newval), "i" (-EFAULT) 207 : GCC_OFF12_ASM() (*uaddr), "Jr" (oldval), "Jr" (newval),
208 "i" (-EFAULT)
198 : "memory"); 209 : "memory");
199 } else 210 } else
200 return -ENOSYS; 211 return -ENOSYS;
diff --git a/arch/mips/include/asm/gic.h b/arch/mips/include/asm/gic.h
deleted file mode 100644
index d7699cf7e135..000000000000
--- a/arch/mips/include/asm/gic.h
+++ /dev/null
@@ -1,384 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2000, 07 MIPS Technologies, Inc.
7 *
8 * GIC Register Definitions
9 *
10 */
11#ifndef _ASM_GICREGS_H
12#define _ASM_GICREGS_H
13
14#include <linux/bitmap.h>
15#include <linux/threads.h>
16
17#include <irq.h>
18
19#undef GICISBYTELITTLEENDIAN
20
21/* Constants */
22#define GIC_POL_POS 1
23#define GIC_POL_NEG 0
24#define GIC_TRIG_EDGE 1
25#define GIC_TRIG_LEVEL 0
26
27#define MSK(n) ((1 << (n)) - 1)
28#define REG32(addr) (*(volatile unsigned int *) (addr))
29#define REG(base, offs) REG32((unsigned long)(base) + offs##_##OFS)
30#define REGP(base, phys) REG32((unsigned long)(base) + (phys))
31
32/* Accessors */
33#define GIC_REG(segment, offset) \
34 REG32(_gic_base + segment##_##SECTION_OFS + offset##_##OFS)
35#define GIC_REG_ADDR(segment, offset) \
36 REG32(_gic_base + segment##_##SECTION_OFS + offset)
37
38#define GIC_ABS_REG(segment, offset) \
39 (_gic_base + segment##_##SECTION_OFS + offset##_##OFS)
40#define GIC_REG_ABS_ADDR(segment, offset) \
41 (_gic_base + segment##_##SECTION_OFS + offset)
42
43#ifdef GICISBYTELITTLEENDIAN
44#define GICREAD(reg, data) ((data) = (reg), (data) = le32_to_cpu(data))
45#define GICWRITE(reg, data) ((reg) = cpu_to_le32(data))
46#else
47#define GICREAD(reg, data) ((data) = (reg))
48#define GICWRITE(reg, data) ((reg) = (data))
49#endif
50#define GICBIS(reg, mask, bits) \
51 do { u32 data; \
52 GICREAD(reg, data); \
53 data &= ~(mask); \
54 data |= ((bits) & (mask)); \
55 GICWRITE((reg), data); \
56 } while (0)
57
58
59/* GIC Address Space */
60#define SHARED_SECTION_OFS 0x0000
61#define SHARED_SECTION_SIZE 0x8000
62#define VPE_LOCAL_SECTION_OFS 0x8000
63#define VPE_LOCAL_SECTION_SIZE 0x4000
64#define VPE_OTHER_SECTION_OFS 0xc000
65#define VPE_OTHER_SECTION_SIZE 0x4000
66#define USM_VISIBLE_SECTION_OFS 0x10000
67#define USM_VISIBLE_SECTION_SIZE 0x10000
68
69/* Register Map for Shared Section */
70
71#define GIC_SH_CONFIG_OFS 0x0000
72
73/* Shared Global Counter */
74#define GIC_SH_COUNTER_31_00_OFS 0x0010
75#define GIC_SH_COUNTER_63_32_OFS 0x0014
76#define GIC_SH_REVISIONID_OFS 0x0020
77
78/* Interrupt Polarity */
79#define GIC_SH_POL_31_0_OFS 0x0100
80#define GIC_SH_POL_63_32_OFS 0x0104
81#define GIC_SH_POL_95_64_OFS 0x0108
82#define GIC_SH_POL_127_96_OFS 0x010c
83#define GIC_SH_POL_159_128_OFS 0x0110
84#define GIC_SH_POL_191_160_OFS 0x0114
85#define GIC_SH_POL_223_192_OFS 0x0118
86#define GIC_SH_POL_255_224_OFS 0x011c
87
88/* Edge/Level Triggering */
89#define GIC_SH_TRIG_31_0_OFS 0x0180
90#define GIC_SH_TRIG_63_32_OFS 0x0184
91#define GIC_SH_TRIG_95_64_OFS 0x0188
92#define GIC_SH_TRIG_127_96_OFS 0x018c
93#define GIC_SH_TRIG_159_128_OFS 0x0190
94#define GIC_SH_TRIG_191_160_OFS 0x0194
95#define GIC_SH_TRIG_223_192_OFS 0x0198
96#define GIC_SH_TRIG_255_224_OFS 0x019c
97
98/* Dual Edge Triggering */
99#define GIC_SH_DUAL_31_0_OFS 0x0200
100#define GIC_SH_DUAL_63_32_OFS 0x0204
101#define GIC_SH_DUAL_95_64_OFS 0x0208
102#define GIC_SH_DUAL_127_96_OFS 0x020c
103#define GIC_SH_DUAL_159_128_OFS 0x0210
104#define GIC_SH_DUAL_191_160_OFS 0x0214
105#define GIC_SH_DUAL_223_192_OFS 0x0218
106#define GIC_SH_DUAL_255_224_OFS 0x021c
107
108/* Set/Clear corresponding bit in Edge Detect Register */
109#define GIC_SH_WEDGE_OFS 0x0280
110
111/* Reset Mask - Disables Interrupt */
112#define GIC_SH_RMASK_31_0_OFS 0x0300
113#define GIC_SH_RMASK_63_32_OFS 0x0304
114#define GIC_SH_RMASK_95_64_OFS 0x0308
115#define GIC_SH_RMASK_127_96_OFS 0x030c
116#define GIC_SH_RMASK_159_128_OFS 0x0310
117#define GIC_SH_RMASK_191_160_OFS 0x0314
118#define GIC_SH_RMASK_223_192_OFS 0x0318
119#define GIC_SH_RMASK_255_224_OFS 0x031c
120
121/* Set Mask (WO) - Enables Interrupt */
122#define GIC_SH_SMASK_31_0_OFS 0x0380
123#define GIC_SH_SMASK_63_32_OFS 0x0384
124#define GIC_SH_SMASK_95_64_OFS 0x0388
125#define GIC_SH_SMASK_127_96_OFS 0x038c
126#define GIC_SH_SMASK_159_128_OFS 0x0390
127#define GIC_SH_SMASK_191_160_OFS 0x0394
128#define GIC_SH_SMASK_223_192_OFS 0x0398
129#define GIC_SH_SMASK_255_224_OFS 0x039c
130
131/* Global Interrupt Mask Register (RO) - Bit Set == Interrupt enabled */
132#define GIC_SH_MASK_31_0_OFS 0x0400
133#define GIC_SH_MASK_63_32_OFS 0x0404
134#define GIC_SH_MASK_95_64_OFS 0x0408
135#define GIC_SH_MASK_127_96_OFS 0x040c
136#define GIC_SH_MASK_159_128_OFS 0x0410
137#define GIC_SH_MASK_191_160_OFS 0x0414
138#define GIC_SH_MASK_223_192_OFS 0x0418
139#define GIC_SH_MASK_255_224_OFS 0x041c
140
141/* Pending Global Interrupts (RO) */
142#define GIC_SH_PEND_31_0_OFS 0x0480
143#define GIC_SH_PEND_63_32_OFS 0x0484
144#define GIC_SH_PEND_95_64_OFS 0x0488
145#define GIC_SH_PEND_127_96_OFS 0x048c
146#define GIC_SH_PEND_159_128_OFS 0x0490
147#define GIC_SH_PEND_191_160_OFS 0x0494
148#define GIC_SH_PEND_223_192_OFS 0x0498
149#define GIC_SH_PEND_255_224_OFS 0x049c
150
151#define GIC_SH_INTR_MAP_TO_PIN_BASE_OFS 0x0500
152
153/* Maps Interrupt X to a Pin */
154#define GIC_SH_MAP_TO_PIN(intr) \
155 (GIC_SH_INTR_MAP_TO_PIN_BASE_OFS + (4 * intr))
156
157#define GIC_SH_INTR_MAP_TO_VPE_BASE_OFS 0x2000
158
159/* Maps Interrupt X to a VPE */
160#define GIC_SH_MAP_TO_VPE_REG_OFF(intr, vpe) \
161 (GIC_SH_INTR_MAP_TO_VPE_BASE_OFS + (32 * (intr)) + (((vpe) / 32) * 4))
162#define GIC_SH_MAP_TO_VPE_REG_BIT(vpe) (1 << ((vpe) % 32))
163
164/* Convert an interrupt number to a byte offset/bit for multi-word registers */
165#define GIC_INTR_OFS(intr) (((intr) / 32)*4)
166#define GIC_INTR_BIT(intr) ((intr) % 32)
167
168/* Polarity : Reset Value is always 0 */
169#define GIC_SH_SET_POLARITY_OFS 0x0100
170#define GIC_SET_POLARITY(intr, pol) \
171 GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_POLARITY_OFS + \
172 GIC_INTR_OFS(intr)), (1 << GIC_INTR_BIT(intr)), \
173 (pol) << GIC_INTR_BIT(intr))
174
175/* Triggering : Reset Value is always 0 */
176#define GIC_SH_SET_TRIGGER_OFS 0x0180
177#define GIC_SET_TRIGGER(intr, trig) \
178 GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_TRIGGER_OFS + \
179 GIC_INTR_OFS(intr)), (1 << GIC_INTR_BIT(intr)), \
180 (trig) << GIC_INTR_BIT(intr))
181
182/* Mask manipulation */
183#define GIC_SH_SMASK_OFS 0x0380
184#define GIC_SET_INTR_MASK(intr) \
185 GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_SMASK_OFS + \
186 GIC_INTR_OFS(intr)), 1 << GIC_INTR_BIT(intr))
187#define GIC_SH_RMASK_OFS 0x0300
188#define GIC_CLR_INTR_MASK(intr) \
189 GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_RMASK_OFS + \
190 GIC_INTR_OFS(intr)), 1 << GIC_INTR_BIT(intr))
191
192/* Register Map for Local Section */
193#define GIC_VPE_CTL_OFS 0x0000
194#define GIC_VPE_PEND_OFS 0x0004
195#define GIC_VPE_MASK_OFS 0x0008
196#define GIC_VPE_RMASK_OFS 0x000c
197#define GIC_VPE_SMASK_OFS 0x0010
198#define GIC_VPE_WD_MAP_OFS 0x0040
199#define GIC_VPE_COMPARE_MAP_OFS 0x0044
200#define GIC_VPE_TIMER_MAP_OFS 0x0048
201#define GIC_VPE_PERFCTR_MAP_OFS 0x0050
202#define GIC_VPE_SWINT0_MAP_OFS 0x0054
203#define GIC_VPE_SWINT1_MAP_OFS 0x0058
204#define GIC_VPE_OTHER_ADDR_OFS 0x0080
205#define GIC_VPE_WD_CONFIG0_OFS 0x0090
206#define GIC_VPE_WD_COUNT0_OFS 0x0094
207#define GIC_VPE_WD_INITIAL0_OFS 0x0098
208#define GIC_VPE_COMPARE_LO_OFS 0x00a0
209#define GIC_VPE_COMPARE_HI_OFS 0x00a4
210
211#define GIC_VPE_EIC_SHADOW_SET_BASE 0x0100
212#define GIC_VPE_EIC_SS(intr) \
213 (GIC_VPE_EIC_SHADOW_SET_BASE + (4 * intr))
214
215#define GIC_VPE_EIC_VEC_BASE 0x0800
216#define GIC_VPE_EIC_VEC(intr) \
217 (GIC_VPE_EIC_VEC_BASE + (4 * intr))
218
219#define GIC_VPE_TENABLE_NMI_OFS 0x1000
220#define GIC_VPE_TENABLE_YQ_OFS 0x1004
221#define GIC_VPE_TENABLE_INT_31_0_OFS 0x1080
222#define GIC_VPE_TENABLE_INT_63_32_OFS 0x1084
223
224/* User Mode Visible Section Register Map */
225#define GIC_UMV_SH_COUNTER_31_00_OFS 0x0000
226#define GIC_UMV_SH_COUNTER_63_32_OFS 0x0004
227
228/* Masks */
229#define GIC_SH_CONFIG_COUNTSTOP_SHF 28
230#define GIC_SH_CONFIG_COUNTSTOP_MSK (MSK(1) << GIC_SH_CONFIG_COUNTSTOP_SHF)
231
232#define GIC_SH_CONFIG_COUNTBITS_SHF 24
233#define GIC_SH_CONFIG_COUNTBITS_MSK (MSK(4) << GIC_SH_CONFIG_COUNTBITS_SHF)
234
235#define GIC_SH_CONFIG_NUMINTRS_SHF 16
236#define GIC_SH_CONFIG_NUMINTRS_MSK (MSK(8) << GIC_SH_CONFIG_NUMINTRS_SHF)
237
238#define GIC_SH_CONFIG_NUMVPES_SHF 0
239#define GIC_SH_CONFIG_NUMVPES_MSK (MSK(8) << GIC_SH_CONFIG_NUMVPES_SHF)
240
241#define GIC_SH_WEDGE_SET(intr) (intr | (0x1 << 31))
242#define GIC_SH_WEDGE_CLR(intr) (intr & ~(0x1 << 31))
243
244#define GIC_MAP_TO_PIN_SHF 31
245#define GIC_MAP_TO_PIN_MSK (MSK(1) << GIC_MAP_TO_PIN_SHF)
246#define GIC_MAP_TO_NMI_SHF 30
247#define GIC_MAP_TO_NMI_MSK (MSK(1) << GIC_MAP_TO_NMI_SHF)
248#define GIC_MAP_TO_YQ_SHF 29
249#define GIC_MAP_TO_YQ_MSK (MSK(1) << GIC_MAP_TO_YQ_SHF)
250#define GIC_MAP_SHF 0
251#define GIC_MAP_MSK (MSK(6) << GIC_MAP_SHF)
252
253/* GIC_VPE_CTL Masks */
254#define GIC_VPE_CTL_PERFCNT_RTBL_SHF 2
255#define GIC_VPE_CTL_PERFCNT_RTBL_MSK (MSK(1) << GIC_VPE_CTL_PERFCNT_RTBL_SHF)
256#define GIC_VPE_CTL_TIMER_RTBL_SHF 1
257#define GIC_VPE_CTL_TIMER_RTBL_MSK (MSK(1) << GIC_VPE_CTL_TIMER_RTBL_SHF)
258#define GIC_VPE_CTL_EIC_MODE_SHF 0
259#define GIC_VPE_CTL_EIC_MODE_MSK (MSK(1) << GIC_VPE_CTL_EIC_MODE_SHF)
260
261/* GIC_VPE_PEND Masks */
262#define GIC_VPE_PEND_WD_SHF 0
263#define GIC_VPE_PEND_WD_MSK (MSK(1) << GIC_VPE_PEND_WD_SHF)
264#define GIC_VPE_PEND_CMP_SHF 1
265#define GIC_VPE_PEND_CMP_MSK (MSK(1) << GIC_VPE_PEND_CMP_SHF)
266#define GIC_VPE_PEND_TIMER_SHF 2
267#define GIC_VPE_PEND_TIMER_MSK (MSK(1) << GIC_VPE_PEND_TIMER_SHF)
268#define GIC_VPE_PEND_PERFCOUNT_SHF 3
269#define GIC_VPE_PEND_PERFCOUNT_MSK (MSK(1) << GIC_VPE_PEND_PERFCOUNT_SHF)
270#define GIC_VPE_PEND_SWINT0_SHF 4
271#define GIC_VPE_PEND_SWINT0_MSK (MSK(1) << GIC_VPE_PEND_SWINT0_SHF)
272#define GIC_VPE_PEND_SWINT1_SHF 5
273#define GIC_VPE_PEND_SWINT1_MSK (MSK(1) << GIC_VPE_PEND_SWINT1_SHF)
274
275/* GIC_VPE_RMASK Masks */
276#define GIC_VPE_RMASK_WD_SHF 0
277#define GIC_VPE_RMASK_WD_MSK (MSK(1) << GIC_VPE_RMASK_WD_SHF)
278#define GIC_VPE_RMASK_CMP_SHF 1
279#define GIC_VPE_RMASK_CMP_MSK (MSK(1) << GIC_VPE_RMASK_CMP_SHF)
280#define GIC_VPE_RMASK_TIMER_SHF 2
281#define GIC_VPE_RMASK_TIMER_MSK (MSK(1) << GIC_VPE_RMASK_TIMER_SHF)
282#define GIC_VPE_RMASK_PERFCNT_SHF 3
283#define GIC_VPE_RMASK_PERFCNT_MSK (MSK(1) << GIC_VPE_RMASK_PERFCNT_SHF)
284#define GIC_VPE_RMASK_SWINT0_SHF 4
285#define GIC_VPE_RMASK_SWINT0_MSK (MSK(1) << GIC_VPE_RMASK_SWINT0_SHF)
286#define GIC_VPE_RMASK_SWINT1_SHF 5
287#define GIC_VPE_RMASK_SWINT1_MSK (MSK(1) << GIC_VPE_RMASK_SWINT1_SHF)
288
289/* GIC_VPE_SMASK Masks */
290#define GIC_VPE_SMASK_WD_SHF 0
291#define GIC_VPE_SMASK_WD_MSK (MSK(1) << GIC_VPE_SMASK_WD_SHF)
292#define GIC_VPE_SMASK_CMP_SHF 1
293#define GIC_VPE_SMASK_CMP_MSK (MSK(1) << GIC_VPE_SMASK_CMP_SHF)
294#define GIC_VPE_SMASK_TIMER_SHF 2
295#define GIC_VPE_SMASK_TIMER_MSK (MSK(1) << GIC_VPE_SMASK_TIMER_SHF)
296#define GIC_VPE_SMASK_PERFCNT_SHF 3
297#define GIC_VPE_SMASK_PERFCNT_MSK (MSK(1) << GIC_VPE_SMASK_PERFCNT_SHF)
298#define GIC_VPE_SMASK_SWINT0_SHF 4
299#define GIC_VPE_SMASK_SWINT0_MSK (MSK(1) << GIC_VPE_SMASK_SWINT0_SHF)
300#define GIC_VPE_SMASK_SWINT1_SHF 5
301#define GIC_VPE_SMASK_SWINT1_MSK (MSK(1) << GIC_VPE_SMASK_SWINT1_SHF)
302
303/*
304 * Set the Mapping of Interrupt X to a VPE.
305 */
306#define GIC_SH_MAP_TO_VPE_SMASK(intr, vpe) \
307 GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_MAP_TO_VPE_REG_OFF(intr, vpe)), \
308 GIC_SH_MAP_TO_VPE_REG_BIT(vpe))
309
310/*
311 * Interrupt Meta-data specification. The ipiflag helps
312 * in building ipi_map.
313 */
314struct gic_intr_map {
315 unsigned int cpunum; /* Directed to this CPU */
316#define GIC_UNUSED 0xdead /* Dummy data */
317 unsigned int pin; /* Directed to this Pin */
318 unsigned int polarity; /* Polarity : +/- */
319 unsigned int trigtype; /* Trigger : Edge/Levl */
320 unsigned int flags; /* Misc flags */
321#define GIC_FLAG_TRANSPARENT 0x01
322};
323
324/*
325 * This is only used in EIC mode. This helps to figure out which
326 * shared interrupts we need to process when we get a vector interrupt.
327 */
328#define GIC_MAX_SHARED_INTR 0x5
329struct gic_shared_intr_map {
330 unsigned int num_shared_intr;
331 unsigned int intr_list[GIC_MAX_SHARED_INTR];
332 unsigned int local_intr_mask;
333};
334
335/* GIC nomenclature for Core Interrupt Pins. */
336#define GIC_CPU_INT0 0 /* Core Interrupt 2 */
337#define GIC_CPU_INT1 1 /* . */
338#define GIC_CPU_INT2 2 /* . */
339#define GIC_CPU_INT3 3 /* . */
340#define GIC_CPU_INT4 4 /* . */
341#define GIC_CPU_INT5 5 /* Core Interrupt 7 */
342
343/* Local GIC interrupts. */
344#define GIC_INT_TMR (GIC_CPU_INT5)
345#define GIC_INT_PERFCTR (GIC_CPU_INT5)
346
347/* Add 2 to convert non-EIC hardware interrupt to EIC vector number. */
348#define GIC_CPU_TO_VEC_OFFSET (2)
349
350/* Mapped interrupt to pin X, then GIC will generate the vector (X+1). */
351#define GIC_PIN_TO_VEC_OFFSET (1)
352
353#include <linux/clocksource.h>
354#include <linux/irq.h>
355
356extern unsigned int gic_present;
357extern unsigned int gic_frequency;
358extern unsigned long _gic_base;
359extern unsigned int gic_irq_base;
360extern unsigned int gic_irq_flags[];
361extern struct gic_shared_intr_map gic_shared_intr_map[];
362
363extern void gic_init(unsigned long gic_base_addr,
364 unsigned long gic_addrspace_size, struct gic_intr_map *intrmap,
365 unsigned int intrmap_size, unsigned int irqbase);
366extern void gic_clocksource_init(unsigned int);
367extern unsigned int gic_compare_int (void);
368extern cycle_t gic_read_count(void);
369extern cycle_t gic_read_compare(void);
370extern void gic_write_compare(cycle_t cnt);
371extern void gic_write_cpu_compare(cycle_t cnt, int cpu);
372extern void gic_send_ipi(unsigned int intr);
373extern unsigned int plat_ipi_call_int_xlate(unsigned int);
374extern unsigned int plat_ipi_resched_int_xlate(unsigned int);
375extern void gic_bind_eic_interrupt(int irq, int set);
376extern unsigned int gic_get_timer_pending(void);
377extern void gic_get_int_mask(unsigned long *dst, const unsigned long *src);
378extern unsigned int gic_get_int(void);
379extern void gic_enable_interrupt(int irq_vec);
380extern void gic_disable_interrupt(int irq_vec);
381extern void gic_irq_ack(struct irq_data *d);
382extern void gic_finish_irq(struct irq_data *d);
383extern void gic_platform_init(int irqs, struct irq_chip *irq_controller);
384#endif /* _ASM_GICREGS_H */
diff --git a/arch/mips/include/asm/hpet.h b/arch/mips/include/asm/hpet.h
new file mode 100644
index 000000000000..18a8f778bfaa
--- /dev/null
+++ b/arch/mips/include/asm/hpet.h
@@ -0,0 +1,73 @@
1#ifndef _ASM_HPET_H
2#define _ASM_HPET_H
3
4#ifdef CONFIG_RS780_HPET
5
6#define HPET_MMAP_SIZE 1024
7
8#define HPET_ID 0x000
9#define HPET_PERIOD 0x004
10#define HPET_CFG 0x010
11#define HPET_STATUS 0x020
12#define HPET_COUNTER 0x0f0
13
14#define HPET_Tn_CFG(n) (0x100 + 0x20 * n)
15#define HPET_Tn_CMP(n) (0x108 + 0x20 * n)
16#define HPET_Tn_ROUTE(n) (0x110 + 0x20 * n)
17
18#define HPET_T0_IRS 0x001
19#define HPET_T1_IRS 0x002
20#define HPET_T3_IRS 0x004
21
22#define HPET_T0_CFG 0x100
23#define HPET_T0_CMP 0x108
24#define HPET_T0_ROUTE 0x110
25#define HPET_T1_CFG 0x120
26#define HPET_T1_CMP 0x128
27#define HPET_T1_ROUTE 0x130
28#define HPET_T2_CFG 0x140
29#define HPET_T2_CMP 0x148
30#define HPET_T2_ROUTE 0x150
31
32#define HPET_ID_REV 0x000000ff
33#define HPET_ID_NUMBER 0x00001f00
34#define HPET_ID_64BIT 0x00002000
35#define HPET_ID_LEGSUP 0x00008000
36#define HPET_ID_VENDOR 0xffff0000
37#define HPET_ID_NUMBER_SHIFT 8
38#define HPET_ID_VENDOR_SHIFT 16
39
40#define HPET_CFG_ENABLE 0x001
41#define HPET_CFG_LEGACY 0x002
42#define HPET_LEGACY_8254 2
43#define HPET_LEGACY_RTC 8
44
45#define HPET_TN_LEVEL 0x0002
46#define HPET_TN_ENABLE 0x0004
47#define HPET_TN_PERIODIC 0x0008
48#define HPET_TN_PERIODIC_CAP 0x0010
49#define HPET_TN_64BIT_CAP 0x0020
50#define HPET_TN_SETVAL 0x0040
51#define HPET_TN_32BIT 0x0100
52#define HPET_TN_ROUTE 0x3e00
53#define HPET_TN_FSB 0x4000
54#define HPET_TN_FSB_CAP 0x8000
55#define HPET_TN_ROUTE_SHIFT 9
56
57/* Max HPET Period is 10^8 femto sec as in HPET spec */
58#define HPET_MAX_PERIOD 100000000UL
59/*
60 * Min HPET period is 10^5 femto sec just for safety. If it is less than this,
61 * then 32 bit HPET counter wrapsaround in less than 0.5 sec.
62 */
63#define HPET_MIN_PERIOD 100000UL
64
65#define HPET_ADDR 0x20000
66#define HPET_MMIO_ADDR 0x90000e0000020000
67#define HPET_FREQ 14318780
68#define HPET_COMPARE_VAL ((HPET_FREQ + HZ / 2) / HZ)
69#define HPET_T0_IRQ 0
70
71extern void __init setup_hpet_timer(void);
72#endif /* CONFIG_RS780_HPET */
73#endif /* _ASM_HPET_H */
diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
index 933b50e125a0..9e777cd42b67 100644
--- a/arch/mips/include/asm/io.h
+++ b/arch/mips/include/asm/io.h
@@ -167,7 +167,7 @@ static inline void * isa_bus_to_virt(unsigned long address)
167 */ 167 */
168#define page_to_phys(page) ((dma_addr_t)page_to_pfn(page) << PAGE_SHIFT) 168#define page_to_phys(page) ((dma_addr_t)page_to_pfn(page) << PAGE_SHIFT)
169 169
170extern void __iomem * __ioremap(phys_t offset, phys_t size, unsigned long flags); 170extern void __iomem * __ioremap(phys_addr_t offset, phys_addr_t size, unsigned long flags);
171extern void __iounmap(const volatile void __iomem *addr); 171extern void __iounmap(const volatile void __iomem *addr);
172 172
173#ifndef CONFIG_PCI 173#ifndef CONFIG_PCI
@@ -175,7 +175,7 @@ struct pci_dev;
175static inline void pci_iounmap(struct pci_dev *dev, void __iomem *addr) {} 175static inline void pci_iounmap(struct pci_dev *dev, void __iomem *addr) {}
176#endif 176#endif
177 177
178static inline void __iomem * __ioremap_mode(phys_t offset, unsigned long size, 178static inline void __iomem * __ioremap_mode(phys_addr_t offset, unsigned long size,
179 unsigned long flags) 179 unsigned long flags)
180{ 180{
181 void __iomem *addr = plat_ioremap(offset, size, flags); 181 void __iomem *addr = plat_ioremap(offset, size, flags);
@@ -183,7 +183,7 @@ static inline void __iomem * __ioremap_mode(phys_t offset, unsigned long size,
183 if (addr) 183 if (addr)
184 return addr; 184 return addr;
185 185
186#define __IS_LOW512(addr) (!((phys_t)(addr) & (phys_t) ~0x1fffffffULL)) 186#define __IS_LOW512(addr) (!((phys_addr_t)(addr) & (phys_addr_t) ~0x1fffffffULL))
187 187
188 if (cpu_has_64bit_addresses) { 188 if (cpu_has_64bit_addresses) {
189 u64 base = UNCAC_BASE; 189 u64 base = UNCAC_BASE;
@@ -197,7 +197,7 @@ static inline void __iomem * __ioremap_mode(phys_t offset, unsigned long size,
197 return (void __iomem *) (unsigned long) (base + offset); 197 return (void __iomem *) (unsigned long) (base + offset);
198 } else if (__builtin_constant_p(offset) && 198 } else if (__builtin_constant_p(offset) &&
199 __builtin_constant_p(size) && __builtin_constant_p(flags)) { 199 __builtin_constant_p(size) && __builtin_constant_p(flags)) {
200 phys_t phys_addr, last_addr; 200 phys_addr_t phys_addr, last_addr;
201 201
202 phys_addr = fixup_bigphys_addr(offset, size); 202 phys_addr = fixup_bigphys_addr(offset, size);
203 203
diff --git a/arch/mips/include/asm/irq.h b/arch/mips/include/asm/irq.h
index 39f07aec640c..5a4e1bb8fb1b 100644
--- a/arch/mips/include/asm/irq.h
+++ b/arch/mips/include/asm/irq.h
@@ -48,4 +48,7 @@ extern int cp0_compare_irq;
48extern int cp0_compare_irq_shift; 48extern int cp0_compare_irq_shift;
49extern int cp0_perfcount_irq; 49extern int cp0_perfcount_irq;
50 50
51void arch_trigger_all_cpu_backtrace(bool);
52#define arch_trigger_all_cpu_backtrace arch_trigger_all_cpu_backtrace
53
51#endif /* _ASM_IRQ_H */ 54#endif /* _ASM_IRQ_H */
diff --git a/arch/mips/include/asm/irq_cpu.h b/arch/mips/include/asm/irq_cpu.h
index 3f11fdb3ed8c..39a160bb41dc 100644
--- a/arch/mips/include/asm/irq_cpu.h
+++ b/arch/mips/include/asm/irq_cpu.h
@@ -19,8 +19,8 @@ extern void rm9k_cpu_irq_init(void);
19 19
20#ifdef CONFIG_IRQ_DOMAIN 20#ifdef CONFIG_IRQ_DOMAIN
21struct device_node; 21struct device_node;
22extern int mips_cpu_intc_init(struct device_node *of_node, 22extern int mips_cpu_irq_of_init(struct device_node *of_node,
23 struct device_node *parent); 23 struct device_node *parent);
24#endif 24#endif
25 25
26#endif /* _ASM_IRQ_CPU_H */ 26#endif /* _ASM_IRQ_CPU_H */
diff --git a/arch/mips/include/asm/mach-ath25/ath25_platform.h b/arch/mips/include/asm/mach-ath25/ath25_platform.h
new file mode 100644
index 000000000000..4f4ee4f9e5ec
--- /dev/null
+++ b/arch/mips/include/asm/mach-ath25/ath25_platform.h
@@ -0,0 +1,73 @@
1#ifndef __ASM_MACH_ATH25_PLATFORM_H
2#define __ASM_MACH_ATH25_PLATFORM_H
3
4#include <linux/etherdevice.h>
5
6/*
7 * This is board-specific data that is stored in a "fixed" location in flash.
8 * It is shared across operating systems, so it should not be changed lightly.
9 * The main reason we need it is in order to extract the ethernet MAC
10 * address(es).
11 */
12struct ath25_boarddata {
13 u32 magic; /* board data is valid */
14#define ATH25_BD_MAGIC 0x35333131 /* "5311", for all 531x/231x platforms */
15 u16 cksum; /* checksum (starting with BD_REV 2) */
16 u16 rev; /* revision of this struct */
17#define BD_REV 4
18 char board_name[64]; /* Name of board */
19 u16 major; /* Board major number */
20 u16 minor; /* Board minor number */
21 u32 flags; /* Board configuration */
22#define BD_ENET0 0x00000001 /* ENET0 is stuffed */
23#define BD_ENET1 0x00000002 /* ENET1 is stuffed */
24#define BD_UART1 0x00000004 /* UART1 is stuffed */
25#define BD_UART0 0x00000008 /* UART0 is stuffed (dma) */
26#define BD_RSTFACTORY 0x00000010 /* Reset factory defaults stuffed */
27#define BD_SYSLED 0x00000020 /* System LED stuffed */
28#define BD_EXTUARTCLK 0x00000040 /* External UART clock */
29#define BD_CPUFREQ 0x00000080 /* cpu freq is valid in nvram */
30#define BD_SYSFREQ 0x00000100 /* sys freq is set in nvram */
31#define BD_WLAN0 0x00000200 /* Enable WLAN0 */
32#define BD_MEMCAP 0x00000400 /* CAP SDRAM @ mem_cap for testing */
33#define BD_DISWATCHDOG 0x00000800 /* disable system watchdog */
34#define BD_WLAN1 0x00001000 /* Enable WLAN1 (ar5212) */
35#define BD_ISCASPER 0x00002000 /* FLAG for AR2312 */
36#define BD_WLAN0_2G_EN 0x00004000 /* FLAG for radio0_2G */
37#define BD_WLAN0_5G_EN 0x00008000 /* FLAG for radio0_2G */
38#define BD_WLAN1_2G_EN 0x00020000 /* FLAG for radio0_2G */
39#define BD_WLAN1_5G_EN 0x00040000 /* FLAG for radio0_2G */
40 u16 reset_config_gpio; /* Reset factory GPIO pin */
41 u16 sys_led_gpio; /* System LED GPIO pin */
42
43 u32 cpu_freq; /* CPU core frequency in Hz */
44 u32 sys_freq; /* System frequency in Hz */
45 u32 cnt_freq; /* Calculated C0_COUNT frequency */
46
47 u8 wlan0_mac[ETH_ALEN];
48 u8 enet0_mac[ETH_ALEN];
49 u8 enet1_mac[ETH_ALEN];
50
51 u16 pci_id; /* Pseudo PCIID for common code */
52 u16 mem_cap; /* cap bank1 in MB */
53
54 /* version 3 */
55 u8 wlan1_mac[ETH_ALEN]; /* (ar5212) */
56};
57
58#define BOARD_CONFIG_BUFSZ 0x1000
59
60/*
61 * Platform device information for the Wireless MAC
62 */
63struct ar231x_board_config {
64 u16 devid;
65
66 /* board config data */
67 struct ath25_boarddata *config;
68
69 /* radio calibration data */
70 const char *radio;
71};
72
73#endif /* __ASM_MACH_ATH25_PLATFORM_H */
diff --git a/arch/mips/include/asm/mach-ath25/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ath25/cpu-feature-overrides.h
new file mode 100644
index 000000000000..ade0356df257
--- /dev/null
+++ b/arch/mips/include/asm/mach-ath25/cpu-feature-overrides.h
@@ -0,0 +1,64 @@
1/*
2 * Atheros AR231x/AR531x SoC specific CPU feature overrides
3 *
4 * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
5 *
6 * This file was derived from: include/asm-mips/cpu-features.h
7 * Copyright (C) 2003, 2004 Ralf Baechle
8 * Copyright (C) 2004 Maciej W. Rozycki
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published
12 * by the Free Software Foundation.
13 *
14 */
15#ifndef __ASM_MACH_ATH25_CPU_FEATURE_OVERRIDES_H
16#define __ASM_MACH_ATH25_CPU_FEATURE_OVERRIDES_H
17
18/*
19 * The Atheros AR531x/AR231x SoCs have MIPS 4Kc/4KEc core.
20 */
21#define cpu_has_tlb 1
22#define cpu_has_4kex 1
23#define cpu_has_3k_cache 0
24#define cpu_has_4k_cache 1
25#define cpu_has_tx39_cache 0
26#define cpu_has_sb1_cache 0
27#define cpu_has_fpu 0
28#define cpu_has_32fpr 0
29#define cpu_has_counter 1
30#define cpu_has_ejtag 1
31
32#if !defined(CONFIG_SOC_AR5312)
33# define cpu_has_llsc 1
34#else
35/*
36 * The MIPS 4Kc V0.9 core in the AR5312/AR2312 have problems with the
37 * ll/sc instructions.
38 */
39# define cpu_has_llsc 0
40#endif
41
42#define cpu_has_mips16 0
43#define cpu_has_mdmx 0
44#define cpu_has_mips3d 0
45#define cpu_has_smartmips 0
46
47#define cpu_has_mips32r1 1
48
49#if !defined(CONFIG_SOC_AR5312)
50# define cpu_has_mips32r2 1
51#endif
52
53#define cpu_has_mips64r1 0
54#define cpu_has_mips64r2 0
55
56#define cpu_has_dsp 0
57#define cpu_has_mipsmt 0
58
59#define cpu_has_64bits 0
60#define cpu_has_64bit_zero_reg 0
61#define cpu_has_64bit_gp_regs 0
62#define cpu_has_64bit_addresses 0
63
64#endif /* __ASM_MACH_ATH25_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mach-ath25/dma-coherence.h b/arch/mips/include/asm/mach-ath25/dma-coherence.h
new file mode 100644
index 000000000000..d8009c93a465
--- /dev/null
+++ b/arch/mips/include/asm/mach-ath25/dma-coherence.h
@@ -0,0 +1,82 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2006 Ralf Baechle <ralf@linux-mips.org>
7 * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
8 *
9 */
10#ifndef __ASM_MACH_ATH25_DMA_COHERENCE_H
11#define __ASM_MACH_ATH25_DMA_COHERENCE_H
12
13#include <linux/device.h>
14
15/*
16 * We need some arbitrary non-zero value to be programmed to the BAR1 register
17 * of PCI host controller to enable DMA. The same value should be used as the
18 * offset to calculate the physical address of DMA buffer for PCI devices.
19 */
20#define AR2315_PCI_HOST_SDRAM_BASEADDR 0x20000000
21
22static inline dma_addr_t ath25_dev_offset(struct device *dev)
23{
24#ifdef CONFIG_PCI
25 extern struct bus_type pci_bus_type;
26
27 if (dev && dev->bus == &pci_bus_type)
28 return AR2315_PCI_HOST_SDRAM_BASEADDR;
29#endif
30 return 0;
31}
32
33static inline dma_addr_t
34plat_map_dma_mem(struct device *dev, void *addr, size_t size)
35{
36 return virt_to_phys(addr) + ath25_dev_offset(dev);
37}
38
39static inline dma_addr_t
40plat_map_dma_mem_page(struct device *dev, struct page *page)
41{
42 return page_to_phys(page) + ath25_dev_offset(dev);
43}
44
45static inline unsigned long
46plat_dma_addr_to_phys(struct device *dev, dma_addr_t dma_addr)
47{
48 return dma_addr - ath25_dev_offset(dev);
49}
50
51static inline void
52plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr, size_t size,
53 enum dma_data_direction direction)
54{
55}
56
57static inline int plat_dma_supported(struct device *dev, u64 mask)
58{
59 return 1;
60}
61
62static inline void plat_extra_sync_for_device(struct device *dev)
63{
64}
65
66static inline int plat_dma_mapping_error(struct device *dev,
67 dma_addr_t dma_addr)
68{
69 return 0;
70}
71
72static inline int plat_device_is_coherent(struct device *dev)
73{
74#ifdef CONFIG_DMA_COHERENT
75 return 1;
76#endif
77#ifdef CONFIG_DMA_NONCOHERENT
78 return 0;
79#endif
80}
81
82#endif /* __ASM_MACH_ATH25_DMA_COHERENCE_H */
diff --git a/arch/mips/include/asm/mach-ath25/gpio.h b/arch/mips/include/asm/mach-ath25/gpio.h
new file mode 100644
index 000000000000..713564b8e8ef
--- /dev/null
+++ b/arch/mips/include/asm/mach-ath25/gpio.h
@@ -0,0 +1,16 @@
1#ifndef __ASM_MACH_ATH25_GPIO_H
2#define __ASM_MACH_ATH25_GPIO_H
3
4#include <asm-generic/gpio.h>
5
6#define gpio_get_value __gpio_get_value
7#define gpio_set_value __gpio_set_value
8#define gpio_cansleep __gpio_cansleep
9#define gpio_to_irq __gpio_to_irq
10
11static inline int irq_to_gpio(unsigned irq)
12{
13 return -EINVAL;
14}
15
16#endif /* __ASM_MACH_ATH25_GPIO_H */
diff --git a/arch/mips/include/asm/mach-ath25/war.h b/arch/mips/include/asm/mach-ath25/war.h
new file mode 100644
index 000000000000..e3a5250ebd67
--- /dev/null
+++ b/arch/mips/include/asm/mach-ath25/war.h
@@ -0,0 +1,25 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2008 Felix Fietkau <nbd@openwrt.org>
7 */
8#ifndef __ASM_MACH_ATH25_WAR_H
9#define __ASM_MACH_ATH25_WAR_H
10
11#define R4600_V1_INDEX_ICACHEOP_WAR 0
12#define R4600_V1_HIT_CACHEOP_WAR 0
13#define R4600_V2_HIT_CACHEOP_WAR 0
14#define R5432_CP0_INTERRUPT_WAR 0
15#define BCM1250_M3_WAR 0
16#define SIBYTE_1956_WAR 0
17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define RM9000_CDEX_SMP_WAR 0
21#define ICACHE_REFILLS_WORKAROUND_WAR 0
22#define R10000_LLSC_WAR 0
23#define MIPS34K_MISSED_ITLB_WAR 0
24
25#endif /* __ASM_MACH_ATH25_WAR_H */
diff --git a/arch/mips/include/asm/mach-au1x00/ioremap.h b/arch/mips/include/asm/mach-au1x00/ioremap.h
index 75a94ad3ac91..99fea1fbb4f5 100644
--- a/arch/mips/include/asm/mach-au1x00/ioremap.h
+++ b/arch/mips/include/asm/mach-au1x00/ioremap.h
@@ -11,10 +11,10 @@
11 11
12#include <linux/types.h> 12#include <linux/types.h>
13 13
14#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_PCI) 14#if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_PCI)
15extern phys_t __fixup_bigphys_addr(phys_t, phys_t); 15extern phys_addr_t __fixup_bigphys_addr(phys_addr_t, phys_addr_t);
16#else 16#else
17static inline phys_t __fixup_bigphys_addr(phys_t phys_addr, phys_t size) 17static inline phys_addr_t __fixup_bigphys_addr(phys_addr_t phys_addr, phys_addr_t size)
18{ 18{
19 return phys_addr; 19 return phys_addr;
20} 20}
@@ -23,12 +23,12 @@ static inline phys_t __fixup_bigphys_addr(phys_t phys_addr, phys_t size)
23/* 23/*
24 * Allow physical addresses to be fixed up to help 36-bit peripherals. 24 * Allow physical addresses to be fixed up to help 36-bit peripherals.
25 */ 25 */
26static inline phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size) 26static inline phys_addr_t fixup_bigphys_addr(phys_addr_t phys_addr, phys_addr_t size)
27{ 27{
28 return __fixup_bigphys_addr(phys_addr, size); 28 return __fixup_bigphys_addr(phys_addr, size);
29} 29}
30 30
31static inline void __iomem *plat_ioremap(phys_t offset, unsigned long size, 31static inline void __iomem *plat_ioremap(phys_addr_t offset, unsigned long size,
32 unsigned long flags) 32 unsigned long flags)
33{ 33{
34 return NULL; 34 return NULL;
diff --git a/arch/mips/include/asm/mach-bcm3384/dma-coherence.h b/arch/mips/include/asm/mach-bcm3384/dma-coherence.h
new file mode 100644
index 000000000000..a3be8e50e1f0
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm3384/dma-coherence.h
@@ -0,0 +1,48 @@
1/*
2 * Copyright (C) 2006 Ralf Baechle <ralf@linux-mips.org>
3 * Copyright (C) 2009 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#ifndef __ASM_MACH_BCM3384_DMA_COHERENCE_H
16#define __ASM_MACH_BCM3384_DMA_COHERENCE_H
17
18struct device;
19
20extern dma_addr_t plat_map_dma_mem(struct device *dev, void *addr, size_t size);
21extern dma_addr_t plat_map_dma_mem_page(struct device *dev, struct page *page);
22extern unsigned long plat_dma_addr_to_phys(struct device *dev,
23 dma_addr_t dma_addr);
24
25static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr,
26 size_t size, enum dma_data_direction direction)
27{
28}
29
30static inline int plat_dma_supported(struct device *dev, u64 mask)
31{
32 /*
33 * we fall back to GFP_DMA when the mask isn't all 1s,
34 * so we can't guarantee allocations that must be
35 * within a tighter range than GFP_DMA..
36 */
37 if (mask < DMA_BIT_MASK(24))
38 return 0;
39
40 return 1;
41}
42
43static inline int plat_device_is_coherent(struct device *dev)
44{
45 return 0;
46}
47
48#endif /* __ASM_MACH_BCM3384_DMA_COHERENCE_H */
diff --git a/arch/mips/include/asm/mach-bcm3384/war.h b/arch/mips/include/asm/mach-bcm3384/war.h
new file mode 100644
index 000000000000..59d7599059b0
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm3384/war.h
@@ -0,0 +1,24 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7 */
8#ifndef __ASM_MIPS_MACH_BCM3384_WAR_H
9#define __ASM_MIPS_MACH_BCM3384_WAR_H
10
11#define R4600_V1_INDEX_ICACHEOP_WAR 0
12#define R4600_V1_HIT_CACHEOP_WAR 0
13#define R4600_V2_HIT_CACHEOP_WAR 0
14#define R5432_CP0_INTERRUPT_WAR 0
15#define BCM1250_M3_WAR 0
16#define SIBYTE_1956_WAR 0
17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define ICACHE_REFILLS_WORKAROUND_WAR 0
21#define R10000_LLSC_WAR 0
22#define MIPS34K_MISSED_ITLB_WAR 0
23
24#endif /* __ASM_MIPS_MACH_BCM3384_WAR_H */
diff --git a/arch/mips/include/asm/mach-bcm47xx/bcm47xx_nvram.h b/arch/mips/include/asm/mach-bcm47xx/bcm47xx_nvram.h
index 36a3fc1aa3ae..ee59ffe99922 100644
--- a/arch/mips/include/asm/mach-bcm47xx/bcm47xx_nvram.h
+++ b/arch/mips/include/asm/mach-bcm47xx/bcm47xx_nvram.h
@@ -14,40 +14,8 @@
14#include <linux/types.h> 14#include <linux/types.h>
15#include <linux/kernel.h> 15#include <linux/kernel.h>
16 16
17struct nvram_header { 17int bcm47xx_nvram_init_from_mem(u32 base, u32 lim);
18 u32 magic; 18int bcm47xx_nvram_getenv(const char *name, char *val, size_t val_len);
19 u32 len;
20 u32 crc_ver_init; /* 0:7 crc, 8:15 ver, 16:31 sdram_init */
21 u32 config_refresh; /* 0:15 sdram_config, 16:31 sdram_refresh */
22 u32 config_ncdl; /* ncdl values for memc */
23};
24
25#define NVRAM_HEADER 0x48534C46 /* 'FLSH' */
26#define NVRAM_VERSION 1
27#define NVRAM_HEADER_SIZE 20
28#define NVRAM_SPACE 0x8000
29
30#define FLASH_MIN 0x00020000 /* Minimum flash size */
31
32#define NVRAM_MAX_VALUE_LEN 255
33#define NVRAM_MAX_PARAM_LEN 64
34
35extern int bcm47xx_nvram_getenv(char *name, char *val, size_t val_len);
36
37static inline void bcm47xx_nvram_parse_macaddr(char *buf, u8 macaddr[6])
38{
39 if (strchr(buf, ':'))
40 sscanf(buf, "%hhx:%hhx:%hhx:%hhx:%hhx:%hhx", &macaddr[0],
41 &macaddr[1], &macaddr[2], &macaddr[3], &macaddr[4],
42 &macaddr[5]);
43 else if (strchr(buf, '-'))
44 sscanf(buf, "%hhx-%hhx-%hhx-%hhx-%hhx-%hhx", &macaddr[0],
45 &macaddr[1], &macaddr[2], &macaddr[3], &macaddr[4],
46 &macaddr[5]);
47 else
48 printk(KERN_WARNING "Can not parse mac address: %s\n", buf);
49}
50
51int bcm47xx_nvram_gpio_pin(const char *name); 19int bcm47xx_nvram_gpio_pin(const char *name);
52 20
53#endif /* __BCM47XX_NVRAM_H */ 21#endif /* __BCM47XX_NVRAM_H */
diff --git a/arch/mips/include/asm/mach-bcm63xx/ioremap.h b/arch/mips/include/asm/mach-bcm63xx/ioremap.h
index ff15e3b14e7a..aea6e64b828f 100644
--- a/arch/mips/include/asm/mach-bcm63xx/ioremap.h
+++ b/arch/mips/include/asm/mach-bcm63xx/ioremap.h
@@ -3,12 +3,12 @@
3 3
4#include <bcm63xx_cpu.h> 4#include <bcm63xx_cpu.h>
5 5
6static inline phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size) 6static inline phys_addr_t fixup_bigphys_addr(phys_addr_t phys_addr, phys_addr_t size)
7{ 7{
8 return phys_addr; 8 return phys_addr;
9} 9}
10 10
11static inline int is_bcm63xx_internal_registers(phys_t offset) 11static inline int is_bcm63xx_internal_registers(phys_addr_t offset)
12{ 12{
13 switch (bcm63xx_get_cpu_id()) { 13 switch (bcm63xx_get_cpu_id()) {
14 case BCM3368_CPU_ID: 14 case BCM3368_CPU_ID:
@@ -32,7 +32,7 @@ static inline int is_bcm63xx_internal_registers(phys_t offset)
32 return 0; 32 return 0;
33} 33}
34 34
35static inline void __iomem *plat_ioremap(phys_t offset, unsigned long size, 35static inline void __iomem *plat_ioremap(phys_addr_t offset, unsigned long size,
36 unsigned long flags) 36 unsigned long flags)
37{ 37{
38 if (is_bcm63xx_internal_registers(offset)) 38 if (is_bcm63xx_internal_registers(offset))
diff --git a/arch/mips/include/asm/mach-generic/ioremap.h b/arch/mips/include/asm/mach-generic/ioremap.h
index b379938d47f0..513371f7c39c 100644
--- a/arch/mips/include/asm/mach-generic/ioremap.h
+++ b/arch/mips/include/asm/mach-generic/ioremap.h
@@ -15,12 +15,12 @@
15 * Allow physical addresses to be fixed up to help peripherals located 15 * Allow physical addresses to be fixed up to help peripherals located
16 * outside the low 32-bit range -- generic pass-through version. 16 * outside the low 32-bit range -- generic pass-through version.
17 */ 17 */
18static inline phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size) 18static inline phys_addr_t fixup_bigphys_addr(phys_addr_t phys_addr, phys_addr_t size)
19{ 19{
20 return phys_addr; 20 return phys_addr;
21} 21}
22 22
23static inline void __iomem *plat_ioremap(phys_t offset, unsigned long size, 23static inline void __iomem *plat_ioremap(phys_addr_t offset, unsigned long size,
24 unsigned long flags) 24 unsigned long flags)
25{ 25{
26 return NULL; 26 return NULL;
diff --git a/arch/mips/include/asm/mach-generic/irq.h b/arch/mips/include/asm/mach-generic/irq.h
index 139cd200e79d..050e18bb1a04 100644
--- a/arch/mips/include/asm/mach-generic/irq.h
+++ b/arch/mips/include/asm/mach-generic/irq.h
@@ -36,4 +36,10 @@
36 36
37#endif /* CONFIG_IRQ_CPU */ 37#endif /* CONFIG_IRQ_CPU */
38 38
39#ifdef CONFIG_MIPS_GIC
40#ifndef MIPS_GIC_IRQ_BASE
41#define MIPS_GIC_IRQ_BASE (MIPS_CPU_IRQ_BASE + 8)
42#endif
43#endif /* CONFIG_MIPS_GIC */
44
39#endif /* __ASM_MACH_GENERIC_IRQ_H */ 45#endif /* __ASM_MACH_GENERIC_IRQ_H */
diff --git a/arch/mips/include/asm/mach-lantiq/lantiq.h b/arch/mips/include/asm/mach-lantiq/lantiq.h
index f196cceb7322..4e5ae6523cb4 100644
--- a/arch/mips/include/asm/mach-lantiq/lantiq.h
+++ b/arch/mips/include/asm/mach-lantiq/lantiq.h
@@ -48,6 +48,8 @@ extern struct clk *clk_get_ppe(void);
48extern unsigned char ltq_boot_select(void); 48extern unsigned char ltq_boot_select(void);
49/* find out what caused the last cpu reset */ 49/* find out what caused the last cpu reset */
50extern int ltq_reset_cause(void); 50extern int ltq_reset_cause(void);
51/* find out the soc type */
52extern int ltq_soc_type(void);
51 53
52#define IOPORT_RESOURCE_START 0x10000000 54#define IOPORT_RESOURCE_START 0x10000000
53#define IOPORT_RESOURCE_END 0xffffffff 55#define IOPORT_RESOURCE_END 0xffffffff
diff --git a/arch/mips/include/asm/mach-loongson/boot_param.h b/arch/mips/include/asm/mach-loongson/boot_param.h
index 3388fc53599e..fa802926523f 100644
--- a/arch/mips/include/asm/mach-loongson/boot_param.h
+++ b/arch/mips/include/asm/mach-loongson/boot_param.h
@@ -10,7 +10,8 @@
10#define VIDEO_ROM 7 10#define VIDEO_ROM 7
11#define ADAPTER_ROM 8 11#define ADAPTER_ROM 8
12#define ACPI_TABLE 9 12#define ACPI_TABLE 9
13#define MAX_MEMORY_TYPE 10 13#define SMBIOS_TABLE 10
14#define MAX_MEMORY_TYPE 11
14 15
15#define LOONGSON3_BOOT_MEM_MAP_MAX 128 16#define LOONGSON3_BOOT_MEM_MAP_MAX 128
16struct efi_memory_map_loongson { 17struct efi_memory_map_loongson {
@@ -42,15 +43,49 @@ struct efi_cpuinfo_loongson {
42 u32 processor_id; /* PRID, e.g. 6305, 6306 */ 43 u32 processor_id; /* PRID, e.g. 6305, 6306 */
43 u32 cputype; /* Loongson_3A/3B, etc. */ 44 u32 cputype; /* Loongson_3A/3B, etc. */
44 u32 total_node; /* num of total numa nodes */ 45 u32 total_node; /* num of total numa nodes */
45 u32 cpu_startup_core_id; /* Core id */ 46 u16 cpu_startup_core_id; /* Boot core id */
47 u16 reserved_cores_mask;
46 u32 cpu_clock_freq; /* cpu_clock */ 48 u32 cpu_clock_freq; /* cpu_clock */
47 u32 nr_cpus; 49 u32 nr_cpus;
48} __packed; 50} __packed;
49 51
52#define MAX_UARTS 64
53struct uart_device {
54 u32 iotype; /* see include/linux/serial_core.h */
55 u32 uartclk;
56 u32 int_offset;
57 u64 uart_base;
58} __packed;
59
60#define MAX_SENSORS 64
61#define SENSOR_TEMPER 0x00000001
62#define SENSOR_VOLTAGE 0x00000002
63#define SENSOR_FAN 0x00000004
64struct sensor_device {
65 char name[32]; /* a formal name */
66 char label[64]; /* a flexible description */
67 u32 type; /* SENSOR_* */
68 u32 id; /* instance id of a sensor-class */
69 u32 fan_policy; /* see loongson_hwmon.h */
70 u32 fan_percent;/* only for constant speed policy */
71 u64 base_addr; /* base address of device registers */
72} __packed;
73
50struct system_loongson { 74struct system_loongson {
51 u16 vers; /* version of system_loongson */ 75 u16 vers; /* version of system_loongson */
52 u32 ccnuma_smp; /* 0: no numa; 1: has numa */ 76 u32 ccnuma_smp; /* 0: no numa; 1: has numa */
53 u32 sing_double_channel; /* 1:single; 2:double */ 77 u32 sing_double_channel; /* 1:single; 2:double */
78 u32 nr_uarts;
79 struct uart_device uarts[MAX_UARTS];
80 u32 nr_sensors;
81 struct sensor_device sensors[MAX_SENSORS];
82 char has_ec;
83 char ec_name[32];
84 u64 ec_base_addr;
85 char has_tcm;
86 char tcm_name[32];
87 u64 tcm_base_addr;
88 u64 workarounds; /* see workarounds.h */
54} __packed; 89} __packed;
55 90
56struct irq_source_routing_table { 91struct irq_source_routing_table {
@@ -149,6 +184,8 @@ struct loongson_system_configuration {
149 u32 nr_nodes; 184 u32 nr_nodes;
150 int cores_per_node; 185 int cores_per_node;
151 int cores_per_package; 186 int cores_per_package;
187 u16 boot_cpu_id;
188 u16 reserved_cpus_mask;
152 enum loongson_cpu_type cputype; 189 enum loongson_cpu_type cputype;
153 u64 ht_control_base; 190 u64 ht_control_base;
154 u64 pci_mem_start_addr; 191 u64 pci_mem_start_addr;
@@ -159,9 +196,15 @@ struct loongson_system_configuration {
159 u64 suspend_addr; 196 u64 suspend_addr;
160 u64 vgabios_addr; 197 u64 vgabios_addr;
161 u32 dma_mask_bits; 198 u32 dma_mask_bits;
199 char ecname[32];
200 u32 nr_uarts;
201 struct uart_device uarts[MAX_UARTS];
202 u32 nr_sensors;
203 struct sensor_device sensors[MAX_SENSORS];
204 u64 workarounds;
162}; 205};
163 206
164extern struct efi_memory_map_loongson *loongson_memmap; 207extern struct efi_memory_map_loongson *loongson_memmap;
165extern struct loongson_system_configuration loongson_sysconf; 208extern struct loongson_system_configuration loongson_sysconf;
166extern int cpuhotplug_workaround; 209
167#endif 210#endif
diff --git a/arch/mips/include/asm/mach-loongson/dma-coherence.h b/arch/mips/include/asm/mach-loongson/dma-coherence.h
index 6a902751cc7f..a90534161bd2 100644
--- a/arch/mips/include/asm/mach-loongson/dma-coherence.h
+++ b/arch/mips/include/asm/mach-loongson/dma-coherence.h
@@ -23,7 +23,7 @@ static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr,
23 size_t size) 23 size_t size)
24{ 24{
25#ifdef CONFIG_CPU_LOONGSON3 25#ifdef CONFIG_CPU_LOONGSON3
26 return virt_to_phys(addr); 26 return phys_to_dma(dev, virt_to_phys(addr));
27#else 27#else
28 return virt_to_phys(addr) | 0x80000000; 28 return virt_to_phys(addr) | 0x80000000;
29#endif 29#endif
@@ -33,7 +33,7 @@ static inline dma_addr_t plat_map_dma_mem_page(struct device *dev,
33 struct page *page) 33 struct page *page)
34{ 34{
35#ifdef CONFIG_CPU_LOONGSON3 35#ifdef CONFIG_CPU_LOONGSON3
36 return page_to_phys(page); 36 return phys_to_dma(dev, page_to_phys(page));
37#else 37#else
38 return page_to_phys(page) | 0x80000000; 38 return page_to_phys(page) | 0x80000000;
39#endif 39#endif
@@ -43,7 +43,7 @@ static inline unsigned long plat_dma_addr_to_phys(struct device *dev,
43 dma_addr_t dma_addr) 43 dma_addr_t dma_addr)
44{ 44{
45#if defined(CONFIG_CPU_LOONGSON3) && defined(CONFIG_64BIT) 45#if defined(CONFIG_CPU_LOONGSON3) && defined(CONFIG_64BIT)
46 return dma_addr; 46 return dma_to_phys(dev, dma_addr);
47#elif defined(CONFIG_CPU_LOONGSON2F) && defined(CONFIG_64BIT) 47#elif defined(CONFIG_CPU_LOONGSON2F) && defined(CONFIG_64BIT)
48 return (dma_addr > 0x8fffffff) ? dma_addr : (dma_addr & 0x0fffffff); 48 return (dma_addr > 0x8fffffff) ? dma_addr : (dma_addr & 0x0fffffff);
49#else 49#else
diff --git a/arch/mips/include/asm/mach-loongson/irq.h b/arch/mips/include/asm/mach-loongson/irq.h
index 34560bda6626..a281cca5f2fb 100644
--- a/arch/mips/include/asm/mach-loongson/irq.h
+++ b/arch/mips/include/asm/mach-loongson/irq.h
@@ -32,8 +32,7 @@
32#define LOONGSON_INT_ROUTER_LPC LOONGSON_INT_ROUTER_ENTRY(0x0a) 32#define LOONGSON_INT_ROUTER_LPC LOONGSON_INT_ROUTER_ENTRY(0x0a)
33#define LOONGSON_INT_ROUTER_HT1(n) LOONGSON_INT_ROUTER_ENTRY(n + 0x18) 33#define LOONGSON_INT_ROUTER_HT1(n) LOONGSON_INT_ROUTER_ENTRY(n + 0x18)
34 34
35#define LOONGSON_INT_CORE0_INT0 0x11 /* route to int 0 of core 0 */ 35#define LOONGSON_INT_COREx_INTy(x, y) (1<<(x) | 1<<(y+4)) /* route to int y of core x */
36#define LOONGSON_INT_CORE0_INT1 0x21 /* route to int 1 of core 0 */
37 36
38#endif 37#endif
39 38
diff --git a/arch/mips/include/asm/mach-loongson/loongson.h b/arch/mips/include/asm/mach-loongson/loongson.h
index 92bf76c21441..5459ac09679f 100644
--- a/arch/mips/include/asm/mach-loongson/loongson.h
+++ b/arch/mips/include/asm/mach-loongson/loongson.h
@@ -35,7 +35,7 @@ extern void __init prom_init_cmdline(void);
35extern void __init prom_init_machtype(void); 35extern void __init prom_init_machtype(void);
36extern void __init prom_init_env(void); 36extern void __init prom_init_env(void);
37#ifdef CONFIG_LOONGSON_UART_BASE 37#ifdef CONFIG_LOONGSON_UART_BASE
38extern unsigned long _loongson_uart_base, loongson_uart_base; 38extern unsigned long _loongson_uart_base[], loongson_uart_base[];
39extern void prom_init_loongson_uart_base(void); 39extern void prom_init_loongson_uart_base(void);
40#endif 40#endif
41 41
diff --git a/arch/mips/include/asm/mach-loongson/loongson_hwmon.h b/arch/mips/include/asm/mach-loongson/loongson_hwmon.h
new file mode 100644
index 000000000000..4431fc54a36c
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson/loongson_hwmon.h
@@ -0,0 +1,55 @@
1#ifndef __LOONGSON_HWMON_H_
2#define __LOONGSON_HWMON_H_
3
4#include <linux/types.h>
5
6#define MIN_TEMP 0
7#define MAX_TEMP 255
8#define NOT_VALID_TEMP 999
9
10typedef int (*get_temp_fun)(int);
11extern int loongson3_cpu_temp(int);
12
13/* 0:Max speed, 1:Manual, 2:Auto */
14enum fan_control_mode {
15 FAN_FULL_MODE = 0,
16 FAN_MANUAL_MODE = 1,
17 FAN_AUTO_MODE = 2,
18 FAN_MODE_END
19};
20
21struct temp_range {
22 u8 low;
23 u8 high;
24 u8 level;
25};
26
27#define CONSTANT_SPEED_POLICY 0 /* at constent speed */
28#define STEP_SPEED_POLICY 1 /* use up/down arrays to describe policy */
29#define KERNEL_HELPER_POLICY 2 /* kernel as a helper to fan control */
30
31#define MAX_STEP_NUM 16
32#define MAX_FAN_LEVEL 255
33
34/* loongson_fan_policy works when fan work at FAN_AUTO_MODE */
35struct loongson_fan_policy {
36 u8 type;
37
38 /* percent only used when type is CONSTANT_SPEED_POLICY */
39 u8 percent;
40
41 /* period between two check. (Unit: S) */
42 u8 adjust_period;
43
44 /* fan adjust usually depend on a temprature input */
45 get_temp_fun depend_temp;
46
47 /* up_step/down_step used when type is STEP_SPEED_POLICY */
48 u8 up_step_num;
49 u8 down_step_num;
50 struct temp_range up_step[MAX_STEP_NUM];
51 struct temp_range down_step[MAX_STEP_NUM];
52 struct delayed_work work;
53};
54
55#endif /* __LOONGSON_HWMON_H_*/
diff --git a/arch/mips/include/asm/mach-loongson/machine.h b/arch/mips/include/asm/mach-loongson/machine.h
index 228e37847a36..cb2b60249cd2 100644
--- a/arch/mips/include/asm/mach-loongson/machine.h
+++ b/arch/mips/include/asm/mach-loongson/machine.h
@@ -26,7 +26,7 @@
26 26
27#ifdef CONFIG_LOONGSON_MACH3X 27#ifdef CONFIG_LOONGSON_MACH3X
28 28
29#define LOONGSON_MACHTYPE MACH_LEMOTE_A1101 29#define LOONGSON_MACHTYPE MACH_LOONGSON_GENERIC
30 30
31#endif /* CONFIG_LOONGSON_MACH3X */ 31#endif /* CONFIG_LOONGSON_MACH3X */
32 32
diff --git a/arch/mips/include/asm/mach-loongson/topology.h b/arch/mips/include/asm/mach-loongson/topology.h
index 5598ba77d2ef..0d8f3b55bdbc 100644
--- a/arch/mips/include/asm/mach-loongson/topology.h
+++ b/arch/mips/include/asm/mach-loongson/topology.h
@@ -3,7 +3,7 @@
3 3
4#ifdef CONFIG_NUMA 4#ifdef CONFIG_NUMA
5 5
6#define cpu_to_node(cpu) ((cpu) >> 2) 6#define cpu_to_node(cpu) (cpu_logical_map(cpu) >> 2)
7#define parent_node(node) (node) 7#define parent_node(node) (node)
8#define cpumask_of_node(node) (&__node_data[(node)]->cpumask) 8#define cpumask_of_node(node) (&__node_data[(node)]->cpumask)
9 9
diff --git a/arch/mips/include/asm/mach-loongson/workarounds.h b/arch/mips/include/asm/mach-loongson/workarounds.h
new file mode 100644
index 000000000000..e180c1422eae
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson/workarounds.h
@@ -0,0 +1,7 @@
1#ifndef __ASM_MACH_LOONGSON_WORKAROUNDS_H_
2#define __ASM_MACH_LOONGSON_WORKAROUNDS_H_
3
4#define WORKAROUND_CPUFREQ 0x00000001
5#define WORKAROUND_CPUHOTPLUG 0x00000002
6
7#endif
diff --git a/arch/mips/include/asm/mach-loongson1/cpufreq.h b/arch/mips/include/asm/mach-loongson1/cpufreq.h
new file mode 100644
index 000000000000..e7765ce30bcf
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson1/cpufreq.h
@@ -0,0 +1,23 @@
1/*
2 * Copyright (c) 2014 Zhang, Keguang <keguang.zhang@gmail.com>
3 *
4 * Loongson 1 CPUFreq platform support.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12
13#ifndef __ASM_MACH_LOONGSON1_CPUFREQ_H
14#define __ASM_MACH_LOONGSON1_CPUFREQ_H
15
16struct plat_ls1x_cpufreq {
17 const char *clk_name; /* CPU clk */
18 const char *osc_clk_name; /* OSC clk */
19 unsigned int max_freq; /* in kHz */
20 unsigned int min_freq; /* in kHz */
21};
22
23#endif /* __ASM_MACH_LOONGSON1_CPUFREQ_H */
diff --git a/arch/mips/include/asm/mach-loongson1/loongson1.h b/arch/mips/include/asm/mach-loongson1/loongson1.h
index 5c437c2ba6b3..20e0c2b155dd 100644
--- a/arch/mips/include/asm/mach-loongson1/loongson1.h
+++ b/arch/mips/include/asm/mach-loongson1/loongson1.h
@@ -16,6 +16,7 @@
16#define DEFAULT_MEMSIZE 256 /* If no memsize provided */ 16#define DEFAULT_MEMSIZE 256 /* If no memsize provided */
17 17
18/* Loongson 1 Register Bases */ 18/* Loongson 1 Register Bases */
19#define LS1X_MUX_BASE 0x1fd00420
19#define LS1X_INTC_BASE 0x1fd01040 20#define LS1X_INTC_BASE 0x1fd01040
20#define LS1X_EHCI_BASE 0x1fe00000 21#define LS1X_EHCI_BASE 0x1fe00000
21#define LS1X_OHCI_BASE 0x1fe08000 22#define LS1X_OHCI_BASE 0x1fe08000
@@ -31,7 +32,10 @@
31#define LS1X_I2C0_BASE 0x1fe58000 32#define LS1X_I2C0_BASE 0x1fe58000
32#define LS1X_I2C1_BASE 0x1fe68000 33#define LS1X_I2C1_BASE 0x1fe68000
33#define LS1X_I2C2_BASE 0x1fe70000 34#define LS1X_I2C2_BASE 0x1fe70000
34#define LS1X_PWM_BASE 0x1fe5c000 35#define LS1X_PWM0_BASE 0x1fe5c000
36#define LS1X_PWM1_BASE 0x1fe5c010
37#define LS1X_PWM2_BASE 0x1fe5c020
38#define LS1X_PWM3_BASE 0x1fe5c030
35#define LS1X_WDT_BASE 0x1fe5c060 39#define LS1X_WDT_BASE 0x1fe5c060
36#define LS1X_RTC_BASE 0x1fe64000 40#define LS1X_RTC_BASE 0x1fe64000
37#define LS1X_AC97_BASE 0x1fe74000 41#define LS1X_AC97_BASE 0x1fe74000
@@ -39,6 +43,8 @@
39#define LS1X_CLK_BASE 0x1fe78030 43#define LS1X_CLK_BASE 0x1fe78030
40 44
41#include <regs-clk.h> 45#include <regs-clk.h>
46#include <regs-mux.h>
47#include <regs-pwm.h>
42#include <regs-wdt.h> 48#include <regs-wdt.h>
43 49
44#endif /* __ASM_MACH_LOONGSON1_LOONGSON1_H */ 50#endif /* __ASM_MACH_LOONGSON1_LOONGSON1_H */
diff --git a/arch/mips/include/asm/mach-loongson1/platform.h b/arch/mips/include/asm/mach-loongson1/platform.h
index 30c13e508fff..47de55e0c835 100644
--- a/arch/mips/include/asm/mach-loongson1/platform.h
+++ b/arch/mips/include/asm/mach-loongson1/platform.h
@@ -13,10 +13,12 @@
13 13
14#include <linux/platform_device.h> 14#include <linux/platform_device.h>
15 15
16extern struct platform_device ls1x_uart_device; 16extern struct platform_device ls1x_uart_pdev;
17extern struct platform_device ls1x_eth0_device; 17extern struct platform_device ls1x_cpufreq_pdev;
18extern struct platform_device ls1x_ehci_device; 18extern struct platform_device ls1x_eth0_pdev;
19extern struct platform_device ls1x_rtc_device; 19extern struct platform_device ls1x_eth1_pdev;
20extern struct platform_device ls1x_ehci_pdev;
21extern struct platform_device ls1x_rtc_pdev;
20 22
21extern void __init ls1x_clk_init(void); 23extern void __init ls1x_clk_init(void);
22extern void __init ls1x_serial_setup(struct platform_device *pdev); 24extern void __init ls1x_serial_setup(struct platform_device *pdev);
diff --git a/arch/mips/include/asm/mach-loongson1/regs-clk.h b/arch/mips/include/asm/mach-loongson1/regs-clk.h
index fb6a3ff9318f..ee2445b10fc3 100644
--- a/arch/mips/include/asm/mach-loongson1/regs-clk.h
+++ b/arch/mips/include/asm/mach-loongson1/regs-clk.h
@@ -20,15 +20,32 @@
20 20
21/* Clock PLL Divisor Register Bits */ 21/* Clock PLL Divisor Register Bits */
22#define DIV_DC_EN (0x1 << 31) 22#define DIV_DC_EN (0x1 << 31)
23#define DIV_DC_RST (0x1 << 30)
23#define DIV_CPU_EN (0x1 << 25) 24#define DIV_CPU_EN (0x1 << 25)
25#define DIV_CPU_RST (0x1 << 24)
24#define DIV_DDR_EN (0x1 << 19) 26#define DIV_DDR_EN (0x1 << 19)
27#define DIV_DDR_RST (0x1 << 18)
28#define RST_DC_EN (0x1 << 5)
29#define RST_DC (0x1 << 4)
30#define RST_DDR_EN (0x1 << 3)
31#define RST_DDR (0x1 << 2)
32#define RST_CPU_EN (0x1 << 1)
33#define RST_CPU 0x1
25 34
26#define DIV_DC_SHIFT 26 35#define DIV_DC_SHIFT 26
27#define DIV_CPU_SHIFT 20 36#define DIV_CPU_SHIFT 20
28#define DIV_DDR_SHIFT 14 37#define DIV_DDR_SHIFT 14
29 38
30#define DIV_DC_WIDTH 5 39#define DIV_DC_WIDTH 4
31#define DIV_CPU_WIDTH 5 40#define DIV_CPU_WIDTH 4
32#define DIV_DDR_WIDTH 5 41#define DIV_DDR_WIDTH 4
42
43#define BYPASS_DC_SHIFT 12
44#define BYPASS_DDR_SHIFT 10
45#define BYPASS_CPU_SHIFT 8
46
47#define BYPASS_DC_WIDTH 1
48#define BYPASS_DDR_WIDTH 1
49#define BYPASS_CPU_WIDTH 1
33 50
34#endif /* __ASM_MACH_LOONGSON1_REGS_CLK_H */ 51#endif /* __ASM_MACH_LOONGSON1_REGS_CLK_H */
diff --git a/arch/mips/include/asm/mach-loongson1/regs-mux.h b/arch/mips/include/asm/mach-loongson1/regs-mux.h
new file mode 100644
index 000000000000..fb1e36efaa19
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson1/regs-mux.h
@@ -0,0 +1,67 @@
1/*
2 * Copyright (c) 2014 Zhang, Keguang <keguang.zhang@gmail.com>
3 *
4 * Loongson 1 MUX Register Definitions.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12#ifndef __ASM_MACH_LOONGSON1_REGS_MUX_H
13#define __ASM_MACH_LOONGSON1_REGS_MUX_H
14
15#define LS1X_MUX_REG(x) \
16 ((void __iomem *)KSEG1ADDR(LS1X_MUX_BASE + (x)))
17
18#define LS1X_MUX_CTRL0 LS1X_MUX_REG(0x0)
19#define LS1X_MUX_CTRL1 LS1X_MUX_REG(0x4)
20
21/* MUX CTRL0 Register Bits */
22#define UART0_USE_PWM23 (0x1 << 28)
23#define UART0_USE_PWM01 (0x1 << 27)
24#define UART1_USE_LCD0_5_6_11 (0x1 << 26)
25#define I2C2_USE_CAN1 (0x1 << 25)
26#define I2C1_USE_CAN0 (0x1 << 24)
27#define NAND3_USE_UART5 (0x1 << 23)
28#define NAND3_USE_UART4 (0x1 << 22)
29#define NAND3_USE_UART1_DAT (0x1 << 21)
30#define NAND3_USE_UART1_CTS (0x1 << 20)
31#define NAND3_USE_PWM23 (0x1 << 19)
32#define NAND3_USE_PWM01 (0x1 << 18)
33#define NAND2_USE_UART5 (0x1 << 17)
34#define NAND2_USE_UART4 (0x1 << 16)
35#define NAND2_USE_UART1_DAT (0x1 << 15)
36#define NAND2_USE_UART1_CTS (0x1 << 14)
37#define NAND2_USE_PWM23 (0x1 << 13)
38#define NAND2_USE_PWM01 (0x1 << 12)
39#define NAND1_USE_UART5 (0x1 << 11)
40#define NAND1_USE_UART4 (0x1 << 10)
41#define NAND1_USE_UART1_DAT (0x1 << 9)
42#define NAND1_USE_UART1_CTS (0x1 << 8)
43#define NAND1_USE_PWM23 (0x1 << 7)
44#define NAND1_USE_PWM01 (0x1 << 6)
45#define GMAC1_USE_UART1 (0x1 << 4)
46#define GMAC1_USE_UART0 (0x1 << 3)
47#define LCD_USE_UART0_DAT (0x1 << 2)
48#define LCD_USE_UART15 (0x1 << 1)
49#define LCD_USE_UART0 0x1
50
51/* MUX CTRL1 Register Bits */
52#define USB_RESET (0x1 << 31)
53#define SPI1_CS_USE_PWM01 (0x1 << 24)
54#define SPI1_USE_CAN (0x1 << 23)
55#define DISABLE_DDR_CONFSPACE (0x1 << 20)
56#define DDR32TO16EN (0x1 << 16)
57#define GMAC1_SHUT (0x1 << 13)
58#define GMAC0_SHUT (0x1 << 12)
59#define USB_SHUT (0x1 << 11)
60#define UART1_3_USE_CAN1 (0x1 << 5)
61#define UART1_2_USE_CAN0 (0x1 << 4)
62#define GMAC1_USE_TXCLK (0x1 << 3)
63#define GMAC0_USE_TXCLK (0x1 << 2)
64#define GMAC1_USE_PWM23 (0x1 << 1)
65#define GMAC0_USE_PWM01 0x1
66
67#endif /* __ASM_MACH_LOONGSON1_REGS_MUX_H */
diff --git a/arch/mips/include/asm/mach-loongson1/regs-pwm.h b/arch/mips/include/asm/mach-loongson1/regs-pwm.h
new file mode 100644
index 000000000000..99f2bcc586f0
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson1/regs-pwm.h
@@ -0,0 +1,29 @@
1/*
2 * Copyright (c) 2014 Zhang, Keguang <keguang.zhang@gmail.com>
3 *
4 * Loongson 1 PWM Register Definitions.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12#ifndef __ASM_MACH_LOONGSON1_REGS_PWM_H
13#define __ASM_MACH_LOONGSON1_REGS_PWM_H
14
15/* Loongson 1 PWM Timer Register Definitions */
16#define PWM_CNT 0x0
17#define PWM_HRC 0x4
18#define PWM_LRC 0x8
19#define PWM_CTRL 0xc
20
21/* PWM Control Register Bits */
22#define CNT_RST (0x1 << 7)
23#define INT_SR (0x1 << 6)
24#define INT_EN (0x1 << 5)
25#define PWM_SINGLE (0x1 << 4)
26#define PWM_OE (0x1 << 3)
27#define CNT_EN 0x1
28
29#endif /* __ASM_MACH_LOONGSON1_REGS_PWM_H */
diff --git a/arch/mips/include/asm/mach-loongson1/regs-wdt.h b/arch/mips/include/asm/mach-loongson1/regs-wdt.h
index 6574568c2084..c39ee982ad3b 100644
--- a/arch/mips/include/asm/mach-loongson1/regs-wdt.h
+++ b/arch/mips/include/asm/mach-loongson1/regs-wdt.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com> 2 * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
3 * 3 *
4 * Loongson 1 watchdog register definitions. 4 * Loongson 1 Watchdog Register Definitions.
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify it 6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the 7 * under the terms of the GNU General Public License as published by the
@@ -12,11 +12,8 @@
12#ifndef __ASM_MACH_LOONGSON1_REGS_WDT_H 12#ifndef __ASM_MACH_LOONGSON1_REGS_WDT_H
13#define __ASM_MACH_LOONGSON1_REGS_WDT_H 13#define __ASM_MACH_LOONGSON1_REGS_WDT_H
14 14
15#define LS1X_WDT_REG(x) \ 15#define WDT_EN 0x0
16 ((void __iomem *)KSEG1ADDR(LS1X_WDT_BASE + (x))) 16#define WDT_TIMER 0x4
17 17#define WDT_SET 0x8
18#define LS1X_WDT_EN LS1X_WDT_REG(0x0)
19#define LS1X_WDT_SET LS1X_WDT_REG(0x4)
20#define LS1X_WDT_TIMER LS1X_WDT_REG(0x8)
21 18
22#endif /* __ASM_MACH_LOONGSON1_REGS_WDT_H */ 19#endif /* __ASM_MACH_LOONGSON1_REGS_WDT_H */
diff --git a/arch/mips/include/asm/mach-malta/irq.h b/arch/mips/include/asm/mach-malta/irq.h
index f2c13d211abb..47cfe64efbb0 100644
--- a/arch/mips/include/asm/mach-malta/irq.h
+++ b/arch/mips/include/asm/mach-malta/irq.h
@@ -2,7 +2,6 @@
2#define __ASM_MACH_MIPS_IRQ_H 2#define __ASM_MACH_MIPS_IRQ_H
3 3
4 4
5#define GIC_NUM_INTRS (24 + NR_CPUS * 2)
6#define NR_IRQS 256 5#define NR_IRQS 256
7 6
8#include_next <irq.h> 7#include_next <irq.h>
diff --git a/arch/mips/include/asm/mach-pmcs-msp71xx/msp_regops.h b/arch/mips/include/asm/mach-pmcs-msp71xx/msp_regops.h
index fc946c835995..2e54b4bff5cf 100644
--- a/arch/mips/include/asm/mach-pmcs-msp71xx/msp_regops.h
+++ b/arch/mips/include/asm/mach-pmcs-msp71xx/msp_regops.h
@@ -49,6 +49,7 @@
49 49
50#include <linux/types.h> 50#include <linux/types.h>
51 51
52#include <asm/compiler.h>
52#include <asm/war.h> 53#include <asm/war.h>
53 54
54#ifndef R10000_LLSC_WAR 55#ifndef R10000_LLSC_WAR
@@ -84,8 +85,8 @@ static inline void set_value_reg32(volatile u32 *const addr,
84 " "__beqz"%0, 1b \n" 85 " "__beqz"%0, 1b \n"
85 " nop \n" 86 " nop \n"
86 " .set pop \n" 87 " .set pop \n"
87 : "=&r" (temp), "=m" (*addr) 88 : "=&r" (temp), "=" GCC_OFF12_ASM() (*addr)
88 : "ir" (~mask), "ir" (value), "m" (*addr)); 89 : "ir" (~mask), "ir" (value), GCC_OFF12_ASM() (*addr));
89} 90}
90 91
91/* 92/*
@@ -105,8 +106,8 @@ static inline void set_reg32(volatile u32 *const addr,
105 " "__beqz"%0, 1b \n" 106 " "__beqz"%0, 1b \n"
106 " nop \n" 107 " nop \n"
107 " .set pop \n" 108 " .set pop \n"
108 : "=&r" (temp), "=m" (*addr) 109 : "=&r" (temp), "=" GCC_OFF12_ASM() (*addr)
109 : "ir" (mask), "m" (*addr)); 110 : "ir" (mask), GCC_OFF12_ASM() (*addr));
110} 111}
111 112
112/* 113/*
@@ -126,8 +127,8 @@ static inline void clear_reg32(volatile u32 *const addr,
126 " "__beqz"%0, 1b \n" 127 " "__beqz"%0, 1b \n"
127 " nop \n" 128 " nop \n"
128 " .set pop \n" 129 " .set pop \n"
129 : "=&r" (temp), "=m" (*addr) 130 : "=&r" (temp), "=" GCC_OFF12_ASM() (*addr)
130 : "ir" (~mask), "m" (*addr)); 131 : "ir" (~mask), GCC_OFF12_ASM() (*addr));
131} 132}
132 133
133/* 134/*
@@ -147,8 +148,8 @@ static inline void toggle_reg32(volatile u32 *const addr,
147 " "__beqz"%0, 1b \n" 148 " "__beqz"%0, 1b \n"
148 " nop \n" 149 " nop \n"
149 " .set pop \n" 150 " .set pop \n"
150 : "=&r" (temp), "=m" (*addr) 151 : "=&r" (temp), "=" GCC_OFF12_ASM() (*addr)
151 : "ir" (mask), "m" (*addr)); 152 : "ir" (mask), GCC_OFF12_ASM() (*addr));
152} 153}
153 154
154/* 155/*
@@ -219,8 +220,8 @@ static inline u32 blocking_read_reg32(volatile u32 *const addr)
219 " .set arch=r4000 \n" \ 220 " .set arch=r4000 \n" \
220 "1: ll %0, %1 #custom_read_reg32 \n" \ 221 "1: ll %0, %1 #custom_read_reg32 \n" \
221 " .set pop \n" \ 222 " .set pop \n" \
222 : "=r" (tmp), "=m" (*address) \ 223 : "=r" (tmp), "=" GCC_OFF12_ASM() (*address) \
223 : "m" (*address)) 224 : GCC_OFF12_ASM() (*address))
224 225
225#define custom_write_reg32(address, tmp) \ 226#define custom_write_reg32(address, tmp) \
226 __asm__ __volatile__( \ 227 __asm__ __volatile__( \
@@ -230,7 +231,7 @@ static inline u32 blocking_read_reg32(volatile u32 *const addr)
230 " "__beqz"%0, 1b \n" \ 231 " "__beqz"%0, 1b \n" \
231 " nop \n" \ 232 " nop \n" \
232 " .set pop \n" \ 233 " .set pop \n" \
233 : "=&r" (tmp), "=m" (*address) \ 234 : "=&r" (tmp), "=" GCC_OFF12_ASM() (*address) \
234 : "0" (tmp), "m" (*address)) 235 : "0" (tmp), GCC_OFF12_ASM() (*address))
235 236
236#endif /* __ASM_REGOPS_H__ */ 237#endif /* __ASM_REGOPS_H__ */
diff --git a/arch/mips/include/asm/mach-ralink/mt7620.h b/arch/mips/include/asm/mach-ralink/mt7620.h
index 6f9b24f51157..1976fb815fd1 100644
--- a/arch/mips/include/asm/mach-ralink/mt7620.h
+++ b/arch/mips/include/asm/mach-ralink/mt7620.h
@@ -13,6 +13,13 @@
13#ifndef _MT7620_REGS_H_ 13#ifndef _MT7620_REGS_H_
14#define _MT7620_REGS_H_ 14#define _MT7620_REGS_H_
15 15
16enum mt762x_soc_type {
17 MT762X_SOC_UNKNOWN = 0,
18 MT762X_SOC_MT7620A,
19 MT762X_SOC_MT7620N,
20 MT762X_SOC_MT7628AN,
21};
22
16#define MT7620_SYSC_BASE 0x10000000 23#define MT7620_SYSC_BASE 0x10000000
17 24
18#define SYSC_REG_CHIP_NAME0 0x00 25#define SYSC_REG_CHIP_NAME0 0x00
@@ -25,11 +32,9 @@
25#define SYSC_REG_CPLL_CONFIG0 0x54 32#define SYSC_REG_CPLL_CONFIG0 0x54
26#define SYSC_REG_CPLL_CONFIG1 0x58 33#define SYSC_REG_CPLL_CONFIG1 0x58
27 34
28#define MT7620N_CHIP_NAME0 0x33365452 35#define MT7620_CHIP_NAME0 0x3637544d
29#define MT7620N_CHIP_NAME1 0x20203235 36#define MT7620_CHIP_NAME1 0x20203032
30 37#define MT7628_CHIP_NAME1 0x20203832
31#define MT7620A_CHIP_NAME0 0x3637544d
32#define MT7620A_CHIP_NAME1 0x20203032
33 38
34#define SYSCFG0_XTAL_FREQ_SEL BIT(6) 39#define SYSCFG0_XTAL_FREQ_SEL BIT(6)
35 40
@@ -74,6 +79,9 @@
74#define SYSCFG0_DRAM_TYPE_DDR1 1 79#define SYSCFG0_DRAM_TYPE_DDR1 1
75#define SYSCFG0_DRAM_TYPE_DDR2 2 80#define SYSCFG0_DRAM_TYPE_DDR2 2
76 81
82#define SYSCFG0_DRAM_TYPE_DDR2_MT7628 0
83#define SYSCFG0_DRAM_TYPE_DDR1_MT7628 1
84
77#define MT7620_DRAM_BASE 0x0 85#define MT7620_DRAM_BASE 0x0
78#define MT7620_SDRAM_SIZE_MIN 2 86#define MT7620_SDRAM_SIZE_MIN 2
79#define MT7620_SDRAM_SIZE_MAX 64 87#define MT7620_SDRAM_SIZE_MAX 64
@@ -82,7 +90,6 @@
82#define MT7620_DDR2_SIZE_MIN 32 90#define MT7620_DDR2_SIZE_MIN 32
83#define MT7620_DDR2_SIZE_MAX 256 91#define MT7620_DDR2_SIZE_MAX 256
84 92
85#define MT7620_GPIO_MODE_I2C BIT(0)
86#define MT7620_GPIO_MODE_UART0_SHIFT 2 93#define MT7620_GPIO_MODE_UART0_SHIFT 2
87#define MT7620_GPIO_MODE_UART0_MASK 0x7 94#define MT7620_GPIO_MODE_UART0_MASK 0x7
88#define MT7620_GPIO_MODE_UART0(x) ((x) << MT7620_GPIO_MODE_UART0_SHIFT) 95#define MT7620_GPIO_MODE_UART0(x) ((x) << MT7620_GPIO_MODE_UART0_SHIFT)
@@ -94,15 +101,40 @@
94#define MT7620_GPIO_MODE_GPIO_UARTF 0x5 101#define MT7620_GPIO_MODE_GPIO_UARTF 0x5
95#define MT7620_GPIO_MODE_GPIO_I2S 0x6 102#define MT7620_GPIO_MODE_GPIO_I2S 0x6
96#define MT7620_GPIO_MODE_GPIO 0x7 103#define MT7620_GPIO_MODE_GPIO 0x7
97#define MT7620_GPIO_MODE_UART1 BIT(5) 104
98#define MT7620_GPIO_MODE_MDIO BIT(8) 105#define MT7620_GPIO_MODE_NAND 0
99#define MT7620_GPIO_MODE_RGMII1 BIT(9) 106#define MT7620_GPIO_MODE_SD 1
100#define MT7620_GPIO_MODE_RGMII2 BIT(10) 107#define MT7620_GPIO_MODE_ND_SD_GPIO 2
101#define MT7620_GPIO_MODE_SPI BIT(11) 108#define MT7620_GPIO_MODE_ND_SD_MASK 0x3
102#define MT7620_GPIO_MODE_SPI_REF_CLK BIT(12) 109#define MT7620_GPIO_MODE_ND_SD_SHIFT 18
103#define MT7620_GPIO_MODE_WLED BIT(13) 110
104#define MT7620_GPIO_MODE_JTAG BIT(15) 111#define MT7620_GPIO_MODE_PCIE_RST 0
105#define MT7620_GPIO_MODE_EPHY BIT(15) 112#define MT7620_GPIO_MODE_PCIE_REF 1
106#define MT7620_GPIO_MODE_WDT BIT(22) 113#define MT7620_GPIO_MODE_PCIE_GPIO 2
114#define MT7620_GPIO_MODE_PCIE_MASK 0x3
115#define MT7620_GPIO_MODE_PCIE_SHIFT 16
116
117#define MT7620_GPIO_MODE_WDT_RST 0
118#define MT7620_GPIO_MODE_WDT_REF 1
119#define MT7620_GPIO_MODE_WDT_GPIO 2
120#define MT7620_GPIO_MODE_WDT_MASK 0x3
121#define MT7620_GPIO_MODE_WDT_SHIFT 21
122
123#define MT7620_GPIO_MODE_I2C 0
124#define MT7620_GPIO_MODE_UART1 5
125#define MT7620_GPIO_MODE_MDIO 8
126#define MT7620_GPIO_MODE_RGMII1 9
127#define MT7620_GPIO_MODE_RGMII2 10
128#define MT7620_GPIO_MODE_SPI 11
129#define MT7620_GPIO_MODE_SPI_REF_CLK 12
130#define MT7620_GPIO_MODE_WLED 13
131#define MT7620_GPIO_MODE_JTAG 15
132#define MT7620_GPIO_MODE_EPHY 15
133#define MT7620_GPIO_MODE_PA 20
134
135static inline int mt7620_get_eco(void)
136{
137 return rt_sysc_r32(SYSC_REG_CHIP_REV) & CHIP_REV_ECO_MASK;
138}
107 139
108#endif 140#endif
diff --git a/arch/mips/include/asm/mach-ralink/pinmux.h b/arch/mips/include/asm/mach-ralink/pinmux.h
new file mode 100644
index 000000000000..be106cb2e26d
--- /dev/null
+++ b/arch/mips/include/asm/mach-ralink/pinmux.h
@@ -0,0 +1,55 @@
1/*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License version 2 as
4 * publishhed by the Free Software Foundation.
5 *
6 * Copyright (C) 2012 John Crispin <blogic@openwrt.org>
7 */
8
9#ifndef _RT288X_PINMUX_H__
10#define _RT288X_PINMUX_H__
11
12#define FUNC(name, value, pin_first, pin_count) \
13 { name, value, pin_first, pin_count }
14
15#define GRP(_name, _func, _mask, _shift) \
16 { .name = _name, .mask = _mask, .shift = _shift, \
17 .func = _func, .gpio = _mask, \
18 .func_count = ARRAY_SIZE(_func) }
19
20#define GRP_G(_name, _func, _mask, _gpio, _shift) \
21 { .name = _name, .mask = _mask, .shift = _shift, \
22 .func = _func, .gpio = _gpio, \
23 .func_count = ARRAY_SIZE(_func) }
24
25struct rt2880_pmx_group;
26
27struct rt2880_pmx_func {
28 const char *name;
29 const char value;
30
31 int pin_first;
32 int pin_count;
33 int *pins;
34
35 int *groups;
36 int group_count;
37
38 int enabled;
39};
40
41struct rt2880_pmx_group {
42 const char *name;
43 int enabled;
44
45 const u32 shift;
46 const char mask;
47 const char gpio;
48
49 struct rt2880_pmx_func *func;
50 int func_count;
51};
52
53extern struct rt2880_pmx_group *rt2880_pinmux_data;
54
55#endif
diff --git a/arch/mips/include/asm/mach-ralink/ralink_regs.h b/arch/mips/include/asm/mach-ralink/ralink_regs.h
index 5a508f9f9432..bd93014490df 100644
--- a/arch/mips/include/asm/mach-ralink/ralink_regs.h
+++ b/arch/mips/include/asm/mach-ralink/ralink_regs.h
@@ -26,6 +26,13 @@ static inline u32 rt_sysc_r32(unsigned reg)
26 return __raw_readl(rt_sysc_membase + reg); 26 return __raw_readl(rt_sysc_membase + reg);
27} 27}
28 28
29static inline void rt_sysc_m32(u32 clr, u32 set, unsigned reg)
30{
31 u32 val = rt_sysc_r32(reg) & ~clr;
32
33 __raw_writel(val | set, rt_sysc_membase + reg);
34}
35
29static inline void rt_memc_w32(u32 val, unsigned reg) 36static inline void rt_memc_w32(u32 val, unsigned reg)
30{ 37{
31 __raw_writel(val, rt_memc_membase + reg); 38 __raw_writel(val, rt_memc_membase + reg);
diff --git a/arch/mips/include/asm/mach-ralink/rt305x.h b/arch/mips/include/asm/mach-ralink/rt305x.h
index 069bf37a6010..96f731bac79a 100644
--- a/arch/mips/include/asm/mach-ralink/rt305x.h
+++ b/arch/mips/include/asm/mach-ralink/rt305x.h
@@ -125,24 +125,29 @@ static inline int soc_is_rt5350(void)
125#define RT305X_GPIO_GE0_TXD0 40 125#define RT305X_GPIO_GE0_TXD0 40
126#define RT305X_GPIO_GE0_RXCLK 51 126#define RT305X_GPIO_GE0_RXCLK 51
127 127
128#define RT305X_GPIO_MODE_I2C BIT(0)
129#define RT305X_GPIO_MODE_SPI BIT(1)
130#define RT305X_GPIO_MODE_UART0_SHIFT 2 128#define RT305X_GPIO_MODE_UART0_SHIFT 2
131#define RT305X_GPIO_MODE_UART0_MASK 0x7 129#define RT305X_GPIO_MODE_UART0_MASK 0x7
132#define RT305X_GPIO_MODE_UART0(x) ((x) << RT305X_GPIO_MODE_UART0_SHIFT) 130#define RT305X_GPIO_MODE_UART0(x) ((x) << RT305X_GPIO_MODE_UART0_SHIFT)
133#define RT305X_GPIO_MODE_UARTF 0x0 131#define RT305X_GPIO_MODE_UARTF 0
134#define RT305X_GPIO_MODE_PCM_UARTF 0x1 132#define RT305X_GPIO_MODE_PCM_UARTF 1
135#define RT305X_GPIO_MODE_PCM_I2S 0x2 133#define RT305X_GPIO_MODE_PCM_I2S 2
136#define RT305X_GPIO_MODE_I2S_UARTF 0x3 134#define RT305X_GPIO_MODE_I2S_UARTF 3
137#define RT305X_GPIO_MODE_PCM_GPIO 0x4 135#define RT305X_GPIO_MODE_PCM_GPIO 4
138#define RT305X_GPIO_MODE_GPIO_UARTF 0x5 136#define RT305X_GPIO_MODE_GPIO_UARTF 5
139#define RT305X_GPIO_MODE_GPIO_I2S 0x6 137#define RT305X_GPIO_MODE_GPIO_I2S 6
140#define RT305X_GPIO_MODE_GPIO 0x7 138#define RT305X_GPIO_MODE_GPIO 7
141#define RT305X_GPIO_MODE_UART1 BIT(5) 139
142#define RT305X_GPIO_MODE_JTAG BIT(6) 140#define RT305X_GPIO_MODE_I2C 0
143#define RT305X_GPIO_MODE_MDIO BIT(7) 141#define RT305X_GPIO_MODE_SPI 1
144#define RT305X_GPIO_MODE_SDRAM BIT(8) 142#define RT305X_GPIO_MODE_UART1 5
145#define RT305X_GPIO_MODE_RGMII BIT(9) 143#define RT305X_GPIO_MODE_JTAG 6
144#define RT305X_GPIO_MODE_MDIO 7
145#define RT305X_GPIO_MODE_SDRAM 8
146#define RT305X_GPIO_MODE_RGMII 9
147#define RT5350_GPIO_MODE_PHY_LED 14
148#define RT5350_GPIO_MODE_SPI_CS1 21
149#define RT3352_GPIO_MODE_LNA 18
150#define RT3352_GPIO_MODE_PA 20
146 151
147#define RT3352_SYSC_REG_SYSCFG0 0x010 152#define RT3352_SYSC_REG_SYSCFG0 0x010
148#define RT3352_SYSC_REG_SYSCFG1 0x014 153#define RT3352_SYSC_REG_SYSCFG1 0x014
diff --git a/arch/mips/include/asm/mach-ralink/rt3883.h b/arch/mips/include/asm/mach-ralink/rt3883.h
index 058382f37f92..0fbe6f9257cd 100644
--- a/arch/mips/include/asm/mach-ralink/rt3883.h
+++ b/arch/mips/include/asm/mach-ralink/rt3883.h
@@ -112,8 +112,6 @@
112#define RT3883_CLKCFG1_PCI_CLK_EN BIT(19) 112#define RT3883_CLKCFG1_PCI_CLK_EN BIT(19)
113#define RT3883_CLKCFG1_UPHY0_CLK_EN BIT(18) 113#define RT3883_CLKCFG1_UPHY0_CLK_EN BIT(18)
114 114
115#define RT3883_GPIO_MODE_I2C BIT(0)
116#define RT3883_GPIO_MODE_SPI BIT(1)
117#define RT3883_GPIO_MODE_UART0_SHIFT 2 115#define RT3883_GPIO_MODE_UART0_SHIFT 2
118#define RT3883_GPIO_MODE_UART0_MASK 0x7 116#define RT3883_GPIO_MODE_UART0_MASK 0x7
119#define RT3883_GPIO_MODE_UART0(x) ((x) << RT3883_GPIO_MODE_UART0_SHIFT) 117#define RT3883_GPIO_MODE_UART0(x) ((x) << RT3883_GPIO_MODE_UART0_SHIFT)
@@ -125,11 +123,15 @@
125#define RT3883_GPIO_MODE_GPIO_UARTF 0x5 123#define RT3883_GPIO_MODE_GPIO_UARTF 0x5
126#define RT3883_GPIO_MODE_GPIO_I2S 0x6 124#define RT3883_GPIO_MODE_GPIO_I2S 0x6
127#define RT3883_GPIO_MODE_GPIO 0x7 125#define RT3883_GPIO_MODE_GPIO 0x7
128#define RT3883_GPIO_MODE_UART1 BIT(5) 126
129#define RT3883_GPIO_MODE_JTAG BIT(6) 127#define RT3883_GPIO_MODE_I2C 0
130#define RT3883_GPIO_MODE_MDIO BIT(7) 128#define RT3883_GPIO_MODE_SPI 1
131#define RT3883_GPIO_MODE_GE1 BIT(9) 129#define RT3883_GPIO_MODE_UART1 5
132#define RT3883_GPIO_MODE_GE2 BIT(10) 130#define RT3883_GPIO_MODE_JTAG 6
131#define RT3883_GPIO_MODE_MDIO 7
132#define RT3883_GPIO_MODE_GE1 9
133#define RT3883_GPIO_MODE_GE2 10
134
133#define RT3883_GPIO_MODE_PCI_SHIFT 11 135#define RT3883_GPIO_MODE_PCI_SHIFT 11
134#define RT3883_GPIO_MODE_PCI_MASK 0x7 136#define RT3883_GPIO_MODE_PCI_MASK 0x7
135#define RT3883_GPIO_MODE_PCI (RT3883_GPIO_MODE_PCI_MASK << RT3883_GPIO_MODE_PCI_SHIFT) 137#define RT3883_GPIO_MODE_PCI (RT3883_GPIO_MODE_PCI_MASK << RT3883_GPIO_MODE_PCI_SHIFT)
diff --git a/arch/mips/include/asm/mach-sead3/irq.h b/arch/mips/include/asm/mach-sead3/irq.h
index d8106f75b9af..5d154cfbcf4c 100644
--- a/arch/mips/include/asm/mach-sead3/irq.h
+++ b/arch/mips/include/asm/mach-sead3/irq.h
@@ -1,7 +1,6 @@
1#ifndef __ASM_MACH_MIPS_IRQ_H 1#ifndef __ASM_MACH_MIPS_IRQ_H
2#define __ASM_MACH_MIPS_IRQ_H 2#define __ASM_MACH_MIPS_IRQ_H
3 3
4#define GIC_NUM_INTRS (24 + NR_CPUS * 2)
5#define NR_IRQS 256 4#define NR_IRQS 256
6 5
7 6
diff --git a/arch/mips/include/asm/mach-tx39xx/ioremap.h b/arch/mips/include/asm/mach-tx39xx/ioremap.h
index 93c6c04ffda3..0874cd2b06d7 100644
--- a/arch/mips/include/asm/mach-tx39xx/ioremap.h
+++ b/arch/mips/include/asm/mach-tx39xx/ioremap.h
@@ -15,12 +15,12 @@
15 * Allow physical addresses to be fixed up to help peripherals located 15 * Allow physical addresses to be fixed up to help peripherals located
16 * outside the low 32-bit range -- generic pass-through version. 16 * outside the low 32-bit range -- generic pass-through version.
17 */ 17 */
18static inline phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size) 18static inline phys_addr_t fixup_bigphys_addr(phys_addr_t phys_addr, phys_addr_t size)
19{ 19{
20 return phys_addr; 20 return phys_addr;
21} 21}
22 22
23static inline void __iomem *plat_ioremap(phys_t offset, unsigned long size, 23static inline void __iomem *plat_ioremap(phys_addr_t offset, unsigned long size,
24 unsigned long flags) 24 unsigned long flags)
25{ 25{
26#define TXX9_DIRECTMAP_BASE 0xff000000ul 26#define TXX9_DIRECTMAP_BASE 0xff000000ul
diff --git a/arch/mips/include/asm/mach-tx49xx/ioremap.h b/arch/mips/include/asm/mach-tx49xx/ioremap.h
index 1e7beae72229..4b6a8441b25f 100644
--- a/arch/mips/include/asm/mach-tx49xx/ioremap.h
+++ b/arch/mips/include/asm/mach-tx49xx/ioremap.h
@@ -15,12 +15,12 @@
15 * Allow physical addresses to be fixed up to help peripherals located 15 * Allow physical addresses to be fixed up to help peripherals located
16 * outside the low 32-bit range -- generic pass-through version. 16 * outside the low 32-bit range -- generic pass-through version.
17 */ 17 */
18static inline phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size) 18static inline phys_addr_t fixup_bigphys_addr(phys_addr_t phys_addr, phys_addr_t size)
19{ 19{
20 return phys_addr; 20 return phys_addr;
21} 21}
22 22
23static inline void __iomem *plat_ioremap(phys_t offset, unsigned long size, 23static inline void __iomem *plat_ioremap(phys_addr_t offset, unsigned long size,
24 unsigned long flags) 24 unsigned long flags)
25{ 25{
26#ifdef CONFIG_64BIT 26#ifdef CONFIG_64BIT
diff --git a/arch/mips/include/asm/mips-boards/maltaint.h b/arch/mips/include/asm/mips-boards/maltaint.h
index e330732ddf98..987ff580466b 100644
--- a/arch/mips/include/asm/mips-boards/maltaint.h
+++ b/arch/mips/include/asm/mips-boards/maltaint.h
@@ -10,7 +10,7 @@
10#ifndef _MIPS_MALTAINT_H 10#ifndef _MIPS_MALTAINT_H
11#define _MIPS_MALTAINT_H 11#define _MIPS_MALTAINT_H
12 12
13#define MIPS_GIC_IRQ_BASE (MIPS_CPU_IRQ_BASE + 8) 13#include <linux/irqchip/mips-gic.h>
14 14
15/* 15/*
16 * Interrupts 0..15 are used for Malta ISA compatible interrupts 16 * Interrupts 0..15 are used for Malta ISA compatible interrupts
@@ -22,29 +22,28 @@
22#define MIPSCPU_INT_SW1 1 22#define MIPSCPU_INT_SW1 1
23#define MIPSCPU_INT_MB0 2 23#define MIPSCPU_INT_MB0 2
24#define MIPSCPU_INT_I8259A MIPSCPU_INT_MB0 24#define MIPSCPU_INT_I8259A MIPSCPU_INT_MB0
25#define MIPSCPU_INT_GIC MIPSCPU_INT_MB0 /* GIC chained interrupt */
25#define MIPSCPU_INT_MB1 3 26#define MIPSCPU_INT_MB1 3
26#define MIPSCPU_INT_SMI MIPSCPU_INT_MB1 27#define MIPSCPU_INT_SMI MIPSCPU_INT_MB1
27#define MIPSCPU_INT_IPI0 MIPSCPU_INT_MB1 /* GIC IPI */
28#define MIPSCPU_INT_MB2 4 28#define MIPSCPU_INT_MB2 4
29#define MIPSCPU_INT_IPI1 MIPSCPU_INT_MB2 /* GIC IPI */
30#define MIPSCPU_INT_MB3 5 29#define MIPSCPU_INT_MB3 5
31#define MIPSCPU_INT_COREHI MIPSCPU_INT_MB3 30#define MIPSCPU_INT_COREHI MIPSCPU_INT_MB3
32#define MIPSCPU_INT_MB4 6 31#define MIPSCPU_INT_MB4 6
33#define MIPSCPU_INT_CORELO MIPSCPU_INT_MB4 32#define MIPSCPU_INT_CORELO MIPSCPU_INT_MB4
34 33
35/* 34/*
36 * Interrupts 64..127 are used for Soc-it Classic interrupts 35 * Interrupts 96..127 are used for Soc-it Classic interrupts
37 */ 36 */
38#define MSC01C_INT_BASE 64 37#define MSC01C_INT_BASE 96
39 38
40/* SOC-it Classic interrupt offsets */ 39/* SOC-it Classic interrupt offsets */
41#define MSC01C_INT_TMR 0 40#define MSC01C_INT_TMR 0
42#define MSC01C_INT_PCI 1 41#define MSC01C_INT_PCI 1
43 42
44/* 43/*
45 * Interrupts 64..127 are used for Soc-it EIC interrupts 44 * Interrupts 96..127 are used for Soc-it EIC interrupts
46 */ 45 */
47#define MSC01E_INT_BASE 64 46#define MSC01E_INT_BASE 96
48 47
49/* SOC-it EIC interrupt offsets */ 48/* SOC-it EIC interrupt offsets */
50#define MSC01E_INT_SW0 1 49#define MSC01E_INT_SW0 1
@@ -63,14 +62,7 @@
63#define MSC01E_INT_PERFCTR 10 62#define MSC01E_INT_PERFCTR 10
64#define MSC01E_INT_CPUCTR 11 63#define MSC01E_INT_CPUCTR 11
65 64
66/* External Interrupts used for IPI */ 65/* GIC external interrupts */
67#define GIC_IPI_EXT_INTR_RESCHED_VPE0 16 66#define GIC_INT_I8259A GIC_SHARED_TO_HWIRQ(3)
68#define GIC_IPI_EXT_INTR_CALLFNC_VPE0 17
69#define GIC_IPI_EXT_INTR_RESCHED_VPE1 18
70#define GIC_IPI_EXT_INTR_CALLFNC_VPE1 19
71#define GIC_IPI_EXT_INTR_RESCHED_VPE2 20
72#define GIC_IPI_EXT_INTR_CALLFNC_VPE2 21
73#define GIC_IPI_EXT_INTR_RESCHED_VPE3 22
74#define GIC_IPI_EXT_INTR_CALLFNC_VPE3 23
75 67
76#endif /* !(_MIPS_MALTAINT_H) */ 68#endif /* !(_MIPS_MALTAINT_H) */
diff --git a/arch/mips/include/asm/mips-boards/sead3int.h b/arch/mips/include/asm/mips-boards/sead3int.h
index 6b17aaf7d901..8932c7de0419 100644
--- a/arch/mips/include/asm/mips-boards/sead3int.h
+++ b/arch/mips/include/asm/mips-boards/sead3int.h
@@ -10,10 +10,23 @@
10#ifndef _MIPS_SEAD3INT_H 10#ifndef _MIPS_SEAD3INT_H
11#define _MIPS_SEAD3INT_H 11#define _MIPS_SEAD3INT_H
12 12
13#include <linux/irqchip/mips-gic.h>
14
13/* SEAD-3 GIC address space definitions. */ 15/* SEAD-3 GIC address space definitions. */
14#define GIC_BASE_ADDR 0x1b1c0000 16#define GIC_BASE_ADDR 0x1b1c0000
15#define GIC_ADDRSPACE_SZ (128 * 1024) 17#define GIC_ADDRSPACE_SZ (128 * 1024)
16 18
17#define MIPS_GIC_IRQ_BASE (MIPS_CPU_IRQ_BASE + 0) 19/* CPU interrupt offsets */
20#define CPU_INT_GIC 2
21#define CPU_INT_EHCI 2
22#define CPU_INT_UART0 4
23#define CPU_INT_UART1 4
24#define CPU_INT_NET 6
25
26/* GIC interrupt offsets */
27#define GIC_INT_NET GIC_SHARED_TO_HWIRQ(0)
28#define GIC_INT_UART1 GIC_SHARED_TO_HWIRQ(2)
29#define GIC_INT_UART0 GIC_SHARED_TO_HWIRQ(3)
30#define GIC_INT_EHCI GIC_SHARED_TO_HWIRQ(5)
18 31
19#endif /* !(_MIPS_SEAD3INT_H) */ 32#endif /* !(_MIPS_SEAD3INT_H) */
diff --git a/arch/mips/include/asm/mips-cm.h b/arch/mips/include/asm/mips-cm.h
index 6a9d2dd005ca..b95a827d763e 100644
--- a/arch/mips/include/asm/mips-cm.h
+++ b/arch/mips/include/asm/mips-cm.h
@@ -30,7 +30,7 @@ extern void __iomem *mips_cm_l2sync_base;
30 * different way by defining a function with the same prototype except for the 30 * different way by defining a function with the same prototype except for the
31 * name mips_cm_phys_base (without underscores). 31 * name mips_cm_phys_base (without underscores).
32 */ 32 */
33extern phys_t __mips_cm_phys_base(void); 33extern phys_addr_t __mips_cm_phys_base(void);
34 34
35/** 35/**
36 * mips_cm_probe - probe for a Coherence Manager 36 * mips_cm_probe - probe for a Coherence Manager
diff --git a/arch/mips/include/asm/mips-cpc.h b/arch/mips/include/asm/mips-cpc.h
index e139a534e0fd..1cebe8c79051 100644
--- a/arch/mips/include/asm/mips-cpc.h
+++ b/arch/mips/include/asm/mips-cpc.h
@@ -25,7 +25,7 @@ extern void __iomem *mips_cpc_base;
25 * memory mapped registers. This is platform dependant & must therefore be 25 * memory mapped registers. This is platform dependant & must therefore be
26 * implemented per-platform. 26 * implemented per-platform.
27 */ 27 */
28extern phys_t mips_cpc_default_phys_base(void); 28extern phys_addr_t mips_cpc_default_phys_base(void);
29 29
30/** 30/**
31 * mips_cpc_phys_base - retrieve the physical base address of the CPC 31 * mips_cpc_phys_base - retrieve the physical base address of the CPC
@@ -35,7 +35,7 @@ extern phys_t mips_cpc_default_phys_base(void);
35 * is present. It may be overriden by individual platforms which determine 35 * is present. It may be overriden by individual platforms which determine
36 * this address in a different way. 36 * this address in a different way.
37 */ 37 */
38extern phys_t __weak mips_cpc_phys_base(void); 38extern phys_addr_t __weak mips_cpc_phys_base(void);
39 39
40/** 40/**
41 * mips_cpc_probe - probe for a Cluster Power Controller 41 * mips_cpc_probe - probe for a Cluster Power Controller
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 22a135ac91de..5e4aef304b02 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -653,6 +653,9 @@
653#define MIPS_CONF5_NF (_ULCAST_(1) << 0) 653#define MIPS_CONF5_NF (_ULCAST_(1) << 0)
654#define MIPS_CONF5_UFR (_ULCAST_(1) << 2) 654#define MIPS_CONF5_UFR (_ULCAST_(1) << 2)
655#define MIPS_CONF5_MRP (_ULCAST_(1) << 3) 655#define MIPS_CONF5_MRP (_ULCAST_(1) << 3)
656#define MIPS_CONF5_MVH (_ULCAST_(1) << 5)
657#define MIPS_CONF5_FRE (_ULCAST_(1) << 8)
658#define MIPS_CONF5_UFE (_ULCAST_(1) << 9)
656#define MIPS_CONF5_MSAEN (_ULCAST_(1) << 27) 659#define MIPS_CONF5_MSAEN (_ULCAST_(1) << 27)
657#define MIPS_CONF5_EVA (_ULCAST_(1) << 28) 660#define MIPS_CONF5_EVA (_ULCAST_(1) << 28)
658#define MIPS_CONF5_CV (_ULCAST_(1) << 29) 661#define MIPS_CONF5_CV (_ULCAST_(1) << 29)
@@ -694,6 +697,7 @@
694#define MIPS_FPIR_W (_ULCAST_(1) << 20) 697#define MIPS_FPIR_W (_ULCAST_(1) << 20)
695#define MIPS_FPIR_L (_ULCAST_(1) << 21) 698#define MIPS_FPIR_L (_ULCAST_(1) << 21)
696#define MIPS_FPIR_F64 (_ULCAST_(1) << 22) 699#define MIPS_FPIR_F64 (_ULCAST_(1) << 22)
700#define MIPS_FPIR_FREP (_ULCAST_(1) << 29)
697 701
698/* 702/*
699 * Bits in the MIPS32 Memory Segmentation registers. 703 * Bits in the MIPS32 Memory Segmentation registers.
@@ -994,6 +998,39 @@ do { \
994 local_irq_restore(__flags); \ 998 local_irq_restore(__flags); \
995} while (0) 999} while (0)
996 1000
1001#define __readx_32bit_c0_register(source) \
1002({ \
1003 unsigned int __res; \
1004 \
1005 __asm__ __volatile__( \
1006 " .set push \n" \
1007 " .set noat \n" \
1008 " .set mips32r2 \n" \
1009 " .insn \n" \
1010 " # mfhc0 $1, %1 \n" \
1011 " .word (0x40410000 | ((%1 & 0x1f) << 11)) \n" \
1012 " move %0, $1 \n" \
1013 " .set pop \n" \
1014 : "=r" (__res) \
1015 : "i" (source)); \
1016 __res; \
1017})
1018
1019#define __writex_32bit_c0_register(register, value) \
1020do { \
1021 __asm__ __volatile__( \
1022 " .set push \n" \
1023 " .set noat \n" \
1024 " .set mips32r2 \n" \
1025 " move $1, %0 \n" \
1026 " # mthc0 $1, %1 \n" \
1027 " .insn \n" \
1028 " .word (0x40c10000 | ((%1 & 0x1f) << 11)) \n" \
1029 " .set pop \n" \
1030 : \
1031 : "r" (value), "i" (register)); \
1032} while (0)
1033
997#define read_c0_index() __read_32bit_c0_register($0, 0) 1034#define read_c0_index() __read_32bit_c0_register($0, 0)
998#define write_c0_index(val) __write_32bit_c0_register($0, 0, val) 1035#define write_c0_index(val) __write_32bit_c0_register($0, 0, val)
999 1036
@@ -1003,9 +1040,15 @@ do { \
1003#define read_c0_entrylo0() __read_ulong_c0_register($2, 0) 1040#define read_c0_entrylo0() __read_ulong_c0_register($2, 0)
1004#define write_c0_entrylo0(val) __write_ulong_c0_register($2, 0, val) 1041#define write_c0_entrylo0(val) __write_ulong_c0_register($2, 0, val)
1005 1042
1043#define readx_c0_entrylo0() __readx_32bit_c0_register(2)
1044#define writex_c0_entrylo0(val) __writex_32bit_c0_register(2, val)
1045
1006#define read_c0_entrylo1() __read_ulong_c0_register($3, 0) 1046#define read_c0_entrylo1() __read_ulong_c0_register($3, 0)
1007#define write_c0_entrylo1(val) __write_ulong_c0_register($3, 0, val) 1047#define write_c0_entrylo1(val) __write_ulong_c0_register($3, 0, val)
1008 1048
1049#define readx_c0_entrylo1() __readx_32bit_c0_register(3)
1050#define writex_c0_entrylo1(val) __writex_32bit_c0_register(3, val)
1051
1009#define read_c0_conf() __read_32bit_c0_register($3, 0) 1052#define read_c0_conf() __read_32bit_c0_register($3, 0)
1010#define write_c0_conf(val) __write_32bit_c0_register($3, 0, val) 1053#define write_c0_conf(val) __write_32bit_c0_register($3, 0, val)
1011 1054
diff --git a/arch/mips/include/asm/octeon/cvmx-cmd-queue.h b/arch/mips/include/asm/octeon/cvmx-cmd-queue.h
index 024a71b2bff9..75739c83f07e 100644
--- a/arch/mips/include/asm/octeon/cvmx-cmd-queue.h
+++ b/arch/mips/include/asm/octeon/cvmx-cmd-queue.h
@@ -76,6 +76,8 @@
76 76
77#include <linux/prefetch.h> 77#include <linux/prefetch.h>
78 78
79#include <asm/compiler.h>
80
79#include <asm/octeon/cvmx-fpa.h> 81#include <asm/octeon/cvmx-fpa.h>
80/** 82/**
81 * By default we disable the max depth support. Most programs 83 * By default we disable the max depth support. Most programs
@@ -273,7 +275,7 @@ static inline void __cvmx_cmd_queue_lock(cvmx_cmd_queue_id_t queue_id,
273 " lbu %[ticket], %[now_serving]\n" 275 " lbu %[ticket], %[now_serving]\n"
274 "4:\n" 276 "4:\n"
275 ".set pop\n" : 277 ".set pop\n" :
276 [ticket_ptr] "=m"(__cvmx_cmd_queue_state_ptr->ticket[__cvmx_cmd_queue_get_index(queue_id)]), 278 [ticket_ptr] "=" GCC_OFF12_ASM()(__cvmx_cmd_queue_state_ptr->ticket[__cvmx_cmd_queue_get_index(queue_id)]),
277 [now_serving] "=m"(qptr->now_serving), [ticket] "=r"(tmp), 279 [now_serving] "=m"(qptr->now_serving), [ticket] "=r"(tmp),
278 [my_ticket] "=r"(my_ticket) 280 [my_ticket] "=r"(my_ticket)
279 ); 281 );
diff --git a/arch/mips/include/asm/octeon/cvmx-pow.h b/arch/mips/include/asm/octeon/cvmx-pow.h
index 4b4d0ecfd9eb..2188e65afb86 100644
--- a/arch/mips/include/asm/octeon/cvmx-pow.h
+++ b/arch/mips/include/asm/octeon/cvmx-pow.h
@@ -1066,7 +1066,7 @@ static inline void __cvmx_pow_warn_if_pending_switch(const char *function)
1066 uint64_t switch_complete; 1066 uint64_t switch_complete;
1067 CVMX_MF_CHORD(switch_complete); 1067 CVMX_MF_CHORD(switch_complete);
1068 if (!switch_complete) 1068 if (!switch_complete)
1069 pr_warning("%s called with tag switch in progress\n", function); 1069 pr_warn("%s called with tag switch in progress\n", function);
1070} 1070}
1071 1071
1072/** 1072/**
@@ -1084,8 +1084,7 @@ static inline void cvmx_pow_tag_sw_wait(void)
1084 if (unlikely(switch_complete)) 1084 if (unlikely(switch_complete))
1085 break; 1085 break;
1086 if (unlikely(cvmx_get_cycle() > start_cycle + MAX_CYCLES)) { 1086 if (unlikely(cvmx_get_cycle() > start_cycle + MAX_CYCLES)) {
1087 pr_warning("Tag switch is taking a long time, " 1087 pr_warn("Tag switch is taking a long time, possible deadlock\n");
1088 "possible deadlock\n");
1089 start_cycle = -MAX_CYCLES - 1; 1088 start_cycle = -MAX_CYCLES - 1;
1090 } 1089 }
1091 } 1090 }
@@ -1296,19 +1295,16 @@ static inline void cvmx_pow_tag_sw_nocheck(uint32_t tag,
1296 __cvmx_pow_warn_if_pending_switch(__func__); 1295 __cvmx_pow_warn_if_pending_switch(__func__);
1297 current_tag = cvmx_pow_get_current_tag(); 1296 current_tag = cvmx_pow_get_current_tag();
1298 if (current_tag.s.type == CVMX_POW_TAG_TYPE_NULL_NULL) 1297 if (current_tag.s.type == CVMX_POW_TAG_TYPE_NULL_NULL)
1299 pr_warning("%s called with NULL_NULL tag\n", 1298 pr_warn("%s called with NULL_NULL tag\n", __func__);
1300 __func__);
1301 if (current_tag.s.type == CVMX_POW_TAG_TYPE_NULL) 1299 if (current_tag.s.type == CVMX_POW_TAG_TYPE_NULL)
1302 pr_warning("%s called with NULL tag\n", __func__); 1300 pr_warn("%s called with NULL tag\n", __func__);
1303 if ((current_tag.s.type == tag_type) 1301 if ((current_tag.s.type == tag_type)
1304 && (current_tag.s.tag == tag)) 1302 && (current_tag.s.tag == tag))
1305 pr_warning("%s called to perform a tag switch to the " 1303 pr_warn("%s called to perform a tag switch to the same tag\n",
1306 "same tag\n", 1304 __func__);
1307 __func__);
1308 if (tag_type == CVMX_POW_TAG_TYPE_NULL) 1305 if (tag_type == CVMX_POW_TAG_TYPE_NULL)
1309 pr_warning("%s called to perform a tag switch to " 1306 pr_warn("%s called to perform a tag switch to NULL. Use cvmx_pow_tag_sw_null() instead\n",
1310 "NULL. Use cvmx_pow_tag_sw_null() instead\n", 1307 __func__);
1311 __func__);
1312 } 1308 }
1313 1309
1314 /* 1310 /*
@@ -1407,23 +1403,19 @@ static inline void cvmx_pow_tag_sw_full_nocheck(cvmx_wqe_t *wqp, uint32_t tag,
1407 __cvmx_pow_warn_if_pending_switch(__func__); 1403 __cvmx_pow_warn_if_pending_switch(__func__);
1408 current_tag = cvmx_pow_get_current_tag(); 1404 current_tag = cvmx_pow_get_current_tag();
1409 if (current_tag.s.type == CVMX_POW_TAG_TYPE_NULL_NULL) 1405 if (current_tag.s.type == CVMX_POW_TAG_TYPE_NULL_NULL)
1410 pr_warning("%s called with NULL_NULL tag\n", 1406 pr_warn("%s called with NULL_NULL tag\n", __func__);
1411 __func__);
1412 if ((current_tag.s.type == tag_type) 1407 if ((current_tag.s.type == tag_type)
1413 && (current_tag.s.tag == tag)) 1408 && (current_tag.s.tag == tag))
1414 pr_warning("%s called to perform a tag switch to " 1409 pr_warn("%s called to perform a tag switch to the same tag\n",
1415 "the same tag\n", 1410 __func__);
1416 __func__);
1417 if (tag_type == CVMX_POW_TAG_TYPE_NULL) 1411 if (tag_type == CVMX_POW_TAG_TYPE_NULL)
1418 pr_warning("%s called to perform a tag switch to " 1412 pr_warn("%s called to perform a tag switch to NULL. Use cvmx_pow_tag_sw_null() instead\n",
1419 "NULL. Use cvmx_pow_tag_sw_null() instead\n", 1413 __func__);
1420 __func__);
1421 if (wqp != cvmx_phys_to_ptr(0x80)) 1414 if (wqp != cvmx_phys_to_ptr(0x80))
1422 if (wqp != cvmx_pow_get_current_wqp()) 1415 if (wqp != cvmx_pow_get_current_wqp())
1423 pr_warning("%s passed WQE(%p) doesn't match " 1416 pr_warn("%s passed WQE(%p) doesn't match the address in the POW(%p)\n",
1424 "the address in the POW(%p)\n", 1417 __func__, wqp,
1425 __func__, wqp, 1418 cvmx_pow_get_current_wqp());
1426 cvmx_pow_get_current_wqp());
1427 } 1419 }
1428 1420
1429 /* 1421 /*
@@ -1507,12 +1499,10 @@ static inline void cvmx_pow_tag_sw_null_nocheck(void)
1507 __cvmx_pow_warn_if_pending_switch(__func__); 1499 __cvmx_pow_warn_if_pending_switch(__func__);
1508 current_tag = cvmx_pow_get_current_tag(); 1500 current_tag = cvmx_pow_get_current_tag();
1509 if (current_tag.s.type == CVMX_POW_TAG_TYPE_NULL_NULL) 1501 if (current_tag.s.type == CVMX_POW_TAG_TYPE_NULL_NULL)
1510 pr_warning("%s called with NULL_NULL tag\n", 1502 pr_warn("%s called with NULL_NULL tag\n", __func__);
1511 __func__);
1512 if (current_tag.s.type == CVMX_POW_TAG_TYPE_NULL) 1503 if (current_tag.s.type == CVMX_POW_TAG_TYPE_NULL)
1513 pr_warning("%s called when we already have a " 1504 pr_warn("%s called when we already have a NULL tag\n",
1514 "NULL tag\n", 1505 __func__);
1515 __func__);
1516 } 1506 }
1517 1507
1518 tag_req.u64 = 0; 1508 tag_req.u64 = 0;
@@ -1725,17 +1715,14 @@ static inline void cvmx_pow_tag_sw_desched_nocheck(
1725 __cvmx_pow_warn_if_pending_switch(__func__); 1715 __cvmx_pow_warn_if_pending_switch(__func__);
1726 current_tag = cvmx_pow_get_current_tag(); 1716 current_tag = cvmx_pow_get_current_tag();
1727 if (current_tag.s.type == CVMX_POW_TAG_TYPE_NULL_NULL) 1717 if (current_tag.s.type == CVMX_POW_TAG_TYPE_NULL_NULL)
1728 pr_warning("%s called with NULL_NULL tag\n", 1718 pr_warn("%s called with NULL_NULL tag\n", __func__);
1729 __func__);
1730 if (current_tag.s.type == CVMX_POW_TAG_TYPE_NULL) 1719 if (current_tag.s.type == CVMX_POW_TAG_TYPE_NULL)
1731 pr_warning("%s called with NULL tag. Deschedule not " 1720 pr_warn("%s called with NULL tag. Deschedule not allowed from NULL state\n",
1732 "allowed from NULL state\n", 1721 __func__);
1733 __func__);
1734 if ((current_tag.s.type != CVMX_POW_TAG_TYPE_ATOMIC) 1722 if ((current_tag.s.type != CVMX_POW_TAG_TYPE_ATOMIC)
1735 && (tag_type != CVMX_POW_TAG_TYPE_ATOMIC)) 1723 && (tag_type != CVMX_POW_TAG_TYPE_ATOMIC))
1736 pr_warning("%s called where neither the before or " 1724 pr_warn("%s called where neither the before or after tag is ATOMIC\n",
1737 "after tag is ATOMIC\n", 1725 __func__);
1738 __func__);
1739 } 1726 }
1740 1727
1741 tag_req.u64 = 0; 1728 tag_req.u64 = 0;
@@ -1832,12 +1819,10 @@ static inline void cvmx_pow_desched(uint64_t no_sched)
1832 __cvmx_pow_warn_if_pending_switch(__func__); 1819 __cvmx_pow_warn_if_pending_switch(__func__);
1833 current_tag = cvmx_pow_get_current_tag(); 1820 current_tag = cvmx_pow_get_current_tag();
1834 if (current_tag.s.type == CVMX_POW_TAG_TYPE_NULL_NULL) 1821 if (current_tag.s.type == CVMX_POW_TAG_TYPE_NULL_NULL)
1835 pr_warning("%s called with NULL_NULL tag\n", 1822 pr_warn("%s called with NULL_NULL tag\n", __func__);
1836 __func__);
1837 if (current_tag.s.type == CVMX_POW_TAG_TYPE_NULL) 1823 if (current_tag.s.type == CVMX_POW_TAG_TYPE_NULL)
1838 pr_warning("%s called with NULL tag. Deschedule not " 1824 pr_warn("%s called with NULL tag. Deschedule not expected from NULL state\n",
1839 "expected from NULL state\n", 1825 __func__);
1840 __func__);
1841 } 1826 }
1842 1827
1843 /* Need to make sure any writes to the work queue entry are complete */ 1828 /* Need to make sure any writes to the work queue entry are complete */
diff --git a/arch/mips/include/asm/octeon/cvmx.h b/arch/mips/include/asm/octeon/cvmx.h
index f991e7701d3d..33db1c806b01 100644
--- a/arch/mips/include/asm/octeon/cvmx.h
+++ b/arch/mips/include/asm/octeon/cvmx.h
@@ -451,67 +451,4 @@ static inline uint32_t cvmx_octeon_num_cores(void)
451 return cvmx_pop(ciu_fuse); 451 return cvmx_pop(ciu_fuse);
452} 452}
453 453
454/**
455 * Read a byte of fuse data
456 * @byte_addr: address to read
457 *
458 * Returns fuse value: 0 or 1
459 */
460static uint8_t cvmx_fuse_read_byte(int byte_addr)
461{
462 union cvmx_mio_fus_rcmd read_cmd;
463
464 read_cmd.u64 = 0;
465 read_cmd.s.addr = byte_addr;
466 read_cmd.s.pend = 1;
467 cvmx_write_csr(CVMX_MIO_FUS_RCMD, read_cmd.u64);
468 while ((read_cmd.u64 = cvmx_read_csr(CVMX_MIO_FUS_RCMD))
469 && read_cmd.s.pend)
470 ;
471 return read_cmd.s.dat;
472}
473
474/**
475 * Read a single fuse bit
476 *
477 * @fuse: Fuse number (0-1024)
478 *
479 * Returns fuse value: 0 or 1
480 */
481static inline int cvmx_fuse_read(int fuse)
482{
483 return (cvmx_fuse_read_byte(fuse >> 3) >> (fuse & 0x7)) & 1;
484}
485
486static inline int cvmx_octeon_model_CN36XX(void)
487{
488 return OCTEON_IS_MODEL(OCTEON_CN38XX)
489 && !cvmx_octeon_is_pass1()
490 && cvmx_fuse_read(264);
491}
492
493static inline int cvmx_octeon_zip_present(void)
494{
495 return octeon_has_feature(OCTEON_FEATURE_ZIP);
496}
497
498static inline int cvmx_octeon_dfa_present(void)
499{
500 if (!OCTEON_IS_MODEL(OCTEON_CN38XX)
501 && !OCTEON_IS_MODEL(OCTEON_CN31XX)
502 && !OCTEON_IS_MODEL(OCTEON_CN58XX))
503 return 0;
504 else if (OCTEON_IS_MODEL(OCTEON_CN3020))
505 return 0;
506 else if (cvmx_octeon_is_pass1())
507 return 1;
508 else
509 return !cvmx_fuse_read(120);
510}
511
512static inline int cvmx_octeon_crypto_present(void)
513{
514 return octeon_has_feature(OCTEON_FEATURE_CRYPTO);
515}
516
517#endif /* __CVMX_H__ */ 454#endif /* __CVMX_H__ */
diff --git a/arch/mips/include/asm/octeon/octeon-feature.h b/arch/mips/include/asm/octeon/octeon-feature.h
index 90e05a8d4b15..c4fe81f47f53 100644
--- a/arch/mips/include/asm/octeon/octeon-feature.h
+++ b/arch/mips/include/asm/octeon/octeon-feature.h
@@ -86,8 +86,6 @@ enum octeon_feature {
86 OCTEON_MAX_FEATURE 86 OCTEON_MAX_FEATURE
87}; 87};
88 88
89static inline int cvmx_fuse_read(int fuse);
90
91/** 89/**
92 * Determine if the current Octeon supports a specific feature. These 90 * Determine if the current Octeon supports a specific feature. These
93 * checks have been optimized to be fairly quick, but they should still 91 * checks have been optimized to be fairly quick, but they should still
@@ -105,33 +103,6 @@ static inline int octeon_has_feature(enum octeon_feature feature)
105 case OCTEON_FEATURE_SAAD: 103 case OCTEON_FEATURE_SAAD:
106 return !OCTEON_IS_MODEL(OCTEON_CN3XXX); 104 return !OCTEON_IS_MODEL(OCTEON_CN3XXX);
107 105
108 case OCTEON_FEATURE_ZIP:
109 if (OCTEON_IS_MODEL(OCTEON_CN30XX)
110 || OCTEON_IS_MODEL(OCTEON_CN50XX)
111 || OCTEON_IS_MODEL(OCTEON_CN52XX))
112 return 0;
113 else if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS1))
114 return 1;
115 else
116 return !cvmx_fuse_read(121);
117
118 case OCTEON_FEATURE_CRYPTO:
119 if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) {
120 union cvmx_mio_fus_dat2 fus_2;
121 fus_2.u64 = cvmx_read_csr(CVMX_MIO_FUS_DAT2);
122 if (fus_2.s.nocrypto || fus_2.s.nomul) {
123 return 0;
124 } else if (!fus_2.s.dorm_crypto) {
125 return 1;
126 } else {
127 union cvmx_rnm_ctl_status st;
128 st.u64 = cvmx_read_csr(CVMX_RNM_CTL_STATUS);
129 return st.s.eer_val;
130 }
131 } else {
132 return !cvmx_fuse_read(90);
133 }
134
135 case OCTEON_FEATURE_DORM_CRYPTO: 106 case OCTEON_FEATURE_DORM_CRYPTO:
136 if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) { 107 if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) {
137 union cvmx_mio_fus_dat2 fus_2; 108 union cvmx_mio_fus_dat2 fus_2;
@@ -188,29 +159,6 @@ static inline int octeon_has_feature(enum octeon_feature feature)
188 && !OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X) 159 && !OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X)
189 && !OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X); 160 && !OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X);
190 161
191 case OCTEON_FEATURE_DFA:
192 if (!OCTEON_IS_MODEL(OCTEON_CN38XX)
193 && !OCTEON_IS_MODEL(OCTEON_CN31XX)
194 && !OCTEON_IS_MODEL(OCTEON_CN58XX))
195 return 0;
196 else if (OCTEON_IS_MODEL(OCTEON_CN3020))
197 return 0;
198 else
199 return !cvmx_fuse_read(120);
200
201 case OCTEON_FEATURE_HFA:
202 if (!OCTEON_IS_MODEL(OCTEON_CN6XXX))
203 return 0;
204 else
205 return !cvmx_fuse_read(90);
206
207 case OCTEON_FEATURE_DFM:
208 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)
209 || OCTEON_IS_MODEL(OCTEON_CN66XX)))
210 return 0;
211 else
212 return !cvmx_fuse_read(90);
213
214 case OCTEON_FEATURE_MDIO_CLAUSE_45: 162 case OCTEON_FEATURE_MDIO_CLAUSE_45:
215 return !(OCTEON_IS_MODEL(OCTEON_CN3XXX) 163 return !(OCTEON_IS_MODEL(OCTEON_CN3XXX)
216 || OCTEON_IS_MODEL(OCTEON_CN58XX) 164 || OCTEON_IS_MODEL(OCTEON_CN58XX)
diff --git a/arch/mips/include/asm/octeon/octeon-model.h b/arch/mips/include/asm/octeon/octeon-model.h
index e2c122c6a657..e8a1c2fd52cd 100644
--- a/arch/mips/include/asm/octeon/octeon-model.h
+++ b/arch/mips/include/asm/octeon/octeon-model.h
@@ -326,8 +326,7 @@ static inline int __octeon_is_model_runtime__(uint32_t model)
326#define OCTEON_IS_COMMON_BINARY() 1 326#define OCTEON_IS_COMMON_BINARY() 1
327#undef OCTEON_MODEL 327#undef OCTEON_MODEL
328 328
329const char *octeon_model_get_string(uint32_t chip_id); 329const char *__init octeon_model_get_string(uint32_t chip_id);
330const char *octeon_model_get_string_buffer(uint32_t chip_id, char *buffer);
331 330
332/* 331/*
333 * Return the octeon family, i.e., ProcessorID of the PrID register. 332 * Return the octeon family, i.e., ProcessorID of the PrID register.
diff --git a/arch/mips/include/asm/paccess.h b/arch/mips/include/asm/paccess.h
index 2474fc5d1751..af81ab0da55f 100644
--- a/arch/mips/include/asm/paccess.h
+++ b/arch/mips/include/asm/paccess.h
@@ -56,6 +56,7 @@ struct __large_pstruct { unsigned long buf[100]; };
56 "1:\t" insn "\t%1,%2\n\t" \ 56 "1:\t" insn "\t%1,%2\n\t" \
57 "move\t%0,$0\n" \ 57 "move\t%0,$0\n" \
58 "2:\n\t" \ 58 "2:\n\t" \
59 ".insn\n\t" \
59 ".section\t.fixup,\"ax\"\n" \ 60 ".section\t.fixup,\"ax\"\n" \
60 "3:\tli\t%0,%3\n\t" \ 61 "3:\tli\t%0,%3\n\t" \
61 "move\t%1,$0\n\t" \ 62 "move\t%1,$0\n\t" \
@@ -94,6 +95,7 @@ extern void __get_dbe_unknown(void);
94 "1:\t" insn "\t%1,%2\n\t" \ 95 "1:\t" insn "\t%1,%2\n\t" \
95 "move\t%0,$0\n" \ 96 "move\t%0,$0\n" \
96 "2:\n\t" \ 97 "2:\n\t" \
98 ".insn\n\t" \
97 ".section\t.fixup,\"ax\"\n" \ 99 ".section\t.fixup,\"ax\"\n" \
98 "3:\tli\t%0,%3\n\t" \ 100 "3:\tli\t%0,%3\n\t" \
99 "j\t2b\n\t" \ 101 "j\t2b\n\t" \
diff --git a/arch/mips/include/asm/page.h b/arch/mips/include/asm/page.h
index 3be81803595d..154b70a10483 100644
--- a/arch/mips/include/asm/page.h
+++ b/arch/mips/include/asm/page.h
@@ -116,7 +116,7 @@ extern void copy_user_highpage(struct page *to, struct page *from,
116/* 116/*
117 * These are used to make use of C type-checking.. 117 * These are used to make use of C type-checking..
118 */ 118 */
119#ifdef CONFIG_64BIT_PHYS_ADDR 119#ifdef CONFIG_PHYS_ADDR_T_64BIT
120 #ifdef CONFIG_CPU_MIPS32 120 #ifdef CONFIG_CPU_MIPS32
121 typedef struct { unsigned long pte_low, pte_high; } pte_t; 121 typedef struct { unsigned long pte_low, pte_high; } pte_t;
122 #define pte_val(x) ((x).pte_low | ((unsigned long long)(x).pte_high << 32)) 122 #define pte_val(x) ((x).pte_low | ((unsigned long long)(x).pte_high << 32))
diff --git a/arch/mips/include/asm/pci.h b/arch/mips/include/asm/pci.h
index 974b0e308963..69529624a005 100644
--- a/arch/mips/include/asm/pci.h
+++ b/arch/mips/include/asm/pci.h
@@ -84,7 +84,7 @@ static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
84 const struct resource *rsrc, resource_size_t *start, 84 const struct resource *rsrc, resource_size_t *start,
85 resource_size_t *end) 85 resource_size_t *end)
86{ 86{
87 phys_t size = resource_size(rsrc); 87 phys_addr_t size = resource_size(rsrc);
88 88
89 *start = fixup_bigphys_addr(rsrc->start, size); 89 *start = fixup_bigphys_addr(rsrc->start, size);
90 *end = rsrc->start + size; 90 *end = rsrc->start + size;
diff --git a/arch/mips/include/asm/pgtable-32.h b/arch/mips/include/asm/pgtable-32.h
index cd7d6064bcbe..68984b612f9d 100644
--- a/arch/mips/include/asm/pgtable-32.h
+++ b/arch/mips/include/asm/pgtable-32.h
@@ -69,7 +69,7 @@ extern int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1,
69# define VMALLOC_END (FIXADDR_START-2*PAGE_SIZE) 69# define VMALLOC_END (FIXADDR_START-2*PAGE_SIZE)
70#endif 70#endif
71 71
72#ifdef CONFIG_64BIT_PHYS_ADDR 72#ifdef CONFIG_PHYS_ADDR_T_64BIT
73#define pte_ERROR(e) \ 73#define pte_ERROR(e) \
74 printk("%s:%d: bad pte %016Lx.\n", __FILE__, __LINE__, pte_val(e)) 74 printk("%s:%d: bad pte %016Lx.\n", __FILE__, __LINE__, pte_val(e))
75#else 75#else
@@ -103,7 +103,7 @@ static inline void pmd_clear(pmd_t *pmdp)
103 pmd_val(*pmdp) = ((unsigned long) invalid_pte_table); 103 pmd_val(*pmdp) = ((unsigned long) invalid_pte_table);
104} 104}
105 105
106#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) 106#if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32)
107#define pte_page(x) pfn_to_page(pte_pfn(x)) 107#define pte_page(x) pfn_to_page(pte_pfn(x))
108#define pte_pfn(x) ((unsigned long)((x).pte_high >> 6)) 108#define pte_pfn(x) ((unsigned long)((x).pte_high >> 6))
109static inline pte_t 109static inline pte_t
@@ -126,7 +126,7 @@ pfn_pte(unsigned long pfn, pgprot_t prot)
126#define pte_pfn(x) ((unsigned long)((x).pte >> _PFN_SHIFT)) 126#define pte_pfn(x) ((unsigned long)((x).pte >> _PFN_SHIFT))
127#define pfn_pte(pfn, prot) __pte(((unsigned long long)(pfn) << _PFN_SHIFT) | pgprot_val(prot)) 127#define pfn_pte(pfn, prot) __pte(((unsigned long long)(pfn) << _PFN_SHIFT) | pgprot_val(prot))
128#endif 128#endif
129#endif /* defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) */ 129#endif /* defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32) */
130 130
131#define __pgd_offset(address) pgd_index(address) 131#define __pgd_offset(address) pgd_index(address)
132#define __pud_offset(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1)) 132#define __pud_offset(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1))
@@ -155,73 +155,75 @@ pfn_pte(unsigned long pfn, pgprot_t prot)
155#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) 155#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
156 156
157/* Swap entries must have VALID bit cleared. */ 157/* Swap entries must have VALID bit cleared. */
158#define __swp_type(x) (((x).val >> 10) & 0x1f) 158#define __swp_type(x) (((x).val >> 10) & 0x1f)
159#define __swp_offset(x) ((x).val >> 15) 159#define __swp_offset(x) ((x).val >> 15)
160#define __swp_entry(type,offset) \ 160#define __swp_entry(type,offset) ((swp_entry_t) { ((type) << 10) | ((offset) << 15) })
161 ((swp_entry_t) { ((type) << 10) | ((offset) << 15) }) 161#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
162#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
162 163
163/* 164/*
164 * Bits 0, 4, 8, and 9 are taken, split up 28 bits of offset into this range: 165 * Encode and decode a nonlinear file mapping entry
165 */ 166 */
166#define PTE_FILE_MAX_BITS 28 167#define pte_to_pgoff(_pte) ((((_pte).pte >> 1 ) & 0x07) | \
167 168 (((_pte).pte >> 2 ) & 0x38) | \
168#define pte_to_pgoff(_pte) ((((_pte).pte >> 1 ) & 0x07) | \ 169 (((_pte).pte >> 10) << 6 ))
169 (((_pte).pte >> 2 ) & 0x38) | \
170 (((_pte).pte >> 10) << 6 ))
171 170
172#define pgoff_to_pte(off) ((pte_t) { (((off) & 0x07) << 1 ) | \ 171#define pgoff_to_pte(off) ((pte_t) { (((off) & 0x07) << 1 ) | \
173 (((off) & 0x38) << 2 ) | \ 172 (((off) & 0x38) << 2 ) | \
174 (((off) >> 6 ) << 10) | \ 173 (((off) >> 6 ) << 10) | \
175 _PAGE_FILE }) 174 _PAGE_FILE })
176 175
176/*
177 * Bits 0, 4, 8, and 9 are taken, split up 28 bits of offset into this range:
178 */
179#define PTE_FILE_MAX_BITS 28
177#else 180#else
178 181
182#if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32)
183
179/* Swap entries must have VALID and GLOBAL bits cleared. */ 184/* Swap entries must have VALID and GLOBAL bits cleared. */
180#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) 185#define __swp_type(x) (((x).val >> 2) & 0x1f)
181#define __swp_type(x) (((x).val >> 2) & 0x1f) 186#define __swp_offset(x) ((x).val >> 7)
182#define __swp_offset(x) ((x).val >> 7) 187#define __swp_entry(type,offset) ((swp_entry_t) { ((type) << 2) | ((offset) << 7) })
183#define __swp_entry(type,offset) \ 188#define __pte_to_swp_entry(pte) ((swp_entry_t) { (pte).pte_high })
184 ((swp_entry_t) { ((type) << 2) | ((offset) << 7) }) 189#define __swp_entry_to_pte(x) ((pte_t) { 0, (x).val })
185#else
186#define __swp_type(x) (((x).val >> 8) & 0x1f)
187#define __swp_offset(x) ((x).val >> 13)
188#define __swp_entry(type,offset) \
189 ((swp_entry_t) { ((type) << 8) | ((offset) << 13) })
190#endif /* defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) */
191 190
192#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
193/* 191/*
194 * Bits 0 and 1 of pte_high are taken, use the rest for the page offset... 192 * Bits 0 and 1 of pte_high are taken, use the rest for the page offset...
195 */ 193 */
196#define PTE_FILE_MAX_BITS 30 194#define pte_to_pgoff(_pte) ((_pte).pte_high >> 2)
197 195#define pgoff_to_pte(off) ((pte_t) { _PAGE_FILE, (off) << 2 })
198#define pte_to_pgoff(_pte) ((_pte).pte_high >> 2)
199#define pgoff_to_pte(off) ((pte_t) { _PAGE_FILE, (off) << 2 })
200 196
197#define PTE_FILE_MAX_BITS 30
201#else 198#else
202/* 199/*
203 * Bits 0, 4, 6, and 7 are taken, split up 28 bits of offset into this range: 200 * Constraints:
201 * _PAGE_PRESENT at bit 0
202 * _PAGE_MODIFIED at bit 4
203 * _PAGE_GLOBAL at bit 6
204 * _PAGE_VALID at bit 7
204 */ 205 */
205#define PTE_FILE_MAX_BITS 28 206#define __swp_type(x) (((x).val >> 8) & 0x1f)
207#define __swp_offset(x) ((x).val >> 13)
208#define __swp_entry(type,offset) ((swp_entry_t) { ((type) << 8) | ((offset) << 13) })
209#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
210#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
206 211
207#define pte_to_pgoff(_pte) ((((_pte).pte >> 1) & 0x7) | \ 212/*
208 (((_pte).pte >> 2) & 0x8) | \ 213 * Encode and decode a nonlinear file mapping entry
209 (((_pte).pte >> 8) << 4)) 214 */
215#define pte_to_pgoff(_pte) ((((_pte).pte >> 1) & 0x7) | \
216 (((_pte).pte >> 2) & 0x8) | \
217 (((_pte).pte >> 8) << 4))
210 218
211#define pgoff_to_pte(off) ((pte_t) { (((off) & 0x7) << 1) | \ 219#define pgoff_to_pte(off) ((pte_t) { (((off) & 0x7) << 1) | \
212 (((off) & 0x8) << 2) | \ 220 (((off) & 0x8) << 2) | \
213 (((off) >> 4) << 8) | \ 221 (((off) >> 4) << 8) | \
214 _PAGE_FILE }) 222 _PAGE_FILE })
215#endif
216 223
217#endif 224#define PTE_FILE_MAX_BITS 28
225#endif /* defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32) */
218 226
219#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) 227#endif /* defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) */
220#define __pte_to_swp_entry(pte) ((swp_entry_t) { (pte).pte_high })
221#define __swp_entry_to_pte(x) ((pte_t) { 0, (x).val })
222#else
223#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
224#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
225#endif
226 228
227#endif /* _ASM_PGTABLE_32_H */ 229#endif /* _ASM_PGTABLE_32_H */
diff --git a/arch/mips/include/asm/pgtable-bits.h b/arch/mips/include/asm/pgtable-bits.h
index e747bfa0be7e..ca11f14f40a3 100644
--- a/arch/mips/include/asm/pgtable-bits.h
+++ b/arch/mips/include/asm/pgtable-bits.h
@@ -32,39 +32,41 @@
32 * unpredictable things. The code (when it is written) to deal with 32 * unpredictable things. The code (when it is written) to deal with
33 * this problem will be in the update_mmu_cache() code for the r4k. 33 * this problem will be in the update_mmu_cache() code for the r4k.
34 */ 34 */
35#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) 35#if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32)
36 36
37/* 37/*
38 * The following bits are directly used by the TLB hardware 38 * The following bits are directly used by the TLB hardware
39 */ 39 */
40#define _PAGE_R4KBUG (1 << 0) /* workaround for r4k bug */ 40#define _PAGE_GLOBAL_SHIFT 0
41#define _PAGE_GLOBAL (1 << 0) 41#define _PAGE_GLOBAL (1 << _PAGE_GLOBAL_SHIFT)
42#define _PAGE_VALID_SHIFT 1 42#define _PAGE_VALID_SHIFT (_PAGE_GLOBAL_SHIFT + 1)
43#define _PAGE_VALID (1 << _PAGE_VALID_SHIFT) 43#define _PAGE_VALID (1 << _PAGE_VALID_SHIFT)
44#define _PAGE_SILENT_READ (1 << 1) /* synonym */ 44#define _PAGE_DIRTY_SHIFT (_PAGE_VALID_SHIFT + 1)
45#define _PAGE_DIRTY_SHIFT 2 45#define _PAGE_DIRTY (1 << _PAGE_DIRTY_SHIFT)
46#define _PAGE_DIRTY (1 << _PAGE_DIRTY_SHIFT) /* The MIPS dirty bit */ 46#define _CACHE_SHIFT (_PAGE_DIRTY_SHIFT + 1)
47#define _PAGE_SILENT_WRITE (1 << 2) 47#define _CACHE_MASK (7 << _CACHE_SHIFT)
48#define _CACHE_SHIFT 3
49#define _CACHE_MASK (7 << 3)
50 48
51/* 49/*
52 * The following bits are implemented in software 50 * The following bits are implemented in software
53 * 51 *
54 * _PAGE_FILE semantics: set:pagecache unset:swap 52 * _PAGE_FILE semantics: set:pagecache unset:swap
55 */ 53 */
56#define _PAGE_PRESENT_SHIFT 6 54#define _PAGE_PRESENT_SHIFT (_CACHE_SHIFT + 3)
57#define _PAGE_PRESENT (1 << _PAGE_PRESENT_SHIFT) 55#define _PAGE_PRESENT (1 << _PAGE_PRESENT_SHIFT)
58#define _PAGE_READ_SHIFT 7 56#define _PAGE_READ_SHIFT (_PAGE_PRESENT_SHIFT + 1)
59#define _PAGE_READ (1 << _PAGE_READ_SHIFT) 57#define _PAGE_READ (1 << _PAGE_READ_SHIFT)
60#define _PAGE_WRITE_SHIFT 8 58#define _PAGE_WRITE_SHIFT (_PAGE_READ_SHIFT + 1)
61#define _PAGE_WRITE (1 << _PAGE_WRITE_SHIFT) 59#define _PAGE_WRITE (1 << _PAGE_WRITE_SHIFT)
62#define _PAGE_ACCESSED_SHIFT 9 60#define _PAGE_ACCESSED_SHIFT (_PAGE_WRITE_SHIFT + 1)
63#define _PAGE_ACCESSED (1 << _PAGE_ACCESSED_SHIFT) 61#define _PAGE_ACCESSED (1 << _PAGE_ACCESSED_SHIFT)
64#define _PAGE_MODIFIED_SHIFT 10 62#define _PAGE_MODIFIED_SHIFT (_PAGE_ACCESSED_SHIFT + 1)
65#define _PAGE_MODIFIED (1 << _PAGE_MODIFIED_SHIFT) 63#define _PAGE_MODIFIED (1 << _PAGE_MODIFIED_SHIFT)
66 64
67#define _PAGE_FILE (1 << 10) 65#define _PAGE_SILENT_READ _PAGE_VALID
66#define _PAGE_SILENT_WRITE _PAGE_DIRTY
67#define _PAGE_FILE _PAGE_MODIFIED
68
69#define _PFN_SHIFT (PAGE_SHIFT - 12 + _CACHE_SHIFT + 3)
68 70
69#elif defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) 71#elif defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
70 72
@@ -172,7 +174,7 @@
172 174
173#define _PFN_SHIFT (PAGE_SHIFT - 12 + _CACHE_SHIFT + 3) 175#define _PFN_SHIFT (PAGE_SHIFT - 12 + _CACHE_SHIFT + 3)
174 176
175#endif /* defined(CONFIG_64BIT_PHYS_ADDR && defined(CONFIG_CPU_MIPS32) */ 177#endif /* defined(CONFIG_PHYS_ADDR_T_64BIT && defined(CONFIG_CPU_MIPS32) */
176 178
177#ifndef _PFN_SHIFT 179#ifndef _PFN_SHIFT
178#define _PFN_SHIFT PAGE_SHIFT 180#define _PFN_SHIFT PAGE_SHIFT
diff --git a/arch/mips/include/asm/pgtable.h b/arch/mips/include/asm/pgtable.h
index d6d1928539b1..62a6ba383d4f 100644
--- a/arch/mips/include/asm/pgtable.h
+++ b/arch/mips/include/asm/pgtable.h
@@ -125,7 +125,7 @@ do { \
125extern void set_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *ptep, 125extern void set_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *ptep,
126 pte_t pteval); 126 pte_t pteval);
127 127
128#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) 128#if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32)
129 129
130#define pte_none(pte) (!(((pte).pte_low | (pte).pte_high) & ~_PAGE_GLOBAL)) 130#define pte_none(pte) (!(((pte).pte_low | (pte).pte_high) & ~_PAGE_GLOBAL))
131#define pte_present(pte) ((pte).pte_low & _PAGE_PRESENT) 131#define pte_present(pte) ((pte).pte_low & _PAGE_PRESENT)
@@ -227,7 +227,7 @@ extern pgd_t swapper_pg_dir[];
227 * The following only work if pte_present() is true. 227 * The following only work if pte_present() is true.
228 * Undefined behaviour if not.. 228 * Undefined behaviour if not..
229 */ 229 */
230#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) 230#if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32)
231static inline int pte_write(pte_t pte) { return pte.pte_low & _PAGE_WRITE; } 231static inline int pte_write(pte_t pte) { return pte.pte_low & _PAGE_WRITE; }
232static inline int pte_dirty(pte_t pte) { return pte.pte_low & _PAGE_MODIFIED; } 232static inline int pte_dirty(pte_t pte) { return pte.pte_low & _PAGE_MODIFIED; }
233static inline int pte_young(pte_t pte) { return pte.pte_low & _PAGE_ACCESSED; } 233static inline int pte_young(pte_t pte) { return pte.pte_low & _PAGE_ACCESSED; }
@@ -297,13 +297,13 @@ static inline pte_t pte_wrprotect(pte_t pte)
297 297
298static inline pte_t pte_mkclean(pte_t pte) 298static inline pte_t pte_mkclean(pte_t pte)
299{ 299{
300 pte_val(pte) &= ~(_PAGE_MODIFIED|_PAGE_SILENT_WRITE); 300 pte_val(pte) &= ~(_PAGE_MODIFIED | _PAGE_SILENT_WRITE);
301 return pte; 301 return pte;
302} 302}
303 303
304static inline pte_t pte_mkold(pte_t pte) 304static inline pte_t pte_mkold(pte_t pte)
305{ 305{
306 pte_val(pte) &= ~(_PAGE_ACCESSED|_PAGE_SILENT_READ); 306 pte_val(pte) &= ~(_PAGE_ACCESSED | _PAGE_SILENT_READ);
307 return pte; 307 return pte;
308} 308}
309 309
@@ -382,13 +382,13 @@ static inline pgprot_t pgprot_writecombine(pgprot_t _prot)
382 */ 382 */
383#define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot)) 383#define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot))
384 384
385#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) 385#if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32)
386static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 386static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
387{ 387{
388 pte.pte_low &= _PAGE_CHG_MASK; 388 pte.pte_low &= _PAGE_CHG_MASK;
389 pte.pte_high &= ~0x3f; 389 pte.pte_high &= (_PFN_MASK | _CACHE_MASK);
390 pte.pte_low |= pgprot_val(newprot); 390 pte.pte_low |= pgprot_val(newprot);
391 pte.pte_high |= pgprot_val(newprot) & 0x3f; 391 pte.pte_high |= pgprot_val(newprot) & ~(_PFN_MASK | _CACHE_MASK);
392 return pte; 392 return pte;
393} 393}
394#else 394#else
@@ -419,7 +419,7 @@ static inline void update_mmu_cache_pmd(struct vm_area_struct *vma,
419 419
420#define kern_addr_valid(addr) (1) 420#define kern_addr_valid(addr) (1)
421 421
422#ifdef CONFIG_64BIT_PHYS_ADDR 422#ifdef CONFIG_PHYS_ADDR_T_64BIT
423extern int remap_pfn_range(struct vm_area_struct *vma, unsigned long from, unsigned long pfn, unsigned long size, pgprot_t prot); 423extern int remap_pfn_range(struct vm_area_struct *vma, unsigned long from, unsigned long pfn, unsigned long size, pgprot_t prot);
424 424
425static inline int io_remap_pfn_range(struct vm_area_struct *vma, 425static inline int io_remap_pfn_range(struct vm_area_struct *vma,
@@ -428,7 +428,7 @@ static inline int io_remap_pfn_range(struct vm_area_struct *vma,
428 unsigned long size, 428 unsigned long size,
429 pgprot_t prot) 429 pgprot_t prot)
430{ 430{
431 phys_t phys_addr_high = fixup_bigphys_addr(pfn << PAGE_SHIFT, size); 431 phys_addr_t phys_addr_high = fixup_bigphys_addr(pfn << PAGE_SHIFT, size);
432 return remap_pfn_range(vma, vaddr, phys_addr_high >> PAGE_SHIFT, size, prot); 432 return remap_pfn_range(vma, vaddr, phys_addr_high >> PAGE_SHIFT, size, prot);
433} 433}
434#define io_remap_pfn_range io_remap_pfn_range 434#define io_remap_pfn_range io_remap_pfn_range
diff --git a/arch/mips/include/asm/prom.h b/arch/mips/include/asm/prom.h
index a9494c0141fb..eaa26270a5e5 100644
--- a/arch/mips/include/asm/prom.h
+++ b/arch/mips/include/asm/prom.h
@@ -22,6 +22,7 @@ extern void device_tree_init(void);
22struct boot_param_header; 22struct boot_param_header;
23 23
24extern void __dt_setup_arch(void *bph); 24extern void __dt_setup_arch(void *bph);
25extern int __dt_register_buses(const char *bus0, const char *bus1);
25 26
26#define dt_setup_arch(sym) \ 27#define dt_setup_arch(sym) \
27({ \ 28({ \
diff --git a/arch/mips/include/asm/r4kcache.h b/arch/mips/include/asm/r4kcache.h
index cd6e0afc6833..e293a8d89a6d 100644
--- a/arch/mips/include/asm/r4kcache.h
+++ b/arch/mips/include/asm/r4kcache.h
@@ -47,79 +47,20 @@ extern void (*r4k_blast_icache)(void);
47 47
48#ifdef CONFIG_MIPS_MT 48#ifdef CONFIG_MIPS_MT
49 49
50/*
51 * Optionally force single-threaded execution during I-cache flushes.
52 */
53#define PROTECT_CACHE_FLUSHES 1
54
55#ifdef PROTECT_CACHE_FLUSHES
56
57extern int mt_protiflush;
58extern int mt_protdflush;
59extern void mt_cflush_lockdown(void);
60extern void mt_cflush_release(void);
61
62#define BEGIN_MT_IPROT \
63 unsigned long flags = 0; \
64 unsigned long mtflags = 0; \
65 if(mt_protiflush) { \
66 local_irq_save(flags); \
67 ehb(); \
68 mtflags = dvpe(); \
69 mt_cflush_lockdown(); \
70 }
71
72#define END_MT_IPROT \
73 if(mt_protiflush) { \
74 mt_cflush_release(); \
75 evpe(mtflags); \
76 local_irq_restore(flags); \
77 }
78
79#define BEGIN_MT_DPROT \
80 unsigned long flags = 0; \
81 unsigned long mtflags = 0; \
82 if(mt_protdflush) { \
83 local_irq_save(flags); \
84 ehb(); \
85 mtflags = dvpe(); \
86 mt_cflush_lockdown(); \
87 }
88
89#define END_MT_DPROT \
90 if(mt_protdflush) { \
91 mt_cflush_release(); \
92 evpe(mtflags); \
93 local_irq_restore(flags); \
94 }
95
96#else
97
98#define BEGIN_MT_IPROT
99#define BEGIN_MT_DPROT
100#define END_MT_IPROT
101#define END_MT_DPROT
102
103#endif /* PROTECT_CACHE_FLUSHES */
104
105#define __iflush_prologue \ 50#define __iflush_prologue \
106 unsigned long redundance; \ 51 unsigned long redundance; \
107 extern int mt_n_iflushes; \ 52 extern int mt_n_iflushes; \
108 BEGIN_MT_IPROT \
109 for (redundance = 0; redundance < mt_n_iflushes; redundance++) { 53 for (redundance = 0; redundance < mt_n_iflushes; redundance++) {
110 54
111#define __iflush_epilogue \ 55#define __iflush_epilogue \
112 END_MT_IPROT \
113 } 56 }
114 57
115#define __dflush_prologue \ 58#define __dflush_prologue \
116 unsigned long redundance; \ 59 unsigned long redundance; \
117 extern int mt_n_dflushes; \ 60 extern int mt_n_dflushes; \
118 BEGIN_MT_DPROT \
119 for (redundance = 0; redundance < mt_n_dflushes; redundance++) { 61 for (redundance = 0; redundance < mt_n_dflushes; redundance++) {
120 62
121#define __dflush_epilogue \ 63#define __dflush_epilogue \
122 END_MT_DPROT \
123 } 64 }
124 65
125#define __inv_dflush_prologue __dflush_prologue 66#define __inv_dflush_prologue __dflush_prologue
diff --git a/arch/mips/include/asm/spinlock.h b/arch/mips/include/asm/spinlock.h
index 78d201fb6c87..c6d06d383ef9 100644
--- a/arch/mips/include/asm/spinlock.h
+++ b/arch/mips/include/asm/spinlock.h
@@ -12,6 +12,7 @@
12#include <linux/compiler.h> 12#include <linux/compiler.h>
13 13
14#include <asm/barrier.h> 14#include <asm/barrier.h>
15#include <asm/compiler.h>
15#include <asm/war.h> 16#include <asm/war.h>
16 17
17/* 18/*
@@ -88,7 +89,7 @@ static inline void arch_spin_lock(arch_spinlock_t *lock)
88 " subu %[ticket], %[ticket], 1 \n" 89 " subu %[ticket], %[ticket], 1 \n"
89 " .previous \n" 90 " .previous \n"
90 " .set pop \n" 91 " .set pop \n"
91 : [ticket_ptr] "+m" (lock->lock), 92 : [ticket_ptr] "+" GCC_OFF12_ASM() (lock->lock),
92 [serving_now_ptr] "+m" (lock->h.serving_now), 93 [serving_now_ptr] "+m" (lock->h.serving_now),
93 [ticket] "=&r" (tmp), 94 [ticket] "=&r" (tmp),
94 [my_ticket] "=&r" (my_ticket) 95 [my_ticket] "=&r" (my_ticket)
@@ -121,7 +122,7 @@ static inline void arch_spin_lock(arch_spinlock_t *lock)
121 " subu %[ticket], %[ticket], 1 \n" 122 " subu %[ticket], %[ticket], 1 \n"
122 " .previous \n" 123 " .previous \n"
123 " .set pop \n" 124 " .set pop \n"
124 : [ticket_ptr] "+m" (lock->lock), 125 : [ticket_ptr] "+" GCC_OFF12_ASM() (lock->lock),
125 [serving_now_ptr] "+m" (lock->h.serving_now), 126 [serving_now_ptr] "+m" (lock->h.serving_now),
126 [ticket] "=&r" (tmp), 127 [ticket] "=&r" (tmp),
127 [my_ticket] "=&r" (my_ticket) 128 [my_ticket] "=&r" (my_ticket)
@@ -163,7 +164,7 @@ static inline unsigned int arch_spin_trylock(arch_spinlock_t *lock)
163 " li %[ticket], 0 \n" 164 " li %[ticket], 0 \n"
164 " .previous \n" 165 " .previous \n"
165 " .set pop \n" 166 " .set pop \n"
166 : [ticket_ptr] "+m" (lock->lock), 167 : [ticket_ptr] "+" GCC_OFF12_ASM() (lock->lock),
167 [ticket] "=&r" (tmp), 168 [ticket] "=&r" (tmp),
168 [my_ticket] "=&r" (tmp2), 169 [my_ticket] "=&r" (tmp2),
169 [now_serving] "=&r" (tmp3) 170 [now_serving] "=&r" (tmp3)
@@ -187,7 +188,7 @@ static inline unsigned int arch_spin_trylock(arch_spinlock_t *lock)
187 " li %[ticket], 0 \n" 188 " li %[ticket], 0 \n"
188 " .previous \n" 189 " .previous \n"
189 " .set pop \n" 190 " .set pop \n"
190 : [ticket_ptr] "+m" (lock->lock), 191 : [ticket_ptr] "+" GCC_OFF12_ASM() (lock->lock),
191 [ticket] "=&r" (tmp), 192 [ticket] "=&r" (tmp),
192 [my_ticket] "=&r" (tmp2), 193 [my_ticket] "=&r" (tmp2),
193 [now_serving] "=&r" (tmp3) 194 [now_serving] "=&r" (tmp3)
@@ -234,8 +235,8 @@ static inline void arch_read_lock(arch_rwlock_t *rw)
234 " beqzl %1, 1b \n" 235 " beqzl %1, 1b \n"
235 " nop \n" 236 " nop \n"
236 " .set reorder \n" 237 " .set reorder \n"
237 : "=m" (rw->lock), "=&r" (tmp) 238 : "=" GCC_OFF12_ASM() (rw->lock), "=&r" (tmp)
238 : "m" (rw->lock) 239 : GCC_OFF12_ASM() (rw->lock)
239 : "memory"); 240 : "memory");
240 } else { 241 } else {
241 do { 242 do {
@@ -244,8 +245,8 @@ static inline void arch_read_lock(arch_rwlock_t *rw)
244 " bltz %1, 1b \n" 245 " bltz %1, 1b \n"
245 " addu %1, 1 \n" 246 " addu %1, 1 \n"
246 "2: sc %1, %0 \n" 247 "2: sc %1, %0 \n"
247 : "=m" (rw->lock), "=&r" (tmp) 248 : "=" GCC_OFF12_ASM() (rw->lock), "=&r" (tmp)
248 : "m" (rw->lock) 249 : GCC_OFF12_ASM() (rw->lock)
249 : "memory"); 250 : "memory");
250 } while (unlikely(!tmp)); 251 } while (unlikely(!tmp));
251 } 252 }
@@ -268,8 +269,8 @@ static inline void arch_read_unlock(arch_rwlock_t *rw)
268 " sub %1, 1 \n" 269 " sub %1, 1 \n"
269 " sc %1, %0 \n" 270 " sc %1, %0 \n"
270 " beqzl %1, 1b \n" 271 " beqzl %1, 1b \n"
271 : "=m" (rw->lock), "=&r" (tmp) 272 : "=" GCC_OFF12_ASM() (rw->lock), "=&r" (tmp)
272 : "m" (rw->lock) 273 : GCC_OFF12_ASM() (rw->lock)
273 : "memory"); 274 : "memory");
274 } else { 275 } else {
275 do { 276 do {
@@ -277,8 +278,8 @@ static inline void arch_read_unlock(arch_rwlock_t *rw)
277 "1: ll %1, %2 # arch_read_unlock \n" 278 "1: ll %1, %2 # arch_read_unlock \n"
278 " sub %1, 1 \n" 279 " sub %1, 1 \n"
279 " sc %1, %0 \n" 280 " sc %1, %0 \n"
280 : "=m" (rw->lock), "=&r" (tmp) 281 : "=" GCC_OFF12_ASM() (rw->lock), "=&r" (tmp)
281 : "m" (rw->lock) 282 : GCC_OFF12_ASM() (rw->lock)
282 : "memory"); 283 : "memory");
283 } while (unlikely(!tmp)); 284 } while (unlikely(!tmp));
284 } 285 }
@@ -298,8 +299,8 @@ static inline void arch_write_lock(arch_rwlock_t *rw)
298 " beqzl %1, 1b \n" 299 " beqzl %1, 1b \n"
299 " nop \n" 300 " nop \n"
300 " .set reorder \n" 301 " .set reorder \n"
301 : "=m" (rw->lock), "=&r" (tmp) 302 : "=" GCC_OFF12_ASM() (rw->lock), "=&r" (tmp)
302 : "m" (rw->lock) 303 : GCC_OFF12_ASM() (rw->lock)
303 : "memory"); 304 : "memory");
304 } else { 305 } else {
305 do { 306 do {
@@ -308,8 +309,8 @@ static inline void arch_write_lock(arch_rwlock_t *rw)
308 " bnez %1, 1b \n" 309 " bnez %1, 1b \n"
309 " lui %1, 0x8000 \n" 310 " lui %1, 0x8000 \n"
310 "2: sc %1, %0 \n" 311 "2: sc %1, %0 \n"
311 : "=m" (rw->lock), "=&r" (tmp) 312 : "=" GCC_OFF12_ASM() (rw->lock), "=&r" (tmp)
312 : "m" (rw->lock) 313 : GCC_OFF12_ASM() (rw->lock)
313 : "memory"); 314 : "memory");
314 } while (unlikely(!tmp)); 315 } while (unlikely(!tmp));
315 } 316 }
@@ -348,8 +349,8 @@ static inline int arch_read_trylock(arch_rwlock_t *rw)
348 __WEAK_LLSC_MB 349 __WEAK_LLSC_MB
349 " li %2, 1 \n" 350 " li %2, 1 \n"
350 "2: \n" 351 "2: \n"
351 : "=m" (rw->lock), "=&r" (tmp), "=&r" (ret) 352 : "=" GCC_OFF12_ASM() (rw->lock), "=&r" (tmp), "=&r" (ret)
352 : "m" (rw->lock) 353 : GCC_OFF12_ASM() (rw->lock)
353 : "memory"); 354 : "memory");
354 } else { 355 } else {
355 __asm__ __volatile__( 356 __asm__ __volatile__(
@@ -365,8 +366,8 @@ static inline int arch_read_trylock(arch_rwlock_t *rw)
365 __WEAK_LLSC_MB 366 __WEAK_LLSC_MB
366 " li %2, 1 \n" 367 " li %2, 1 \n"
367 "2: \n" 368 "2: \n"
368 : "=m" (rw->lock), "=&r" (tmp), "=&r" (ret) 369 : "=" GCC_OFF12_ASM() (rw->lock), "=&r" (tmp), "=&r" (ret)
369 : "m" (rw->lock) 370 : GCC_OFF12_ASM() (rw->lock)
370 : "memory"); 371 : "memory");
371 } 372 }
372 373
@@ -392,8 +393,8 @@ static inline int arch_write_trylock(arch_rwlock_t *rw)
392 " li %2, 1 \n" 393 " li %2, 1 \n"
393 " .set reorder \n" 394 " .set reorder \n"
394 "2: \n" 395 "2: \n"
395 : "=m" (rw->lock), "=&r" (tmp), "=&r" (ret) 396 : "=" GCC_OFF12_ASM() (rw->lock), "=&r" (tmp), "=&r" (ret)
396 : "m" (rw->lock) 397 : GCC_OFF12_ASM() (rw->lock)
397 : "memory"); 398 : "memory");
398 } else { 399 } else {
399 do { 400 do {
@@ -405,8 +406,9 @@ static inline int arch_write_trylock(arch_rwlock_t *rw)
405 " sc %1, %0 \n" 406 " sc %1, %0 \n"
406 " li %2, 1 \n" 407 " li %2, 1 \n"
407 "2: \n" 408 "2: \n"
408 : "=m" (rw->lock), "=&r" (tmp), "=&r" (ret) 409 : "=" GCC_OFF12_ASM() (rw->lock), "=&r" (tmp),
409 : "m" (rw->lock) 410 "=&r" (ret)
411 : GCC_OFF12_ASM() (rw->lock)
410 : "memory"); 412 : "memory");
411 } while (unlikely(!tmp)); 413 } while (unlikely(!tmp));
412 414
diff --git a/arch/mips/include/asm/thread_info.h b/arch/mips/include/asm/thread_info.h
index 7de865805deb..99eea59604e9 100644
--- a/arch/mips/include/asm/thread_info.h
+++ b/arch/mips/include/asm/thread_info.h
@@ -116,6 +116,7 @@ static inline struct thread_info *current_thread_info(void)
116#define TIF_LOAD_WATCH 25 /* If set, load watch registers */ 116#define TIF_LOAD_WATCH 25 /* If set, load watch registers */
117#define TIF_SYSCALL_TRACEPOINT 26 /* syscall tracepoint instrumentation */ 117#define TIF_SYSCALL_TRACEPOINT 26 /* syscall tracepoint instrumentation */
118#define TIF_32BIT_FPREGS 27 /* 32-bit floating point registers */ 118#define TIF_32BIT_FPREGS 27 /* 32-bit floating point registers */
119#define TIF_HYBRID_FPREGS 28 /* 64b FP registers, odd singles in bits 63:32 of even doubles */
119#define TIF_USEDMSA 29 /* MSA has been used this quantum */ 120#define TIF_USEDMSA 29 /* MSA has been used this quantum */
120#define TIF_MSA_CTX_LIVE 30 /* MSA context must be preserved */ 121#define TIF_MSA_CTX_LIVE 30 /* MSA context must be preserved */
121#define TIF_SYSCALL_TRACE 31 /* syscall trace active */ 122#define TIF_SYSCALL_TRACE 31 /* syscall trace active */
@@ -135,6 +136,7 @@ static inline struct thread_info *current_thread_info(void)
135#define _TIF_FPUBOUND (1<<TIF_FPUBOUND) 136#define _TIF_FPUBOUND (1<<TIF_FPUBOUND)
136#define _TIF_LOAD_WATCH (1<<TIF_LOAD_WATCH) 137#define _TIF_LOAD_WATCH (1<<TIF_LOAD_WATCH)
137#define _TIF_32BIT_FPREGS (1<<TIF_32BIT_FPREGS) 138#define _TIF_32BIT_FPREGS (1<<TIF_32BIT_FPREGS)
139#define _TIF_HYBRID_FPREGS (1<<TIF_HYBRID_FPREGS)
138#define _TIF_USEDMSA (1<<TIF_USEDMSA) 140#define _TIF_USEDMSA (1<<TIF_USEDMSA)
139#define _TIF_MSA_CTX_LIVE (1<<TIF_MSA_CTX_LIVE) 141#define _TIF_MSA_CTX_LIVE (1<<TIF_MSA_CTX_LIVE)
140#define _TIF_SYSCALL_TRACEPOINT (1<<TIF_SYSCALL_TRACEPOINT) 142#define _TIF_SYSCALL_TRACEPOINT (1<<TIF_SYSCALL_TRACEPOINT)
diff --git a/arch/mips/include/asm/time.h b/arch/mips/include/asm/time.h
index 8f3047d611ee..8ab2874225c4 100644
--- a/arch/mips/include/asm/time.h
+++ b/arch/mips/include/asm/time.h
@@ -46,19 +46,17 @@ extern unsigned int mips_hpt_frequency;
46 * so it lives here. 46 * so it lives here.
47 */ 47 */
48extern int (*perf_irq)(void); 48extern int (*perf_irq)(void);
49extern int __weak get_c0_perfcount_int(void);
49 50
50/* 51/*
51 * Initialize the calling CPU's compare interrupt as clockevent device 52 * Initialize the calling CPU's compare interrupt as clockevent device
52 */ 53 */
53extern unsigned int __weak get_c0_compare_int(void); 54extern unsigned int __weak get_c0_compare_int(void);
54extern int r4k_clockevent_init(void); 55extern int r4k_clockevent_init(void);
55extern int gic_clockevent_init(void);
56 56
57static inline int mips_clockevent_init(void) 57static inline int mips_clockevent_init(void)
58{ 58{
59#if defined(CONFIG_CEVT_GIC) 59#ifdef CONFIG_CEVT_R4K
60 return (gic_clockevent_init() | r4k_clockevent_init());
61#elif defined(CONFIG_CEVT_R4K)
62 return r4k_clockevent_init(); 60 return r4k_clockevent_init();
63#else 61#else
64 return -ENXIO; 62 return -ENXIO;
diff --git a/arch/mips/include/asm/types.h b/arch/mips/include/asm/types.h
index a845aafedee4..148d42a17f30 100644
--- a/arch/mips/include/asm/types.h
+++ b/arch/mips/include/asm/types.h
@@ -11,23 +11,7 @@
11#ifndef _ASM_TYPES_H 11#ifndef _ASM_TYPES_H
12#define _ASM_TYPES_H 12#define _ASM_TYPES_H
13 13
14# include <asm-generic/int-ll64.h> 14#include <asm-generic/int-ll64.h>
15#include <uapi/asm/types.h> 15#include <uapi/asm/types.h>
16 16
17/*
18 * These aren't exported outside the kernel to avoid name space clashes
19 */
20#ifndef __ASSEMBLY__
21
22/*
23 * Don't use phys_t. You've been warned.
24 */
25#ifdef CONFIG_64BIT_PHYS_ADDR
26typedef unsigned long long phys_t;
27#else
28typedef unsigned long phys_t;
29#endif
30
31#endif /* __ASSEMBLY__ */
32
33#endif /* _ASM_TYPES_H */ 17#endif /* _ASM_TYPES_H */
diff --git a/arch/mips/include/asm/uaccess.h b/arch/mips/include/asm/uaccess.h
index 22a5624e2fd2..bf8b32450ef6 100644
--- a/arch/mips/include/asm/uaccess.h
+++ b/arch/mips/include/asm/uaccess.h
@@ -1325,33 +1325,6 @@ strncpy_from_user(char *__to, const char __user *__from, long __len)
1325 return res; 1325 return res;
1326} 1326}
1327 1327
1328/* Returns: 0 if bad, string length+1 (memory size) of string if ok */
1329static inline long __strlen_user(const char __user *s)
1330{
1331 long res;
1332
1333 if (segment_eq(get_fs(), get_ds())) {
1334 __asm__ __volatile__(
1335 "move\t$4, %1\n\t"
1336 __MODULE_JAL(__strlen_kernel_nocheck_asm)
1337 "move\t%0, $2"
1338 : "=r" (res)
1339 : "r" (s)
1340 : "$2", "$4", __UA_t0, "$31");
1341 } else {
1342 might_fault();
1343 __asm__ __volatile__(
1344 "move\t$4, %1\n\t"
1345 __MODULE_JAL(__strlen_user_nocheck_asm)
1346 "move\t%0, $2"
1347 : "=r" (res)
1348 : "r" (s)
1349 : "$2", "$4", __UA_t0, "$31");
1350 }
1351
1352 return res;
1353}
1354
1355/* 1328/*
1356 * strlen_user: - Get the size of a string in user space. 1329 * strlen_user: - Get the size of a string in user space.
1357 * @str: The string to measure. 1330 * @str: The string to measure.
diff --git a/arch/mips/include/asm/uasm.h b/arch/mips/include/asm/uasm.h
index 708c5d414905..fc1cdd25fcda 100644
--- a/arch/mips/include/asm/uasm.h
+++ b/arch/mips/include/asm/uasm.h
@@ -136,9 +136,11 @@ Ip_u1s2(_lui);
136Ip_u2s3u1(_lw); 136Ip_u2s3u1(_lw);
137Ip_u3u1u2(_lwx); 137Ip_u3u1u2(_lwx);
138Ip_u1u2u3(_mfc0); 138Ip_u1u2u3(_mfc0);
139Ip_u1u2u3(_mfhc0);
139Ip_u1(_mfhi); 140Ip_u1(_mfhi);
140Ip_u1(_mflo); 141Ip_u1(_mflo);
141Ip_u1u2u3(_mtc0); 142Ip_u1u2u3(_mtc0);
143Ip_u1u2u3(_mthc0);
142Ip_u3u1u2(_mul); 144Ip_u3u1u2(_mul);
143Ip_u3u1u2(_or); 145Ip_u3u1u2(_or);
144Ip_u2u1u3(_ori); 146Ip_u2u1u3(_ori);
diff --git a/arch/mips/include/uapi/asm/inst.h b/arch/mips/include/uapi/asm/inst.h
index 4bfdb9d4c186..89c22433b1c6 100644
--- a/arch/mips/include/uapi/asm/inst.h
+++ b/arch/mips/include/uapi/asm/inst.h
@@ -108,9 +108,10 @@ enum rt_op {
108 */ 108 */
109enum cop_op { 109enum cop_op {
110 mfc_op = 0x00, dmfc_op = 0x01, 110 mfc_op = 0x00, dmfc_op = 0x01,
111 cfc_op = 0x02, mfhc_op = 0x03, 111 cfc_op = 0x02, mfhc0_op = 0x02,
112 mtc_op = 0x04, dmtc_op = 0x05, 112 mfhc_op = 0x03, mtc_op = 0x04,
113 ctc_op = 0x06, mthc_op = 0x07, 113 dmtc_op = 0x05, ctc_op = 0x06,
114 mthc0_op = 0x06, mthc_op = 0x07,
114 bc_op = 0x08, cop_op = 0x10, 115 bc_op = 0x08, cop_op = 0x10,
115 copm_op = 0x18 116 copm_op = 0x18
116}; 117};
generated by cgit v1.2.2 (git 2.25.0) at 2025-05-31 18:48:33 -0400