aboutsummaryrefslogtreecommitdiffstats
path: root/arch/mips/include
diff options
context:
space:
mode:
Diffstat (limited to 'arch/mips/include')
-rw-r--r--arch/mips/include/asm/Kbuild14
-rw-r--r--arch/mips/include/asm/addrspace.h4
-rw-r--r--arch/mips/include/asm/atomic.h2
-rw-r--r--arch/mips/include/asm/barrier.h6
-rw-r--r--arch/mips/include/asm/bmips.h55
-rw-r--r--arch/mips/include/asm/cacheops.h93
-rw-r--r--arch/mips/include/asm/cpu-features.h8
-rw-r--r--arch/mips/include/asm/cpu-info.h1
-rw-r--r--arch/mips/include/asm/cpu-type.h203
-rw-r--r--arch/mips/include/asm/cpu.h44
-rw-r--r--arch/mips/include/asm/cputime.h6
-rw-r--r--arch/mips/include/asm/current.h1
-rw-r--r--arch/mips/include/asm/dec/ioasic.h2
-rw-r--r--arch/mips/include/asm/dec/ioasic_addrs.h2
-rw-r--r--arch/mips/include/asm/dec/kn01.h12
-rw-r--r--arch/mips/include/asm/dec/kn02ca.h2
-rw-r--r--arch/mips/include/asm/dec/prom.h2
-rw-r--r--arch/mips/include/asm/elf.h1
-rw-r--r--arch/mips/include/asm/emergency-restart.h6
-rw-r--r--arch/mips/include/asm/jump_label.h2
-rw-r--r--arch/mips/include/asm/kvm_host.h7
-rw-r--r--arch/mips/include/asm/local64.h1
-rw-r--r--arch/mips/include/asm/mach-ath79/ar933x_uart_platform.h18
-rw-r--r--arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h2
-rw-r--r--arch/mips/include/asm/mach-au1x00/au1000.h4
-rw-r--r--arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h110
-rw-r--r--arch/mips/include/asm/mach-bcm47xx/bcm47xx_nvram.h2
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_nvram.h2
-rw-r--r--arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h12
-rw-r--r--arch/mips/include/asm/mach-cavium-octeon/gpio.h21
-rw-r--r--arch/mips/include/asm/mach-dec/cpu-feature-overrides.h87
-rw-r--r--arch/mips/include/asm/mach-generic/dma-coherence.h10
-rw-r--r--arch/mips/include/asm/mach-ip22/cpu-feature-overrides.h2
-rw-r--r--arch/mips/include/asm/mach-ip27/cpu-feature-overrides.h2
-rw-r--r--arch/mips/include/asm/mach-ip27/dma-coherence.h10
-rw-r--r--arch/mips/include/asm/mach-ip28/cpu-feature-overrides.h2
-rw-r--r--arch/mips/include/asm/mach-ip32/dma-coherence.h11
-rw-r--r--arch/mips/include/asm/mach-jazz/dma-coherence.h10
-rw-r--r--arch/mips/include/asm/mach-lantiq/falcon/cpu-feature-overrides.h58
-rw-r--r--arch/mips/include/asm/mach-loongson/dma-coherence.h10
-rw-r--r--arch/mips/include/asm/mach-powertv/asic.h120
-rw-r--r--arch/mips/include/asm/mach-powertv/asic_reg_map.h90
-rw-r--r--arch/mips/include/asm/mach-powertv/asic_regs.h125
-rw-r--r--arch/mips/include/asm/mach-powertv/cpu-feature-overrides.h60
-rw-r--r--arch/mips/include/asm/mach-powertv/dma-coherence.h117
-rw-r--r--arch/mips/include/asm/mach-powertv/interrupts.h253
-rw-r--r--arch/mips/include/asm/mach-powertv/ioremap.h167
-rw-r--r--arch/mips/include/asm/mach-powertv/irq.h25
-rw-r--r--arch/mips/include/asm/mach-powertv/powertv-clock.h29
-rw-r--r--arch/mips/include/asm/mach-powertv/war.h27
-rw-r--r--arch/mips/include/asm/mach-ralink/mt7620.h40
-rw-r--r--arch/mips/include/asm/mach-ralink/mt7620/cpu-feature-overrides.h57
-rw-r--r--arch/mips/include/asm/mips-boards/piix4.h78
-rw-r--r--arch/mips/include/asm/mipsregs.h7
-rw-r--r--arch/mips/include/asm/mmu_context.h22
-rw-r--r--arch/mips/include/asm/mutex.h9
-rw-r--r--arch/mips/include/asm/netlogic/xlp-hal/bridge.h4
-rw-r--r--arch/mips/include/asm/netlogic/xlp-hal/iomap.h10
-rw-r--r--arch/mips/include/asm/netlogic/xlp-hal/pic.h5
-rw-r--r--arch/mips/include/asm/netlogic/xlp-hal/sys.h31
-rw-r--r--arch/mips/include/asm/netlogic/xlp-hal/xlp.h18
-rw-r--r--arch/mips/include/asm/netlogic/xlr/pic.h2
-rw-r--r--arch/mips/include/asm/octeon/octeon.h2
-rw-r--r--arch/mips/include/asm/parport.h1
-rw-r--r--arch/mips/include/asm/pci.h17
-rw-r--r--arch/mips/include/asm/percpu.h6
-rw-r--r--arch/mips/include/asm/pgalloc.h9
-rw-r--r--arch/mips/include/asm/prom.h14
-rw-r--r--arch/mips/include/asm/ptrace.h14
-rw-r--r--arch/mips/include/asm/r4kcache.h41
-rw-r--r--arch/mips/include/asm/scatterlist.h6
-rw-r--r--arch/mips/include/asm/sections.h6
-rw-r--r--arch/mips/include/asm/segment.h6
-rw-r--r--arch/mips/include/asm/serial.h1
-rw-r--r--arch/mips/include/asm/setup.h8
-rw-r--r--arch/mips/include/asm/stackframe.h24
-rw-r--r--arch/mips/include/asm/syscall.h116
-rw-r--r--arch/mips/include/asm/thread_info.h42
-rw-r--r--arch/mips/include/asm/time.h2
-rw-r--r--arch/mips/include/asm/timex.h33
-rw-r--r--arch/mips/include/asm/ucontext.h1
-rw-r--r--arch/mips/include/asm/unistd.h7
-rw-r--r--arch/mips/include/asm/vga.h3
-rw-r--r--arch/mips/include/asm/xor.h1
-rw-r--r--arch/mips/include/uapi/asm/Kbuild5
-rw-r--r--arch/mips/include/uapi/asm/auxvec.h4
-rw-r--r--arch/mips/include/uapi/asm/errno.h2
-rw-r--r--arch/mips/include/uapi/asm/ipcbuf.h1
-rw-r--r--arch/mips/include/uapi/asm/siginfo.h9
-rw-r--r--arch/mips/include/uapi/asm/socket.h2
90 files changed, 1109 insertions, 1417 deletions
diff --git a/arch/mips/include/asm/Kbuild b/arch/mips/include/asm/Kbuild
index 9b54b7a403d4..1acbb8b77a71 100644
--- a/arch/mips/include/asm/Kbuild
+++ b/arch/mips/include/asm/Kbuild
@@ -1,2 +1,16 @@
1# MIPS headers 1# MIPS headers
2generic-y += cputime.h
3generic-y += current.h
4generic-y += emergency-restart.h
5generic-y += local64.h
6generic-y += mutex.h
7generic-y += parport.h
8generic-y += percpu.h
9generic-y += scatterlist.h
10generic-y += sections.h
11generic-y += segment.h
12generic-y += serial.h
2generic-y += trace_clock.h 13generic-y += trace_clock.h
14generic-y += preempt.h
15generic-y += ucontext.h
16generic-y += xor.h
diff --git a/arch/mips/include/asm/addrspace.h b/arch/mips/include/asm/addrspace.h
index 13d61c002e4f..3f745459fdb5 100644
--- a/arch/mips/include/asm/addrspace.h
+++ b/arch/mips/include/asm/addrspace.h
@@ -58,7 +58,7 @@
58 58
59/* 59/*
60 * Memory segments (64bit kernel mode addresses) 60 * Memory segments (64bit kernel mode addresses)
61 * The compatibility segments use the full 64-bit sign extended value. Note 61 * The compatibility segments use the full 64-bit sign extended value. Note
62 * the R8000 doesn't have them so don't reference these in generic MIPS code. 62 * the R8000 doesn't have them so don't reference these in generic MIPS code.
63 */ 63 */
64#define XKUSEG _CONST64_(0x0000000000000000) 64#define XKUSEG _CONST64_(0x0000000000000000)
@@ -131,7 +131,7 @@
131 131
132/* 132/*
133 * The ultimate limited of the 64-bit MIPS architecture: 2 bits for selecting 133 * The ultimate limited of the 64-bit MIPS architecture: 2 bits for selecting
134 * the region, 3 bits for the CCA mode. This leaves 59 bits of which the 134 * the region, 3 bits for the CCA mode. This leaves 59 bits of which the
135 * R8000 implements most with its 48-bit physical address space. 135 * R8000 implements most with its 48-bit physical address space.
136 */ 136 */
137#define TO_PHYS_MASK _CONST64_(0x07ffffffffffffff) /* 2^^59 - 1 */ 137#define TO_PHYS_MASK _CONST64_(0x07ffffffffffffff) /* 2^^59 - 1 */
diff --git a/arch/mips/include/asm/atomic.h b/arch/mips/include/asm/atomic.h
index 08b607969a16..7eed2f261710 100644
--- a/arch/mips/include/asm/atomic.h
+++ b/arch/mips/include/asm/atomic.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Atomic operations that C can't guarantee us. Useful for 2 * Atomic operations that C can't guarantee us. Useful for
3 * resource counting etc.. 3 * resource counting etc..
4 * 4 *
5 * But use these as seldom as possible since they are much more slower 5 * But use these as seldom as possible since they are much more slower
diff --git a/arch/mips/include/asm/barrier.h b/arch/mips/include/asm/barrier.h
index 314ab5532019..f26d8e1bf3c3 100644
--- a/arch/mips/include/asm/barrier.h
+++ b/arch/mips/include/asm/barrier.h
@@ -18,7 +18,7 @@
18 * over this barrier. All reads preceding this primitive are guaranteed 18 * over this barrier. All reads preceding this primitive are guaranteed
19 * to access memory (but not necessarily other CPUs' caches) before any 19 * to access memory (but not necessarily other CPUs' caches) before any
20 * reads following this primitive that depend on the data return by 20 * reads following this primitive that depend on the data return by
21 * any of the preceding reads. This primitive is much lighter weight than 21 * any of the preceding reads. This primitive is much lighter weight than
22 * rmb() on most CPUs, and is never heavier weight than is 22 * rmb() on most CPUs, and is never heavier weight than is
23 * rmb(). 23 * rmb().
24 * 24 *
@@ -43,7 +43,7 @@
43 * </programlisting> 43 * </programlisting>
44 * 44 *
45 * because the read of "*q" depends on the read of "p" and these 45 * because the read of "*q" depends on the read of "p" and these
46 * two reads are separated by a read_barrier_depends(). However, 46 * two reads are separated by a read_barrier_depends(). However,
47 * the following code, with the same initial values for "a" and "b": 47 * the following code, with the same initial values for "a" and "b":
48 * 48 *
49 * <programlisting> 49 * <programlisting>
@@ -57,7 +57,7 @@
57 * </programlisting> 57 * </programlisting>
58 * 58 *
59 * does not enforce ordering, since there is no data dependency between 59 * does not enforce ordering, since there is no data dependency between
60 * the read of "a" and the read of "b". Therefore, on some CPUs, such 60 * the read of "a" and the read of "b". Therefore, on some CPUs, such
61 * as Alpha, "y" could be set to 3 and "x" to 0. Use rmb() 61 * as Alpha, "y" could be set to 3 and "x" to 0. Use rmb()
62 * in cases like this where there are no data dependencies. 62 * in cases like this where there are no data dependencies.
63 */ 63 */
diff --git a/arch/mips/include/asm/bmips.h b/arch/mips/include/asm/bmips.h
index 552a65a0cf2b..27bd060d716e 100644
--- a/arch/mips/include/asm/bmips.h
+++ b/arch/mips/include/asm/bmips.h
@@ -65,44 +65,33 @@ static inline unsigned long bmips_read_zscm_reg(unsigned int offset)
65{ 65{
66 unsigned long ret; 66 unsigned long ret;
67 67
68 __asm__ __volatile__( 68 barrier();
69 ".set push\n" 69 cache_op(Index_Load_Tag_S, ZSCM_REG_BASE + offset);
70 ".set noreorder\n" 70 __sync();
71 "cache %1, 0(%2)\n" 71 _ssnop();
72 "sync\n" 72 _ssnop();
73 "_ssnop\n" 73 _ssnop();
74 "_ssnop\n" 74 _ssnop();
75 "_ssnop\n" 75 _ssnop();
76 "_ssnop\n" 76 _ssnop();
77 "_ssnop\n" 77 _ssnop();
78 "_ssnop\n" 78 ret = read_c0_ddatalo();
79 "_ssnop\n" 79 _ssnop();
80 "mfc0 %0, $28, 3\n" 80
81 "_ssnop\n"
82 ".set pop\n"
83 : "=&r" (ret)
84 : "i" (Index_Load_Tag_S), "r" (ZSCM_REG_BASE + offset)
85 : "memory");
86 return ret; 81 return ret;
87} 82}
88 83
89static inline void bmips_write_zscm_reg(unsigned int offset, unsigned long data) 84static inline void bmips_write_zscm_reg(unsigned int offset, unsigned long data)
90{ 85{
91 __asm__ __volatile__( 86 write_c0_ddatalo(data);
92 ".set push\n" 87 _ssnop();
93 ".set noreorder\n" 88 _ssnop();
94 "mtc0 %0, $28, 3\n" 89 _ssnop();
95 "_ssnop\n" 90 cache_op(Index_Store_Tag_S, ZSCM_REG_BASE + offset);
96 "_ssnop\n" 91 _ssnop();
97 "_ssnop\n" 92 _ssnop();
98 "cache %1, 0(%2)\n" 93 _ssnop();
99 "_ssnop\n" 94 barrier();
100 "_ssnop\n"
101 "_ssnop\n"
102 : /* no outputs */
103 : "r" (data),
104 "i" (Index_Store_Tag_S), "r" (ZSCM_REG_BASE + offset)
105 : "memory");
106} 95}
107 96
108#endif /* !defined(__ASSEMBLY__) */ 97#endif /* !defined(__ASSEMBLY__) */
diff --git a/arch/mips/include/asm/cacheops.h b/arch/mips/include/asm/cacheops.h
index 68f37e3eccc7..c75025f27c20 100644
--- a/arch/mips/include/asm/cacheops.h
+++ b/arch/mips/include/asm/cacheops.h
@@ -14,56 +14,52 @@
14/* 14/*
15 * Cache Operations available on all MIPS processors with R4000-style caches 15 * Cache Operations available on all MIPS processors with R4000-style caches
16 */ 16 */
17#define Index_Invalidate_I 0x00 17#define Index_Invalidate_I 0x00
18#define Index_Writeback_Inv_D 0x01 18#define Index_Writeback_Inv_D 0x01
19#define Index_Load_Tag_I 0x04 19#define Index_Load_Tag_I 0x04
20#define Index_Load_Tag_D 0x05 20#define Index_Load_Tag_D 0x05
21#define Index_Store_Tag_I 0x08 21#define Index_Store_Tag_I 0x08
22#define Index_Store_Tag_D 0x09 22#define Index_Store_Tag_D 0x09
23#if defined(CONFIG_CPU_LOONGSON2) 23#define Hit_Invalidate_I 0x10
24#define Hit_Invalidate_I 0x00 24#define Hit_Invalidate_D 0x11
25#else 25#define Hit_Writeback_Inv_D 0x15
26#define Hit_Invalidate_I 0x10
27#endif
28#define Hit_Invalidate_D 0x11
29#define Hit_Writeback_Inv_D 0x15
30 26
31/* 27/*
32 * R4000-specific cacheops 28 * R4000-specific cacheops
33 */ 29 */
34#define Create_Dirty_Excl_D 0x0d 30#define Create_Dirty_Excl_D 0x0d
35#define Fill 0x14 31#define Fill 0x14
36#define Hit_Writeback_I 0x18 32#define Hit_Writeback_I 0x18
37#define Hit_Writeback_D 0x19 33#define Hit_Writeback_D 0x19
38 34
39/* 35/*
40 * R4000SC and R4400SC-specific cacheops 36 * R4000SC and R4400SC-specific cacheops
41 */ 37 */
42#define Index_Invalidate_SI 0x02 38#define Index_Invalidate_SI 0x02
43#define Index_Writeback_Inv_SD 0x03 39#define Index_Writeback_Inv_SD 0x03
44#define Index_Load_Tag_SI 0x06 40#define Index_Load_Tag_SI 0x06
45#define Index_Load_Tag_SD 0x07 41#define Index_Load_Tag_SD 0x07
46#define Index_Store_Tag_SI 0x0A 42#define Index_Store_Tag_SI 0x0A
47#define Index_Store_Tag_SD 0x0B 43#define Index_Store_Tag_SD 0x0B
48#define Create_Dirty_Excl_SD 0x0f 44#define Create_Dirty_Excl_SD 0x0f
49#define Hit_Invalidate_SI 0x12 45#define Hit_Invalidate_SI 0x12
50#define Hit_Invalidate_SD 0x13 46#define Hit_Invalidate_SD 0x13
51#define Hit_Writeback_Inv_SD 0x17 47#define Hit_Writeback_Inv_SD 0x17
52#define Hit_Writeback_SD 0x1b 48#define Hit_Writeback_SD 0x1b
53#define Hit_Set_Virtual_SI 0x1e 49#define Hit_Set_Virtual_SI 0x1e
54#define Hit_Set_Virtual_SD 0x1f 50#define Hit_Set_Virtual_SD 0x1f
55 51
56/* 52/*
57 * R5000-specific cacheops 53 * R5000-specific cacheops
58 */ 54 */
59#define R5K_Page_Invalidate_S 0x17 55#define R5K_Page_Invalidate_S 0x17
60 56
61/* 57/*
62 * RM7000-specific cacheops 58 * RM7000-specific cacheops
63 */ 59 */
64#define Page_Invalidate_T 0x16 60#define Page_Invalidate_T 0x16
65#define Index_Store_Tag_T 0x0a 61#define Index_Store_Tag_T 0x0a
66#define Index_Load_Tag_T 0x06 62#define Index_Load_Tag_T 0x06
67 63
68/* 64/*
69 * R10000-specific cacheops 65 * R10000-specific cacheops
@@ -71,17 +67,22 @@
71 * Cacheops 0x02, 0x06, 0x0a, 0x0c-0x0e, 0x16, 0x1a and 0x1e are unused. 67 * Cacheops 0x02, 0x06, 0x0a, 0x0c-0x0e, 0x16, 0x1a and 0x1e are unused.
72 * Most of the _S cacheops are identical to the R4000SC _SD cacheops. 68 * Most of the _S cacheops are identical to the R4000SC _SD cacheops.
73 */ 69 */
74#define Index_Writeback_Inv_S 0x03 70#define Index_Writeback_Inv_S 0x03
75#define Index_Load_Tag_S 0x07 71#define Index_Load_Tag_S 0x07
76#define Index_Store_Tag_S 0x0B 72#define Index_Store_Tag_S 0x0B
77#define Hit_Invalidate_S 0x13 73#define Hit_Invalidate_S 0x13
78#define Cache_Barrier 0x14 74#define Cache_Barrier 0x14
79#define Hit_Writeback_Inv_S 0x17 75#define Hit_Writeback_Inv_S 0x17
80#define Index_Load_Data_I 0x18 76#define Index_Load_Data_I 0x18
81#define Index_Load_Data_D 0x19 77#define Index_Load_Data_D 0x19
82#define Index_Load_Data_S 0x1b 78#define Index_Load_Data_S 0x1b
83#define Index_Store_Data_I 0x1c 79#define Index_Store_Data_I 0x1c
84#define Index_Store_Data_D 0x1d 80#define Index_Store_Data_D 0x1d
85#define Index_Store_Data_S 0x1f 81#define Index_Store_Data_S 0x1f
82
83/*
84 * Loongson2-specific cacheops
85 */
86#define Hit_Invalidate_I_Loongson23 0x00
86 87
87#endif /* __ASM_CACHEOPS_H */ 88#endif /* __ASM_CACHEOPS_H */
diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
index fa44f3ec5302..d445d060e346 100644
--- a/arch/mips/include/asm/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
@@ -13,12 +13,6 @@
13#include <asm/cpu-info.h> 13#include <asm/cpu-info.h>
14#include <cpu-feature-overrides.h> 14#include <cpu-feature-overrides.h>
15 15
16#ifndef current_cpu_type
17#define current_cpu_type() current_cpu_data.cputype
18#endif
19
20#define boot_cpu_type() cpu_data[0].cputype
21
22/* 16/*
23 * SMP assumption: Options of CPU 0 are a superset of all processors. 17 * SMP assumption: Options of CPU 0 are a superset of all processors.
24 * This is true for all known MIPS systems. 18 * This is true for all known MIPS systems.
@@ -193,7 +187,7 @@
193 187
194/* 188/*
195 * MIPS32, MIPS64, VR5500, IDT32332, IDT32334 and maybe a few other 189 * MIPS32, MIPS64, VR5500, IDT32332, IDT32334 and maybe a few other
196 * pre-MIPS32/MIPS53 processors have CLO, CLZ. The IDT RC64574 is 64-bit and 190 * pre-MIPS32/MIPS64 processors have CLO, CLZ. The IDT RC64574 is 64-bit and
197 * has CLO and CLZ but not DCLO nor DCLZ. For 64-bit kernels 191 * has CLO and CLZ but not DCLO nor DCLZ. For 64-bit kernels
198 * cpu_has_clo_clz also indicates the availability of DCLO and DCLZ. 192 * cpu_has_clo_clz also indicates the availability of DCLO and DCLZ.
199 */ 193 */
diff --git a/arch/mips/include/asm/cpu-info.h b/arch/mips/include/asm/cpu-info.h
index 41401d8eb7d1..21c8e29c8f91 100644
--- a/arch/mips/include/asm/cpu-info.h
+++ b/arch/mips/include/asm/cpu-info.h
@@ -84,6 +84,7 @@ struct cpuinfo_mips {
84extern struct cpuinfo_mips cpu_data[]; 84extern struct cpuinfo_mips cpu_data[];
85#define current_cpu_data cpu_data[smp_processor_id()] 85#define current_cpu_data cpu_data[smp_processor_id()]
86#define raw_current_cpu_data cpu_data[raw_smp_processor_id()] 86#define raw_current_cpu_data cpu_data[raw_smp_processor_id()]
87#define boot_cpu_data cpu_data[0]
87 88
88extern void cpu_probe(void); 89extern void cpu_probe(void);
89extern void cpu_report(void); 90extern void cpu_report(void);
diff --git a/arch/mips/include/asm/cpu-type.h b/arch/mips/include/asm/cpu-type.h
new file mode 100644
index 000000000000..4a402cc60c03
--- /dev/null
+++ b/arch/mips/include/asm/cpu-type.h
@@ -0,0 +1,203 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2003, 2004 Ralf Baechle
7 * Copyright (C) 2004 Maciej W. Rozycki
8 */
9#ifndef __ASM_CPU_TYPE_H
10#define __ASM_CPU_TYPE_H
11
12#include <linux/smp.h>
13#include <linux/compiler.h>
14
15static inline int __pure __get_cpu_type(const int cpu_type)
16{
17 switch (cpu_type) {
18#if defined(CONFIG_SYS_HAS_CPU_LOONGSON2E) || \
19 defined(CONFIG_SYS_HAS_CPU_LOONGSON2F)
20 case CPU_LOONGSON2:
21#endif
22
23#ifdef CONFIG_SYS_HAS_CPU_LOONGSON1B
24 case CPU_LOONGSON1:
25#endif
26
27#ifdef CONFIG_SYS_HAS_CPU_MIPS32_R1
28 case CPU_4KC:
29 case CPU_ALCHEMY:
30 case CPU_BMIPS3300:
31 case CPU_BMIPS4350:
32 case CPU_PR4450:
33 case CPU_BMIPS32:
34 case CPU_JZRISC:
35#endif
36
37#if defined(CONFIG_SYS_HAS_CPU_MIPS32_R1) || \
38 defined(CONFIG_SYS_HAS_CPU_MIPS32_R2)
39 case CPU_4KEC:
40#endif
41
42#ifdef CONFIG_SYS_HAS_CPU_MIPS32_R2
43 case CPU_4KSC:
44 case CPU_24K:
45 case CPU_34K:
46 case CPU_1004K:
47 case CPU_74K:
48 case CPU_M14KC:
49 case CPU_M14KEC:
50#endif
51
52#ifdef CONFIG_SYS_HAS_CPU_MIPS64_R1
53 case CPU_5KC:
54 case CPU_5KE:
55 case CPU_20KC:
56 case CPU_25KF:
57 case CPU_SB1:
58 case CPU_SB1A:
59#endif
60
61#ifdef CONFIG_SYS_HAS_CPU_MIPS64_R2
62 /*
63 * All MIPS64 R2 processors have their own special symbols. That is,
64 * there currently is no pure R2 core
65 */
66#endif
67
68#ifdef CONFIG_SYS_HAS_CPU_R3000
69 case CPU_R2000:
70 case CPU_R3000:
71 case CPU_R3000A:
72 case CPU_R3041:
73 case CPU_R3051:
74 case CPU_R3052:
75 case CPU_R3081:
76 case CPU_R3081E:
77#endif
78
79#ifdef CONFIG_SYS_HAS_CPU_TX39XX
80 case CPU_TX3912:
81 case CPU_TX3922:
82 case CPU_TX3927:
83#endif
84
85#ifdef CONFIG_SYS_HAS_CPU_VR41XX
86 case CPU_VR41XX:
87 case CPU_VR4111:
88 case CPU_VR4121:
89 case CPU_VR4122:
90 case CPU_VR4131:
91 case CPU_VR4133:
92 case CPU_VR4181:
93 case CPU_VR4181A:
94#endif
95
96#ifdef CONFIG_SYS_HAS_CPU_R4300
97 case CPU_R4300:
98 case CPU_R4310:
99#endif
100
101#ifdef CONFIG_SYS_HAS_CPU_R4X00
102 case CPU_R4000PC:
103 case CPU_R4000SC:
104 case CPU_R4000MC:
105 case CPU_R4200:
106 case CPU_R4400PC:
107 case CPU_R4400SC:
108 case CPU_R4400MC:
109 case CPU_R4600:
110 case CPU_R4700:
111 case CPU_R4640:
112 case CPU_R4650:
113#endif
114
115#ifdef CONFIG_SYS_HAS_CPU_TX49XX
116 case CPU_TX49XX:
117#endif
118
119#ifdef CONFIG_SYS_HAS_CPU_R5000
120 case CPU_R5000:
121#endif
122
123#ifdef CONFIG_SYS_HAS_CPU_R5432
124 case CPU_R5432:
125#endif
126
127#ifdef CONFIG_SYS_HAS_CPU_R5500
128 case CPU_R5500:
129#endif
130
131#ifdef CONFIG_SYS_HAS_CPU_R6000
132 case CPU_R6000:
133 case CPU_R6000A:
134#endif
135
136#ifdef CONFIG_SYS_HAS_CPU_NEVADA
137 case CPU_NEVADA:
138#endif
139
140#ifdef CONFIG_SYS_HAS_CPU_R8000
141 case CPU_R8000:
142#endif
143
144#ifdef CONFIG_SYS_HAS_CPU_R10000
145 case CPU_R10000:
146 case CPU_R12000:
147 case CPU_R14000:
148#endif
149#ifdef CONFIG_SYS_HAS_CPU_RM7000
150 case CPU_RM7000:
151 case CPU_SR71000:
152#endif
153#ifdef CONFIG_SYS_HAS_CPU_RM9000
154 case CPU_RM9000:
155#endif
156#ifdef CONFIG_SYS_HAS_CPU_SB1
157 case CPU_SB1:
158 case CPU_SB1A:
159#endif
160#ifdef CONFIG_SYS_HAS_CPU_CAVIUM_OCTEON
161 case CPU_CAVIUM_OCTEON:
162 case CPU_CAVIUM_OCTEON_PLUS:
163 case CPU_CAVIUM_OCTEON2:
164#endif
165
166#ifdef CONFIG_SYS_HAS_CPU_BMIPS4380
167 case CPU_BMIPS4380:
168#endif
169
170#ifdef CONFIG_SYS_HAS_CPU_BMIPS5000
171 case CPU_BMIPS5000:
172#endif
173
174#ifdef CONFIG_SYS_HAS_CPU_XLP
175 case CPU_XLP:
176#endif
177
178#ifdef CONFIG_SYS_HAS_CPU_XLR
179 case CPU_XLR:
180#endif
181 break;
182 default:
183 unreachable();
184 }
185
186 return cpu_type;
187}
188
189static inline int __pure current_cpu_type(void)
190{
191 const int cpu_type = current_cpu_data.cputype;
192
193 return __get_cpu_type(cpu_type);
194}
195
196static inline int __pure boot_cpu_type(void)
197{
198 const int cpu_type = cpu_data[0].cputype;
199
200 return __get_cpu_type(cpu_type);
201}
202
203#endif /* __ASM_CPU_TYPE_H */
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index 632bbe5a79ea..d2035e16502a 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -3,15 +3,14 @@
3 * various MIPS cpu types. 3 * various MIPS cpu types.
4 * 4 *
5 * Copyright (C) 1996 David S. Miller (davem@davemloft.net) 5 * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
6 * Copyright (C) 2004 Maciej W. Rozycki 6 * Copyright (C) 2004, 2013 Maciej W. Rozycki
7 */ 7 */
8#ifndef _ASM_CPU_H 8#ifndef _ASM_CPU_H
9#define _ASM_CPU_H 9#define _ASM_CPU_H
10 10
11/* Assigned Company values for bits 23:16 of the PRId Register 11/*
12 (CP0 register 15, select 0). As of the MIPS32 and MIPS64 specs from 12 As of the MIPS32 and MIPS64 specs from MTI, the PRId register (CP0
13 MTI, the PRId register is defined in this (backwards compatible) 13 register 15, select 0) is defined in this (backwards compatible) way:
14 way:
15 14
16 +----------------+----------------+----------------+----------------+ 15 +----------------+----------------+----------------+----------------+
17 | Company Options| Company ID | Processor ID | Revision | 16 | Company Options| Company ID | Processor ID | Revision |
@@ -23,6 +22,14 @@
23 spec. 22 spec.
24*/ 23*/
25 24
25#define PRID_OPT_MASK 0xff000000
26
27/*
28 * Assigned Company values for bits 23:16 of the PRId register.
29 */
30
31#define PRID_COMP_MASK 0xff0000
32
26#define PRID_COMP_LEGACY 0x000000 33#define PRID_COMP_LEGACY 0x000000
27#define PRID_COMP_MIPS 0x010000 34#define PRID_COMP_MIPS 0x010000
28#define PRID_COMP_BROADCOM 0x020000 35#define PRID_COMP_BROADCOM 0x020000
@@ -38,10 +45,17 @@
38#define PRID_COMP_INGENIC 0xd00000 45#define PRID_COMP_INGENIC 0xd00000
39 46
40/* 47/*
41 * Assigned values for the product ID register. In order to detect a 48 * Assigned Processor ID (implementation) values for bits 15:8 of the PRId
42 * certain CPU type exactly eventually additional registers may need to 49 * register. In order to detect a certain CPU type exactly eventually
43 * be examined. These are valid when 23:16 == PRID_COMP_LEGACY 50 * additional registers may need to be examined.
44 */ 51 */
52
53#define PRID_IMP_MASK 0xff00
54
55/*
56 * These are valid when 23:16 == PRID_COMP_LEGACY
57 */
58
45#define PRID_IMP_R2000 0x0100 59#define PRID_IMP_R2000 0x0100
46#define PRID_IMP_AU1_REV1 0x0100 60#define PRID_IMP_AU1_REV1 0x0100
47#define PRID_IMP_AU1_REV2 0x0200 61#define PRID_IMP_AU1_REV2 0x0200
@@ -141,6 +155,9 @@
141#define PRID_IMP_CAVIUM_CN68XX 0x9100 155#define PRID_IMP_CAVIUM_CN68XX 0x9100
142#define PRID_IMP_CAVIUM_CN66XX 0x9200 156#define PRID_IMP_CAVIUM_CN66XX 0x9200
143#define PRID_IMP_CAVIUM_CN61XX 0x9300 157#define PRID_IMP_CAVIUM_CN61XX 0x9300
158#define PRID_IMP_CAVIUM_CNF71XX 0x9400
159#define PRID_IMP_CAVIUM_CN78XX 0x9500
160#define PRID_IMP_CAVIUM_CN70XX 0x9600
144 161
145/* 162/*
146 * These are the PRID's for when 23:16 == PRID_COMP_INGENIC 163 * These are the PRID's for when 23:16 == PRID_COMP_INGENIC
@@ -176,13 +193,18 @@
176 193
177#define PRID_IMP_NETLOGIC_XLP8XX 0x1000 194#define PRID_IMP_NETLOGIC_XLP8XX 0x1000
178#define PRID_IMP_NETLOGIC_XLP3XX 0x1100 195#define PRID_IMP_NETLOGIC_XLP3XX 0x1100
196#define PRID_IMP_NETLOGIC_XLP2XX 0x1200
179 197
180/* 198/*
181 * Definitions for 7:0 on legacy processors 199 * Particular Revision values for bits 7:0 of the PRId register.
182 */ 200 */
183 201
184#define PRID_REV_MASK 0x00ff 202#define PRID_REV_MASK 0x00ff
185 203
204/*
205 * Definitions for 7:0 on legacy processors
206 */
207
186#define PRID_REV_TX4927 0x0022 208#define PRID_REV_TX4927 0x0022
187#define PRID_REV_TX4937 0x0030 209#define PRID_REV_TX4937 0x0030
188#define PRID_REV_R4400 0x0040 210#define PRID_REV_R4400 0x0040
@@ -223,6 +245,8 @@
223 * 31 16 15 8 7 0 245 * 31 16 15 8 7 0
224 */ 246 */
225 247
248#define FPIR_IMP_MASK 0xff00
249
226#define FPIR_IMP_NONE 0x0000 250#define FPIR_IMP_NONE 0x0000
227 251
228enum cpu_type_enum { 252enum cpu_type_enum {
@@ -272,7 +296,7 @@ enum cpu_type_enum {
272 */ 296 */
273 CPU_5KC, CPU_5KE, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2, 297 CPU_5KC, CPU_5KE, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2,
274 CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS, CPU_CAVIUM_OCTEON2, 298 CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS, CPU_CAVIUM_OCTEON2,
275 CPU_XLR, CPU_XLP, 299 CPU_CAVIUM_OCTEON3, CPU_XLR, CPU_XLP,
276 300
277 CPU_LAST 301 CPU_LAST
278}; 302};
diff --git a/arch/mips/include/asm/cputime.h b/arch/mips/include/asm/cputime.h
deleted file mode 100644
index c00eacbdd979..000000000000
--- a/arch/mips/include/asm/cputime.h
+++ /dev/null
@@ -1,6 +0,0 @@
1#ifndef __MIPS_CPUTIME_H
2#define __MIPS_CPUTIME_H
3
4#include <asm-generic/cputime.h>
5
6#endif /* __MIPS_CPUTIME_H */
diff --git a/arch/mips/include/asm/current.h b/arch/mips/include/asm/current.h
deleted file mode 100644
index 4c51401b5537..000000000000
--- a/arch/mips/include/asm/current.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-generic/current.h>
diff --git a/arch/mips/include/asm/dec/ioasic.h b/arch/mips/include/asm/dec/ioasic.h
index 98badd6bf22d..be4d62a5a10e 100644
--- a/arch/mips/include/asm/dec/ioasic.h
+++ b/arch/mips/include/asm/dec/ioasic.h
@@ -33,6 +33,6 @@ static inline u32 ioasic_read(unsigned int reg)
33 33
34extern void init_ioasic_irqs(int base); 34extern void init_ioasic_irqs(int base);
35 35
36extern void dec_ioasic_clocksource_init(void); 36extern int dec_ioasic_clocksource_init(void);
37 37
38#endif /* __ASM_DEC_IOASIC_H */ 38#endif /* __ASM_DEC_IOASIC_H */
diff --git a/arch/mips/include/asm/dec/ioasic_addrs.h b/arch/mips/include/asm/dec/ioasic_addrs.h
index a8665a7611c2..8bd95971fe2d 100644
--- a/arch/mips/include/asm/dec/ioasic_addrs.h
+++ b/arch/mips/include/asm/dec/ioasic_addrs.h
@@ -40,7 +40,7 @@
40#define IOASIC_FLOPPY (11*IOASIC_SLOT_SIZE) /* FDC (maxine) */ 40#define IOASIC_FLOPPY (11*IOASIC_SLOT_SIZE) /* FDC (maxine) */
41#define IOASIC_SCSI (12*IOASIC_SLOT_SIZE) /* ASC SCSI */ 41#define IOASIC_SCSI (12*IOASIC_SLOT_SIZE) /* ASC SCSI */
42#define IOASIC_FDC_DMA (13*IOASIC_SLOT_SIZE) /* FDC DMA (maxine) */ 42#define IOASIC_FDC_DMA (13*IOASIC_SLOT_SIZE) /* FDC DMA (maxine) */
43#define IOASIC_SCSI_DMA (14*IOASIC_SLOT_SIZE) /* ??? */ 43#define IOASIC_SCSI_DMA (14*IOASIC_SLOT_SIZE) /* ??? */
44#define IOASIC_RES_15 (15*IOASIC_SLOT_SIZE) /* unused? */ 44#define IOASIC_RES_15 (15*IOASIC_SLOT_SIZE) /* unused? */
45 45
46 46
diff --git a/arch/mips/include/asm/dec/kn01.h b/arch/mips/include/asm/dec/kn01.h
index 0eb3241de706..88d9ffd74258 100644
--- a/arch/mips/include/asm/dec/kn01.h
+++ b/arch/mips/include/asm/dec/kn01.h
@@ -57,12 +57,12 @@
57/* 57/*
58 * System Control & Status Register bits. 58 * System Control & Status Register bits.
59 */ 59 */
60#define KN01_CSR_MNFMOD (1<<15) /* MNFMOD manufacturing jumper */ 60#define KN01_CSR_MNFMOD (1<<15) /* MNFMOD manufacturing jumper */
61#define KN01_CSR_STATUS (1<<14) /* self-test result status output */ 61#define KN01_CSR_STATUS (1<<14) /* self-test result status output */
62#define KN01_CSR_PARDIS (1<<13) /* parity error disable */ 62#define KN01_CSR_PARDIS (1<<13) /* parity error disable */
63#define KN01_CSR_CRSRTST (1<<12) /* PCC test output */ 63#define KN01_CSR_CRSRTST (1<<12) /* PCC test output */
64#define KN01_CSR_MONO (1<<11) /* mono/color fb SIMM installed */ 64#define KN01_CSR_MONO (1<<11) /* mono/color fb SIMM installed */
65#define KN01_CSR_MEMERR (1<<10) /* write timeout error status & ack*/ 65#define KN01_CSR_MEMERR (1<<10) /* write timeout error status & ack*/
66#define KN01_CSR_VINT (1<<9) /* PCC area detect #2 status & ack */ 66#define KN01_CSR_VINT (1<<9) /* PCC area detect #2 status & ack */
67#define KN01_CSR_TXDIS (1<<8) /* DZ11 transmit disable */ 67#define KN01_CSR_TXDIS (1<<8) /* DZ11 transmit disable */
68#define KN01_CSR_VBGTRG (1<<2) /* blue DAC voltage over green (r/o) */ 68#define KN01_CSR_VBGTRG (1<<2) /* blue DAC voltage over green (r/o) */
diff --git a/arch/mips/include/asm/dec/kn02ca.h b/arch/mips/include/asm/dec/kn02ca.h
index 69dc2a9a2d0f..92c0fe256099 100644
--- a/arch/mips/include/asm/dec/kn02ca.h
+++ b/arch/mips/include/asm/dec/kn02ca.h
@@ -68,7 +68,7 @@
68#define KN03CA_IO_SSR_ISDN_RST (1<<12) /* ~ISDN (Am79C30A) reset */ 68#define KN03CA_IO_SSR_ISDN_RST (1<<12) /* ~ISDN (Am79C30A) reset */
69 69
70#define KN03CA_IO_SSR_FLOPPY_RST (1<<7) /* ~FDC (82077) reset */ 70#define KN03CA_IO_SSR_FLOPPY_RST (1<<7) /* ~FDC (82077) reset */
71#define KN03CA_IO_SSR_VIDEO_RST (1<<6) /* ~framebuffer reset */ 71#define KN03CA_IO_SSR_VIDEO_RST (1<<6) /* ~framebuffer reset */
72#define KN03CA_IO_SSR_AB_RST (1<<5) /* ACCESS.bus reset */ 72#define KN03CA_IO_SSR_AB_RST (1<<5) /* ACCESS.bus reset */
73#define KN03CA_IO_SSR_RES_4 (1<<4) /* unused */ 73#define KN03CA_IO_SSR_RES_4 (1<<4) /* unused */
74#define KN03CA_IO_SSR_RES_3 (1<<4) /* unused */ 74#define KN03CA_IO_SSR_RES_3 (1<<4) /* unused */
diff --git a/arch/mips/include/asm/dec/prom.h b/arch/mips/include/asm/dec/prom.h
index 446577712bee..c0ead6313845 100644
--- a/arch/mips/include/asm/dec/prom.h
+++ b/arch/mips/include/asm/dec/prom.h
@@ -49,7 +49,7 @@
49 49
50#ifdef CONFIG_64BIT 50#ifdef CONFIG_64BIT
51 51
52#define prom_is_rex(magic) 1 /* KN04 and KN05 are REX PROMs. */ 52#define prom_is_rex(magic) 1 /* KN04 and KN05 are REX PROMs. */
53 53
54#else /* !CONFIG_64BIT */ 54#else /* !CONFIG_64BIT */
55 55
diff --git a/arch/mips/include/asm/elf.h b/arch/mips/include/asm/elf.h
index cf3ae2480b1d..a66359ef4ece 100644
--- a/arch/mips/include/asm/elf.h
+++ b/arch/mips/include/asm/elf.h
@@ -331,6 +331,7 @@ extern int dump_task_fpu(struct task_struct *, elf_fpregset_t *);
331#define ELF_CORE_COPY_FPREGS(tsk, elf_fpregs) \ 331#define ELF_CORE_COPY_FPREGS(tsk, elf_fpregs) \
332 dump_task_fpu(tsk, elf_fpregs) 332 dump_task_fpu(tsk, elf_fpregs)
333 333
334#define CORE_DUMP_USE_REGSET
334#define ELF_EXEC_PAGESIZE PAGE_SIZE 335#define ELF_EXEC_PAGESIZE PAGE_SIZE
335 336
336/* This yields a mask that user programs can use to figure out what 337/* This yields a mask that user programs can use to figure out what
diff --git a/arch/mips/include/asm/emergency-restart.h b/arch/mips/include/asm/emergency-restart.h
deleted file mode 100644
index 108d8c48e42e..000000000000
--- a/arch/mips/include/asm/emergency-restart.h
+++ /dev/null
@@ -1,6 +0,0 @@
1#ifndef _ASM_EMERGENCY_RESTART_H
2#define _ASM_EMERGENCY_RESTART_H
3
4#include <asm-generic/emergency-restart.h>
5
6#endif /* _ASM_EMERGENCY_RESTART_H */
diff --git a/arch/mips/include/asm/jump_label.h b/arch/mips/include/asm/jump_label.h
index 4d6d77ed9b9d..e194f957ca8c 100644
--- a/arch/mips/include/asm/jump_label.h
+++ b/arch/mips/include/asm/jump_label.h
@@ -22,7 +22,7 @@
22 22
23static __always_inline bool arch_static_branch(struct static_key *key) 23static __always_inline bool arch_static_branch(struct static_key *key)
24{ 24{
25 asm goto("1:\tnop\n\t" 25 asm_volatile_goto("1:\tnop\n\t"
26 "nop\n\t" 26 "nop\n\t"
27 ".pushsection __jump_table, \"aw\"\n\t" 27 ".pushsection __jump_table, \"aw\"\n\t"
28 WORD_INSN " 1b, %l[l_yes], %0\n\t" 28 WORD_INSN " 1b, %l[l_yes], %0\n\t"
diff --git a/arch/mips/include/asm/kvm_host.h b/arch/mips/include/asm/kvm_host.h
index 4d6fa0bf1305..32966969f2f9 100644
--- a/arch/mips/include/asm/kvm_host.h
+++ b/arch/mips/include/asm/kvm_host.h
@@ -27,13 +27,6 @@
27 27
28#define KVM_COALESCED_MMIO_PAGE_OFFSET 1 28#define KVM_COALESCED_MMIO_PAGE_OFFSET 1
29 29
30/* Don't support huge pages */
31#define KVM_HPAGE_GFN_SHIFT(x) 0
32
33/* We don't currently support large pages. */
34#define KVM_NR_PAGE_SIZES 1
35#define KVM_PAGES_PER_HPAGE(x) 1
36
37 30
38 31
39/* Special address that contains the comm page, used for reducing # of traps */ 32/* Special address that contains the comm page, used for reducing # of traps */
diff --git a/arch/mips/include/asm/local64.h b/arch/mips/include/asm/local64.h
deleted file mode 100644
index 36c93b5cc239..000000000000
--- a/arch/mips/include/asm/local64.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-generic/local64.h>
diff --git a/arch/mips/include/asm/mach-ath79/ar933x_uart_platform.h b/arch/mips/include/asm/mach-ath79/ar933x_uart_platform.h
deleted file mode 100644
index 6cb30f2b7198..000000000000
--- a/arch/mips/include/asm/mach-ath79/ar933x_uart_platform.h
+++ /dev/null
@@ -1,18 +0,0 @@
1/*
2 * Platform data definition for Atheros AR933X UART
3 *
4 * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 */
10
11#ifndef _AR933X_UART_PLATFORM_H
12#define _AR933X_UART_PLATFORM_H
13
14struct ar933x_uart_platform_data {
15 unsigned uartclk;
16};
17
18#endif /* _AR933X_UART_PLATFORM_H */
diff --git a/arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h
index ddb947e9221f..0089a740e5ae 100644
--- a/arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h
@@ -42,8 +42,6 @@
42#define cpu_has_mips64r1 0 42#define cpu_has_mips64r1 0
43#define cpu_has_mips64r2 0 43#define cpu_has_mips64r2 0
44 44
45#define cpu_has_dsp 0
46#define cpu_has_dsp2 0
47#define cpu_has_mipsmt 0 45#define cpu_has_mipsmt 0
48 46
49#define cpu_has_64bits 0 47#define cpu_has_64bits 0
diff --git a/arch/mips/include/asm/mach-au1x00/au1000.h b/arch/mips/include/asm/mach-au1x00/au1000.h
index 3e11a468cdf8..54f9e84db8ac 100644
--- a/arch/mips/include/asm/mach-au1x00/au1000.h
+++ b/arch/mips/include/asm/mach-au1x00/au1000.h
@@ -43,6 +43,8 @@
43#include <linux/io.h> 43#include <linux/io.h>
44#include <linux/irq.h> 44#include <linux/irq.h>
45 45
46#include <asm/cpu.h>
47
46/* cpu pipeline flush */ 48/* cpu pipeline flush */
47void static inline au_sync(void) 49void static inline au_sync(void)
48{ 50{
@@ -140,7 +142,7 @@ static inline int au1xxx_cpu_needs_config_od(void)
140 142
141static inline int alchemy_get_cputype(void) 143static inline int alchemy_get_cputype(void)
142{ 144{
143 switch (read_c0_prid() & 0xffff0000) { 145 switch (read_c0_prid() & (PRID_OPT_MASK | PRID_COMP_MASK)) {
144 case 0x00030000: 146 case 0x00030000:
145 return ALCHEMY_CPU_AU1000; 147 return ALCHEMY_CPU_AU1000;
146 break; 148 break;
diff --git a/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h b/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h
new file mode 100644
index 000000000000..00867dd05a69
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h
@@ -0,0 +1,110 @@
1#ifndef __BCM47XX_BOARD_H
2#define __BCM47XX_BOARD_H
3
4enum bcm47xx_board {
5 BCM47XX_BOARD_ASUS_RTAC66U,
6 BCM47XX_BOARD_ASUS_RTN10,
7 BCM47XX_BOARD_ASUS_RTN10D,
8 BCM47XX_BOARD_ASUS_RTN10U,
9 BCM47XX_BOARD_ASUS_RTN12,
10 BCM47XX_BOARD_ASUS_RTN12B1,
11 BCM47XX_BOARD_ASUS_RTN12C1,
12 BCM47XX_BOARD_ASUS_RTN12D1,
13 BCM47XX_BOARD_ASUS_RTN12HP,
14 BCM47XX_BOARD_ASUS_RTN15U,
15 BCM47XX_BOARD_ASUS_RTN16,
16 BCM47XX_BOARD_ASUS_RTN53,
17 BCM47XX_BOARD_ASUS_RTN66U,
18 BCM47XX_BOARD_ASUS_WL300G,
19 BCM47XX_BOARD_ASUS_WL320GE,
20 BCM47XX_BOARD_ASUS_WL330GE,
21 BCM47XX_BOARD_ASUS_WL500GD,
22 BCM47XX_BOARD_ASUS_WL500GPV1,
23 BCM47XX_BOARD_ASUS_WL500GPV2,
24 BCM47XX_BOARD_ASUS_WL500W,
25 BCM47XX_BOARD_ASUS_WL520GC,
26 BCM47XX_BOARD_ASUS_WL520GU,
27 BCM47XX_BOARD_ASUS_WL700GE,
28 BCM47XX_BOARD_ASUS_WLHDD,
29
30 BCM47XX_BOARD_BELKIN_F7D4301,
31
32 BCM47XX_BOARD_BUFFALO_WBR2_G54,
33 BCM47XX_BOARD_BUFFALO_WHR2_A54G54,
34 BCM47XX_BOARD_BUFFALO_WHR_G125,
35 BCM47XX_BOARD_BUFFALO_WHR_G54S,
36 BCM47XX_BOARD_BUFFALO_WHR_HP_G54,
37 BCM47XX_BOARD_BUFFALO_WLA2_G54L,
38 BCM47XX_BOARD_BUFFALO_WZR_G300N,
39 BCM47XX_BOARD_BUFFALO_WZR_RS_G54,
40 BCM47XX_BOARD_BUFFALO_WZR_RS_G54HP,
41
42 BCM47XX_BOARD_CISCO_M10V1,
43 BCM47XX_BOARD_CISCO_M20V1,
44
45 BCM47XX_BOARD_DELL_TM2300,
46
47 BCM47XX_BOARD_DLINK_DIR130,
48 BCM47XX_BOARD_DLINK_DIR330,
49
50 BCM47XX_BOARD_HUAWEI_E970,
51
52 BCM47XX_BOARD_LINKSYS_E900V1,
53 BCM47XX_BOARD_LINKSYS_E1000V1,
54 BCM47XX_BOARD_LINKSYS_E1000V2,
55 BCM47XX_BOARD_LINKSYS_E1000V21,
56 BCM47XX_BOARD_LINKSYS_E1200V2,
57 BCM47XX_BOARD_LINKSYS_E2000V1,
58 BCM47XX_BOARD_LINKSYS_E3000V1,
59 BCM47XX_BOARD_LINKSYS_E3200V1,
60 BCM47XX_BOARD_LINKSYS_E4200V1,
61 BCM47XX_BOARD_LINKSYS_WRT150NV1,
62 BCM47XX_BOARD_LINKSYS_WRT150NV11,
63 BCM47XX_BOARD_LINKSYS_WRT160NV1,
64 BCM47XX_BOARD_LINKSYS_WRT160NV3,
65 BCM47XX_BOARD_LINKSYS_WRT300NV11,
66 BCM47XX_BOARD_LINKSYS_WRT310NV1,
67 BCM47XX_BOARD_LINKSYS_WRT310NV2,
68 BCM47XX_BOARD_LINKSYS_WRT54G3GV2,
69 BCM47XX_BOARD_LINKSYS_WRT610NV1,
70 BCM47XX_BOARD_LINKSYS_WRT610NV2,
71 BCM47XX_BOARD_LINKSYS_WRTSL54GS,
72
73 BCM47XX_BOARD_MOTOROLA_WE800G,
74 BCM47XX_BOARD_MOTOROLA_WR850GP,
75 BCM47XX_BOARD_MOTOROLA_WR850GV2V3,
76
77 BCM47XX_BOARD_NETGEAR_WGR614V8,
78 BCM47XX_BOARD_NETGEAR_WGR614V9,
79 BCM47XX_BOARD_NETGEAR_WNDR3300,
80 BCM47XX_BOARD_NETGEAR_WNDR3400V1,
81 BCM47XX_BOARD_NETGEAR_WNDR3400V2,
82 BCM47XX_BOARD_NETGEAR_WNDR3400VCNA,
83 BCM47XX_BOARD_NETGEAR_WNDR3700V3,
84 BCM47XX_BOARD_NETGEAR_WNDR4000,
85 BCM47XX_BOARD_NETGEAR_WNDR4500V1,
86 BCM47XX_BOARD_NETGEAR_WNDR4500V2,
87 BCM47XX_BOARD_NETGEAR_WNR2000,
88 BCM47XX_BOARD_NETGEAR_WNR3500L,
89 BCM47XX_BOARD_NETGEAR_WNR3500U,
90 BCM47XX_BOARD_NETGEAR_WNR3500V2,
91 BCM47XX_BOARD_NETGEAR_WNR3500V2VC,
92 BCM47XX_BOARD_NETGEAR_WNR834BV2,
93
94 BCM47XX_BOARD_PHICOMM_M1,
95
96 BCM47XX_BOARD_SIMPLETECH_SIMPLESHARE,
97
98 BCM47XX_BOARD_ZTE_H218N,
99
100 BCM47XX_BOARD_UNKNOWN,
101 BCM47XX_BOARD_NO,
102};
103
104#define BCM47XX_BOARD_MAX_NAME 30
105
106void bcm47xx_board_detect(void);
107enum bcm47xx_board bcm47xx_board_get(void);
108const char *bcm47xx_board_get_name(void);
109
110#endif /* __BCM47XX_BOARD_H */
diff --git a/arch/mips/include/asm/mach-bcm47xx/bcm47xx_nvram.h b/arch/mips/include/asm/mach-bcm47xx/bcm47xx_nvram.h
index b8e7be8f34dd..36a3fc1aa3ae 100644
--- a/arch/mips/include/asm/mach-bcm47xx/bcm47xx_nvram.h
+++ b/arch/mips/include/asm/mach-bcm47xx/bcm47xx_nvram.h
@@ -48,4 +48,6 @@ static inline void bcm47xx_nvram_parse_macaddr(char *buf, u8 macaddr[6])
48 printk(KERN_WARNING "Can not parse mac address: %s\n", buf); 48 printk(KERN_WARNING "Can not parse mac address: %s\n", buf);
49} 49}
50 50
51int bcm47xx_nvram_gpio_pin(const char *name);
52
51#endif /* __BCM47XX_NVRAM_H */ 53#endif /* __BCM47XX_NVRAM_H */
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_nvram.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_nvram.h
index 4e0b6bc1165e..348df49dcc9f 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_nvram.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_nvram.h
@@ -30,4 +30,6 @@ u8 *bcm63xx_nvram_get_name(void);
30 */ 30 */
31int bcm63xx_nvram_get_mac_address(u8 *mac); 31int bcm63xx_nvram_get_mac_address(u8 *mac);
32 32
33int bcm63xx_nvram_get_psi_size(void);
34
33#endif /* BCM63XX_NVRAM_H */ 35#endif /* BCM63XX_NVRAM_H */
diff --git a/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h b/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h
index 47fb247f9663..f9f448650505 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h
@@ -52,23 +52,11 @@ static inline int plat_dma_supported(struct device *dev, u64 mask)
52 return 0; 52 return 0;
53} 53}
54 54
55static inline void plat_extra_sync_for_device(struct device *dev)
56{
57 BUG();
58}
59
60static inline int plat_device_is_coherent(struct device *dev) 55static inline int plat_device_is_coherent(struct device *dev)
61{ 56{
62 return 1; 57 return 1;
63} 58}
64 59
65static inline int plat_dma_mapping_error(struct device *dev,
66 dma_addr_t dma_addr)
67{
68 BUG();
69 return 0;
70}
71
72dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr); 60dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr);
73phys_addr_t dma_to_phys(struct device *dev, dma_addr_t daddr); 61phys_addr_t dma_to_phys(struct device *dev, dma_addr_t daddr);
74 62
diff --git a/arch/mips/include/asm/mach-cavium-octeon/gpio.h b/arch/mips/include/asm/mach-cavium-octeon/gpio.h
new file mode 100644
index 000000000000..34e9f7aabab4
--- /dev/null
+++ b/arch/mips/include/asm/mach-cavium-octeon/gpio.h
@@ -0,0 +1,21 @@
1#ifndef __ASM_MACH_CAVIUM_OCTEON_GPIO_H
2#define __ASM_MACH_CAVIUM_OCTEON_GPIO_H
3
4#ifdef CONFIG_GPIOLIB
5#define gpio_get_value __gpio_get_value
6#define gpio_set_value __gpio_set_value
7#define gpio_cansleep __gpio_cansleep
8#else
9int gpio_request(unsigned gpio, const char *label);
10void gpio_free(unsigned gpio);
11int gpio_direction_input(unsigned gpio);
12int gpio_direction_output(unsigned gpio, int value);
13int gpio_get_value(unsigned gpio);
14void gpio_set_value(unsigned gpio, int value);
15#endif
16
17#include <asm-generic/gpio.h>
18
19#define gpio_to_irq __gpio_to_irq
20
21#endif /* __ASM_MACH_GENERIC_GPIO_H */
diff --git a/arch/mips/include/asm/mach-dec/cpu-feature-overrides.h b/arch/mips/include/asm/mach-dec/cpu-feature-overrides.h
new file mode 100644
index 000000000000..acce27fd2bb8
--- /dev/null
+++ b/arch/mips/include/asm/mach-dec/cpu-feature-overrides.h
@@ -0,0 +1,87 @@
1/*
2 * CPU feature overrides for DECstation systems. Two variations
3 * are generally applicable.
4 *
5 * Copyright (C) 2013 Maciej W. Rozycki
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
11 */
12#ifndef __ASM_MACH_DEC_CPU_FEATURE_OVERRIDES_H
13#define __ASM_MACH_DEC_CPU_FEATURE_OVERRIDES_H
14
15/* Generic ones first. */
16#define cpu_has_tlb 1
17#define cpu_has_tx39_cache 0
18#define cpu_has_fpu 1
19#define cpu_has_divec 0
20#define cpu_has_prefetch 0
21#define cpu_has_mcheck 0
22#define cpu_has_ejtag 0
23#define cpu_has_mips16 0
24#define cpu_has_mdmx 0
25#define cpu_has_mips3d 0
26#define cpu_has_smartmips 0
27#define cpu_has_rixi 0
28#define cpu_has_vtag_icache 0
29#define cpu_has_ic_fills_f_dc 0
30#define cpu_has_pindexed_dcache 0
31#define cpu_has_local_ebase 0
32#define cpu_icache_snoops_remote_store 1
33#define cpu_has_mips_4 0
34#define cpu_has_mips_5 0
35#define cpu_has_mips32r1 0
36#define cpu_has_mips32r2 0
37#define cpu_has_mips64r1 0
38#define cpu_has_mips64r2 0
39#define cpu_has_dsp 0
40#define cpu_has_mipsmt 0
41#define cpu_has_userlocal 0
42
43/* R3k-specific ones. */
44#ifdef CONFIG_CPU_R3000
45#define cpu_has_4kex 0
46#define cpu_has_3k_cache 1
47#define cpu_has_4k_cache 0
48#define cpu_has_32fpr 0
49#define cpu_has_counter 0
50#define cpu_has_watch 0
51#define cpu_has_vce 0
52#define cpu_has_cache_cdex_p 0
53#define cpu_has_cache_cdex_s 0
54#define cpu_has_llsc 0
55#define cpu_has_dc_aliases 0
56#define cpu_has_mips_2 0
57#define cpu_has_mips_3 0
58#define cpu_has_nofpuex 1
59#define cpu_has_inclusive_pcaches 0
60#define cpu_dcache_line_size() 4
61#define cpu_icache_line_size() 4
62#define cpu_scache_line_size() 0
63#endif /* CONFIG_CPU_R3000 */
64
65/* R4k-specific ones. */
66#ifdef CONFIG_CPU_R4X00
67#define cpu_has_4kex 1
68#define cpu_has_3k_cache 0
69#define cpu_has_4k_cache 1
70#define cpu_has_32fpr 1
71#define cpu_has_counter 1
72#define cpu_has_watch 1
73#define cpu_has_vce 1
74#define cpu_has_cache_cdex_p 1
75#define cpu_has_cache_cdex_s 1
76#define cpu_has_llsc 1
77#define cpu_has_dc_aliases (PAGE_SIZE < 0x4000)
78#define cpu_has_mips_2 1
79#define cpu_has_mips_3 1
80#define cpu_has_nofpuex 0
81#define cpu_has_inclusive_pcaches 1
82#define cpu_dcache_line_size() 16
83#define cpu_icache_line_size() 16
84#define cpu_scache_line_size() 32
85#endif /* CONFIG_CPU_R4X00 */
86
87#endif /* __ASM_MACH_DEC_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mach-generic/dma-coherence.h b/arch/mips/include/asm/mach-generic/dma-coherence.h
index 74cb99257d5b..a9e8f6b62b0b 100644
--- a/arch/mips/include/asm/mach-generic/dma-coherence.h
+++ b/arch/mips/include/asm/mach-generic/dma-coherence.h
@@ -47,16 +47,6 @@ static inline int plat_dma_supported(struct device *dev, u64 mask)
47 return 1; 47 return 1;
48} 48}
49 49
50static inline void plat_extra_sync_for_device(struct device *dev)
51{
52}
53
54static inline int plat_dma_mapping_error(struct device *dev,
55 dma_addr_t dma_addr)
56{
57 return 0;
58}
59
60static inline int plat_device_is_coherent(struct device *dev) 50static inline int plat_device_is_coherent(struct device *dev)
61{ 51{
62#ifdef CONFIG_DMA_COHERENT 52#ifdef CONFIG_DMA_COHERENT
diff --git a/arch/mips/include/asm/mach-ip22/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ip22/cpu-feature-overrides.h
index f4caacd25552..1bcb6421205e 100644
--- a/arch/mips/include/asm/mach-ip22/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-ip22/cpu-feature-overrides.h
@@ -8,6 +8,8 @@
8#ifndef __ASM_MACH_IP22_CPU_FEATURE_OVERRIDES_H 8#ifndef __ASM_MACH_IP22_CPU_FEATURE_OVERRIDES_H
9#define __ASM_MACH_IP22_CPU_FEATURE_OVERRIDES_H 9#define __ASM_MACH_IP22_CPU_FEATURE_OVERRIDES_H
10 10
11#include <asm/cpu.h>
12
11/* 13/*
12 * IP22 with a variety of processors so we can't use defaults for everything. 14 * IP22 with a variety of processors so we can't use defaults for everything.
13 */ 15 */
diff --git a/arch/mips/include/asm/mach-ip27/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ip27/cpu-feature-overrides.h
index 1d2b6ff60d33..d6111aa2e886 100644
--- a/arch/mips/include/asm/mach-ip27/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-ip27/cpu-feature-overrides.h
@@ -8,6 +8,8 @@
8#ifndef __ASM_MACH_IP27_CPU_FEATURE_OVERRIDES_H 8#ifndef __ASM_MACH_IP27_CPU_FEATURE_OVERRIDES_H
9#define __ASM_MACH_IP27_CPU_FEATURE_OVERRIDES_H 9#define __ASM_MACH_IP27_CPU_FEATURE_OVERRIDES_H
10 10
11#include <asm/cpu.h>
12
11/* 13/*
12 * IP27 only comes with R10000 family processors all using the same config 14 * IP27 only comes with R10000 family processors all using the same config
13 */ 15 */
diff --git a/arch/mips/include/asm/mach-ip27/dma-coherence.h b/arch/mips/include/asm/mach-ip27/dma-coherence.h
index 06c441968e6e..4ffddfdb5062 100644
--- a/arch/mips/include/asm/mach-ip27/dma-coherence.h
+++ b/arch/mips/include/asm/mach-ip27/dma-coherence.h
@@ -58,16 +58,6 @@ static inline int plat_dma_supported(struct device *dev, u64 mask)
58 return 1; 58 return 1;
59} 59}
60 60
61static inline void plat_extra_sync_for_device(struct device *dev)
62{
63}
64
65static inline int plat_dma_mapping_error(struct device *dev,
66 dma_addr_t dma_addr)
67{
68 return 0;
69}
70
71static inline int plat_device_is_coherent(struct device *dev) 61static inline int plat_device_is_coherent(struct device *dev)
72{ 62{
73 return 1; /* IP27 non-cohernet mode is unsupported */ 63 return 1; /* IP27 non-cohernet mode is unsupported */
diff --git a/arch/mips/include/asm/mach-ip28/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ip28/cpu-feature-overrides.h
index 65e9c856390d..4cec06d133db 100644
--- a/arch/mips/include/asm/mach-ip28/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-ip28/cpu-feature-overrides.h
@@ -9,6 +9,8 @@
9#ifndef __ASM_MACH_IP28_CPU_FEATURE_OVERRIDES_H 9#ifndef __ASM_MACH_IP28_CPU_FEATURE_OVERRIDES_H
10#define __ASM_MACH_IP28_CPU_FEATURE_OVERRIDES_H 10#define __ASM_MACH_IP28_CPU_FEATURE_OVERRIDES_H
11 11
12#include <asm/cpu.h>
13
12/* 14/*
13 * IP28 only comes with R10000 family processors all using the same config 15 * IP28 only comes with R10000 family processors all using the same config
14 */ 16 */
diff --git a/arch/mips/include/asm/mach-ip32/dma-coherence.h b/arch/mips/include/asm/mach-ip32/dma-coherence.h
index 073f0c4760ba..104cfbc3ed63 100644
--- a/arch/mips/include/asm/mach-ip32/dma-coherence.h
+++ b/arch/mips/include/asm/mach-ip32/dma-coherence.h
@@ -80,17 +80,6 @@ static inline int plat_dma_supported(struct device *dev, u64 mask)
80 return 1; 80 return 1;
81} 81}
82 82
83static inline void plat_extra_sync_for_device(struct device *dev)
84{
85 return;
86}
87
88static inline int plat_dma_mapping_error(struct device *dev,
89 dma_addr_t dma_addr)
90{
91 return 0;
92}
93
94static inline int plat_device_is_coherent(struct device *dev) 83static inline int plat_device_is_coherent(struct device *dev)
95{ 84{
96 return 0; /* IP32 is non-cohernet */ 85 return 0; /* IP32 is non-cohernet */
diff --git a/arch/mips/include/asm/mach-jazz/dma-coherence.h b/arch/mips/include/asm/mach-jazz/dma-coherence.h
index 9fc1e9ad7038..949003ef97b3 100644
--- a/arch/mips/include/asm/mach-jazz/dma-coherence.h
+++ b/arch/mips/include/asm/mach-jazz/dma-coherence.h
@@ -48,16 +48,6 @@ static inline int plat_dma_supported(struct device *dev, u64 mask)
48 return 1; 48 return 1;
49} 49}
50 50
51static inline void plat_extra_sync_for_device(struct device *dev)
52{
53}
54
55static inline int plat_dma_mapping_error(struct device *dev,
56 dma_addr_t dma_addr)
57{
58 return 0;
59}
60
61static inline int plat_device_is_coherent(struct device *dev) 51static inline int plat_device_is_coherent(struct device *dev)
62{ 52{
63 return 0; 53 return 0;
diff --git a/arch/mips/include/asm/mach-lantiq/falcon/cpu-feature-overrides.h b/arch/mips/include/asm/mach-lantiq/falcon/cpu-feature-overrides.h
new file mode 100644
index 000000000000..096a10072430
--- /dev/null
+++ b/arch/mips/include/asm/mach-lantiq/falcon/cpu-feature-overrides.h
@@ -0,0 +1,58 @@
1/*
2 * Lantiq FALCON specific CPU feature overrides
3 *
4 * Copyright (C) 2013 Thomas Langer, Lantiq Deutschland
5 *
6 * This file was derived from: include/asm-mips/cpu-features.h
7 * Copyright (C) 2003, 2004 Ralf Baechle
8 * Copyright (C) 2004 Maciej W. Rozycki
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published
12 * by the Free Software Foundation.
13 *
14 */
15#ifndef __ASM_MACH_FALCON_CPU_FEATURE_OVERRIDES_H
16#define __ASM_MACH_FALCON_CPU_FEATURE_OVERRIDES_H
17
18#define cpu_has_tlb 1
19#define cpu_has_4kex 1
20#define cpu_has_3k_cache 0
21#define cpu_has_4k_cache 1
22#define cpu_has_tx39_cache 0
23#define cpu_has_sb1_cache 0
24#define cpu_has_fpu 0
25#define cpu_has_32fpr 0
26#define cpu_has_counter 1
27#define cpu_has_watch 1
28#define cpu_has_divec 1
29
30#define cpu_has_prefetch 1
31#define cpu_has_ejtag 1
32#define cpu_has_llsc 1
33
34#define cpu_has_mips16 1
35#define cpu_has_mdmx 0
36#define cpu_has_mips3d 0
37#define cpu_has_smartmips 0
38
39#define cpu_has_mips32r1 1
40#define cpu_has_mips32r2 1
41#define cpu_has_mips64r1 0
42#define cpu_has_mips64r2 0
43
44#define cpu_has_dsp 1
45#define cpu_has_mipsmt 1
46
47#define cpu_has_vint 1
48#define cpu_has_veic 1
49
50#define cpu_has_64bits 0
51#define cpu_has_64bit_zero_reg 0
52#define cpu_has_64bit_gp_regs 0
53#define cpu_has_64bit_addresses 0
54
55#define cpu_dcache_line_size() 32
56#define cpu_icache_line_size() 32
57
58#endif /* __ASM_MACH_FALCON_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mach-loongson/dma-coherence.h b/arch/mips/include/asm/mach-loongson/dma-coherence.h
index e1433055fe98..aeb2c05d6145 100644
--- a/arch/mips/include/asm/mach-loongson/dma-coherence.h
+++ b/arch/mips/include/asm/mach-loongson/dma-coherence.h
@@ -53,16 +53,6 @@ static inline int plat_dma_supported(struct device *dev, u64 mask)
53 return 1; 53 return 1;
54} 54}
55 55
56static inline void plat_extra_sync_for_device(struct device *dev)
57{
58}
59
60static inline int plat_dma_mapping_error(struct device *dev,
61 dma_addr_t dma_addr)
62{
63 return 0;
64}
65
66static inline int plat_device_is_coherent(struct device *dev) 56static inline int plat_device_is_coherent(struct device *dev)
67{ 57{
68 return 0; 58 return 0;
diff --git a/arch/mips/include/asm/mach-powertv/asic.h b/arch/mips/include/asm/mach-powertv/asic.h
deleted file mode 100644
index b341108d12f1..000000000000
--- a/arch/mips/include/asm/mach-powertv/asic.h
+++ /dev/null
@@ -1,120 +0,0 @@
1/*
2 * Copyright (C) 2009 Cisco Systems, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
17 */
18
19#ifndef _ASM_MACH_POWERTV_ASIC_H
20#define _ASM_MACH_POWERTV_ASIC_H
21
22#include <linux/ioport.h>
23#include <linux/platform_device.h>
24#include <asm/mach-powertv/asic_regs.h>
25
26#define DVR_CAPABLE (1<<0)
27#define PCIE_CAPABLE (1<<1)
28#define FFS_CAPABLE (1<<2)
29#define DISPLAY_CAPABLE (1<<3)
30
31/* Platform Family types
32 * For compitability, the new value must be added in the end */
33enum family_type {
34 FAMILY_8500,
35 FAMILY_8500RNG,
36 FAMILY_4500,
37 FAMILY_1500,
38 FAMILY_8600,
39 FAMILY_4600,
40 FAMILY_4600VZA,
41 FAMILY_8600VZB,
42 FAMILY_1500VZE,
43 FAMILY_1500VZF,
44 FAMILY_8700,
45 FAMILIES
46};
47
48/* Register maps for each ASIC */
49extern const struct register_map calliope_register_map;
50extern const struct register_map cronus_register_map;
51extern const struct register_map gaia_register_map;
52extern const struct register_map zeus_register_map;
53
54extern struct resource dvr_cronus_resources[];
55extern struct resource dvr_gaia_resources[];
56extern struct resource dvr_zeus_resources[];
57extern struct resource non_dvr_calliope_resources[];
58extern struct resource non_dvr_cronus_resources[];
59extern struct resource non_dvr_cronuslite_resources[];
60extern struct resource non_dvr_gaia_resources[];
61extern struct resource non_dvr_vz_calliope_resources[];
62extern struct resource non_dvr_vze_calliope_resources[];
63extern struct resource non_dvr_vzf_calliope_resources[];
64extern struct resource non_dvr_zeus_resources[];
65
66extern void powertv_platform_init(void);
67extern void platform_alloc_bootmem(void);
68extern enum asic_type platform_get_asic(void);
69extern enum family_type platform_get_family(void);
70extern int platform_supports_dvr(void);
71extern int platform_supports_ffs(void);
72extern int platform_supports_pcie(void);
73extern int platform_supports_display(void);
74extern void configure_platform(void);
75
76/* Platform Resources */
77#define ASIC_RESOURCE_GET_EXISTS 1
78extern struct resource *asic_resource_get(const char *name);
79extern void platform_release_memory(void *baddr, int size);
80
81/* USB configuration */
82struct usb_hcd; /* Forward reference */
83extern void platform_configure_usb_ehci(void);
84extern void platform_unconfigure_usb_ehci(void);
85extern void platform_configure_usb_ohci(void);
86extern void platform_unconfigure_usb_ohci(void);
87
88/* Resource for ASIC registers */
89extern struct resource asic_resource;
90extern int platform_usb_devices_init(struct platform_device **echi_dev,
91 struct platform_device **ohci_dev);
92
93/* Reboot Cause */
94extern void set_reboot_cause(char code, unsigned int data, unsigned int data2);
95extern void set_locked_reboot_cause(char code, unsigned int data,
96 unsigned int data2);
97
98enum sys_reboot_type {
99 sys_unknown_reboot = 0x00, /* Unknown reboot cause */
100 sys_davic_change = 0x01, /* Reboot due to change in DAVIC
101 * mode */
102 sys_user_reboot = 0x02, /* Reboot initiated by user */
103 sys_system_reboot = 0x03, /* Reboot initiated by OS */
104 sys_trap_reboot = 0x04, /* Reboot due to a CPU trap */
105 sys_silent_reboot = 0x05, /* Silent reboot */
106 sys_boot_ldr_reboot = 0x06, /* Bootloader reboot */
107 sys_power_up_reboot = 0x07, /* Power on bootup. Older
108 * drivers may report as
109 * userReboot. */
110 sys_code_change = 0x08, /* Reboot to take code change.
111 * Older drivers may report as
112 * userReboot. */
113 sys_hardware_reset = 0x09, /* HW watchdog or front-panel
114 * reset button reset. Older
115 * drivers may report as
116 * userReboot. */
117 sys_watchdogInterrupt = 0x0A /* Pre-watchdog interrupt */
118};
119
120#endif /* _ASM_MACH_POWERTV_ASIC_H */
diff --git a/arch/mips/include/asm/mach-powertv/asic_reg_map.h b/arch/mips/include/asm/mach-powertv/asic_reg_map.h
deleted file mode 100644
index 20348e817b09..000000000000
--- a/arch/mips/include/asm/mach-powertv/asic_reg_map.h
+++ /dev/null
@@ -1,90 +0,0 @@
1/*
2 * asic_reg_map.h
3 *
4 * A macro-enclosed list of the elements for the register_map structure for
5 * use in defining and manipulating the structure.
6 *
7 * Copyright (C) 2009 Cisco Systems, Inc.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 */
23
24REGISTER_MAP_ELEMENT(eic_slow0_strt_add)
25REGISTER_MAP_ELEMENT(eic_cfg_bits)
26REGISTER_MAP_ELEMENT(eic_ready_status)
27REGISTER_MAP_ELEMENT(chipver3)
28REGISTER_MAP_ELEMENT(chipver2)
29REGISTER_MAP_ELEMENT(chipver1)
30REGISTER_MAP_ELEMENT(chipver0)
31REGISTER_MAP_ELEMENT(uart1_intstat)
32REGISTER_MAP_ELEMENT(uart1_inten)
33REGISTER_MAP_ELEMENT(uart1_config1)
34REGISTER_MAP_ELEMENT(uart1_config2)
35REGISTER_MAP_ELEMENT(uart1_divisorhi)
36REGISTER_MAP_ELEMENT(uart1_divisorlo)
37REGISTER_MAP_ELEMENT(uart1_data)
38REGISTER_MAP_ELEMENT(uart1_status)
39REGISTER_MAP_ELEMENT(int_stat_3)
40REGISTER_MAP_ELEMENT(int_stat_2)
41REGISTER_MAP_ELEMENT(int_stat_1)
42REGISTER_MAP_ELEMENT(int_stat_0)
43REGISTER_MAP_ELEMENT(int_config)
44REGISTER_MAP_ELEMENT(int_int_scan)
45REGISTER_MAP_ELEMENT(ien_int_3)
46REGISTER_MAP_ELEMENT(ien_int_2)
47REGISTER_MAP_ELEMENT(ien_int_1)
48REGISTER_MAP_ELEMENT(ien_int_0)
49REGISTER_MAP_ELEMENT(int_level_3_3)
50REGISTER_MAP_ELEMENT(int_level_3_2)
51REGISTER_MAP_ELEMENT(int_level_3_1)
52REGISTER_MAP_ELEMENT(int_level_3_0)
53REGISTER_MAP_ELEMENT(int_level_2_3)
54REGISTER_MAP_ELEMENT(int_level_2_2)
55REGISTER_MAP_ELEMENT(int_level_2_1)
56REGISTER_MAP_ELEMENT(int_level_2_0)
57REGISTER_MAP_ELEMENT(int_level_1_3)
58REGISTER_MAP_ELEMENT(int_level_1_2)
59REGISTER_MAP_ELEMENT(int_level_1_1)
60REGISTER_MAP_ELEMENT(int_level_1_0)
61REGISTER_MAP_ELEMENT(int_level_0_3)
62REGISTER_MAP_ELEMENT(int_level_0_2)
63REGISTER_MAP_ELEMENT(int_level_0_1)
64REGISTER_MAP_ELEMENT(int_level_0_0)
65REGISTER_MAP_ELEMENT(int_docsis_en)
66REGISTER_MAP_ELEMENT(mips_pll_setup)
67REGISTER_MAP_ELEMENT(fs432x4b4_usb_ctl)
68REGISTER_MAP_ELEMENT(test_bus)
69REGISTER_MAP_ELEMENT(crt_spare)
70REGISTER_MAP_ELEMENT(usb2_ohci_int_mask)
71REGISTER_MAP_ELEMENT(usb2_strap)
72REGISTER_MAP_ELEMENT(ehci_hcapbase)
73REGISTER_MAP_ELEMENT(ohci_hc_revision)
74REGISTER_MAP_ELEMENT(bcm1_bs_lmi_steer)
75REGISTER_MAP_ELEMENT(usb2_control)
76REGISTER_MAP_ELEMENT(usb2_stbus_obc)
77REGISTER_MAP_ELEMENT(usb2_stbus_mess_size)
78REGISTER_MAP_ELEMENT(usb2_stbus_chunk_size)
79REGISTER_MAP_ELEMENT(pcie_regs)
80REGISTER_MAP_ELEMENT(tim_ch)
81REGISTER_MAP_ELEMENT(tim_cl)
82REGISTER_MAP_ELEMENT(gpio_dout)
83REGISTER_MAP_ELEMENT(gpio_din)
84REGISTER_MAP_ELEMENT(gpio_dir)
85REGISTER_MAP_ELEMENT(watchdog)
86REGISTER_MAP_ELEMENT(front_panel)
87REGISTER_MAP_ELEMENT(misc_clk_ctl1)
88REGISTER_MAP_ELEMENT(misc_clk_ctl2)
89REGISTER_MAP_ELEMENT(crt_ext_ctl)
90REGISTER_MAP_ELEMENT(register_maps)
diff --git a/arch/mips/include/asm/mach-powertv/asic_regs.h b/arch/mips/include/asm/mach-powertv/asic_regs.h
deleted file mode 100644
index 06712abb3e55..000000000000
--- a/arch/mips/include/asm/mach-powertv/asic_regs.h
+++ /dev/null
@@ -1,125 +0,0 @@
1/*
2 * Copyright (C) 2009 Cisco Systems, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
17 */
18
19#ifndef __ASM_MACH_POWERTV_ASIC_H_
20#define __ASM_MACH_POWERTV_ASIC_H_
21#include <linux/io.h>
22
23/* ASIC types */
24enum asic_type {
25 ASIC_UNKNOWN,
26 ASIC_ZEUS,
27 ASIC_CALLIOPE,
28 ASIC_CRONUS,
29 ASIC_CRONUSLITE,
30 ASIC_GAIA,
31 ASICS /* Number of supported ASICs */
32};
33
34/* hardcoded values read from Chip Version registers */
35#define CRONUS_10 0x0B4C1C20
36#define CRONUS_11 0x0B4C1C21
37#define CRONUSLITE_10 0x0B4C1C40
38
39#define NAND_FLASH_BASE 0x03000000
40#define CALLIOPE_IO_BASE 0x08000000
41#define GAIA_IO_BASE 0x09000000
42#define CRONUS_IO_BASE 0x09000000
43#define ZEUS_IO_BASE 0x09000000
44
45#define ASIC_IO_SIZE 0x01000000
46
47/* Definitions for backward compatibility */
48#define UART1_INTSTAT uart1_intstat
49#define UART1_INTEN uart1_inten
50#define UART1_CONFIG1 uart1_config1
51#define UART1_CONFIG2 uart1_config2
52#define UART1_DIVISORHI uart1_divisorhi
53#define UART1_DIVISORLO uart1_divisorlo
54#define UART1_DATA uart1_data
55#define UART1_STATUS uart1_status
56
57/* ASIC register enumeration */
58union register_map_entry {
59 unsigned long phys;
60 u32 *virt;
61};
62
63#define REGISTER_MAP_ELEMENT(x) union register_map_entry x;
64struct register_map {
65#include <asm/mach-powertv/asic_reg_map.h>
66};
67#undef REGISTER_MAP_ELEMENT
68
69/**
70 * register_map_offset_phys - add an offset to the physical address
71 * @map: Pointer to the &struct register_map
72 * @offset: Value to add
73 *
74 * Only adds the base to non-zero physical addresses
75 */
76static inline void register_map_offset_phys(struct register_map *map,
77 unsigned long offset)
78{
79#define REGISTER_MAP_ELEMENT(x) do { \
80 if (map->x.phys != 0) \
81 map->x.phys += offset; \
82 } while (false);
83
84#include <asm/mach-powertv/asic_reg_map.h>
85#undef REGISTER_MAP_ELEMENT
86}
87
88/**
89 * register_map_virtualize - Convert &register_map to virtual addresses
90 * @map: Pointer to &register_map to virtualize
91 */
92static inline void register_map_virtualize(struct register_map *map)
93{
94#define REGISTER_MAP_ELEMENT(x) do { \
95 map->x.virt = (!map->x.phys) ? NULL : \
96 UNCAC_ADDR(phys_to_virt(map->x.phys)); \
97 } while (false);
98
99#include <asm/mach-powertv/asic_reg_map.h>
100#undef REGISTER_MAP_ELEMENT
101}
102
103extern struct register_map _asic_register_map;
104extern unsigned long asic_phy_base;
105
106/*
107 * Macros to interface to registers through their ioremapped address
108 * asic_reg_phys_addr Returns the physical address of the given register
109 * asic_reg_addr Returns the iomapped virtual address of the given
110 * register.
111 */
112#define asic_reg_addr(x) (_asic_register_map.x.virt)
113#define asic_reg_phys_addr(x) (virt_to_phys((void *) CAC_ADDR( \
114 (unsigned long) asic_reg_addr(x))))
115
116/*
117 * The asic_reg macro is gone. It should be replaced by either asic_read or
118 * asic_write, as appropriate.
119 */
120
121#define asic_read(x) readl(asic_reg_addr(x))
122#define asic_write(v, x) writel(v, asic_reg_addr(x))
123
124extern void asic_irq_init(void);
125#endif
diff --git a/arch/mips/include/asm/mach-powertv/cpu-feature-overrides.h b/arch/mips/include/asm/mach-powertv/cpu-feature-overrides.h
deleted file mode 100644
index 58c76ec32a19..000000000000
--- a/arch/mips/include/asm/mach-powertv/cpu-feature-overrides.h
+++ /dev/null
@@ -1,60 +0,0 @@
1/*
2 * Copyright (C) 2010 Cisco Systems, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
17 */
18
19#ifndef _ASM_MACH_POWERTV_CPU_FEATURE_OVERRIDES_H_
20#define _ASM_MACH_POWERTV_CPU_FEATURE_OVERRIDES_H_
21#define cpu_has_tlb 1
22#define cpu_has_4kex 1
23#define cpu_has_3k_cache 0
24#define cpu_has_4k_cache 1
25#define cpu_has_tx39_cache 0
26#define cpu_has_fpu 0
27#define cpu_has_counter 1
28#define cpu_has_watch 1
29#define cpu_has_divec 1
30#define cpu_has_vce 0
31#define cpu_has_cache_cdex_p 0
32#define cpu_has_cache_cdex_s 0
33#define cpu_has_mcheck 1
34#define cpu_has_ejtag 1
35#define cpu_has_llsc 1
36#define cpu_has_mips16 0
37#define cpu_has_mdmx 0
38#define cpu_has_mips3d 0
39#define cpu_has_smartmips 0
40#define cpu_has_vtag_icache 0
41#define cpu_has_dc_aliases 0
42#define cpu_has_ic_fills_f_dc 0
43#define cpu_has_mips32r1 0
44#define cpu_has_mips32r2 1
45#define cpu_has_mips64r1 0
46#define cpu_has_mips64r2 0
47#define cpu_has_dsp 0
48#define cpu_has_dsp2 0
49#define cpu_has_mipsmt 0
50#define cpu_has_userlocal 0
51#define cpu_has_nofpuex 0
52#define cpu_has_64bits 0
53#define cpu_has_64bit_zero_reg 0
54#define cpu_has_vint 1
55#define cpu_has_veic 1
56#define cpu_has_inclusive_pcaches 0
57
58#define cpu_dcache_line_size() 32
59#define cpu_icache_line_size() 32
60#endif
diff --git a/arch/mips/include/asm/mach-powertv/dma-coherence.h b/arch/mips/include/asm/mach-powertv/dma-coherence.h
deleted file mode 100644
index f8316720a218..000000000000
--- a/arch/mips/include/asm/mach-powertv/dma-coherence.h
+++ /dev/null
@@ -1,117 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Version from mach-generic modified to support PowerTV port
7 * Portions Copyright (C) 2009 Cisco Systems, Inc.
8 * Copyright (C) 2006 Ralf Baechle <ralf@linux-mips.org>
9 *
10 */
11
12#ifndef __ASM_MACH_POWERTV_DMA_COHERENCE_H
13#define __ASM_MACH_POWERTV_DMA_COHERENCE_H
14
15#include <linux/sched.h>
16#include <linux/device.h>
17#include <asm/mach-powertv/asic.h>
18
19static inline bool is_kseg2(void *addr)
20{
21 return (unsigned long)addr >= KSEG2;
22}
23
24static inline unsigned long virt_to_phys_from_pte(void *addr)
25{
26 pgd_t *pgd;
27 pud_t *pud;
28 pmd_t *pmd;
29 pte_t *ptep, pte;
30
31 unsigned long virt_addr = (unsigned long)addr;
32 unsigned long phys_addr = 0UL;
33
34 /* get the page global directory. */
35 pgd = pgd_offset_k(virt_addr);
36
37 if (!pgd_none(*pgd)) {
38 /* get the page upper directory */
39 pud = pud_offset(pgd, virt_addr);
40 if (!pud_none(*pud)) {
41 /* get the page middle directory */
42 pmd = pmd_offset(pud, virt_addr);
43 if (!pmd_none(*pmd)) {
44 /* get a pointer to the page table entry */
45 ptep = pte_offset(pmd, virt_addr);
46 pte = *ptep;
47 /* check for a valid page */
48 if (pte_present(pte)) {
49 /* get the physical address the page is
50 * referring to */
51 phys_addr = (unsigned long)
52 page_to_phys(pte_page(pte));
53 /* add the offset within the page */
54 phys_addr |= (virt_addr & ~PAGE_MASK);
55 }
56 }
57 }
58 }
59
60 return phys_addr;
61}
62
63static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr,
64 size_t size)
65{
66 if (is_kseg2(addr))
67 return phys_to_dma(virt_to_phys_from_pte(addr));
68 else
69 return phys_to_dma(virt_to_phys(addr));
70}
71
72static inline dma_addr_t plat_map_dma_mem_page(struct device *dev,
73 struct page *page)
74{
75 return phys_to_dma(page_to_phys(page));
76}
77
78static inline unsigned long plat_dma_addr_to_phys(struct device *dev,
79 dma_addr_t dma_addr)
80{
81 return dma_to_phys(dma_addr);
82}
83
84static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr,
85 size_t size, enum dma_data_direction direction)
86{
87}
88
89static inline int plat_dma_supported(struct device *dev, u64 mask)
90{
91 /*
92 * we fall back to GFP_DMA when the mask isn't all 1s,
93 * so we can't guarantee allocations that must be
94 * within a tighter range than GFP_DMA..
95 */
96 if (mask < DMA_BIT_MASK(24))
97 return 0;
98
99 return 1;
100}
101
102static inline void plat_extra_sync_for_device(struct device *dev)
103{
104}
105
106static inline int plat_dma_mapping_error(struct device *dev,
107 dma_addr_t dma_addr)
108{
109 return 0;
110}
111
112static inline int plat_device_is_coherent(struct device *dev)
113{
114 return 0;
115}
116
117#endif /* __ASM_MACH_POWERTV_DMA_COHERENCE_H */
diff --git a/arch/mips/include/asm/mach-powertv/interrupts.h b/arch/mips/include/asm/mach-powertv/interrupts.h
deleted file mode 100644
index 6c463be62156..000000000000
--- a/arch/mips/include/asm/mach-powertv/interrupts.h
+++ /dev/null
@@ -1,253 +0,0 @@
1/*
2 * Copyright (C) 2009 Cisco Systems, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
17 */
18
19#ifndef _ASM_MACH_POWERTV_INTERRUPTS_H_
20#define _ASM_MACH_POWERTV_INTERRUPTS_H_
21
22/*
23 * Defines for all of the interrupt lines
24 */
25
26/* Definitions for backward compatibility */
27#define kIrq_Uart1 irq_uart1
28
29#define ibase 0
30
31/*------------- Register: int_stat_3 */
32/* 126 unused (bit 31) */
33#define irq_asc2video (ibase+126) /* ASC 2 Video Interrupt */
34#define irq_asc1video (ibase+125) /* ASC 1 Video Interrupt */
35#define irq_comms_block_wd (ibase+124) /* ASC 1 Video Interrupt */
36#define irq_fdma_mailbox (ibase+123) /* FDMA Mailbox Output */
37#define irq_fdma_gp (ibase+122) /* FDMA GP Output */
38#define irq_mips_pic (ibase+121) /* MIPS Performance Counter
39 * Interrupt */
40#define irq_mips_timer (ibase+120) /* MIPS Timer Interrupt */
41#define irq_memory_protect (ibase+119) /* Memory Protection Interrupt
42 * -- Ored by glue logic inside
43 * SPARC ILC (see
44 * INT_MEM_PROT_STAT, below,
45 * for individual interrupts)
46 */
47/* 118 unused (bit 22) */
48#define irq_sbag (ibase+117) /* SBAG Interrupt -- Ored by
49 * glue logic inside SPARC ILC
50 * (see INT_SBAG_STAT, below,
51 * for individual interrupts) */
52#define irq_qam_b_fec (ibase+116) /* QAM B FEC Interrupt */
53#define irq_qam_a_fec (ibase+115) /* QAM A FEC Interrupt */
54/* 114 unused (bit 18) */
55#define irq_mailbox (ibase+113) /* Mailbox Debug Interrupt --
56 * Ored by glue logic inside
57 * SPARC ILC (see
58 * INT_MAILBOX_STAT, below, for
59 * individual interrupts) */
60#define irq_fuse_stat1 (ibase+112) /* Fuse Status 1 */
61#define irq_fuse_stat2 (ibase+111) /* Fuse Status 2 */
62#define irq_fuse_stat3 (ibase+110) /* Blitter Interrupt / Fuse
63 * Status 3 */
64#define irq_blitter (ibase+110) /* Blitter Interrupt / Fuse
65 * Status 3 */
66#define irq_avc1_pp0 (ibase+109) /* AVC Decoder #1 PP0
67 * Interrupt */
68#define irq_avc1_pp1 (ibase+108) /* AVC Decoder #1 PP1
69 * Interrupt */
70#define irq_avc1_mbe (ibase+107) /* AVC Decoder #1 MBE
71 * Interrupt */
72#define irq_avc2_pp0 (ibase+106) /* AVC Decoder #2 PP0
73 * Interrupt */
74#define irq_avc2_pp1 (ibase+105) /* AVC Decoder #2 PP1
75 * Interrupt */
76#define irq_avc2_mbe (ibase+104) /* AVC Decoder #2 MBE
77 * Interrupt */
78#define irq_zbug_spi (ibase+103) /* Zbug SPI Slave Interrupt */
79#define irq_qam_mod2 (ibase+102) /* QAM Modulator 2 DMA
80 * Interrupt */
81#define irq_ir_rx (ibase+101) /* IR RX 2 Interrupt */
82#define irq_aud_dsp2 (ibase+100) /* Audio DSP #2 Interrupt */
83#define irq_aud_dsp1 (ibase+99) /* Audio DSP #1 Interrupt */
84#define irq_docsis (ibase+98) /* DOCSIS Debug Interrupt */
85#define irq_sd_dvp1 (ibase+97) /* SD DVP #1 Interrupt */
86#define irq_sd_dvp2 (ibase+96) /* SD DVP #2 Interrupt */
87/*------------- Register: int_stat_2 */
88#define irq_hd_dvp (ibase+95) /* HD DVP Interrupt */
89#define kIrq_Prewatchdog (ibase+94) /* watchdog Pre-Interrupt */
90#define irq_timer2 (ibase+93) /* Programmable Timer
91 * Interrupt 2 */
92#define irq_1394 (ibase+92) /* 1394 Firewire Interrupt */
93#define irq_usbohci (ibase+91) /* USB 2.0 OHCI Interrupt */
94#define irq_usbehci (ibase+90) /* USB 2.0 EHCI Interrupt */
95#define irq_pciexp (ibase+89) /* PCI Express 0 Interrupt */
96#define irq_pciexp0 (ibase+89) /* PCI Express 0 Interrupt */
97#define irq_afe1 (ibase+88) /* AFE 1 Interrupt */
98#define irq_sata (ibase+87) /* SATA 1 Interrupt */
99#define irq_sata1 (ibase+87) /* SATA 1 Interrupt */
100#define irq_dtcp (ibase+86) /* DTCP Interrupt */
101#define irq_pciexp1 (ibase+85) /* PCI Express 1 Interrupt */
102/* 84 unused (bit 20) */
103/* 83 unused (bit 19) */
104/* 82 unused (bit 18) */
105#define irq_sata2 (ibase+81) /* SATA2 Interrupt */
106#define irq_uart2 (ibase+80) /* UART2 Interrupt */
107#define irq_legacy_usb (ibase+79) /* Legacy USB Host ISR (1.1
108 * Host module) */
109#define irq_pod (ibase+78) /* POD Interrupt */
110#define irq_slave_usb (ibase+77) /* Slave USB */
111#define irq_denc1 (ibase+76) /* DENC #1 VTG Interrupt */
112#define irq_vbi_vtg (ibase+75) /* VBI VTG Interrupt */
113#define irq_afe2 (ibase+74) /* AFE 2 Interrupt */
114#define irq_denc2 (ibase+73) /* DENC #2 VTG Interrupt */
115#define irq_asc2 (ibase+72) /* ASC #2 Interrupt */
116#define irq_asc1 (ibase+71) /* ASC #1 Interrupt */
117#define irq_mod_dma (ibase+70) /* Modulator DMA Interrupt */
118#define irq_byte_eng1 (ibase+69) /* Byte Engine Interrupt [1] */
119#define irq_byte_eng0 (ibase+68) /* Byte Engine Interrupt [0] */
120/* 67 unused (bit 03) */
121/* 66 unused (bit 02) */
122/* 65 unused (bit 01) */
123/* 64 unused (bit 00) */
124/*------------- Register: int_stat_1 */
125/* 63 unused (bit 31) */
126/* 62 unused (bit 30) */
127/* 61 unused (bit 29) */
128/* 60 unused (bit 28) */
129/* 59 unused (bit 27) */
130/* 58 unused (bit 26) */
131/* 57 unused (bit 25) */
132/* 56 unused (bit 24) */
133#define irq_buf_dma_mem2mem (ibase+55) /* BufDMA Memory to Memory
134 * Interrupt */
135#define irq_buf_dma_usbtransmit (ibase+54) /* BufDMA USB Transmit
136 * Interrupt */
137#define irq_buf_dma_qpskpodtransmit (ibase+53) /* BufDMA QPSK/POD Tramsit
138 * Interrupt */
139#define irq_buf_dma_transmit_error (ibase+52) /* BufDMA Transmit Error
140 * Interrupt */
141#define irq_buf_dma_usbrecv (ibase+51) /* BufDMA USB Receive
142 * Interrupt */
143#define irq_buf_dma_qpskpodrecv (ibase+50) /* BufDMA QPSK/POD Receive
144 * Interrupt */
145#define irq_buf_dma_recv_error (ibase+49) /* BufDMA Receive Error
146 * Interrupt */
147#define irq_qamdma_transmit_play (ibase+48) /* QAMDMA Transmit/Play
148 * Interrupt */
149#define irq_qamdma_transmit_error (ibase+47) /* QAMDMA Transmit Error
150 * Interrupt */
151#define irq_qamdma_recv2high (ibase+46) /* QAMDMA Receive 2 High
152 * (Chans 63-32) */
153#define irq_qamdma_recv2low (ibase+45) /* QAMDMA Receive 2 Low
154 * (Chans 31-0) */
155#define irq_qamdma_recv1high (ibase+44) /* QAMDMA Receive 1 High
156 * (Chans 63-32) */
157#define irq_qamdma_recv1low (ibase+43) /* QAMDMA Receive 1 Low
158 * (Chans 31-0) */
159#define irq_qamdma_recv_error (ibase+42) /* QAMDMA Receive Error
160 * Interrupt */
161#define irq_mpegsplice (ibase+41) /* MPEG Splice Interrupt */
162#define irq_deinterlace_rdy (ibase+40) /* Deinterlacer Frame Ready
163 * Interrupt */
164#define irq_ext_in0 (ibase+39) /* External Interrupt irq_in0 */
165#define irq_gpio3 (ibase+38) /* GP I/O IRQ 3 - From GP I/O
166 * Module */
167#define irq_gpio2 (ibase+37) /* GP I/O IRQ 2 - From GP I/O
168 * Module (ABE_intN) */
169#define irq_pcrcmplt1 (ibase+36) /* PCR Capture Complete or
170 * Discontinuity 1 */
171#define irq_pcrcmplt2 (ibase+35) /* PCR Capture Complete or
172 * Discontinuity 2 */
173#define irq_parse_peierr (ibase+34) /* PID Parser Error Detect
174 * (PEI) */
175#define irq_parse_cont_err (ibase+33) /* PID Parser continuity error
176 * detect */
177#define irq_ds1framer (ibase+32) /* DS1 Framer Interrupt */
178/*------------- Register: int_stat_0 */
179#define irq_gpio1 (ibase+31) /* GP I/O IRQ 1 - From GP I/O
180 * Module */
181#define irq_gpio0 (ibase+30) /* GP I/O IRQ 0 - From GP I/O
182 * Module */
183#define irq_qpsk_out_aloha (ibase+29) /* QPSK Output Slotted Aloha
184 * (chan 3) Transmission
185 * Completed OK */
186#define irq_qpsk_out_tdma (ibase+28) /* QPSK Output TDMA (chan 2)
187 * Transmission Completed OK */
188#define irq_qpsk_out_reserve (ibase+27) /* QPSK Output Reservation
189 * (chan 1) Transmission
190 * Completed OK */
191#define irq_qpsk_out_aloha_err (ibase+26) /* QPSK Output Slotted Aloha
192 * (chan 3)Transmission
193 * completed with Errors. */
194#define irq_qpsk_out_tdma_err (ibase+25) /* QPSK Output TDMA (chan 2)
195 * Transmission completed with
196 * Errors. */
197#define irq_qpsk_out_rsrv_err (ibase+24) /* QPSK Output Reservation
198 * (chan 1) Transmission
199 * completed with Errors */
200#define irq_aloha_fail (ibase+23) /* Unsuccessful Resend of Aloha
201 * for N times. Aloha retry
202 * timeout for channel 3. */
203#define irq_timer1 (ibase+22) /* Programmable Timer
204 * Interrupt */
205#define irq_keyboard (ibase+21) /* Keyboard Module Interrupt */
206#define irq_i2c (ibase+20) /* I2C Module Interrupt */
207#define irq_spi (ibase+19) /* SPI Module Interrupt */
208#define irq_irblaster (ibase+18) /* IR Blaster Interrupt */
209#define irq_splice_detect (ibase+17) /* PID Key Change Interrupt or
210 * Splice Detect Interrupt */
211#define irq_se_micro (ibase+16) /* Secure Micro I/F Module
212 * Interrupt */
213#define irq_uart1 (ibase+15) /* UART Interrupt */
214#define irq_irrecv (ibase+14) /* IR Receiver Interrupt */
215#define irq_host_int1 (ibase+13) /* Host-to-Host Interrupt 1 */
216#define irq_host_int0 (ibase+12) /* Host-to-Host Interrupt 0 */
217#define irq_qpsk_hecerr (ibase+11) /* QPSK HEC Error Interrupt */
218#define irq_qpsk_crcerr (ibase+10) /* QPSK AAL-5 CRC Error
219 * Interrupt */
220/* 9 unused (bit 09) */
221/* 8 unused (bit 08) */
222#define irq_psicrcerr (ibase+7) /* QAM PSI CRC Error
223 * Interrupt */
224#define irq_psilength_err (ibase+6) /* QAM PSI Length Error
225 * Interrupt */
226#define irq_esfforward (ibase+5) /* ESF Interrupt Mark From
227 * Forward Path Reference -
228 * every 3ms when forward Mbits
229 * and forward slot control
230 * bytes are updated. */
231#define irq_esfreverse (ibase+4) /* ESF Interrupt Mark from
232 * Reverse Path Reference -
233 * delayed from forward mark by
234 * the ranging delay plus a
235 * fixed amount. When reverse
236 * Mbits and reverse slot
237 * control bytes are updated.
238 * Occurs every 3ms for 3.0M and
239 * 1.554 M upstream rates and
240 * every 6 ms for 256K upstream
241 * rate. */
242#define irq_aloha_timeout (ibase+3) /* Slotted-Aloha timeout on
243 * Channel 1. */
244#define irq_reservation (ibase+2) /* Partial (or Incremental)
245 * Reservation Message Completed
246 * or Slotted aloha verify for
247 * channel 1. */
248#define irq_aloha3 (ibase+1) /* Slotted-Aloha Message Verify
249 * Interrupt or Reservation
250 * increment completed for
251 * channel 3. */
252#define irq_mpeg_d (ibase+0) /* MPEG Decoder Interrupt */
253#endif /* _ASM_MACH_POWERTV_INTERRUPTS_H_ */
diff --git a/arch/mips/include/asm/mach-powertv/ioremap.h b/arch/mips/include/asm/mach-powertv/ioremap.h
deleted file mode 100644
index c86ef094ec37..000000000000
--- a/arch/mips/include/asm/mach-powertv/ioremap.h
+++ /dev/null
@@ -1,167 +0,0 @@
1/*
2 * This program is free software; you can redistribute it and/or
3 * modify it under the terms of the GNU General Public License
4 * as published by the Free Software Foundation; either version
5 * 2 of the License, or (at your option) any later version.
6 *
7 * Portions Copyright (C) Cisco Systems, Inc.
8 */
9#ifndef __ASM_MACH_POWERTV_IOREMAP_H
10#define __ASM_MACH_POWERTV_IOREMAP_H
11
12#include <linux/types.h>
13#include <linux/log2.h>
14#include <linux/compiler.h>
15
16#include <asm/pgtable-bits.h>
17#include <asm/addrspace.h>
18
19/* We're going to mess with bits, so get sizes */
20#define IOR_BPC 8 /* Bits per char */
21#define IOR_PHYS_BITS (IOR_BPC * sizeof(phys_addr_t))
22#define IOR_DMA_BITS (IOR_BPC * sizeof(dma_addr_t))
23
24/*
25 * Define the granularity of physical/DMA mapping in terms of the number
26 * of bits that defines the offset within a grain. These will be the
27 * least significant bits of the address. The rest of a physical or DMA
28 * address will be used to index into an appropriate table to find the
29 * offset to add to the address to yield the corresponding DMA or physical
30 * address, respectively.
31 */
32#define IOR_LSBITS 22 /* Bits in a grain */
33
34/*
35 * Compute the number of most significant address bits after removing those
36 * used for the offset within a grain and then compute the number of table
37 * entries for the conversion.
38 */
39#define IOR_PHYS_MSBITS (IOR_PHYS_BITS - IOR_LSBITS)
40#define IOR_NUM_PHYS_TO_DMA ((phys_addr_t) 1 << IOR_PHYS_MSBITS)
41
42#define IOR_DMA_MSBITS (IOR_DMA_BITS - IOR_LSBITS)
43#define IOR_NUM_DMA_TO_PHYS ((dma_addr_t) 1 << IOR_DMA_MSBITS)
44
45/*
46 * Define data structures used as elements in the arrays for the conversion
47 * between physical and DMA addresses. We do some slightly fancy math to
48 * compute the width of the offset element of the conversion tables so
49 * that we can have the smallest conversion tables. Next, round up the
50 * sizes to the next higher power of two, i.e. the offset element will have
51 * 8, 16, 32, 64, etc. bits. This eliminates the need to mask off any
52 * bits. Finally, we compute a shift value that puts the most significant
53 * bits of the offset into the most significant bits of the offset element.
54 * This makes it more efficient on processors without barrel shifters and
55 * easier to see the values if the conversion table is dumped in binary.
56 */
57#define _IOR_OFFSET_WIDTH(n) (1 << order_base_2(n))
58#define IOR_OFFSET_WIDTH(n) \
59 (_IOR_OFFSET_WIDTH(n) < 8 ? 8 : _IOR_OFFSET_WIDTH(n))
60
61#define IOR_PHYS_OFFSET_BITS IOR_OFFSET_WIDTH(IOR_PHYS_MSBITS)
62#define IOR_PHYS_SHIFT (IOR_PHYS_BITS - IOR_PHYS_OFFSET_BITS)
63
64#define IOR_DMA_OFFSET_BITS IOR_OFFSET_WIDTH(IOR_DMA_MSBITS)
65#define IOR_DMA_SHIFT (IOR_DMA_BITS - IOR_DMA_OFFSET_BITS)
66
67struct ior_phys_to_dma {
68 dma_addr_t offset:IOR_DMA_OFFSET_BITS __packed
69 __aligned((IOR_DMA_OFFSET_BITS / IOR_BPC));
70};
71
72struct ior_dma_to_phys {
73 dma_addr_t offset:IOR_PHYS_OFFSET_BITS __packed
74 __aligned((IOR_PHYS_OFFSET_BITS / IOR_BPC));
75};
76
77extern struct ior_phys_to_dma _ior_phys_to_dma[IOR_NUM_PHYS_TO_DMA];
78extern struct ior_dma_to_phys _ior_dma_to_phys[IOR_NUM_DMA_TO_PHYS];
79
80static inline dma_addr_t _phys_to_dma_offset_raw(phys_addr_t phys)
81{
82 return (dma_addr_t)_ior_phys_to_dma[phys >> IOR_LSBITS].offset;
83}
84
85static inline dma_addr_t _dma_to_phys_offset_raw(dma_addr_t dma)
86{
87 return (dma_addr_t)_ior_dma_to_phys[dma >> IOR_LSBITS].offset;
88}
89
90/* These are not portable and should not be used in drivers. Drivers should
91 * be using ioremap() and friends to map physical addresses to virtual
92 * addresses and dma_map*() and friends to map virtual addresses into DMA
93 * addresses and back.
94 */
95static inline dma_addr_t phys_to_dma(phys_addr_t phys)
96{
97 return phys + (_phys_to_dma_offset_raw(phys) << IOR_PHYS_SHIFT);
98}
99
100static inline phys_addr_t dma_to_phys(dma_addr_t dma)
101{
102 return dma + (_dma_to_phys_offset_raw(dma) << IOR_DMA_SHIFT);
103}
104
105extern void ioremap_add_map(dma_addr_t phys, phys_addr_t alias,
106 dma_addr_t size);
107
108/*
109 * Allow physical addresses to be fixed up to help peripherals located
110 * outside the low 32-bit range -- generic pass-through version.
111 */
112static inline phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size)
113{
114 return phys_addr;
115}
116
117/*
118 * Handle the special case of addresses the area aliased into the first
119 * 512 MiB of the processor's physical address space. These turn into either
120 * kseg0 or kseg1 addresses, depending on flags.
121 */
122static inline void __iomem *plat_ioremap(phys_t start, unsigned long size,
123 unsigned long flags)
124{
125 phys_addr_t start_offset;
126 void __iomem *result = NULL;
127
128 /* Start by checking to see whether this is an aliased address */
129 start_offset = _dma_to_phys_offset_raw(start);
130
131 /*
132 * If:
133 * o the memory is aliased into the first 512 MiB, and
134 * o the start and end are in the same RAM bank, and
135 * o we don't have a zero size or wrap around, and
136 * o we are supposed to create an uncached mapping,
137 * handle this is a kseg0 or kseg1 address
138 */
139 if (start_offset != 0) {
140 phys_addr_t last;
141 dma_addr_t dma_to_phys_offset;
142
143 last = start + size - 1;
144 dma_to_phys_offset =
145 _dma_to_phys_offset_raw(last) << IOR_DMA_SHIFT;
146
147 if (dma_to_phys_offset == start_offset &&
148 size != 0 && start <= last) {
149 phys_t adjusted_start;
150 adjusted_start = start + start_offset;
151 if (flags == _CACHE_UNCACHED)
152 result = (void __iomem *) (unsigned long)
153 CKSEG1ADDR(adjusted_start);
154 else
155 result = (void __iomem *) (unsigned long)
156 CKSEG0ADDR(adjusted_start);
157 }
158 }
159
160 return result;
161}
162
163static inline int plat_iounmap(const volatile void __iomem *addr)
164{
165 return 0;
166}
167#endif /* __ASM_MACH_POWERTV_IOREMAP_H */
diff --git a/arch/mips/include/asm/mach-powertv/irq.h b/arch/mips/include/asm/mach-powertv/irq.h
deleted file mode 100644
index 4bd5d0c61a91..000000000000
--- a/arch/mips/include/asm/mach-powertv/irq.h
+++ /dev/null
@@ -1,25 +0,0 @@
1/*
2 * Copyright (C) 2009 Cisco Systems, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
17 */
18
19#ifndef _ASM_MACH_POWERTV_IRQ_H
20#define _ASM_MACH_POWERTV_IRQ_H
21#include <asm/mach-powertv/interrupts.h>
22
23#define MIPS_CPU_IRQ_BASE ibase
24#define NR_IRQS 127
25#endif
diff --git a/arch/mips/include/asm/mach-powertv/powertv-clock.h b/arch/mips/include/asm/mach-powertv/powertv-clock.h
deleted file mode 100644
index 6f3e9a0fcf8c..000000000000
--- a/arch/mips/include/asm/mach-powertv/powertv-clock.h
+++ /dev/null
@@ -1,29 +0,0 @@
1/*
2 * Copyright (C) 2009 Cisco Systems, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
17 */
18/*
19 * Local definitions for the powertv PCI code
20 */
21
22#ifndef _POWERTV_PCI_POWERTV_PCI_H_
23#define _POWERTV_PCI_POWERTV_PCI_H_
24extern int asic_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
25extern int asic_pcie_init(void);
26extern int asic_pcie_init(void);
27
28extern int log_level;
29#endif
diff --git a/arch/mips/include/asm/mach-powertv/war.h b/arch/mips/include/asm/mach-powertv/war.h
deleted file mode 100644
index c5651c8e58d1..000000000000
--- a/arch/mips/include/asm/mach-powertv/war.h
+++ /dev/null
@@ -1,27 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * This version for the PowerTV platform copied from the Malta version.
7 *
8 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
9 * Portions copyright (C) 2009 Cisco Systems, Inc.
10 */
11#ifndef __ASM_MACH_POWERTV_WAR_H
12#define __ASM_MACH_POWERTV_WAR_H
13
14#define R4600_V1_INDEX_ICACHEOP_WAR 0
15#define R4600_V1_HIT_CACHEOP_WAR 0
16#define R4600_V2_HIT_CACHEOP_WAR 0
17#define R5432_CP0_INTERRUPT_WAR 0
18#define BCM1250_M3_WAR 0
19#define SIBYTE_1956_WAR 0
20#define MIPS4K_ICACHE_REFILL_WAR 1
21#define MIPS_CACHE_SYNC_WAR 1
22#define TX49XX_ICACHE_INDEX_INV_WAR 0
23#define ICACHE_REFILLS_WORKAROUND_WAR 1
24#define R10000_LLSC_WAR 0
25#define MIPS34K_MISSED_ITLB_WAR 0
26
27#endif /* __ASM_MACH_POWERTV_WAR_H */
diff --git a/arch/mips/include/asm/mach-ralink/mt7620.h b/arch/mips/include/asm/mach-ralink/mt7620.h
index 9809972ea882..6f9b24f51157 100644
--- a/arch/mips/include/asm/mach-ralink/mt7620.h
+++ b/arch/mips/include/asm/mach-ralink/mt7620.h
@@ -20,6 +20,8 @@
20#define SYSC_REG_CHIP_REV 0x0c 20#define SYSC_REG_CHIP_REV 0x0c
21#define SYSC_REG_SYSTEM_CONFIG0 0x10 21#define SYSC_REG_SYSTEM_CONFIG0 0x10
22#define SYSC_REG_SYSTEM_CONFIG1 0x14 22#define SYSC_REG_SYSTEM_CONFIG1 0x14
23#define SYSC_REG_CLKCFG0 0x2c
24#define SYSC_REG_CPU_SYS_CLKCFG 0x3c
23#define SYSC_REG_CPLL_CONFIG0 0x54 25#define SYSC_REG_CPLL_CONFIG0 0x54
24#define SYSC_REG_CPLL_CONFIG1 0x58 26#define SYSC_REG_CPLL_CONFIG1 0x58
25 27
@@ -29,20 +31,42 @@
29#define MT7620A_CHIP_NAME0 0x3637544d 31#define MT7620A_CHIP_NAME0 0x3637544d
30#define MT7620A_CHIP_NAME1 0x20203032 32#define MT7620A_CHIP_NAME1 0x20203032
31 33
34#define SYSCFG0_XTAL_FREQ_SEL BIT(6)
35
32#define CHIP_REV_PKG_MASK 0x1 36#define CHIP_REV_PKG_MASK 0x1
33#define CHIP_REV_PKG_SHIFT 16 37#define CHIP_REV_PKG_SHIFT 16
34#define CHIP_REV_VER_MASK 0xf 38#define CHIP_REV_VER_MASK 0xf
35#define CHIP_REV_VER_SHIFT 8 39#define CHIP_REV_VER_SHIFT 8
36#define CHIP_REV_ECO_MASK 0xf 40#define CHIP_REV_ECO_MASK 0xf
37 41
38#define CPLL_SW_CONFIG_SHIFT 31 42#define CLKCFG0_PERI_CLK_SEL BIT(4)
39#define CPLL_SW_CONFIG_MASK 0x1 43
40#define CPLL_CPU_CLK_SHIFT 24 44#define CPU_SYS_CLKCFG_OCP_RATIO_SHIFT 16
41#define CPLL_CPU_CLK_MASK 0x1 45#define CPU_SYS_CLKCFG_OCP_RATIO_MASK 0xf
42#define CPLL_MULT_RATIO_SHIFT 16 46#define CPU_SYS_CLKCFG_OCP_RATIO_1 0 /* 1:1 (Reserved) */
43#define CPLL_MULT_RATIO 0x7 47#define CPU_SYS_CLKCFG_OCP_RATIO_1_5 1 /* 1:1.5 (Reserved) */
44#define CPLL_DIV_RATIO_SHIFT 10 48#define CPU_SYS_CLKCFG_OCP_RATIO_2 2 /* 1:2 */
45#define CPLL_DIV_RATIO 0x3 49#define CPU_SYS_CLKCFG_OCP_RATIO_2_5 3 /* 1:2.5 (Reserved) */
50#define CPU_SYS_CLKCFG_OCP_RATIO_3 4 /* 1:3 */
51#define CPU_SYS_CLKCFG_OCP_RATIO_3_5 5 /* 1:3.5 (Reserved) */
52#define CPU_SYS_CLKCFG_OCP_RATIO_4 6 /* 1:4 */
53#define CPU_SYS_CLKCFG_OCP_RATIO_5 7 /* 1:5 */
54#define CPU_SYS_CLKCFG_OCP_RATIO_10 8 /* 1:10 */
55#define CPU_SYS_CLKCFG_CPU_FDIV_SHIFT 8
56#define CPU_SYS_CLKCFG_CPU_FDIV_MASK 0x1f
57#define CPU_SYS_CLKCFG_CPU_FFRAC_SHIFT 0
58#define CPU_SYS_CLKCFG_CPU_FFRAC_MASK 0x1f
59
60#define CPLL_CFG0_SW_CFG BIT(31)
61#define CPLL_CFG0_PLL_MULT_RATIO_SHIFT 16
62#define CPLL_CFG0_PLL_MULT_RATIO_MASK 0x7
63#define CPLL_CFG0_LC_CURFCK BIT(15)
64#define CPLL_CFG0_BYPASS_REF_CLK BIT(14)
65#define CPLL_CFG0_PLL_DIV_RATIO_SHIFT 10
66#define CPLL_CFG0_PLL_DIV_RATIO_MASK 0x3
67
68#define CPLL_CFG1_CPU_AUX1 BIT(25)
69#define CPLL_CFG1_CPU_AUX0 BIT(24)
46 70
47#define SYSCFG0_DRAM_TYPE_MASK 0x3 71#define SYSCFG0_DRAM_TYPE_MASK 0x3
48#define SYSCFG0_DRAM_TYPE_SHIFT 4 72#define SYSCFG0_DRAM_TYPE_SHIFT 4
diff --git a/arch/mips/include/asm/mach-ralink/mt7620/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ralink/mt7620/cpu-feature-overrides.h
new file mode 100644
index 000000000000..f7bb8cfc5eb1
--- /dev/null
+++ b/arch/mips/include/asm/mach-ralink/mt7620/cpu-feature-overrides.h
@@ -0,0 +1,57 @@
1/*
2 * Ralink MT7620 specific CPU feature overrides
3 *
4 * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 *
7 * This file was derived from: include/asm-mips/cpu-features.h
8 * Copyright (C) 2003, 2004 Ralf Baechle
9 * Copyright (C) 2004 Maciej W. Rozycki
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License version 2 as published
13 * by the Free Software Foundation.
14 *
15 */
16#ifndef _MT7620_CPU_FEATURE_OVERRIDES_H
17#define _MT7620_CPU_FEATURE_OVERRIDES_H
18
19#define cpu_has_tlb 1
20#define cpu_has_4kex 1
21#define cpu_has_3k_cache 0
22#define cpu_has_4k_cache 1
23#define cpu_has_tx39_cache 0
24#define cpu_has_sb1_cache 0
25#define cpu_has_fpu 0
26#define cpu_has_32fpr 0
27#define cpu_has_counter 1
28#define cpu_has_watch 1
29#define cpu_has_divec 1
30
31#define cpu_has_prefetch 1
32#define cpu_has_ejtag 1
33#define cpu_has_llsc 1
34
35#define cpu_has_mips16 1
36#define cpu_has_mdmx 0
37#define cpu_has_mips3d 0
38#define cpu_has_smartmips 0
39
40#define cpu_has_mips32r1 1
41#define cpu_has_mips32r2 1
42#define cpu_has_mips64r1 0
43#define cpu_has_mips64r2 0
44
45#define cpu_has_dsp 1
46#define cpu_has_dsp2 0
47#define cpu_has_mipsmt 0
48
49#define cpu_has_64bits 0
50#define cpu_has_64bit_zero_reg 0
51#define cpu_has_64bit_gp_regs 0
52#define cpu_has_64bit_addresses 0
53
54#define cpu_dcache_line_size() 32
55#define cpu_icache_line_size() 32
56
57#endif /* _MT7620_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mips-boards/piix4.h b/arch/mips/include/asm/mips-boards/piix4.h
index a02596cf1abd..e33227998713 100644
--- a/arch/mips/include/asm/mips-boards/piix4.h
+++ b/arch/mips/include/asm/mips-boards/piix4.h
@@ -1,6 +1,7 @@
1/* 1/*
2 * Carsten Langgaard, carstenl@mips.com 2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. 3 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
4 * Copyright (C) 2013 Imagination Technologies Ltd.
4 * 5 *
5 * This program is free software; you can distribute it and/or modify it 6 * This program is free software; you can distribute it and/or modify it
6 * under the terms of the GNU General Public License (Version 2) as 7 * under the terms of the GNU General Public License (Version 2) as
@@ -20,61 +21,26 @@
20#ifndef __ASM_MIPS_BOARDS_PIIX4_H 21#ifndef __ASM_MIPS_BOARDS_PIIX4_H
21#define __ASM_MIPS_BOARDS_PIIX4_H 22#define __ASM_MIPS_BOARDS_PIIX4_H
22 23
23/************************************************************************ 24/* PIRQX Route Control */
24 * IO register offsets 25#define PIIX4_FUNC0_PIRQRC 0x60
25 ************************************************************************/ 26#define PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_DISABLE (1 << 7)
26#define PIIX4_ICTLR1_ICW1 0x20 27#define PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_MASK 0xf
27#define PIIX4_ICTLR1_ICW2 0x21 28#define PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_MAX 16
28#define PIIX4_ICTLR1_ICW3 0x21 29/* Top Of Memory */
29#define PIIX4_ICTLR1_ICW4 0x21 30#define PIIX4_FUNC0_TOM 0x69
30#define PIIX4_ICTLR2_ICW1 0xa0 31#define PIIX4_FUNC0_TOM_TOP_OF_MEMORY_MASK 0xf0
31#define PIIX4_ICTLR2_ICW2 0xa1 32/* Deterministic Latency Control */
32#define PIIX4_ICTLR2_ICW3 0xa1 33#define PIIX4_FUNC0_DLC 0x82
33#define PIIX4_ICTLR2_ICW4 0xa1 34#define PIIX4_FUNC0_DLC_USBPR_EN (1 << 2)
34#define PIIX4_ICTLR1_OCW1 0x21 35#define PIIX4_FUNC0_DLC_PASSIVE_RELEASE_EN (1 << 1)
35#define PIIX4_ICTLR1_OCW2 0x20 36#define PIIX4_FUNC0_DLC_DELAYED_TRANSACTION_EN (1 << 0)
36#define PIIX4_ICTLR1_OCW3 0x20 37
37#define PIIX4_ICTLR1_OCW4 0x20 38/* IDE Timing */
38#define PIIX4_ICTLR2_OCW1 0xa1 39#define PIIX4_FUNC1_IDETIM_PRIMARY_LO 0x40
39#define PIIX4_ICTLR2_OCW2 0xa0 40#define PIIX4_FUNC1_IDETIM_PRIMARY_HI 0x41
40#define PIIX4_ICTLR2_OCW3 0xa0 41#define PIIX4_FUNC1_IDETIM_PRIMARY_HI_IDE_DECODE_EN (1 << 7)
41#define PIIX4_ICTLR2_OCW4 0xa0 42#define PIIX4_FUNC1_IDETIM_SECONDARY_LO 0x42
42 43#define PIIX4_FUNC1_IDETIM_SECONDARY_HI 0x43
43 44#define PIIX4_FUNC1_IDETIM_SECONDARY_HI_IDE_DECODE_EN (1 << 7)
44/************************************************************************
45 * Register encodings.
46 ************************************************************************/
47#define PIIX4_OCW2_NSEOI (0x1 << 5)
48#define PIIX4_OCW2_SEOI (0x3 << 5)
49#define PIIX4_OCW2_RNSEOI (0x5 << 5)
50#define PIIX4_OCW2_RAEOIS (0x4 << 5)
51#define PIIX4_OCW2_RAEOIC (0x0 << 5)
52#define PIIX4_OCW2_RSEOI (0x7 << 5)
53#define PIIX4_OCW2_SP (0x6 << 5)
54#define PIIX4_OCW2_NOP (0x2 << 5)
55
56#define PIIX4_OCW2_SEL (0x0 << 3)
57
58#define PIIX4_OCW2_ILS_0 0
59#define PIIX4_OCW2_ILS_1 1
60#define PIIX4_OCW2_ILS_2 2
61#define PIIX4_OCW2_ILS_3 3
62#define PIIX4_OCW2_ILS_4 4
63#define PIIX4_OCW2_ILS_5 5
64#define PIIX4_OCW2_ILS_6 6
65#define PIIX4_OCW2_ILS_7 7
66#define PIIX4_OCW2_ILS_8 0
67#define PIIX4_OCW2_ILS_9 1
68#define PIIX4_OCW2_ILS_10 2
69#define PIIX4_OCW2_ILS_11 3
70#define PIIX4_OCW2_ILS_12 4
71#define PIIX4_OCW2_ILS_13 5
72#define PIIX4_OCW2_ILS_14 6
73#define PIIX4_OCW2_ILS_15 7
74
75#define PIIX4_OCW3_SEL (0x1 << 3)
76
77#define PIIX4_OCW3_IRR 0x2
78#define PIIX4_OCW3_ISR 0x3
79 45
80#endif /* __ASM_MIPS_BOARDS_PIIX4_H */ 46#endif /* __ASM_MIPS_BOARDS_PIIX4_H */
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index fed1c3e9b486..e0331414c7d6 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -603,6 +603,13 @@
603#define MIPS_CONF4_MMUEXTDEF (_ULCAST_(3) << 14) 603#define MIPS_CONF4_MMUEXTDEF (_ULCAST_(3) << 14)
604#define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14) 604#define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14)
605 605
606#define MIPS_CONF5_NF (_ULCAST_(1) << 0)
607#define MIPS_CONF5_UFR (_ULCAST_(1) << 2)
608#define MIPS_CONF5_MSAEN (_ULCAST_(1) << 27)
609#define MIPS_CONF5_EVA (_ULCAST_(1) << 28)
610#define MIPS_CONF5_CV (_ULCAST_(1) << 29)
611#define MIPS_CONF5_K (_ULCAST_(1) << 30)
612
606#define MIPS_CONF6_SYND (_ULCAST_(1) << 13) 613#define MIPS_CONF6_SYND (_ULCAST_(1) << 13)
607 614
608#define MIPS_CONF7_WII (_ULCAST_(1) << 31) 615#define MIPS_CONF7_WII (_ULCAST_(1) << 31)
diff --git a/arch/mips/include/asm/mmu_context.h b/arch/mips/include/asm/mmu_context.h
index 3b29079b5424..e277bbad2871 100644
--- a/arch/mips/include/asm/mmu_context.h
+++ b/arch/mips/include/asm/mmu_context.h
@@ -24,21 +24,21 @@
24#endif /* SMTC */ 24#endif /* SMTC */
25#include <asm-generic/mm_hooks.h> 25#include <asm-generic/mm_hooks.h>
26 26
27#ifdef CONFIG_MIPS_PGD_C0_CONTEXT
28
29#define TLBMISS_HANDLER_SETUP_PGD(pgd) \ 27#define TLBMISS_HANDLER_SETUP_PGD(pgd) \
30do { \ 28do { \
31 extern void tlbmiss_handler_setup_pgd(unsigned long); \ 29 extern void tlbmiss_handler_setup_pgd(unsigned long); \
32 tlbmiss_handler_setup_pgd((unsigned long)(pgd)); \ 30 tlbmiss_handler_setup_pgd((unsigned long)(pgd)); \
33} while (0) 31} while (0)
34 32
33#ifdef CONFIG_MIPS_PGD_C0_CONTEXT
35#define TLBMISS_HANDLER_SETUP() \ 34#define TLBMISS_HANDLER_SETUP() \
36 do { \ 35 do { \
37 TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir); \ 36 TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir); \
38 write_c0_xcontext((unsigned long) smp_processor_id() << 51); \ 37 write_c0_xcontext((unsigned long) smp_processor_id() << \
38 SMP_CPUID_REGSHIFT); \
39 } while (0) 39 } while (0)
40 40
41#else /* CONFIG_MIPS_PGD_C0_CONTEXT: using pgd_current*/ 41#else /* !CONFIG_MIPS_PGD_C0_CONTEXT: using pgd_current*/
42 42
43/* 43/*
44 * For the fast tlb miss handlers, we keep a per cpu array of pointers 44 * For the fast tlb miss handlers, we keep a per cpu array of pointers
@@ -47,21 +47,11 @@ do { \
47 */ 47 */
48extern unsigned long pgd_current[]; 48extern unsigned long pgd_current[];
49 49
50#define TLBMISS_HANDLER_SETUP_PGD(pgd) \
51 pgd_current[smp_processor_id()] = (unsigned long)(pgd)
52
53#ifdef CONFIG_32BIT
54#define TLBMISS_HANDLER_SETUP() \ 50#define TLBMISS_HANDLER_SETUP() \
55 write_c0_context((unsigned long) smp_processor_id() << 25); \ 51 write_c0_context((unsigned long) smp_processor_id() << \
52 SMP_CPUID_REGSHIFT); \
56 back_to_back_c0_hazard(); \ 53 back_to_back_c0_hazard(); \
57 TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir) 54 TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir)
58#endif
59#ifdef CONFIG_64BIT
60#define TLBMISS_HANDLER_SETUP() \
61 write_c0_context((unsigned long) smp_processor_id() << 26); \
62 back_to_back_c0_hazard(); \
63 TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir)
64#endif
65#endif /* CONFIG_MIPS_PGD_C0_CONTEXT*/ 55#endif /* CONFIG_MIPS_PGD_C0_CONTEXT*/
66#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) 56#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
67 57
diff --git a/arch/mips/include/asm/mutex.h b/arch/mips/include/asm/mutex.h
deleted file mode 100644
index 458c1f7fbc18..000000000000
--- a/arch/mips/include/asm/mutex.h
+++ /dev/null
@@ -1,9 +0,0 @@
1/*
2 * Pull in the generic implementation for the mutex fastpath.
3 *
4 * TODO: implement optimized primitives instead, or leave the generic
5 * implementation in place, or pick the atomic_xchg() based generic
6 * implementation. (see asm-generic/mutex-xchg.h for details)
7 */
8
9#include <asm-generic/mutex-dec.h>
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/bridge.h b/arch/mips/include/asm/netlogic/xlp-hal/bridge.h
index 790f0f1e55c6..4e8eacb9588a 100644
--- a/arch/mips/include/asm/netlogic/xlp-hal/bridge.h
+++ b/arch/mips/include/asm/netlogic/xlp-hal/bridge.h
@@ -88,6 +88,7 @@
88#define BRIDGE_DRAM_LIMIT6 0x22 88#define BRIDGE_DRAM_LIMIT6 0x22
89#define BRIDGE_DRAM_LIMIT7 0x23 89#define BRIDGE_DRAM_LIMIT7 0x23
90 90
91#define BRIDGE_DRAM_NODE_TRANSLN(i) (0x24 + (i))
91#define BRIDGE_DRAM_NODE_TRANSLN0 0x24 92#define BRIDGE_DRAM_NODE_TRANSLN0 0x24
92#define BRIDGE_DRAM_NODE_TRANSLN1 0x25 93#define BRIDGE_DRAM_NODE_TRANSLN1 0x25
93#define BRIDGE_DRAM_NODE_TRANSLN2 0x26 94#define BRIDGE_DRAM_NODE_TRANSLN2 0x26
@@ -96,6 +97,8 @@
96#define BRIDGE_DRAM_NODE_TRANSLN5 0x29 97#define BRIDGE_DRAM_NODE_TRANSLN5 0x29
97#define BRIDGE_DRAM_NODE_TRANSLN6 0x2a 98#define BRIDGE_DRAM_NODE_TRANSLN6 0x2a
98#define BRIDGE_DRAM_NODE_TRANSLN7 0x2b 99#define BRIDGE_DRAM_NODE_TRANSLN7 0x2b
100
101#define BRIDGE_DRAM_CHNL_TRANSLN(i) (0x2c + (i))
99#define BRIDGE_DRAM_CHNL_TRANSLN0 0x2c 102#define BRIDGE_DRAM_CHNL_TRANSLN0 0x2c
100#define BRIDGE_DRAM_CHNL_TRANSLN1 0x2d 103#define BRIDGE_DRAM_CHNL_TRANSLN1 0x2d
101#define BRIDGE_DRAM_CHNL_TRANSLN2 0x2e 104#define BRIDGE_DRAM_CHNL_TRANSLN2 0x2e
@@ -104,6 +107,7 @@
104#define BRIDGE_DRAM_CHNL_TRANSLN5 0x31 107#define BRIDGE_DRAM_CHNL_TRANSLN5 0x31
105#define BRIDGE_DRAM_CHNL_TRANSLN6 0x32 108#define BRIDGE_DRAM_CHNL_TRANSLN6 0x32
106#define BRIDGE_DRAM_CHNL_TRANSLN7 0x33 109#define BRIDGE_DRAM_CHNL_TRANSLN7 0x33
110
107#define BRIDGE_PCIEMEM_BASE0 0x34 111#define BRIDGE_PCIEMEM_BASE0 0x34
108#define BRIDGE_PCIEMEM_BASE1 0x35 112#define BRIDGE_PCIEMEM_BASE1 0x35
109#define BRIDGE_PCIEMEM_BASE2 0x36 113#define BRIDGE_PCIEMEM_BASE2 0x36
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/iomap.h b/arch/mips/include/asm/netlogic/xlp-hal/iomap.h
index 9fac46fb7913..55eee77adaca 100644
--- a/arch/mips/include/asm/netlogic/xlp-hal/iomap.h
+++ b/arch/mips/include/asm/netlogic/xlp-hal/iomap.h
@@ -72,6 +72,12 @@
72#define XLP_IO_USB_OHCI2_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 4) 72#define XLP_IO_USB_OHCI2_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 4)
73#define XLP_IO_USB_OHCI3_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 5) 73#define XLP_IO_USB_OHCI3_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 5)
74 74
75/* XLP2xx has an updated USB block */
76#define XLP2XX_IO_USB_OFFSET(node, i) XLP_HDR_OFFSET(node, 0, 4, i)
77#define XLP2XX_IO_USB_XHCI0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 4, 1)
78#define XLP2XX_IO_USB_XHCI1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 4, 2)
79#define XLP2XX_IO_USB_XHCI2_OFFSET(node) XLP_HDR_OFFSET(node, 0, 4, 3)
80
75#define XLP_IO_NAE_OFFSET(node) XLP_HDR_OFFSET(node, 0, 3, 0) 81#define XLP_IO_NAE_OFFSET(node) XLP_HDR_OFFSET(node, 0, 3, 0)
76#define XLP_IO_POE_OFFSET(node) XLP_HDR_OFFSET(node, 0, 3, 1) 82#define XLP_IO_POE_OFFSET(node) XLP_HDR_OFFSET(node, 0, 3, 1)
77 83
@@ -88,6 +94,9 @@
88#define XLP_IO_I2C0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 2) 94#define XLP_IO_I2C0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 2)
89#define XLP_IO_I2C1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 3) 95#define XLP_IO_I2C1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 3)
90#define XLP_IO_GPIO_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 4) 96#define XLP_IO_GPIO_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 4)
97/* on 2XX, all I2C busses are on the same block */
98#define XLP2XX_IO_I2C_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 7)
99
91/* system management */ 100/* system management */
92#define XLP_IO_SYS_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 5) 101#define XLP_IO_SYS_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 5)
93#define XLP_IO_JTAG_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 6) 102#define XLP_IO_JTAG_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 6)
@@ -145,6 +154,7 @@
145#define PCI_DEVICE_ID_NLM_NOR 0x1015 154#define PCI_DEVICE_ID_NLM_NOR 0x1015
146#define PCI_DEVICE_ID_NLM_NAND 0x1016 155#define PCI_DEVICE_ID_NLM_NAND 0x1016
147#define PCI_DEVICE_ID_NLM_MMC 0x1018 156#define PCI_DEVICE_ID_NLM_MMC 0x1018
157#define PCI_DEVICE_ID_NLM_XHCI 0x101d
148 158
149#ifndef __ASSEMBLY__ 159#ifndef __ASSEMBLY__
150 160
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/pic.h b/arch/mips/include/asm/netlogic/xlp-hal/pic.h
index 4b5108dfaa16..105389b79f09 100644
--- a/arch/mips/include/asm/netlogic/xlp-hal/pic.h
+++ b/arch/mips/include/asm/netlogic/xlp-hal/pic.h
@@ -208,13 +208,14 @@
208#define PIC_LOCAL_SCHEDULING 1 208#define PIC_LOCAL_SCHEDULING 1
209#define PIC_GLOBAL_SCHEDULING 0 209#define PIC_GLOBAL_SCHEDULING 0
210 210
211#define PIC_CLK_HZ 133333333
212
213#define nlm_read_pic_reg(b, r) nlm_read_reg64(b, r) 211#define nlm_read_pic_reg(b, r) nlm_read_reg64(b, r)
214#define nlm_write_pic_reg(b, r, v) nlm_write_reg64(b, r, v) 212#define nlm_write_pic_reg(b, r, v) nlm_write_reg64(b, r, v)
215#define nlm_get_pic_pcibase(node) nlm_pcicfg_base(XLP_IO_PIC_OFFSET(node)) 213#define nlm_get_pic_pcibase(node) nlm_pcicfg_base(XLP_IO_PIC_OFFSET(node))
216#define nlm_get_pic_regbase(node) (nlm_get_pic_pcibase(node) + XLP_IO_PCI_HDRSZ) 214#define nlm_get_pic_regbase(node) (nlm_get_pic_pcibase(node) + XLP_IO_PCI_HDRSZ)
217 215
216/* We use PIC on node 0 as a timer */
217#define pic_timer_freq() nlm_get_pic_frequency(0)
218
218/* IRT and h/w interrupt routines */ 219/* IRT and h/w interrupt routines */
219static inline int 220static inline int
220nlm_pic_read_irt(uint64_t base, int irt_index) 221nlm_pic_read_irt(uint64_t base, int irt_index)
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/sys.h b/arch/mips/include/asm/netlogic/xlp-hal/sys.h
index 470e52bfc061..fcf2833c16ca 100644
--- a/arch/mips/include/asm/netlogic/xlp-hal/sys.h
+++ b/arch/mips/include/asm/netlogic/xlp-hal/sys.h
@@ -117,6 +117,36 @@
117#define SYS_SCRTCH2 0x4b 117#define SYS_SCRTCH2 0x4b
118#define SYS_SCRTCH3 0x4c 118#define SYS_SCRTCH3 0x4c
119 119
120/* PLL registers XLP2XX */
121#define SYS_PLL_CTRL0 0x240
122#define SYS_PLL_CTRL1 0x241
123#define SYS_PLL_CTRL2 0x242
124#define SYS_PLL_CTRL3 0x243
125#define SYS_DMC_PLL_CTRL0 0x244
126#define SYS_DMC_PLL_CTRL1 0x245
127#define SYS_DMC_PLL_CTRL2 0x246
128#define SYS_DMC_PLL_CTRL3 0x247
129
130#define SYS_PLL_CTRL0_DEVX(x) (0x248 + (x) * 4)
131#define SYS_PLL_CTRL1_DEVX(x) (0x249 + (x) * 4)
132#define SYS_PLL_CTRL2_DEVX(x) (0x24a + (x) * 4)
133#define SYS_PLL_CTRL3_DEVX(x) (0x24b + (x) * 4)
134
135#define SYS_CPU_PLL_CHG_CTRL 0x288
136#define SYS_PLL_CHG_CTRL 0x289
137#define SYS_CLK_DEV_DIS 0x28a
138#define SYS_CLK_DEV_SEL 0x28b
139#define SYS_CLK_DEV_DIV 0x28c
140#define SYS_CLK_DEV_CHG 0x28d
141#define SYS_CLK_DEV_SEL_REG 0x28e
142#define SYS_CLK_DEV_DIV_REG 0x28f
143#define SYS_CPU_PLL_LOCK 0x29f
144#define SYS_SYS_PLL_LOCK 0x2a0
145#define SYS_PLL_MEM_CMD 0x2a1
146#define SYS_CPU_PLL_MEM_REQ 0x2a2
147#define SYS_SYS_PLL_MEM_REQ 0x2a3
148#define SYS_PLL_MEM_STAT 0x2a4
149
120#ifndef __ASSEMBLY__ 150#ifndef __ASSEMBLY__
121 151
122#define nlm_read_sys_reg(b, r) nlm_read_reg(b, r) 152#define nlm_read_sys_reg(b, r) nlm_read_reg(b, r)
@@ -124,5 +154,6 @@
124#define nlm_get_sys_pcibase(node) nlm_pcicfg_base(XLP_IO_SYS_OFFSET(node)) 154#define nlm_get_sys_pcibase(node) nlm_pcicfg_base(XLP_IO_SYS_OFFSET(node))
125#define nlm_get_sys_regbase(node) (nlm_get_sys_pcibase(node) + XLP_IO_PCI_HDRSZ) 155#define nlm_get_sys_regbase(node) (nlm_get_sys_pcibase(node) + XLP_IO_PCI_HDRSZ)
126 156
157unsigned int nlm_get_pic_frequency(int node);
127#endif 158#endif
128#endif 159#endif
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/xlp.h b/arch/mips/include/asm/netlogic/xlp-hal/xlp.h
index f4ea0f7f3965..470f2095b346 100644
--- a/arch/mips/include/asm/netlogic/xlp-hal/xlp.h
+++ b/arch/mips/include/asm/netlogic/xlp-hal/xlp.h
@@ -41,15 +41,22 @@
41#define PIC_PCIE_LINK_1_IRQ 20 41#define PIC_PCIE_LINK_1_IRQ 20
42#define PIC_PCIE_LINK_2_IRQ 21 42#define PIC_PCIE_LINK_2_IRQ 21
43#define PIC_PCIE_LINK_3_IRQ 22 43#define PIC_PCIE_LINK_3_IRQ 22
44
44#define PIC_EHCI_0_IRQ 23 45#define PIC_EHCI_0_IRQ 23
45#define PIC_EHCI_1_IRQ 24 46#define PIC_EHCI_1_IRQ 24
46#define PIC_OHCI_0_IRQ 25 47#define PIC_OHCI_0_IRQ 25
47#define PIC_OHCI_1_IRQ 26 48#define PIC_OHCI_1_IRQ 26
48#define PIC_OHCI_2_IRQ 27 49#define PIC_OHCI_2_IRQ 27
49#define PIC_OHCI_3_IRQ 28 50#define PIC_OHCI_3_IRQ 28
51#define PIC_2XX_XHCI_0_IRQ 23
52#define PIC_2XX_XHCI_1_IRQ 24
53#define PIC_2XX_XHCI_2_IRQ 25
54
50#define PIC_MMC_IRQ 29 55#define PIC_MMC_IRQ 29
51#define PIC_I2C_0_IRQ 30 56#define PIC_I2C_0_IRQ 30
52#define PIC_I2C_1_IRQ 31 57#define PIC_I2C_1_IRQ 31
58#define PIC_I2C_2_IRQ 32
59#define PIC_I2C_3_IRQ 33
53 60
54#ifndef __ASSEMBLY__ 61#ifndef __ASSEMBLY__
55 62
@@ -59,7 +66,18 @@ void xlp_wakeup_secondary_cpus(void);
59 66
60void xlp_mmu_init(void); 67void xlp_mmu_init(void);
61void nlm_hal_init(void); 68void nlm_hal_init(void);
69int xlp_get_dram_map(int n, uint64_t *dram_map);
70
71/* Device tree related */
72void xlp_early_init_devtree(void);
62void *xlp_dt_init(void *fdtp); 73void *xlp_dt_init(void *fdtp);
63 74
75static inline int cpu_is_xlpii(void)
76{
77 int chip = read_c0_prid() & 0xff00;
78
79 return chip == PRID_IMP_NETLOGIC_XLP2XX;
80}
81
64#endif /* !__ASSEMBLY__ */ 82#endif /* !__ASSEMBLY__ */
65#endif /* _ASM_NLM_XLP_H */ 83#endif /* _ASM_NLM_XLP_H */
diff --git a/arch/mips/include/asm/netlogic/xlr/pic.h b/arch/mips/include/asm/netlogic/xlr/pic.h
index 63c99176dffe..3c80a75233bd 100644
--- a/arch/mips/include/asm/netlogic/xlr/pic.h
+++ b/arch/mips/include/asm/netlogic/xlr/pic.h
@@ -36,6 +36,8 @@
36#define _ASM_NLM_XLR_PIC_H 36#define _ASM_NLM_XLR_PIC_H
37 37
38#define PIC_CLK_HZ 66666666 38#define PIC_CLK_HZ 66666666
39#define pic_timer_freq() PIC_CLK_HZ
40
39/* PIC hardware interrupt numbers */ 41/* PIC hardware interrupt numbers */
40#define PIC_IRT_WD_INDEX 0 42#define PIC_IRT_WD_INDEX 0
41#define PIC_IRT_TIMER_0_INDEX 1 43#define PIC_IRT_TIMER_0_INDEX 1
diff --git a/arch/mips/include/asm/octeon/octeon.h b/arch/mips/include/asm/octeon/octeon.h
index a2eed23c49a9..f5d77b91537f 100644
--- a/arch/mips/include/asm/octeon/octeon.h
+++ b/arch/mips/include/asm/octeon/octeon.h
@@ -251,4 +251,6 @@ extern void (*octeon_irq_setup_secondary)(void);
251typedef void (*octeon_irq_ip4_handler_t)(void); 251typedef void (*octeon_irq_ip4_handler_t)(void);
252void octeon_irq_set_ip4_handler(octeon_irq_ip4_handler_t); 252void octeon_irq_set_ip4_handler(octeon_irq_ip4_handler_t);
253 253
254extern void octeon_fixup_irqs(void);
255
254#endif /* __ASM_OCTEON_OCTEON_H */ 256#endif /* __ASM_OCTEON_OCTEON_H */
diff --git a/arch/mips/include/asm/parport.h b/arch/mips/include/asm/parport.h
deleted file mode 100644
index cf252af64590..000000000000
--- a/arch/mips/include/asm/parport.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-generic/parport.h>
diff --git a/arch/mips/include/asm/pci.h b/arch/mips/include/asm/pci.h
index fa8e0aa250ca..12d6842962be 100644
--- a/arch/mips/include/asm/pci.h
+++ b/arch/mips/include/asm/pci.h
@@ -83,6 +83,18 @@ static inline void pcibios_penalize_isa_irq(int irq, int active)
83extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, 83extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
84 enum pci_mmap_state mmap_state, int write_combine); 84 enum pci_mmap_state mmap_state, int write_combine);
85 85
86#define HAVE_ARCH_PCI_RESOURCE_TO_USER
87
88static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
89 const struct resource *rsrc, resource_size_t *start,
90 resource_size_t *end)
91{
92 phys_t size = resource_size(rsrc);
93
94 *start = fixup_bigphys_addr(rsrc->start, size);
95 *end = rsrc->start + size;
96}
97
86/* 98/*
87 * Dynamic DMA mapping stuff. 99 * Dynamic DMA mapping stuff.
88 * MIPS has everything mapped statically. 100 * MIPS has everything mapped statically.
@@ -136,11 +148,6 @@ static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
136 return channel ? 15 : 14; 148 return channel ? 15 : 14;
137} 149}
138 150
139#ifdef CONFIG_CPU_CAVIUM_OCTEON
140/* MSI arch hook for OCTEON */
141#define arch_setup_msi_irqs arch_setup_msi_irqs
142#endif
143
144extern char * (*pcibios_plat_setup)(char *str); 151extern char * (*pcibios_plat_setup)(char *str);
145 152
146#ifdef CONFIG_OF 153#ifdef CONFIG_OF
diff --git a/arch/mips/include/asm/percpu.h b/arch/mips/include/asm/percpu.h
deleted file mode 100644
index 844e763e9332..000000000000
--- a/arch/mips/include/asm/percpu.h
+++ /dev/null
@@ -1,6 +0,0 @@
1#ifndef __ASM_PERCPU_H
2#define __ASM_PERCPU_H
3
4#include <asm-generic/percpu.h>
5
6#endif /* __ASM_PERCPU_H */
diff --git a/arch/mips/include/asm/pgalloc.h b/arch/mips/include/asm/pgalloc.h
index 881d18b4e298..b336037e8768 100644
--- a/arch/mips/include/asm/pgalloc.h
+++ b/arch/mips/include/asm/pgalloc.h
@@ -80,9 +80,12 @@ static inline struct page *pte_alloc_one(struct mm_struct *mm,
80 struct page *pte; 80 struct page *pte;
81 81
82 pte = alloc_pages(GFP_KERNEL | __GFP_REPEAT, PTE_ORDER); 82 pte = alloc_pages(GFP_KERNEL | __GFP_REPEAT, PTE_ORDER);
83 if (pte) { 83 if (!pte)
84 clear_highpage(pte); 84 return NULL;
85 pgtable_page_ctor(pte); 85 clear_highpage(pte);
86 if (!pgtable_page_ctor(pte)) {
87 __free_page(pte);
88 return NULL;
86 } 89 }
87 return pte; 90 return pte;
88} 91}
diff --git a/arch/mips/include/asm/prom.h b/arch/mips/include/asm/prom.h
index 1e7e0961064b..ccd2b75f152c 100644
--- a/arch/mips/include/asm/prom.h
+++ b/arch/mips/include/asm/prom.h
@@ -17,22 +17,8 @@
17#include <linux/types.h> 17#include <linux/types.h>
18#include <asm/bootinfo.h> 18#include <asm/bootinfo.h>
19 19
20extern int early_init_dt_scan_memory_arch(unsigned long node,
21 const char *uname, int depth, void *data);
22
23extern void device_tree_init(void); 20extern void device_tree_init(void);
24 21
25static inline unsigned long pci_address_to_pio(phys_addr_t address)
26{
27 /*
28 * The ioport address can be directly used by inX() / outX()
29 */
30 BUG_ON(address > IO_SPACE_LIMIT);
31
32 return (unsigned long) address;
33}
34#define pci_address_to_pio pci_address_to_pio
35
36struct boot_param_header; 22struct boot_param_header;
37 23
38extern void __dt_setup_arch(struct boot_param_header *bph); 24extern void __dt_setup_arch(struct boot_param_header *bph);
diff --git a/arch/mips/include/asm/ptrace.h b/arch/mips/include/asm/ptrace.h
index 5e6cd0947393..7bba9da110af 100644
--- a/arch/mips/include/asm/ptrace.h
+++ b/arch/mips/include/asm/ptrace.h
@@ -81,7 +81,6 @@ static inline long regs_return_value(struct pt_regs *regs)
81 81
82#define instruction_pointer(regs) ((regs)->cp0_epc) 82#define instruction_pointer(regs) ((regs)->cp0_epc)
83#define profile_pc(regs) instruction_pointer(regs) 83#define profile_pc(regs) instruction_pointer(regs)
84#define user_stack_pointer(r) ((r)->regs[29])
85 84
86extern asmlinkage void syscall_trace_enter(struct pt_regs *regs); 85extern asmlinkage void syscall_trace_enter(struct pt_regs *regs);
87extern asmlinkage void syscall_trace_leave(struct pt_regs *regs); 86extern asmlinkage void syscall_trace_leave(struct pt_regs *regs);
@@ -100,4 +99,17 @@ static inline void die_if_kernel(const char *str, struct pt_regs *regs)
100 (struct pt_regs *)((sp | (THREAD_SIZE - 1)) + 1 - 32) - 1; \ 99 (struct pt_regs *)((sp | (THREAD_SIZE - 1)) + 1 - 32) - 1; \
101}) 100})
102 101
102/* Helpers for working with the user stack pointer */
103
104static inline unsigned long user_stack_pointer(struct pt_regs *regs)
105{
106 return regs->regs[29];
107}
108
109static inline void user_stack_pointer_set(struct pt_regs *regs,
110 unsigned long val)
111{
112 regs->regs[29] = val;
113}
114
103#endif /* _ASM_PTRACE_H */ 115#endif /* _ASM_PTRACE_H */
diff --git a/arch/mips/include/asm/r4kcache.h b/arch/mips/include/asm/r4kcache.h
index a0b2650516ac..34d1a1917125 100644
--- a/arch/mips/include/asm/r4kcache.h
+++ b/arch/mips/include/asm/r4kcache.h
@@ -15,6 +15,7 @@
15#include <asm/asm.h> 15#include <asm/asm.h>
16#include <asm/cacheops.h> 16#include <asm/cacheops.h>
17#include <asm/cpu-features.h> 17#include <asm/cpu-features.h>
18#include <asm/cpu-type.h>
18#include <asm/mipsmtregs.h> 19#include <asm/mipsmtregs.h>
19 20
20/* 21/*
@@ -162,7 +163,15 @@ static inline void flush_scache_line_indexed(unsigned long addr)
162static inline void flush_icache_line(unsigned long addr) 163static inline void flush_icache_line(unsigned long addr)
163{ 164{
164 __iflush_prologue 165 __iflush_prologue
165 cache_op(Hit_Invalidate_I, addr); 166 switch (boot_cpu_type()) {
167 case CPU_LOONGSON2:
168 cache_op(Hit_Invalidate_I_Loongson23, addr);
169 break;
170
171 default:
172 cache_op(Hit_Invalidate_I, addr);
173 break;
174 }
166 __iflush_epilogue 175 __iflush_epilogue
167} 176}
168 177
@@ -208,7 +217,15 @@ static inline void flush_scache_line(unsigned long addr)
208 */ 217 */
209static inline void protected_flush_icache_line(unsigned long addr) 218static inline void protected_flush_icache_line(unsigned long addr)
210{ 219{
211 protected_cache_op(Hit_Invalidate_I, addr); 220 switch (boot_cpu_type()) {
221 case CPU_LOONGSON2:
222 protected_cache_op(Hit_Invalidate_I_Loongson23, addr);
223 break;
224
225 default:
226 protected_cache_op(Hit_Invalidate_I, addr);
227 break;
228 }
212} 229}
213 230
214/* 231/*
@@ -412,8 +429,8 @@ __BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 64
412__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 128) 429__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 128)
413 430
414/* build blast_xxx_range, protected_blast_xxx_range */ 431/* build blast_xxx_range, protected_blast_xxx_range */
415#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot) \ 432#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot, extra) \
416static inline void prot##blast_##pfx##cache##_range(unsigned long start, \ 433static inline void prot##extra##blast_##pfx##cache##_range(unsigned long start, \
417 unsigned long end) \ 434 unsigned long end) \
418{ \ 435{ \
419 unsigned long lsize = cpu_##desc##_line_size(); \ 436 unsigned long lsize = cpu_##desc##_line_size(); \
@@ -432,13 +449,15 @@ static inline void prot##blast_##pfx##cache##_range(unsigned long start, \
432 __##pfx##flush_epilogue \ 449 __##pfx##flush_epilogue \
433} 450}
434 451
435__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_) 452__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_, )
436__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_) 453__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_, )
437__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_) 454__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_, )
438__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, ) 455__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I_Loongson23, \
439__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, ) 456 protected_, loongson23_)
457__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, , )
458__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, , )
440/* blast_inv_dcache_range */ 459/* blast_inv_dcache_range */
441__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, ) 460__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, , )
442__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD, ) 461__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD, , )
443 462
444#endif /* _ASM_R4KCACHE_H */ 463#endif /* _ASM_R4KCACHE_H */
diff --git a/arch/mips/include/asm/scatterlist.h b/arch/mips/include/asm/scatterlist.h
deleted file mode 100644
index 7ee0e646d82c..000000000000
--- a/arch/mips/include/asm/scatterlist.h
+++ /dev/null
@@ -1,6 +0,0 @@
1#ifndef __ASM_SCATTERLIST_H
2#define __ASM_SCATTERLIST_H
3
4#include <asm-generic/scatterlist.h>
5
6#endif /* __ASM_SCATTERLIST_H */
diff --git a/arch/mips/include/asm/sections.h b/arch/mips/include/asm/sections.h
deleted file mode 100644
index b7e37262c246..000000000000
--- a/arch/mips/include/asm/sections.h
+++ /dev/null
@@ -1,6 +0,0 @@
1#ifndef _ASM_SECTIONS_H
2#define _ASM_SECTIONS_H
3
4#include <asm-generic/sections.h>
5
6#endif /* _ASM_SECTIONS_H */
diff --git a/arch/mips/include/asm/segment.h b/arch/mips/include/asm/segment.h
deleted file mode 100644
index 92ac001fc483..000000000000
--- a/arch/mips/include/asm/segment.h
+++ /dev/null
@@ -1,6 +0,0 @@
1#ifndef _ASM_SEGMENT_H
2#define _ASM_SEGMENT_H
3
4/* Only here because we have some old header files that expect it.. */
5
6#endif /* _ASM_SEGMENT_H */
diff --git a/arch/mips/include/asm/serial.h b/arch/mips/include/asm/serial.h
deleted file mode 100644
index a0cb0caff152..000000000000
--- a/arch/mips/include/asm/serial.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-generic/serial.h>
diff --git a/arch/mips/include/asm/setup.h b/arch/mips/include/asm/setup.h
index e26589ef36ee..d7bfdeba9e84 100644
--- a/arch/mips/include/asm/setup.h
+++ b/arch/mips/include/asm/setup.h
@@ -5,6 +5,14 @@
5 5
6extern void setup_early_printk(void); 6extern void setup_early_printk(void);
7 7
8#ifdef CONFIG_EARLY_PRINTK_8250
9extern void setup_8250_early_printk_port(unsigned long base,
10 unsigned int reg_shift, unsigned int timeout);
11#else
12static inline void setup_8250_early_printk_port(unsigned long base,
13 unsigned int reg_shift, unsigned int timeout) {}
14#endif
15
8extern void set_handler(unsigned long offset, void *addr, unsigned long len); 16extern void set_handler(unsigned long offset, void *addr, unsigned long len);
9extern void set_uncached_handler(unsigned long offset, void *addr, unsigned long len); 17extern void set_uncached_handler(unsigned long offset, void *addr, unsigned long len);
10 18
diff --git a/arch/mips/include/asm/stackframe.h b/arch/mips/include/asm/stackframe.h
index 23fc95e65673..4857e2c8df5a 100644
--- a/arch/mips/include/asm/stackframe.h
+++ b/arch/mips/include/asm/stackframe.h
@@ -17,6 +17,7 @@
17#include <asm/asmmacro.h> 17#include <asm/asmmacro.h>
18#include <asm/mipsregs.h> 18#include <asm/mipsregs.h>
19#include <asm/asm-offsets.h> 19#include <asm/asm-offsets.h>
20#include <asm/thread_info.h>
20 21
21/* 22/*
22 * For SMTC kernel, global IE should be left set, and interrupts 23 * For SMTC kernel, global IE should be left set, and interrupts
@@ -93,21 +94,8 @@
93 .endm 94 .endm
94 95
95#ifdef CONFIG_SMP 96#ifdef CONFIG_SMP
96#ifdef CONFIG_MIPS_MT_SMTC
97#define PTEBASE_SHIFT 19 /* TCBIND */
98#define CPU_ID_REG CP0_TCBIND
99#define CPU_ID_MFC0 mfc0
100#elif defined(CONFIG_MIPS_PGD_C0_CONTEXT)
101#define PTEBASE_SHIFT 48 /* XCONTEXT */
102#define CPU_ID_REG CP0_XCONTEXT
103#define CPU_ID_MFC0 MFC0
104#else
105#define PTEBASE_SHIFT 23 /* CONTEXT */
106#define CPU_ID_REG CP0_CONTEXT
107#define CPU_ID_MFC0 MFC0
108#endif
109 .macro get_saved_sp /* SMP variation */ 97 .macro get_saved_sp /* SMP variation */
110 CPU_ID_MFC0 k0, CPU_ID_REG 98 ASM_CPUID_MFC0 k0, ASM_SMP_CPUID_REG
111#if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32) 99#if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32)
112 lui k1, %hi(kernelsp) 100 lui k1, %hi(kernelsp)
113#else 101#else
@@ -117,17 +105,17 @@
117 daddiu k1, %hi(kernelsp) 105 daddiu k1, %hi(kernelsp)
118 dsll k1, 16 106 dsll k1, 16
119#endif 107#endif
120 LONG_SRL k0, PTEBASE_SHIFT 108 LONG_SRL k0, SMP_CPUID_PTRSHIFT
121 LONG_ADDU k1, k0 109 LONG_ADDU k1, k0
122 LONG_L k1, %lo(kernelsp)(k1) 110 LONG_L k1, %lo(kernelsp)(k1)
123 .endm 111 .endm
124 112
125 .macro set_saved_sp stackp temp temp2 113 .macro set_saved_sp stackp temp temp2
126 CPU_ID_MFC0 \temp, CPU_ID_REG 114 ASM_CPUID_MFC0 \temp, ASM_SMP_CPUID_REG
127 LONG_SRL \temp, PTEBASE_SHIFT 115 LONG_SRL \temp, SMP_CPUID_PTRSHIFT
128 LONG_S \stackp, kernelsp(\temp) 116 LONG_S \stackp, kernelsp(\temp)
129 .endm 117 .endm
130#else 118#else /* !CONFIG_SMP */
131 .macro get_saved_sp /* Uniprocessor variation */ 119 .macro get_saved_sp /* Uniprocessor variation */
132#ifdef CONFIG_CPU_JUMP_WORKAROUNDS 120#ifdef CONFIG_CPU_JUMP_WORKAROUNDS
133 /* 121 /*
diff --git a/arch/mips/include/asm/syscall.h b/arch/mips/include/asm/syscall.h
new file mode 100644
index 000000000000..81c89132c59d
--- /dev/null
+++ b/arch/mips/include/asm/syscall.h
@@ -0,0 +1,116 @@
1/*
2 * Access to user system call parameters and results
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * See asm-generic/syscall.h for descriptions of what we must do here.
9 *
10 * Copyright (C) 2012 Ralf Baechle <ralf@linux-mips.org>
11 */
12
13#ifndef __ASM_MIPS_SYSCALL_H
14#define __ASM_MIPS_SYSCALL_H
15
16#include <linux/audit.h>
17#include <linux/elf-em.h>
18#include <linux/kernel.h>
19#include <linux/sched.h>
20#include <linux/uaccess.h>
21#include <asm/ptrace.h>
22
23static inline long syscall_get_nr(struct task_struct *task,
24 struct pt_regs *regs)
25{
26 return regs->regs[2];
27}
28
29static inline unsigned long mips_get_syscall_arg(unsigned long *arg,
30 struct task_struct *task, struct pt_regs *regs, unsigned int n)
31{
32 unsigned long usp = regs->regs[29];
33
34 switch (n) {
35 case 0: case 1: case 2: case 3:
36 *arg = regs->regs[4 + n];
37
38 return 0;
39
40#ifdef CONFIG_32BIT
41 case 4: case 5: case 6: case 7:
42 return get_user(*arg, (int *)usp + 4 * n);
43#endif
44
45#ifdef CONFIG_64BIT
46 case 4: case 5: case 6: case 7:
47#ifdef CONFIG_MIPS32_O32
48 if (test_thread_flag(TIF_32BIT_REGS))
49 return get_user(*arg, (int *)usp + 4 * n);
50 else
51#endif
52 *arg = regs->regs[4 + n];
53
54 return 0;
55#endif
56
57 default:
58 BUG();
59 }
60}
61
62static inline long syscall_get_return_value(struct task_struct *task,
63 struct pt_regs *regs)
64{
65 return regs->regs[2];
66}
67
68static inline void syscall_set_return_value(struct task_struct *task,
69 struct pt_regs *regs,
70 int error, long val)
71{
72 if (error) {
73 regs->regs[2] = -error;
74 regs->regs[7] = -1;
75 } else {
76 regs->regs[2] = val;
77 regs->regs[7] = 0;
78 }
79}
80
81static inline void syscall_get_arguments(struct task_struct *task,
82 struct pt_regs *regs,
83 unsigned int i, unsigned int n,
84 unsigned long *args)
85{
86 unsigned long arg;
87 int ret;
88
89 while (n--)
90 ret |= mips_get_syscall_arg(&arg, task, regs, i++);
91
92 /*
93 * No way to communicate an error because this is a void function.
94 */
95#if 0
96 return ret;
97#endif
98}
99
100extern const unsigned long sys_call_table[];
101extern const unsigned long sys32_call_table[];
102extern const unsigned long sysn32_call_table[];
103
104static inline int __syscall_get_arch(void)
105{
106 int arch = EM_MIPS;
107#ifdef CONFIG_64BIT
108 arch |= __AUDIT_ARCH_64BIT;
109#endif
110#if defined(__LITTLE_ENDIAN)
111 arch |= __AUDIT_ARCH_LE;
112#endif
113 return arch;
114}
115
116#endif /* __ASM_MIPS_SYSCALL_H */
diff --git a/arch/mips/include/asm/thread_info.h b/arch/mips/include/asm/thread_info.h
index 61215a34acc6..f9b24bfbdbae 100644
--- a/arch/mips/include/asm/thread_info.h
+++ b/arch/mips/include/asm/thread_info.h
@@ -116,6 +116,7 @@ static inline struct thread_info *current_thread_info(void)
116#define TIF_32BIT_ADDR 23 /* 32-bit address space (o32/n32) */ 116#define TIF_32BIT_ADDR 23 /* 32-bit address space (o32/n32) */
117#define TIF_FPUBOUND 24 /* thread bound to FPU-full CPU set */ 117#define TIF_FPUBOUND 24 /* thread bound to FPU-full CPU set */
118#define TIF_LOAD_WATCH 25 /* If set, load watch registers */ 118#define TIF_LOAD_WATCH 25 /* If set, load watch registers */
119#define TIF_SYSCALL_TRACEPOINT 26 /* syscall tracepoint instrumentation */
119#define TIF_SYSCALL_TRACE 31 /* syscall trace active */ 120#define TIF_SYSCALL_TRACE 31 /* syscall trace active */
120 121
121#define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE) 122#define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE)
@@ -132,21 +133,54 @@ static inline struct thread_info *current_thread_info(void)
132#define _TIF_32BIT_ADDR (1<<TIF_32BIT_ADDR) 133#define _TIF_32BIT_ADDR (1<<TIF_32BIT_ADDR)
133#define _TIF_FPUBOUND (1<<TIF_FPUBOUND) 134#define _TIF_FPUBOUND (1<<TIF_FPUBOUND)
134#define _TIF_LOAD_WATCH (1<<TIF_LOAD_WATCH) 135#define _TIF_LOAD_WATCH (1<<TIF_LOAD_WATCH)
136#define _TIF_SYSCALL_TRACEPOINT (1<<TIF_SYSCALL_TRACEPOINT)
135 137
136#define _TIF_WORK_SYSCALL_ENTRY (_TIF_NOHZ | _TIF_SYSCALL_TRACE | \ 138#define _TIF_WORK_SYSCALL_ENTRY (_TIF_NOHZ | _TIF_SYSCALL_TRACE | \
137 _TIF_SYSCALL_AUDIT) 139 _TIF_SYSCALL_AUDIT | _TIF_SYSCALL_TRACEPOINT)
138 140
139/* work to do in syscall_trace_leave() */ 141/* work to do in syscall_trace_leave() */
140#define _TIF_WORK_SYSCALL_EXIT (_TIF_NOHZ | _TIF_SYSCALL_TRACE | \ 142#define _TIF_WORK_SYSCALL_EXIT (_TIF_NOHZ | _TIF_SYSCALL_TRACE | \
141 _TIF_SYSCALL_AUDIT) 143 _TIF_SYSCALL_AUDIT | _TIF_SYSCALL_TRACEPOINT)
142 144
143/* work to do on interrupt/exception return */ 145/* work to do on interrupt/exception return */
144#define _TIF_WORK_MASK \ 146#define _TIF_WORK_MASK \
145 (_TIF_SIGPENDING | _TIF_NEED_RESCHED | _TIF_NOTIFY_RESUME) 147 (_TIF_SIGPENDING | _TIF_NEED_RESCHED | _TIF_NOTIFY_RESUME)
146/* work to do on any return to u-space */ 148/* work to do on any return to u-space */
147#define _TIF_ALLWORK_MASK (_TIF_NOHZ | _TIF_WORK_MASK | \ 149#define _TIF_ALLWORK_MASK (_TIF_NOHZ | _TIF_WORK_MASK | \
148 _TIF_WORK_SYSCALL_EXIT) 150 _TIF_WORK_SYSCALL_EXIT | \
151 _TIF_SYSCALL_TRACEPOINT)
149 152
150#endif /* __KERNEL__ */ 153/*
154 * We stash processor id into a COP0 register to retrieve it fast
155 * at kernel exception entry.
156 */
157#if defined(CONFIG_MIPS_MT_SMTC)
158#define SMP_CPUID_REG 2, 2 /* TCBIND */
159#define ASM_SMP_CPUID_REG $2, 2
160#define SMP_CPUID_PTRSHIFT 19
161#elif defined(CONFIG_MIPS_PGD_C0_CONTEXT)
162#define SMP_CPUID_REG 20, 0 /* XCONTEXT */
163#define ASM_SMP_CPUID_REG $20
164#define SMP_CPUID_PTRSHIFT 48
165#else
166#define SMP_CPUID_REG 4, 0 /* CONTEXT */
167#define ASM_SMP_CPUID_REG $4
168#define SMP_CPUID_PTRSHIFT 23
169#endif
151 170
171#ifdef CONFIG_64BIT
172#define SMP_CPUID_REGSHIFT (SMP_CPUID_PTRSHIFT + 3)
173#else
174#define SMP_CPUID_REGSHIFT (SMP_CPUID_PTRSHIFT + 2)
175#endif
176
177#ifdef CONFIG_MIPS_MT_SMTC
178#define ASM_CPUID_MFC0 mfc0
179#define UASM_i_CPUID_MFC0 uasm_i_mfc0
180#else
181#define ASM_CPUID_MFC0 MFC0
182#define UASM_i_CPUID_MFC0 UASM_i_MFC0
183#endif
184
185#endif /* __KERNEL__ */
152#endif /* _ASM_THREAD_INFO_H */ 186#endif /* _ASM_THREAD_INFO_H */
diff --git a/arch/mips/include/asm/time.h b/arch/mips/include/asm/time.h
index 2d7b9df4542d..24f534a7fbc3 100644
--- a/arch/mips/include/asm/time.h
+++ b/arch/mips/include/asm/time.h
@@ -75,7 +75,7 @@ extern int init_r4k_clocksource(void);
75 75
76static inline int init_mips_clocksource(void) 76static inline int init_mips_clocksource(void)
77{ 77{
78#if defined(CONFIG_CSRC_R4K) && !defined(CONFIG_CSRC_GIC) 78#ifdef CONFIG_CSRC_R4K
79 return init_r4k_clocksource(); 79 return init_r4k_clocksource();
80#else 80#else
81 return 0; 81 return 0;
diff --git a/arch/mips/include/asm/timex.h b/arch/mips/include/asm/timex.h
index 6529704aa73a..c5424757da65 100644
--- a/arch/mips/include/asm/timex.h
+++ b/arch/mips/include/asm/timex.h
@@ -10,7 +10,9 @@
10 10
11#ifdef __KERNEL__ 11#ifdef __KERNEL__
12 12
13#include <asm/cpu-features.h>
13#include <asm/mipsregs.h> 14#include <asm/mipsregs.h>
15#include <asm/cpu-type.h>
14 16
15/* 17/*
16 * This is the clock rate of the i8253 PIT. A MIPS system may not have 18 * This is the clock rate of the i8253 PIT. A MIPS system may not have
@@ -33,9 +35,38 @@
33 35
34typedef unsigned int cycles_t; 36typedef unsigned int cycles_t;
35 37
38/*
39 * On R4000/R4400 before version 5.0 an erratum exists such that if the
40 * cycle counter is read in the exact moment that it is matching the
41 * compare register, no interrupt will be generated.
42 *
43 * There is a suggested workaround and also the erratum can't strike if
44 * the compare interrupt isn't being used as the clock source device.
45 * However for now the implementaton of this function doesn't get these
46 * fine details right.
47 */
36static inline cycles_t get_cycles(void) 48static inline cycles_t get_cycles(void)
37{ 49{
38 return 0; 50 switch (boot_cpu_type()) {
51 case CPU_R4400PC:
52 case CPU_R4400SC:
53 case CPU_R4400MC:
54 if ((read_c0_prid() & 0xff) >= 0x0050)
55 return read_c0_count();
56 break;
57
58 case CPU_R4000PC:
59 case CPU_R4000SC:
60 case CPU_R4000MC:
61 break;
62
63 default:
64 if (cpu_has_counter)
65 return read_c0_count();
66 break;
67 }
68
69 return 0; /* no usable counter */
39} 70}
40 71
41#endif /* __KERNEL__ */ 72#endif /* __KERNEL__ */
diff --git a/arch/mips/include/asm/ucontext.h b/arch/mips/include/asm/ucontext.h
deleted file mode 100644
index 9bc07b9f30fb..000000000000
--- a/arch/mips/include/asm/ucontext.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-generic/ucontext.h>
diff --git a/arch/mips/include/asm/unistd.h b/arch/mips/include/asm/unistd.h
index 63c9c886173a..4d3b92886665 100644
--- a/arch/mips/include/asm/unistd.h
+++ b/arch/mips/include/asm/unistd.h
@@ -14,6 +14,13 @@
14 14
15#include <uapi/asm/unistd.h> 15#include <uapi/asm/unistd.h>
16 16
17#ifdef CONFIG_MIPS32_N32
18#define NR_syscalls (__NR_N32_Linux + __NR_N32_Linux_syscalls)
19#elif defined(CONFIG_64BIT)
20#define NR_syscalls (__NR_64_Linux + __NR_64_Linux_syscalls)
21#else
22#define NR_syscalls (__NR_O32_Linux + __NR_O32_Linux_syscalls)
23#endif
17 24
18#ifndef __ASSEMBLY__ 25#ifndef __ASSEMBLY__
19 26
diff --git a/arch/mips/include/asm/vga.h b/arch/mips/include/asm/vga.h
index f4cff7e4fa8a..f82c83749a08 100644
--- a/arch/mips/include/asm/vga.h
+++ b/arch/mips/include/asm/vga.h
@@ -6,6 +6,7 @@
6#ifndef _ASM_VGA_H 6#ifndef _ASM_VGA_H
7#define _ASM_VGA_H 7#define _ASM_VGA_H
8 8
9#include <asm/addrspace.h>
9#include <asm/byteorder.h> 10#include <asm/byteorder.h>
10 11
11/* 12/*
@@ -13,7 +14,7 @@
13 * access the videoram directly without any black magic. 14 * access the videoram directly without any black magic.
14 */ 15 */
15 16
16#define VGA_MAP_MEM(x, s) (0xb0000000L + (unsigned long)(x)) 17#define VGA_MAP_MEM(x, s) CKSEG1ADDR(0x10000000L + (unsigned long)(x))
17 18
18#define vga_readb(x) (*(x)) 19#define vga_readb(x) (*(x))
19#define vga_writeb(x, y) (*(y) = (x)) 20#define vga_writeb(x, y) (*(y) = (x))
diff --git a/arch/mips/include/asm/xor.h b/arch/mips/include/asm/xor.h
deleted file mode 100644
index c82eb12a5b18..000000000000
--- a/arch/mips/include/asm/xor.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-generic/xor.h>
diff --git a/arch/mips/include/uapi/asm/Kbuild b/arch/mips/include/uapi/asm/Kbuild
index 350ccccadcb9..be7196eacb88 100644
--- a/arch/mips/include/uapi/asm/Kbuild
+++ b/arch/mips/include/uapi/asm/Kbuild
@@ -1,7 +1,9 @@
1# UAPI Header export list 1# UAPI Header export list
2include include/uapi/asm-generic/Kbuild.asm 2include include/uapi/asm-generic/Kbuild.asm
3 3
4header-y += auxvec.h 4generic-y += auxvec.h
5generic-y += ipcbuf.h
6
5header-y += bitsperlong.h 7header-y += bitsperlong.h
6header-y += break.h 8header-y += break.h
7header-y += byteorder.h 9header-y += byteorder.h
@@ -11,7 +13,6 @@ header-y += fcntl.h
11header-y += inst.h 13header-y += inst.h
12header-y += ioctl.h 14header-y += ioctl.h
13header-y += ioctls.h 15header-y += ioctls.h
14header-y += ipcbuf.h
15header-y += kvm_para.h 16header-y += kvm_para.h
16header-y += mman.h 17header-y += mman.h
17header-y += msgbuf.h 18header-y += msgbuf.h
diff --git a/arch/mips/include/uapi/asm/auxvec.h b/arch/mips/include/uapi/asm/auxvec.h
deleted file mode 100644
index 7cf7f2d21943..000000000000
--- a/arch/mips/include/uapi/asm/auxvec.h
+++ /dev/null
@@ -1,4 +0,0 @@
1#ifndef _ASM_AUXVEC_H
2#define _ASM_AUXVEC_H
3
4#endif /* _ASM_AUXVEC_H */
diff --git a/arch/mips/include/uapi/asm/errno.h b/arch/mips/include/uapi/asm/errno.h
index 31575e2fd1bd..02d645d7aa9a 100644
--- a/arch/mips/include/uapi/asm/errno.h
+++ b/arch/mips/include/uapi/asm/errno.h
@@ -102,7 +102,7 @@
102#define EWOULDBLOCK EAGAIN /* Operation would block */ 102#define EWOULDBLOCK EAGAIN /* Operation would block */
103#define EALREADY 149 /* Operation already in progress */ 103#define EALREADY 149 /* Operation already in progress */
104#define EINPROGRESS 150 /* Operation now in progress */ 104#define EINPROGRESS 150 /* Operation now in progress */
105#define ESTALE 151 /* Stale NFS file handle */ 105#define ESTALE 151 /* Stale file handle */
106#define ECANCELED 158 /* AIO operation canceled */ 106#define ECANCELED 158 /* AIO operation canceled */
107 107
108/* 108/*
diff --git a/arch/mips/include/uapi/asm/ipcbuf.h b/arch/mips/include/uapi/asm/ipcbuf.h
deleted file mode 100644
index 84c7e51cb6d0..000000000000
--- a/arch/mips/include/uapi/asm/ipcbuf.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-generic/ipcbuf.h>
diff --git a/arch/mips/include/uapi/asm/siginfo.h b/arch/mips/include/uapi/asm/siginfo.h
index 88e292b7719e..e81174432bab 100644
--- a/arch/mips/include/uapi/asm/siginfo.h
+++ b/arch/mips/include/uapi/asm/siginfo.h
@@ -33,6 +33,8 @@ struct siginfo;
33#error _MIPS_SZLONG neither 32 nor 64 33#error _MIPS_SZLONG neither 32 nor 64
34#endif 34#endif
35 35
36#define __ARCH_SIGSYS
37
36#include <asm-generic/siginfo.h> 38#include <asm-generic/siginfo.h>
37 39
38typedef struct siginfo { 40typedef struct siginfo {
@@ -97,6 +99,13 @@ typedef struct siginfo {
97 __ARCH_SI_BAND_T _band; /* POLL_IN, POLL_OUT, POLL_MSG */ 99 __ARCH_SI_BAND_T _band; /* POLL_IN, POLL_OUT, POLL_MSG */
98 int _fd; 100 int _fd;
99 } _sigpoll; 101 } _sigpoll;
102
103 /* SIGSYS */
104 struct {
105 void __user *_call_addr; /* calling user insn */
106 int _syscall; /* triggering system call number */
107 unsigned int _arch; /* AUDIT_ARCH_* of syscall */
108 } _sigsys;
100 } _sifields; 109 } _sifields;
101} siginfo_t; 110} siginfo_t;
102 111
diff --git a/arch/mips/include/uapi/asm/socket.h b/arch/mips/include/uapi/asm/socket.h
index 61c01f054d1b..0df9787cd84d 100644
--- a/arch/mips/include/uapi/asm/socket.h
+++ b/arch/mips/include/uapi/asm/socket.h
@@ -94,4 +94,6 @@
94 94
95#define SO_BUSY_POLL 46 95#define SO_BUSY_POLL 46
96 96
97#define SO_MAX_PACING_RATE 47
98
97#endif /* _UAPI_ASM_SOCKET_H */ 99#endif /* _UAPI_ASM_SOCKET_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-13 07:21:55 -0400