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-rw-r--r--arch/mips/include/asm/bmips.h110
-rw-r--r--arch/mips/include/asm/bootinfo.h1
-rw-r--r--arch/mips/include/asm/branch.h5
-rw-r--r--arch/mips/include/asm/cpu.h6
-rw-r--r--arch/mips/include/asm/gio_device.h56
-rw-r--r--arch/mips/include/asm/hazards.h7
-rw-r--r--arch/mips/include/asm/hugetlb.h2
-rw-r--r--arch/mips/include/asm/kprobes.h5
-rw-r--r--arch/mips/include/asm/mach-ath79/ar71xx_regs.h81
-rw-r--r--arch/mips/include/asm/mach-ath79/ar933x_uart.h67
-rw-r--r--arch/mips/include/asm/mach-ath79/ar933x_uart_platform.h18
-rw-r--r--arch/mips/include/asm/mach-ath79/ath79.h11
-rw-r--r--arch/mips/include/asm/mach-ath79/irq.h8
-rw-r--r--arch/mips/include/asm/mach-ath79/pci-ath724x.h21
-rw-r--r--arch/mips/include/asm/mach-au1x00/au1000.h273
-rw-r--r--arch/mips/include/asm/mach-au1x00/au1100_mmc.h2
-rw-r--r--arch/mips/include/asm/mach-au1x00/au1200fb.h14
-rw-r--r--arch/mips/include/asm/mach-au1x00/au1550nd.h16
-rw-r--r--arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h31
-rw-r--r--arch/mips/include/asm/mach-au1x00/cpu-feature-overrides.h3
-rw-r--r--arch/mips/include/asm/mach-au1x00/gpio-au1300.h241
-rw-r--r--arch/mips/include/asm/mach-au1x00/gpio.h3
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h597
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h2
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h2
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_irq.h12
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h231
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/ioremap.h42
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/irq.h7
-rw-r--r--arch/mips/include/asm/mach-db1x00/bcsr.h36
-rw-r--r--arch/mips/include/asm/mach-db1x00/db1200.h11
-rw-r--r--arch/mips/include/asm/mach-db1x00/db1300.h40
-rw-r--r--arch/mips/include/asm/mach-db1x00/db1x00.h79
-rw-r--r--arch/mips/include/asm/mach-db1x00/irq.h23
-rw-r--r--arch/mips/include/asm/mach-generic/floppy.h2
-rw-r--r--arch/mips/include/asm/mach-jazz/floppy.h2
-rw-r--r--arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h23
-rw-r--r--arch/mips/include/asm/mach-pb1x00/mc146818rtc.h34
-rw-r--r--arch/mips/include/asm/mach-pb1x00/pb1000.h87
-rw-r--r--arch/mips/include/asm/mach-pb1x00/pb1200.h139
-rw-r--r--arch/mips/include/asm/mach-pb1x00/pb1550.h73
-rw-r--r--arch/mips/include/asm/mipsregs.h9
-rw-r--r--arch/mips/include/asm/module.h6
-rw-r--r--arch/mips/include/asm/netlogic/common.h76
-rw-r--r--arch/mips/include/asm/netlogic/haldefs.h163
-rw-r--r--arch/mips/include/asm/netlogic/xlp-hal/bridge.h187
-rw-r--r--arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h83
-rw-r--r--arch/mips/include/asm/netlogic/xlp-hal/iomap.h153
-rw-r--r--arch/mips/include/asm/netlogic/xlp-hal/pic.h411
-rw-r--r--arch/mips/include/asm/netlogic/xlp-hal/sys.h129
-rw-r--r--arch/mips/include/asm/netlogic/xlp-hal/uart.h191
-rw-r--r--arch/mips/include/asm/netlogic/xlp-hal/xlp.h51
-rw-r--r--arch/mips/include/asm/netlogic/xlr/iomap.h22
-rw-r--r--arch/mips/include/asm/netlogic/xlr/msidef.h84
-rw-r--r--arch/mips/include/asm/netlogic/xlr/pic.h69
-rw-r--r--arch/mips/include/asm/netlogic/xlr/xlr.h13
-rw-r--r--arch/mips/include/asm/page.h8
-rw-r--r--arch/mips/include/asm/pgtable-32.h18
-rw-r--r--arch/mips/include/asm/tlbmisc.h10
-rw-r--r--arch/mips/include/asm/traps.h13
60 files changed, 3324 insertions, 795 deletions
diff --git a/arch/mips/include/asm/bmips.h b/arch/mips/include/asm/bmips.h
new file mode 100644
index 000000000000..552a65a0cf2b
--- /dev/null
+++ b/arch/mips/include/asm/bmips.h
@@ -0,0 +1,110 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2011 by Kevin Cernekee (cernekee@gmail.com)
7 *
8 * Definitions for BMIPS processors
9 */
10#ifndef _ASM_BMIPS_H
11#define _ASM_BMIPS_H
12
13#include <linux/compiler.h>
14#include <linux/linkage.h>
15#include <asm/addrspace.h>
16#include <asm/mipsregs.h>
17#include <asm/hazards.h>
18
19/* NOTE: the CBR register returns a PA, and it can be above 0xff00_0000 */
20#define BMIPS_GET_CBR() ((void __iomem *)(CKSEG1 | \
21 (unsigned long) \
22 ((read_c0_brcm_cbr() >> 18) << 18)))
23
24#define BMIPS_RAC_CONFIG 0x00000000
25#define BMIPS_RAC_ADDRESS_RANGE 0x00000004
26#define BMIPS_RAC_CONFIG_1 0x00000008
27#define BMIPS_L2_CONFIG 0x0000000c
28#define BMIPS_LMB_CONTROL 0x0000001c
29#define BMIPS_SYSTEM_BASE 0x00000020
30#define BMIPS_PERF_GLOBAL_CONTROL 0x00020000
31#define BMIPS_PERF_CONTROL_0 0x00020004
32#define BMIPS_PERF_CONTROL_1 0x00020008
33#define BMIPS_PERF_COUNTER_0 0x00020010
34#define BMIPS_PERF_COUNTER_1 0x00020014
35#define BMIPS_PERF_COUNTER_2 0x00020018
36#define BMIPS_PERF_COUNTER_3 0x0002001c
37#define BMIPS_RELO_VECTOR_CONTROL_0 0x00030000
38#define BMIPS_RELO_VECTOR_CONTROL_1 0x00038000
39
40#define BMIPS_NMI_RESET_VEC 0x80000000
41#define BMIPS_WARM_RESTART_VEC 0x80000380
42
43#define ZSCM_REG_BASE 0x97000000
44
45#if !defined(__ASSEMBLY__)
46
47#include <linux/cpumask.h>
48#include <asm/r4kcache.h>
49
50extern struct plat_smp_ops bmips_smp_ops;
51extern char bmips_reset_nmi_vec;
52extern char bmips_reset_nmi_vec_end;
53extern char bmips_smp_movevec;
54extern char bmips_smp_int_vec;
55extern char bmips_smp_int_vec_end;
56
57extern int bmips_smp_enabled;
58extern int bmips_cpu_offset;
59extern cpumask_t bmips_booted_mask;
60
61extern void bmips_ebase_setup(void);
62extern asmlinkage void plat_wired_tlb_setup(void);
63
64static inline unsigned long bmips_read_zscm_reg(unsigned int offset)
65{
66 unsigned long ret;
67
68 __asm__ __volatile__(
69 ".set push\n"
70 ".set noreorder\n"
71 "cache %1, 0(%2)\n"
72 "sync\n"
73 "_ssnop\n"
74 "_ssnop\n"
75 "_ssnop\n"
76 "_ssnop\n"
77 "_ssnop\n"
78 "_ssnop\n"
79 "_ssnop\n"
80 "mfc0 %0, $28, 3\n"
81 "_ssnop\n"
82 ".set pop\n"
83 : "=&r" (ret)
84 : "i" (Index_Load_Tag_S), "r" (ZSCM_REG_BASE + offset)
85 : "memory");
86 return ret;
87}
88
89static inline void bmips_write_zscm_reg(unsigned int offset, unsigned long data)
90{
91 __asm__ __volatile__(
92 ".set push\n"
93 ".set noreorder\n"
94 "mtc0 %0, $28, 3\n"
95 "_ssnop\n"
96 "_ssnop\n"
97 "_ssnop\n"
98 "cache %1, 0(%2)\n"
99 "_ssnop\n"
100 "_ssnop\n"
101 "_ssnop\n"
102 : /* no outputs */
103 : "r" (data),
104 "i" (Index_Store_Tag_S), "r" (ZSCM_REG_BASE + offset)
105 : "memory");
106}
107
108#endif /* !defined(__ASSEMBLY__) */
109
110#endif /* _ASM_BMIPS_H */
diff --git a/arch/mips/include/asm/bootinfo.h b/arch/mips/include/asm/bootinfo.h
index 35cd1bab69c3..7a51d879e6ca 100644
--- a/arch/mips/include/asm/bootinfo.h
+++ b/arch/mips/include/asm/bootinfo.h
@@ -86,6 +86,7 @@ extern unsigned long mips_machtype;
86#define BOOT_MEM_RAM 1 86#define BOOT_MEM_RAM 1
87#define BOOT_MEM_ROM_DATA 2 87#define BOOT_MEM_ROM_DATA 2
88#define BOOT_MEM_RESERVED 3 88#define BOOT_MEM_RESERVED 3
89#define BOOT_MEM_INIT_RAM 4
89 90
90/* 91/*
91 * A memory map that's built upon what was determined 92 * A memory map that's built upon what was determined
diff --git a/arch/mips/include/asm/branch.h b/arch/mips/include/asm/branch.h
index 37c6857c8d4a..888766ae1f85 100644
--- a/arch/mips/include/asm/branch.h
+++ b/arch/mips/include/asm/branch.h
@@ -9,6 +9,7 @@
9#define _ASM_BRANCH_H 9#define _ASM_BRANCH_H
10 10
11#include <asm/ptrace.h> 11#include <asm/ptrace.h>
12#include <asm/inst.h>
12 13
13static inline int delay_slot(struct pt_regs *regs) 14static inline int delay_slot(struct pt_regs *regs)
14{ 15{
@@ -23,7 +24,11 @@ static inline unsigned long exception_epc(struct pt_regs *regs)
23 return regs->cp0_epc + 4; 24 return regs->cp0_epc + 4;
24} 25}
25 26
27#define BRANCH_LIKELY_TAKEN 0x0001
28
26extern int __compute_return_epc(struct pt_regs *regs); 29extern int __compute_return_epc(struct pt_regs *regs);
30extern int __compute_return_epc_for_insn(struct pt_regs *regs,
31 union mips_instruction insn);
27 32
28static inline int compute_return_epc(struct pt_regs *regs) 33static inline int compute_return_epc(struct pt_regs *regs)
29{ 34{
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index 2f7f41873f24..f9fa2a479dd0 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -169,6 +169,10 @@
169#define PRID_IMP_NETLOGIC_XLS412B 0x4c00 169#define PRID_IMP_NETLOGIC_XLS412B 0x4c00
170#define PRID_IMP_NETLOGIC_XLS408B 0x4e00 170#define PRID_IMP_NETLOGIC_XLS408B 0x4e00
171#define PRID_IMP_NETLOGIC_XLS404B 0x4f00 171#define PRID_IMP_NETLOGIC_XLS404B 0x4f00
172#define PRID_IMP_NETLOGIC_AU13XX 0x8000
173
174#define PRID_IMP_NETLOGIC_XLP8XX 0x1000
175#define PRID_IMP_NETLOGIC_XLP3XX 0x1100
172 176
173/* 177/*
174 * Definitions for 7:0 on legacy processors 178 * Definitions for 7:0 on legacy processors
@@ -263,7 +267,7 @@ enum cpu_type_enum {
263 */ 267 */
264 CPU_5KC, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2, 268 CPU_5KC, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2,
265 CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS, CPU_CAVIUM_OCTEON2, 269 CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS, CPU_CAVIUM_OCTEON2,
266 CPU_XLR, 270 CPU_XLR, CPU_XLP,
267 271
268 CPU_LAST 272 CPU_LAST
269}; 273};
diff --git a/arch/mips/include/asm/gio_device.h b/arch/mips/include/asm/gio_device.h
new file mode 100644
index 000000000000..5437c84664bf
--- /dev/null
+++ b/arch/mips/include/asm/gio_device.h
@@ -0,0 +1,56 @@
1#include <linux/device.h>
2#include <linux/mod_devicetable.h>
3
4struct gio_device_id {
5 __u8 id;
6};
7
8struct gio_device {
9 struct device dev;
10 struct resource resource;
11 unsigned int irq;
12 unsigned int slotno;
13
14 const char *name;
15 struct gio_device_id id;
16 unsigned id32:1;
17 unsigned gio64:1;
18};
19#define to_gio_device(d) container_of(d, struct gio_device, dev)
20
21struct gio_driver {
22 const char *name;
23 struct module *owner;
24 const struct gio_device_id *id_table;
25
26 int (*probe)(struct gio_device *, const struct gio_device_id *);
27 void (*remove)(struct gio_device *);
28 int (*suspend)(struct gio_device *, pm_message_t);
29 int (*resume)(struct gio_device *);
30 void (*shutdown)(struct gio_device *);
31
32 struct device_driver driver;
33};
34#define to_gio_driver(drv) container_of(drv, struct gio_driver, driver)
35
36extern const struct gio_device_id *gio_match_device(const struct gio_device_id *,
37 const struct gio_device *);
38extern struct gio_device *gio_dev_get(struct gio_device *);
39extern void gio_dev_put(struct gio_device *);
40
41extern int gio_device_register(struct gio_device *);
42extern void gio_device_unregister(struct gio_device *);
43extern void gio_release_dev(struct device *);
44
45static inline void gio_device_free(struct gio_device *dev)
46{
47 gio_release_dev(&dev->dev);
48}
49
50extern int gio_register_driver(struct gio_driver *);
51extern void gio_unregister_driver(struct gio_driver *);
52
53#define gio_get_drvdata(_dev) drv_get_drvdata(&(_dev)->dev)
54#define gio_set_drvdata(_dev, data) drv_set_drvdata(&(_dev)->dev, (data))
55
56extern void gio_set_master(struct gio_device *);
diff --git a/arch/mips/include/asm/hazards.h b/arch/mips/include/asm/hazards.h
index 4e332165d7b7..b4c20e4f87cd 100644
--- a/arch/mips/include/asm/hazards.h
+++ b/arch/mips/include/asm/hazards.h
@@ -87,7 +87,8 @@ do { \
87 : "=r" (tmp)); \ 87 : "=r" (tmp)); \
88} while (0) 88} while (0)
89 89
90#elif defined(CONFIG_CPU_MIPSR1) && !defined(CONFIG_MIPS_ALCHEMY) 90#elif (defined(CONFIG_CPU_MIPSR1) && !defined(CONFIG_MIPS_ALCHEMY)) || \
91 defined(CONFIG_CPU_BMIPS)
91 92
92/* 93/*
93 * These are slightly complicated by the fact that we guarantee R1 kernels to 94 * These are slightly complicated by the fact that we guarantee R1 kernels to
@@ -139,8 +140,8 @@ do { \
139} while (0) 140} while (0)
140 141
141#elif defined(CONFIG_MIPS_ALCHEMY) || defined(CONFIG_CPU_CAVIUM_OCTEON) || \ 142#elif defined(CONFIG_MIPS_ALCHEMY) || defined(CONFIG_CPU_CAVIUM_OCTEON) || \
142 defined(CONFIG_CPU_LOONGSON2) || defined(CONFIG_CPU_R10000) || \ 143 defined(CONFIG_CPU_LOONGSON2) || defined(CONFIG_CPU_R10000) || \
143 defined(CONFIG_CPU_R5500) 144 defined(CONFIG_CPU_R5500)
144 145
145/* 146/*
146 * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer. 147 * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer.
diff --git a/arch/mips/include/asm/hugetlb.h b/arch/mips/include/asm/hugetlb.h
index c565b7c3f0b5..58d36889f09b 100644
--- a/arch/mips/include/asm/hugetlb.h
+++ b/arch/mips/include/asm/hugetlb.h
@@ -70,7 +70,7 @@ static inline pte_t huge_ptep_get_and_clear(struct mm_struct *mm,
70static inline void huge_ptep_clear_flush(struct vm_area_struct *vma, 70static inline void huge_ptep_clear_flush(struct vm_area_struct *vma,
71 unsigned long addr, pte_t *ptep) 71 unsigned long addr, pte_t *ptep)
72{ 72{
73 flush_tlb_mm(vma->vm_mm); 73 flush_tlb_page(vma, addr & huge_page_mask(hstate_vma(vma)));
74} 74}
75 75
76static inline int huge_pte_none(pte_t pte) 76static inline int huge_pte_none(pte_t pte)
diff --git a/arch/mips/include/asm/kprobes.h b/arch/mips/include/asm/kprobes.h
index e6ea4d4d7205..1fbbca01e681 100644
--- a/arch/mips/include/asm/kprobes.h
+++ b/arch/mips/include/asm/kprobes.h
@@ -74,6 +74,8 @@ struct prev_kprobe {
74 : MAX_JPROBES_STACK_SIZE) 74 : MAX_JPROBES_STACK_SIZE)
75 75
76 76
77#define SKIP_DELAYSLOT 0x0001
78
77/* per-cpu kprobe control block */ 79/* per-cpu kprobe control block */
78struct kprobe_ctlblk { 80struct kprobe_ctlblk {
79 unsigned long kprobe_status; 81 unsigned long kprobe_status;
@@ -82,6 +84,9 @@ struct kprobe_ctlblk {
82 unsigned long kprobe_saved_epc; 84 unsigned long kprobe_saved_epc;
83 unsigned long jprobe_saved_sp; 85 unsigned long jprobe_saved_sp;
84 struct pt_regs jprobe_saved_regs; 86 struct pt_regs jprobe_saved_regs;
87 /* Per-thread fields, used while emulating branches */
88 unsigned long flags;
89 unsigned long target_epc;
85 u8 jprobes_stack[MAX_JPROBES_STACK_SIZE]; 90 u8 jprobes_stack[MAX_JPROBES_STACK_SIZE];
86 struct prev_kprobe prev_kprobe; 91 struct prev_kprobe prev_kprobe;
87}; 92};
diff --git a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
index cda1c8070b27..2f0becb4ec8f 100644
--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
@@ -20,6 +20,10 @@
20#include <linux/bitops.h> 20#include <linux/bitops.h>
21 21
22#define AR71XX_APB_BASE 0x18000000 22#define AR71XX_APB_BASE 0x18000000
23#define AR71XX_EHCI_BASE 0x1b000000
24#define AR71XX_EHCI_SIZE 0x1000
25#define AR71XX_OHCI_BASE 0x1c000000
26#define AR71XX_OHCI_SIZE 0x1000
23#define AR71XX_SPI_BASE 0x1f000000 27#define AR71XX_SPI_BASE 0x1f000000
24#define AR71XX_SPI_SIZE 0x01000000 28#define AR71XX_SPI_SIZE 0x01000000
25 29
@@ -27,6 +31,8 @@
27#define AR71XX_DDR_CTRL_SIZE 0x100 31#define AR71XX_DDR_CTRL_SIZE 0x100
28#define AR71XX_UART_BASE (AR71XX_APB_BASE + 0x00020000) 32#define AR71XX_UART_BASE (AR71XX_APB_BASE + 0x00020000)
29#define AR71XX_UART_SIZE 0x100 33#define AR71XX_UART_SIZE 0x100
34#define AR71XX_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000)
35#define AR71XX_USB_CTRL_SIZE 0x100
30#define AR71XX_GPIO_BASE (AR71XX_APB_BASE + 0x00040000) 36#define AR71XX_GPIO_BASE (AR71XX_APB_BASE + 0x00040000)
31#define AR71XX_GPIO_SIZE 0x100 37#define AR71XX_GPIO_SIZE 0x100
32#define AR71XX_PLL_BASE (AR71XX_APB_BASE + 0x00050000) 38#define AR71XX_PLL_BASE (AR71XX_APB_BASE + 0x00050000)
@@ -34,9 +40,26 @@
34#define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000) 40#define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000)
35#define AR71XX_RESET_SIZE 0x100 41#define AR71XX_RESET_SIZE 0x100
36 42
43#define AR7240_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000)
44#define AR7240_USB_CTRL_SIZE 0x100
45#define AR7240_OHCI_BASE 0x1b000000
46#define AR7240_OHCI_SIZE 0x1000
47
48#define AR724X_EHCI_BASE 0x1b000000
49#define AR724X_EHCI_SIZE 0x1000
50
51#define AR913X_EHCI_BASE 0x1b000000
52#define AR913X_EHCI_SIZE 0x1000
37#define AR913X_WMAC_BASE (AR71XX_APB_BASE + 0x000C0000) 53#define AR913X_WMAC_BASE (AR71XX_APB_BASE + 0x000C0000)
38#define AR913X_WMAC_SIZE 0x30000 54#define AR913X_WMAC_SIZE 0x30000
39 55
56#define AR933X_UART_BASE (AR71XX_APB_BASE + 0x00020000)
57#define AR933X_UART_SIZE 0x14
58#define AR933X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
59#define AR933X_WMAC_SIZE 0x20000
60#define AR933X_EHCI_BASE 0x1b000000
61#define AR933X_EHCI_SIZE 0x1000
62
40/* 63/*
41 * DDR_CTRL block 64 * DDR_CTRL block
42 */ 65 */
@@ -63,6 +86,11 @@
63#define AR913X_DDR_REG_FLUSH_USB 0x84 86#define AR913X_DDR_REG_FLUSH_USB 0x84
64#define AR913X_DDR_REG_FLUSH_WMAC 0x88 87#define AR913X_DDR_REG_FLUSH_WMAC 0x88
65 88
89#define AR933X_DDR_REG_FLUSH_GE0 0x7c
90#define AR933X_DDR_REG_FLUSH_GE1 0x80
91#define AR933X_DDR_REG_FLUSH_USB 0x84
92#define AR933X_DDR_REG_FLUSH_WMAC 0x88
93
66/* 94/*
67 * PLL block 95 * PLL block
68 */ 96 */
@@ -104,6 +132,30 @@
104#define AR913X_AHB_DIV_SHIFT 19 132#define AR913X_AHB_DIV_SHIFT 19
105#define AR913X_AHB_DIV_MASK 0x1 133#define AR913X_AHB_DIV_MASK 0x1
106 134
135#define AR933X_PLL_CPU_CONFIG_REG 0x00
136#define AR933X_PLL_CLOCK_CTRL_REG 0x08
137
138#define AR933X_PLL_CPU_CONFIG_NINT_SHIFT 10
139#define AR933X_PLL_CPU_CONFIG_NINT_MASK 0x3f
140#define AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT 16
141#define AR933X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f
142#define AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT 23
143#define AR933X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7
144
145#define AR933X_PLL_CLOCK_CTRL_BYPASS BIT(2)
146#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT 5
147#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK 0x3
148#define AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT 10
149#define AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK 0x3
150#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT 15
151#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK 0x7
152
153/*
154 * USB_CONFIG block
155 */
156#define AR71XX_USB_CTRL_REG_FLADJ 0x00
157#define AR71XX_USB_CTRL_REG_CONFIG 0x04
158
107/* 159/*
108 * RESET block 160 * RESET block
109 */ 161 */
@@ -130,6 +182,13 @@
130 182
131#define AR724X_RESET_REG_RESET_MODULE 0x1c 183#define AR724X_RESET_REG_RESET_MODULE 0x1c
132 184
185#define AR933X_RESET_REG_RESET_MODULE 0x1c
186#define AR933X_RESET_REG_BOOTSTRAP 0xac
187
188#define MISC_INT_ETHSW BIT(12)
189#define MISC_INT_TIMER4 BIT(10)
190#define MISC_INT_TIMER3 BIT(9)
191#define MISC_INT_TIMER2 BIT(8)
133#define MISC_INT_DMA BIT(7) 192#define MISC_INT_DMA BIT(7)
134#define MISC_INT_OHCI BIT(6) 193#define MISC_INT_OHCI BIT(6)
135#define MISC_INT_PERFC BIT(5) 194#define MISC_INT_PERFC BIT(5)
@@ -158,14 +217,29 @@
158#define AR71XX_RESET_PCI_BUS BIT(1) 217#define AR71XX_RESET_PCI_BUS BIT(1)
159#define AR71XX_RESET_PCI_CORE BIT(0) 218#define AR71XX_RESET_PCI_CORE BIT(0)
160 219
220#define AR7240_RESET_USB_HOST BIT(5)
221#define AR7240_RESET_OHCI_DLL BIT(3)
222
161#define AR724X_RESET_GE1_MDIO BIT(23) 223#define AR724X_RESET_GE1_MDIO BIT(23)
162#define AR724X_RESET_GE0_MDIO BIT(22) 224#define AR724X_RESET_GE0_MDIO BIT(22)
163#define AR724X_RESET_PCIE_PHY_SERIAL BIT(10) 225#define AR724X_RESET_PCIE_PHY_SERIAL BIT(10)
164#define AR724X_RESET_PCIE_PHY BIT(7) 226#define AR724X_RESET_PCIE_PHY BIT(7)
165#define AR724X_RESET_PCIE BIT(6) 227#define AR724X_RESET_PCIE BIT(6)
166#define AR724X_RESET_OHCI_DLL BIT(3) 228#define AR724X_RESET_USB_HOST BIT(5)
229#define AR724X_RESET_USB_PHY BIT(4)
230#define AR724X_RESET_USBSUS_OVERRIDE BIT(3)
167 231
168#define AR913X_RESET_AMBA2WMAC BIT(22) 232#define AR913X_RESET_AMBA2WMAC BIT(22)
233#define AR913X_RESET_USBSUS_OVERRIDE BIT(10)
234#define AR913X_RESET_USB_HOST BIT(5)
235#define AR913X_RESET_USB_PHY BIT(4)
236
237#define AR933X_RESET_WMAC BIT(11)
238#define AR933X_RESET_USB_HOST BIT(5)
239#define AR933X_RESET_USB_PHY BIT(4)
240#define AR933X_RESET_USBSUS_OVERRIDE BIT(3)
241
242#define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0)
169 243
170#define REV_ID_MAJOR_MASK 0xfff0 244#define REV_ID_MAJOR_MASK 0xfff0
171#define REV_ID_MAJOR_AR71XX 0x00a0 245#define REV_ID_MAJOR_AR71XX 0x00a0
@@ -173,6 +247,8 @@
173#define REV_ID_MAJOR_AR7240 0x00c0 247#define REV_ID_MAJOR_AR7240 0x00c0
174#define REV_ID_MAJOR_AR7241 0x0100 248#define REV_ID_MAJOR_AR7241 0x0100
175#define REV_ID_MAJOR_AR7242 0x1100 249#define REV_ID_MAJOR_AR7242 0x1100
250#define REV_ID_MAJOR_AR9330 0x0110
251#define REV_ID_MAJOR_AR9331 0x1110
176 252
177#define AR71XX_REV_ID_MINOR_MASK 0x3 253#define AR71XX_REV_ID_MINOR_MASK 0x3
178#define AR71XX_REV_ID_MINOR_AR7130 0x0 254#define AR71XX_REV_ID_MINOR_AR7130 0x0
@@ -187,6 +263,8 @@
187#define AR913X_REV_ID_REVISION_MASK 0x3 263#define AR913X_REV_ID_REVISION_MASK 0x3
188#define AR913X_REV_ID_REVISION_SHIFT 2 264#define AR913X_REV_ID_REVISION_SHIFT 2
189 265
266#define AR933X_REV_ID_REVISION_MASK 0x3
267
190#define AR724X_REV_ID_REVISION_MASK 0x3 268#define AR724X_REV_ID_REVISION_MASK 0x3
191 269
192/* 270/*
@@ -229,5 +307,6 @@
229#define AR71XX_GPIO_COUNT 16 307#define AR71XX_GPIO_COUNT 16
230#define AR724X_GPIO_COUNT 18 308#define AR724X_GPIO_COUNT 18
231#define AR913X_GPIO_COUNT 22 309#define AR913X_GPIO_COUNT 22
310#define AR933X_GPIO_COUNT 30
232 311
233#endif /* __ASM_MACH_AR71XX_REGS_H */ 312#endif /* __ASM_MACH_AR71XX_REGS_H */
diff --git a/arch/mips/include/asm/mach-ath79/ar933x_uart.h b/arch/mips/include/asm/mach-ath79/ar933x_uart.h
new file mode 100644
index 000000000000..52730555937f
--- /dev/null
+++ b/arch/mips/include/asm/mach-ath79/ar933x_uart.h
@@ -0,0 +1,67 @@
1/*
2 * Atheros AR933X UART defines
3 *
4 * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 */
10
11#ifndef __AR933X_UART_H
12#define __AR933X_UART_H
13
14#define AR933X_UART_REGS_SIZE 20
15#define AR933X_UART_FIFO_SIZE 16
16
17#define AR933X_UART_DATA_REG 0x00
18#define AR933X_UART_CS_REG 0x04
19#define AR933X_UART_CLOCK_REG 0x08
20#define AR933X_UART_INT_REG 0x0c
21#define AR933X_UART_INT_EN_REG 0x10
22
23#define AR933X_UART_DATA_TX_RX_MASK 0xff
24#define AR933X_UART_DATA_RX_CSR BIT(8)
25#define AR933X_UART_DATA_TX_CSR BIT(9)
26
27#define AR933X_UART_CS_PARITY_S 0
28#define AR933X_UART_CS_PARITY_M 0x3
29#define AR933X_UART_CS_PARITY_NONE 0
30#define AR933X_UART_CS_PARITY_ODD 1
31#define AR933X_UART_CS_PARITY_EVEN 2
32#define AR933X_UART_CS_IF_MODE_S 2
33#define AR933X_UART_CS_IF_MODE_M 0x3
34#define AR933X_UART_CS_IF_MODE_NONE 0
35#define AR933X_UART_CS_IF_MODE_DTE 1
36#define AR933X_UART_CS_IF_MODE_DCE 2
37#define AR933X_UART_CS_FLOW_CTRL_S 4
38#define AR933X_UART_CS_FLOW_CTRL_M 0x3
39#define AR933X_UART_CS_DMA_EN BIT(6)
40#define AR933X_UART_CS_TX_READY_ORIDE BIT(7)
41#define AR933X_UART_CS_RX_READY_ORIDE BIT(8)
42#define AR933X_UART_CS_TX_READY BIT(9)
43#define AR933X_UART_CS_RX_BREAK BIT(10)
44#define AR933X_UART_CS_TX_BREAK BIT(11)
45#define AR933X_UART_CS_HOST_INT BIT(12)
46#define AR933X_UART_CS_HOST_INT_EN BIT(13)
47#define AR933X_UART_CS_TX_BUSY BIT(14)
48#define AR933X_UART_CS_RX_BUSY BIT(15)
49
50#define AR933X_UART_CLOCK_STEP_M 0xffff
51#define AR933X_UART_CLOCK_SCALE_M 0xfff
52#define AR933X_UART_CLOCK_SCALE_S 16
53#define AR933X_UART_CLOCK_STEP_M 0xffff
54
55#define AR933X_UART_INT_RX_VALID BIT(0)
56#define AR933X_UART_INT_TX_READY BIT(1)
57#define AR933X_UART_INT_RX_FRAMING_ERR BIT(2)
58#define AR933X_UART_INT_RX_OFLOW_ERR BIT(3)
59#define AR933X_UART_INT_TX_OFLOW_ERR BIT(4)
60#define AR933X_UART_INT_RX_PARITY_ERR BIT(5)
61#define AR933X_UART_INT_RX_BREAK_ON BIT(6)
62#define AR933X_UART_INT_RX_BREAK_OFF BIT(7)
63#define AR933X_UART_INT_RX_FULL BIT(8)
64#define AR933X_UART_INT_TX_EMPTY BIT(9)
65#define AR933X_UART_INT_ALLINTS 0x3ff
66
67#endif /* __AR933X_UART_H */
diff --git a/arch/mips/include/asm/mach-ath79/ar933x_uart_platform.h b/arch/mips/include/asm/mach-ath79/ar933x_uart_platform.h
new file mode 100644
index 000000000000..6cb30f2b7198
--- /dev/null
+++ b/arch/mips/include/asm/mach-ath79/ar933x_uart_platform.h
@@ -0,0 +1,18 @@
1/*
2 * Platform data definition for Atheros AR933X UART
3 *
4 * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 */
10
11#ifndef _AR933X_UART_PLATFORM_H
12#define _AR933X_UART_PLATFORM_H
13
14struct ar933x_uart_platform_data {
15 unsigned uartclk;
16};
17
18#endif /* _AR933X_UART_PLATFORM_H */
diff --git a/arch/mips/include/asm/mach-ath79/ath79.h b/arch/mips/include/asm/mach-ath79/ath79.h
index 6a9f168506fe..6d0c6c9d5622 100644
--- a/arch/mips/include/asm/mach-ath79/ath79.h
+++ b/arch/mips/include/asm/mach-ath79/ath79.h
@@ -26,10 +26,13 @@ enum ath79_soc_type {
26 ATH79_SOC_AR7241, 26 ATH79_SOC_AR7241,
27 ATH79_SOC_AR7242, 27 ATH79_SOC_AR7242,
28 ATH79_SOC_AR9130, 28 ATH79_SOC_AR9130,
29 ATH79_SOC_AR9132 29 ATH79_SOC_AR9132,
30 ATH79_SOC_AR9330,
31 ATH79_SOC_AR9331,
30}; 32};
31 33
32extern enum ath79_soc_type ath79_soc; 34extern enum ath79_soc_type ath79_soc;
35extern unsigned int ath79_soc_rev;
33 36
34static inline int soc_is_ar71xx(void) 37static inline int soc_is_ar71xx(void)
35{ 38{
@@ -66,6 +69,12 @@ static inline int soc_is_ar913x(void)
66 ath79_soc == ATH79_SOC_AR9132); 69 ath79_soc == ATH79_SOC_AR9132);
67} 70}
68 71
72static inline int soc_is_ar933x(void)
73{
74 return (ath79_soc == ATH79_SOC_AR9330 ||
75 ath79_soc == ATH79_SOC_AR9331);
76}
77
69extern void __iomem *ath79_ddr_base; 78extern void __iomem *ath79_ddr_base;
70extern void __iomem *ath79_pll_base; 79extern void __iomem *ath79_pll_base;
71extern void __iomem *ath79_reset_base; 80extern void __iomem *ath79_reset_base;
diff --git a/arch/mips/include/asm/mach-ath79/irq.h b/arch/mips/include/asm/mach-ath79/irq.h
index 189bc6eb9c10..519958fe4e3c 100644
--- a/arch/mips/include/asm/mach-ath79/irq.h
+++ b/arch/mips/include/asm/mach-ath79/irq.h
@@ -10,10 +10,10 @@
10#define __ASM_MACH_ATH79_IRQ_H 10#define __ASM_MACH_ATH79_IRQ_H
11 11
12#define MIPS_CPU_IRQ_BASE 0 12#define MIPS_CPU_IRQ_BASE 0
13#define NR_IRQS 16 13#define NR_IRQS 40
14 14
15#define ATH79_MISC_IRQ_BASE 8 15#define ATH79_MISC_IRQ_BASE 8
16#define ATH79_MISC_IRQ_COUNT 8 16#define ATH79_MISC_IRQ_COUNT 32
17 17
18#define ATH79_CPU_IRQ_IP2 (MIPS_CPU_IRQ_BASE + 2) 18#define ATH79_CPU_IRQ_IP2 (MIPS_CPU_IRQ_BASE + 2)
19#define ATH79_CPU_IRQ_USB (MIPS_CPU_IRQ_BASE + 3) 19#define ATH79_CPU_IRQ_USB (MIPS_CPU_IRQ_BASE + 3)
@@ -30,6 +30,10 @@
30#define ATH79_MISC_IRQ_PERFC (ATH79_MISC_IRQ_BASE + 5) 30#define ATH79_MISC_IRQ_PERFC (ATH79_MISC_IRQ_BASE + 5)
31#define ATH79_MISC_IRQ_OHCI (ATH79_MISC_IRQ_BASE + 6) 31#define ATH79_MISC_IRQ_OHCI (ATH79_MISC_IRQ_BASE + 6)
32#define ATH79_MISC_IRQ_DMA (ATH79_MISC_IRQ_BASE + 7) 32#define ATH79_MISC_IRQ_DMA (ATH79_MISC_IRQ_BASE + 7)
33#define ATH79_MISC_IRQ_TIMER2 (ATH79_MISC_IRQ_BASE + 8)
34#define ATH79_MISC_IRQ_TIMER3 (ATH79_MISC_IRQ_BASE + 9)
35#define ATH79_MISC_IRQ_TIMER4 (ATH79_MISC_IRQ_BASE + 10)
36#define ATH79_MISC_IRQ_ETHSW (ATH79_MISC_IRQ_BASE + 12)
33 37
34#include_next <irq.h> 38#include_next <irq.h>
35 39
diff --git a/arch/mips/include/asm/mach-ath79/pci-ath724x.h b/arch/mips/include/asm/mach-ath79/pci-ath724x.h
new file mode 100644
index 000000000000..454885fa30c3
--- /dev/null
+++ b/arch/mips/include/asm/mach-ath79/pci-ath724x.h
@@ -0,0 +1,21 @@
1/*
2 * Atheros 724x PCI support
3 *
4 * Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 */
10
11#ifndef __ASM_MACH_ATH79_PCI_ATH724X_H
12#define __ASM_MACH_ATH79_PCI_ATH724X_H
13
14struct ath724x_pci_data {
15 int irq;
16 void *pdata;
17};
18
19void ath724x_pci_add_data(struct ath724x_pci_data *data, int size);
20
21#endif /* __ASM_MACH_ATH79_PCI_ATH724X_H */
diff --git a/arch/mips/include/asm/mach-au1x00/au1000.h b/arch/mips/include/asm/mach-au1x00/au1000.h
index de24ec57dd2f..569828d3ccab 100644
--- a/arch/mips/include/asm/mach-au1x00/au1000.h
+++ b/arch/mips/include/asm/mach-au1x00/au1000.h
@@ -136,6 +136,7 @@ static inline int au1xxx_cpu_needs_config_od(void)
136#define ALCHEMY_CPU_AU1100 2 136#define ALCHEMY_CPU_AU1100 2
137#define ALCHEMY_CPU_AU1550 3 137#define ALCHEMY_CPU_AU1550 3
138#define ALCHEMY_CPU_AU1200 4 138#define ALCHEMY_CPU_AU1200 4
139#define ALCHEMY_CPU_AU1300 5
139 140
140static inline int alchemy_get_cputype(void) 141static inline int alchemy_get_cputype(void)
141{ 142{
@@ -156,6 +157,9 @@ static inline int alchemy_get_cputype(void)
156 case 0x05030000: 157 case 0x05030000:
157 return ALCHEMY_CPU_AU1200; 158 return ALCHEMY_CPU_AU1200;
158 break; 159 break;
160 case 0x800c0000:
161 return ALCHEMY_CPU_AU1300;
162 break;
159 } 163 }
160 164
161 return ALCHEMY_CPU_UNKNOWN; 165 return ALCHEMY_CPU_UNKNOWN;
@@ -166,6 +170,7 @@ static inline int alchemy_get_uarts(int type)
166{ 170{
167 switch (type) { 171 switch (type) {
168 case ALCHEMY_CPU_AU1000: 172 case ALCHEMY_CPU_AU1000:
173 case ALCHEMY_CPU_AU1300:
169 return 4; 174 return 4;
170 case ALCHEMY_CPU_AU1500: 175 case ALCHEMY_CPU_AU1500:
171 case ALCHEMY_CPU_AU1200: 176 case ALCHEMY_CPU_AU1200:
@@ -243,6 +248,7 @@ extern unsigned long au1xxx_calc_clock(void);
243/* PM: arch/mips/alchemy/common/sleeper.S, power.c, irq.c */ 248/* PM: arch/mips/alchemy/common/sleeper.S, power.c, irq.c */
244void alchemy_sleep_au1000(void); 249void alchemy_sleep_au1000(void);
245void alchemy_sleep_au1550(void); 250void alchemy_sleep_au1550(void);
251void alchemy_sleep_au1300(void);
246void au_sleep(void); 252void au_sleep(void);
247 253
248/* USB: drivers/usb/host/alchemy-common.c */ 254/* USB: drivers/usb/host/alchemy-common.c */
@@ -251,6 +257,7 @@ enum alchemy_usb_block {
251 ALCHEMY_USB_UDC0, 257 ALCHEMY_USB_UDC0,
252 ALCHEMY_USB_EHCI0, 258 ALCHEMY_USB_EHCI0,
253 ALCHEMY_USB_OTG0, 259 ALCHEMY_USB_OTG0,
260 ALCHEMY_USB_OHCI1,
254}; 261};
255int alchemy_usb_control(int block, int enable); 262int alchemy_usb_control(int block, int enable);
256 263
@@ -263,14 +270,92 @@ struct alchemy_pci_platdata {
263 unsigned long pci_cfg_clr; 270 unsigned long pci_cfg_clr;
264}; 271};
265 272
266/* SOC Interrupt numbers */ 273/* Multifunction pins: Each of these pins can either be assigned to the
274 * GPIO controller or a on-chip peripheral.
275 * Call "au1300_pinfunc_to_dev()" or "au1300_pinfunc_to_gpio()" to
276 * assign one of these to either the GPIO controller or the device.
277 */
278enum au1300_multifunc_pins {
279 /* wake-from-str pins 0-3 */
280 AU1300_PIN_WAKE0 = 0, AU1300_PIN_WAKE1, AU1300_PIN_WAKE2,
281 AU1300_PIN_WAKE3,
282 /* external clock sources for PSCs: 4-5 */
283 AU1300_PIN_EXTCLK0, AU1300_PIN_EXTCLK1,
284 /* 8bit MMC interface on SD0: 6-9 */
285 AU1300_PIN_SD0DAT4, AU1300_PIN_SD0DAT5, AU1300_PIN_SD0DAT6,
286 AU1300_PIN_SD0DAT7,
287 /* aux clk input for freqgen 3: 10 */
288 AU1300_PIN_FG3AUX,
289 /* UART1 pins: 11-18 */
290 AU1300_PIN_U1RI, AU1300_PIN_U1DCD, AU1300_PIN_U1DSR,
291 AU1300_PIN_U1CTS, AU1300_PIN_U1RTS, AU1300_PIN_U1DTR,
292 AU1300_PIN_U1RX, AU1300_PIN_U1TX,
293 /* UART0 pins: 19-24 */
294 AU1300_PIN_U0RI, AU1300_PIN_U0DCD, AU1300_PIN_U0DSR,
295 AU1300_PIN_U0CTS, AU1300_PIN_U0RTS, AU1300_PIN_U0DTR,
296 /* UART2: 25-26 */
297 AU1300_PIN_U2RX, AU1300_PIN_U2TX,
298 /* UART3: 27-28 */
299 AU1300_PIN_U3RX, AU1300_PIN_U3TX,
300 /* LCD controller PWMs, ext pixclock: 29-31 */
301 AU1300_PIN_LCDPWM0, AU1300_PIN_LCDPWM1, AU1300_PIN_LCDCLKIN,
302 /* SD1 interface: 32-37 */
303 AU1300_PIN_SD1DAT0, AU1300_PIN_SD1DAT1, AU1300_PIN_SD1DAT2,
304 AU1300_PIN_SD1DAT3, AU1300_PIN_SD1CMD, AU1300_PIN_SD1CLK,
305 /* SD2 interface: 38-43 */
306 AU1300_PIN_SD2DAT0, AU1300_PIN_SD2DAT1, AU1300_PIN_SD2DAT2,
307 AU1300_PIN_SD2DAT3, AU1300_PIN_SD2CMD, AU1300_PIN_SD2CLK,
308 /* PSC0/1 clocks: 44-45 */
309 AU1300_PIN_PSC0CLK, AU1300_PIN_PSC1CLK,
310 /* PSCs: 46-49/50-53/54-57/58-61 */
311 AU1300_PIN_PSC0SYNC0, AU1300_PIN_PSC0SYNC1, AU1300_PIN_PSC0D0,
312 AU1300_PIN_PSC0D1,
313 AU1300_PIN_PSC1SYNC0, AU1300_PIN_PSC1SYNC1, AU1300_PIN_PSC1D0,
314 AU1300_PIN_PSC1D1,
315 AU1300_PIN_PSC2SYNC0, AU1300_PIN_PSC2SYNC1, AU1300_PIN_PSC2D0,
316 AU1300_PIN_PSC2D1,
317 AU1300_PIN_PSC3SYNC0, AU1300_PIN_PSC3SYNC1, AU1300_PIN_PSC3D0,
318 AU1300_PIN_PSC3D1,
319 /* PCMCIA interface: 62-70 */
320 AU1300_PIN_PCE2, AU1300_PIN_PCE1, AU1300_PIN_PIOS16,
321 AU1300_PIN_PIOR, AU1300_PIN_PWE, AU1300_PIN_PWAIT,
322 AU1300_PIN_PREG, AU1300_PIN_POE, AU1300_PIN_PIOW,
323 /* camera interface H/V sync inputs: 71-72 */
324 AU1300_PIN_CIMLS, AU1300_PIN_CIMFS,
325 /* PSC2/3 clocks: 73-74 */
326 AU1300_PIN_PSC2CLK, AU1300_PIN_PSC3CLK,
327};
328
329/* GPIC (Au1300) pin management: arch/mips/alchemy/common/gpioint.c */
330extern void au1300_pinfunc_to_gpio(enum au1300_multifunc_pins gpio);
331extern void au1300_pinfunc_to_dev(enum au1300_multifunc_pins gpio);
332extern void au1300_set_irq_priority(unsigned int irq, int p);
333extern void au1300_set_dbdma_gpio(int dchan, unsigned int gpio);
334
335/* Au1300 allows to disconnect certain blocks from internal power supply */
336enum au1300_vss_block {
337 AU1300_VSS_MPE = 0,
338 AU1300_VSS_BSA,
339 AU1300_VSS_GPE,
340 AU1300_VSS_MGP,
341};
267 342
343extern void au1300_vss_block_control(int block, int enable);
344
345
346/* SOC Interrupt numbers */
347/* Au1000-style (IC0/1): 2 controllers with 32 sources each */
268#define AU1000_INTC0_INT_BASE (MIPS_CPU_IRQ_BASE + 8) 348#define AU1000_INTC0_INT_BASE (MIPS_CPU_IRQ_BASE + 8)
269#define AU1000_INTC0_INT_LAST (AU1000_INTC0_INT_BASE + 31) 349#define AU1000_INTC0_INT_LAST (AU1000_INTC0_INT_BASE + 31)
270#define AU1000_INTC1_INT_BASE (AU1000_INTC0_INT_LAST + 1) 350#define AU1000_INTC1_INT_BASE (AU1000_INTC0_INT_LAST + 1)
271#define AU1000_INTC1_INT_LAST (AU1000_INTC1_INT_BASE + 31) 351#define AU1000_INTC1_INT_LAST (AU1000_INTC1_INT_BASE + 31)
272#define AU1000_MAX_INTR AU1000_INTC1_INT_LAST 352#define AU1000_MAX_INTR AU1000_INTC1_INT_LAST
273 353
354/* Au1300-style (GPIC): 1 controller with up to 128 sources */
355#define ALCHEMY_GPIC_INT_BASE (MIPS_CPU_IRQ_BASE + 8)
356#define ALCHEMY_GPIC_INT_NUM 128
357#define ALCHEMY_GPIC_INT_LAST (ALCHEMY_GPIC_INT_BASE + ALCHEMY_GPIC_INT_NUM - 1)
358
274enum soc_au1000_ints { 359enum soc_au1000_ints {
275 AU1000_FIRST_INT = AU1000_INTC0_INT_BASE, 360 AU1000_FIRST_INT = AU1000_INTC0_INT_BASE,
276 AU1000_UART0_INT = AU1000_FIRST_INT, 361 AU1000_UART0_INT = AU1000_FIRST_INT,
@@ -591,24 +676,77 @@ enum soc_au1200_ints {
591 676
592#endif /* !defined (_LANGUAGE_ASSEMBLY) */ 677#endif /* !defined (_LANGUAGE_ASSEMBLY) */
593 678
679/* Au1300 peripheral interrupt numbers */
680#define AU1300_FIRST_INT (ALCHEMY_GPIC_INT_BASE)
681#define AU1300_UART1_INT (AU1300_FIRST_INT + 17)
682#define AU1300_UART2_INT (AU1300_FIRST_INT + 25)
683#define AU1300_UART3_INT (AU1300_FIRST_INT + 27)
684#define AU1300_SD1_INT (AU1300_FIRST_INT + 32)
685#define AU1300_SD2_INT (AU1300_FIRST_INT + 38)
686#define AU1300_PSC0_INT (AU1300_FIRST_INT + 48)
687#define AU1300_PSC1_INT (AU1300_FIRST_INT + 52)
688#define AU1300_PSC2_INT (AU1300_FIRST_INT + 56)
689#define AU1300_PSC3_INT (AU1300_FIRST_INT + 60)
690#define AU1300_NAND_INT (AU1300_FIRST_INT + 62)
691#define AU1300_DDMA_INT (AU1300_FIRST_INT + 75)
692#define AU1300_MMU_INT (AU1300_FIRST_INT + 76)
693#define AU1300_MPU_INT (AU1300_FIRST_INT + 77)
694#define AU1300_GPU_INT (AU1300_FIRST_INT + 78)
695#define AU1300_UDMA_INT (AU1300_FIRST_INT + 79)
696#define AU1300_TOY_INT (AU1300_FIRST_INT + 80)
697#define AU1300_TOY_MATCH0_INT (AU1300_FIRST_INT + 81)
698#define AU1300_TOY_MATCH1_INT (AU1300_FIRST_INT + 82)
699#define AU1300_TOY_MATCH2_INT (AU1300_FIRST_INT + 83)
700#define AU1300_RTC_INT (AU1300_FIRST_INT + 84)
701#define AU1300_RTC_MATCH0_INT (AU1300_FIRST_INT + 85)
702#define AU1300_RTC_MATCH1_INT (AU1300_FIRST_INT + 86)
703#define AU1300_RTC_MATCH2_INT (AU1300_FIRST_INT + 87)
704#define AU1300_UART0_INT (AU1300_FIRST_INT + 88)
705#define AU1300_SD0_INT (AU1300_FIRST_INT + 89)
706#define AU1300_USB_INT (AU1300_FIRST_INT + 90)
707#define AU1300_LCD_INT (AU1300_FIRST_INT + 91)
708#define AU1300_BSA_INT (AU1300_FIRST_INT + 92)
709#define AU1300_MPE_INT (AU1300_FIRST_INT + 93)
710#define AU1300_ITE_INT (AU1300_FIRST_INT + 94)
711#define AU1300_AES_INT (AU1300_FIRST_INT + 95)
712#define AU1300_CIM_INT (AU1300_FIRST_INT + 96)
713
714/**********************************************************************/
715
594/* 716/*
595 * Physical base addresses for integrated peripherals 717 * Physical base addresses for integrated peripherals
596 * 0..au1000 1..au1500 2..au1100 3..au1550 4..au1200 718 * 0..au1000 1..au1500 2..au1100 3..au1550 4..au1200 5..au1300
597 */ 719 */
598 720
599#define AU1000_AC97_PHYS_ADDR 0x10000000 /* 012 */ 721#define AU1000_AC97_PHYS_ADDR 0x10000000 /* 012 */
722#define AU1300_ROM_PHYS_ADDR 0x10000000 /* 5 */
723#define AU1300_OTP_PHYS_ADDR 0x10002000 /* 5 */
724#define AU1300_VSS_PHYS_ADDR 0x10003000 /* 5 */
725#define AU1300_UART0_PHYS_ADDR 0x10100000 /* 5 */
726#define AU1300_UART1_PHYS_ADDR 0x10101000 /* 5 */
727#define AU1300_UART2_PHYS_ADDR 0x10102000 /* 5 */
728#define AU1300_UART3_PHYS_ADDR 0x10103000 /* 5 */
600#define AU1000_USB_OHCI_PHYS_ADDR 0x10100000 /* 012 */ 729#define AU1000_USB_OHCI_PHYS_ADDR 0x10100000 /* 012 */
601#define AU1000_USB_UDC_PHYS_ADDR 0x10200000 /* 0123 */ 730#define AU1000_USB_UDC_PHYS_ADDR 0x10200000 /* 0123 */
731#define AU1300_GPIC_PHYS_ADDR 0x10200000 /* 5 */
602#define AU1000_IRDA_PHYS_ADDR 0x10300000 /* 02 */ 732#define AU1000_IRDA_PHYS_ADDR 0x10300000 /* 02 */
603#define AU1200_AES_PHYS_ADDR 0x10300000 /* 4 */ 733#define AU1200_AES_PHYS_ADDR 0x10300000 /* 45 */
604#define AU1000_IC0_PHYS_ADDR 0x10400000 /* 01234 */ 734#define AU1000_IC0_PHYS_ADDR 0x10400000 /* 01234 */
735#define AU1300_GPU_PHYS_ADDR 0x10500000 /* 5 */
605#define AU1000_MAC0_PHYS_ADDR 0x10500000 /* 023 */ 736#define AU1000_MAC0_PHYS_ADDR 0x10500000 /* 023 */
606#define AU1000_MAC1_PHYS_ADDR 0x10510000 /* 023 */ 737#define AU1000_MAC1_PHYS_ADDR 0x10510000 /* 023 */
607#define AU1000_MACEN_PHYS_ADDR 0x10520000 /* 023 */ 738#define AU1000_MACEN_PHYS_ADDR 0x10520000 /* 023 */
608#define AU1100_SD0_PHYS_ADDR 0x10600000 /* 24 */ 739#define AU1100_SD0_PHYS_ADDR 0x10600000 /* 245 */
740#define AU1300_SD1_PHYS_ADDR 0x10601000 /* 5 */
741#define AU1300_SD2_PHYS_ADDR 0x10602000 /* 5 */
609#define AU1100_SD1_PHYS_ADDR 0x10680000 /* 24 */ 742#define AU1100_SD1_PHYS_ADDR 0x10680000 /* 24 */
743#define AU1300_SYS_PHYS_ADDR 0x10900000 /* 5 */
610#define AU1550_PSC2_PHYS_ADDR 0x10A00000 /* 3 */ 744#define AU1550_PSC2_PHYS_ADDR 0x10A00000 /* 3 */
611#define AU1550_PSC3_PHYS_ADDR 0x10B00000 /* 3 */ 745#define AU1550_PSC3_PHYS_ADDR 0x10B00000 /* 3 */
746#define AU1300_PSC0_PHYS_ADDR 0x10A00000 /* 5 */
747#define AU1300_PSC1_PHYS_ADDR 0x10A01000 /* 5 */
748#define AU1300_PSC2_PHYS_ADDR 0x10A02000 /* 5 */
749#define AU1300_PSC3_PHYS_ADDR 0x10A03000 /* 5 */
612#define AU1000_I2S_PHYS_ADDR 0x11000000 /* 02 */ 750#define AU1000_I2S_PHYS_ADDR 0x11000000 /* 02 */
613#define AU1500_MAC0_PHYS_ADDR 0x11500000 /* 1 */ 751#define AU1500_MAC0_PHYS_ADDR 0x11500000 /* 1 */
614#define AU1500_MAC1_PHYS_ADDR 0x11510000 /* 1 */ 752#define AU1500_MAC1_PHYS_ADDR 0x11510000 /* 1 */
@@ -622,37 +760,96 @@ enum soc_au1200_ints {
622#define AU1000_SSI1_PHYS_ADDR 0x11680000 /* 02 */ 760#define AU1000_SSI1_PHYS_ADDR 0x11680000 /* 02 */
623#define AU1500_GPIO2_PHYS_ADDR 0x11700000 /* 1234 */ 761#define AU1500_GPIO2_PHYS_ADDR 0x11700000 /* 1234 */
624#define AU1000_IC1_PHYS_ADDR 0x11800000 /* 01234 */ 762#define AU1000_IC1_PHYS_ADDR 0x11800000 /* 01234 */
625#define AU1000_SYS_PHYS_ADDR 0x11900000 /* 01234 */ 763#define AU1000_SYS_PHYS_ADDR 0x11900000 /* 012345 */
626#define AU1550_PSC0_PHYS_ADDR 0x11A00000 /* 34 */ 764#define AU1550_PSC0_PHYS_ADDR 0x11A00000 /* 34 */
627#define AU1550_PSC1_PHYS_ADDR 0x11B00000 /* 34 */ 765#define AU1550_PSC1_PHYS_ADDR 0x11B00000 /* 34 */
628#define AU1000_MEM_PHYS_ADDR 0x14000000 /* 01234 */ 766#define AU1000_MEM_PHYS_ADDR 0x14000000 /* 01234 */
629#define AU1000_STATIC_MEM_PHYS_ADDR 0x14001000 /* 01234 */ 767#define AU1000_STATIC_MEM_PHYS_ADDR 0x14001000 /* 01234 */
768#define AU1300_UDMA_PHYS_ADDR 0x14001800 /* 5 */
630#define AU1000_DMA_PHYS_ADDR 0x14002000 /* 012 */ 769#define AU1000_DMA_PHYS_ADDR 0x14002000 /* 012 */
631#define AU1550_DBDMA_PHYS_ADDR 0x14002000 /* 34 */ 770#define AU1550_DBDMA_PHYS_ADDR 0x14002000 /* 345 */
632#define AU1550_DBDMA_CONF_PHYS_ADDR 0x14003000 /* 34 */ 771#define AU1550_DBDMA_CONF_PHYS_ADDR 0x14003000 /* 345 */
633#define AU1000_MACDMA0_PHYS_ADDR 0x14004000 /* 0123 */ 772#define AU1000_MACDMA0_PHYS_ADDR 0x14004000 /* 0123 */
634#define AU1000_MACDMA1_PHYS_ADDR 0x14004200 /* 0123 */ 773#define AU1000_MACDMA1_PHYS_ADDR 0x14004200 /* 0123 */
635#define AU1200_CIM_PHYS_ADDR 0x14004000 /* 4 */ 774#define AU1200_CIM_PHYS_ADDR 0x14004000 /* 45 */
636#define AU1500_PCI_PHYS_ADDR 0x14005000 /* 13 */ 775#define AU1500_PCI_PHYS_ADDR 0x14005000 /* 13 */
637#define AU1550_PE_PHYS_ADDR 0x14008000 /* 3 */ 776#define AU1550_PE_PHYS_ADDR 0x14008000 /* 3 */
638#define AU1200_MAEBE_PHYS_ADDR 0x14010000 /* 4 */ 777#define AU1200_MAEBE_PHYS_ADDR 0x14010000 /* 4 */
639#define AU1200_MAEFE_PHYS_ADDR 0x14012000 /* 4 */ 778#define AU1200_MAEFE_PHYS_ADDR 0x14012000 /* 4 */
779#define AU1300_MAEITE_PHYS_ADDR 0x14010000 /* 5 */
780#define AU1300_MAEMPE_PHYS_ADDR 0x14014000 /* 5 */
640#define AU1550_USB_OHCI_PHYS_ADDR 0x14020000 /* 3 */ 781#define AU1550_USB_OHCI_PHYS_ADDR 0x14020000 /* 3 */
641#define AU1200_USB_CTL_PHYS_ADDR 0x14020000 /* 4 */ 782#define AU1200_USB_CTL_PHYS_ADDR 0x14020000 /* 4 */
642#define AU1200_USB_OTG_PHYS_ADDR 0x14020020 /* 4 */ 783#define AU1200_USB_OTG_PHYS_ADDR 0x14020020 /* 4 */
643#define AU1200_USB_OHCI_PHYS_ADDR 0x14020100 /* 4 */ 784#define AU1200_USB_OHCI_PHYS_ADDR 0x14020100 /* 4 */
644#define AU1200_USB_EHCI_PHYS_ADDR 0x14020200 /* 4 */ 785#define AU1200_USB_EHCI_PHYS_ADDR 0x14020200 /* 4 */
645#define AU1200_USB_UDC_PHYS_ADDR 0x14022000 /* 4 */ 786#define AU1200_USB_UDC_PHYS_ADDR 0x14022000 /* 4 */
787#define AU1300_USB_EHCI_PHYS_ADDR 0x14020000 /* 5 */
788#define AU1300_USB_OHCI0_PHYS_ADDR 0x14020400 /* 5 */
789#define AU1300_USB_OHCI1_PHYS_ADDR 0x14020800 /* 5 */
790#define AU1300_USB_CTL_PHYS_ADDR 0x14021000 /* 5 */
791#define AU1300_USB_OTG_PHYS_ADDR 0x14022000 /* 5 */
792#define AU1300_MAEBSA_PHYS_ADDR 0x14030000 /* 5 */
646#define AU1100_LCD_PHYS_ADDR 0x15000000 /* 2 */ 793#define AU1100_LCD_PHYS_ADDR 0x15000000 /* 2 */
647#define AU1200_LCD_PHYS_ADDR 0x15000000 /* 4 */ 794#define AU1200_LCD_PHYS_ADDR 0x15000000 /* 45 */
648#define AU1500_PCI_MEM_PHYS_ADDR 0x400000000ULL /* 13 */ 795#define AU1500_PCI_MEM_PHYS_ADDR 0x400000000ULL /* 13 */
649#define AU1500_PCI_IO_PHYS_ADDR 0x500000000ULL /* 13 */ 796#define AU1500_PCI_IO_PHYS_ADDR 0x500000000ULL /* 13 */
650#define AU1500_PCI_CONFIG0_PHYS_ADDR 0x600000000ULL /* 13 */ 797#define AU1500_PCI_CONFIG0_PHYS_ADDR 0x600000000ULL /* 13 */
651#define AU1500_PCI_CONFIG1_PHYS_ADDR 0x680000000ULL /* 13 */ 798#define AU1500_PCI_CONFIG1_PHYS_ADDR 0x680000000ULL /* 13 */
652#define AU1000_PCMCIA_IO_PHYS_ADDR 0xF00000000ULL /* 01234 */ 799#define AU1000_PCMCIA_IO_PHYS_ADDR 0xF00000000ULL /* 012345 */
653#define AU1000_PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL /* 01234 */ 800#define AU1000_PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL /* 012345 */
654#define AU1000_PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL /* 01234 */ 801#define AU1000_PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL /* 012345 */
655 802
803/**********************************************************************/
804
805
806/*
807 * Au1300 GPIO+INT controller (GPIC) register offsets and bits
808 * Registers are 128bits (0x10 bytes), divided into 4 "banks".
809 */
810#define AU1300_GPIC_PINVAL 0x0000
811#define AU1300_GPIC_PINVALCLR 0x0010
812#define AU1300_GPIC_IPEND 0x0020
813#define AU1300_GPIC_PRIENC 0x0030
814#define AU1300_GPIC_IEN 0x0040 /* int_mask in manual */
815#define AU1300_GPIC_IDIS 0x0050 /* int_maskclr in manual */
816#define AU1300_GPIC_DMASEL 0x0060
817#define AU1300_GPIC_DEVSEL 0x0080
818#define AU1300_GPIC_DEVCLR 0x0090
819#define AU1300_GPIC_RSTVAL 0x00a0
820/* pin configuration space. one 32bit register for up to 128 IRQs */
821#define AU1300_GPIC_PINCFG 0x1000
822
823#define GPIC_GPIO_TO_BIT(gpio) \
824 (1 << ((gpio) & 0x1f))
825
826#define GPIC_GPIO_BANKOFF(gpio) \
827 (((gpio) >> 5) * 4)
828
829/* Pin Control bits: who owns the pin, what does it do */
830#define GPIC_CFG_PC_GPIN 0
831#define GPIC_CFG_PC_DEV 1
832#define GPIC_CFG_PC_GPOLOW 2
833#define GPIC_CFG_PC_GPOHIGH 3
834#define GPIC_CFG_PC_MASK 3
835
836/* assign pin to MIPS IRQ line */
837#define GPIC_CFG_IL_SET(x) (((x) & 3) << 2)
838#define GPIC_CFG_IL_MASK (3 << 2)
839
840/* pin interrupt type setup */
841#define GPIC_CFG_IC_OFF (0 << 4)
842#define GPIC_CFG_IC_LEVEL_LOW (1 << 4)
843#define GPIC_CFG_IC_LEVEL_HIGH (2 << 4)
844#define GPIC_CFG_IC_EDGE_FALL (5 << 4)
845#define GPIC_CFG_IC_EDGE_RISE (6 << 4)
846#define GPIC_CFG_IC_EDGE_BOTH (7 << 4)
847#define GPIC_CFG_IC_MASK (7 << 4)
848
849/* allow interrupt to wake cpu from 'wait' */
850#define GPIC_CFG_IDLEWAKE (1 << 7)
851
852/***********************************************************************/
656 853
657/* Au1000 SDRAM memory controller register offsets */ 854/* Au1000 SDRAM memory controller register offsets */
658#define AU1000_MEM_SDMODE0 0x0000 855#define AU1000_MEM_SDMODE0 0x0000
@@ -1068,44 +1265,20 @@ enum soc_au1200_ints {
1068#define SSI_ENABLE_CD (1 << 1) 1265#define SSI_ENABLE_CD (1 << 1)
1069#define SSI_ENABLE_E (1 << 0) 1266#define SSI_ENABLE_E (1 << 0)
1070 1267
1071/* IrDA Controller */ 1268
1072#define IRDA_BASE 0xB0300000 1269/*
1073#define IR_RING_PTR_STATUS (IRDA_BASE + 0x00) 1270 * The IrDA peripheral has an IRFIRSEL pin, but on the DB/PB boards it's not
1074#define IR_RING_BASE_ADDR_H (IRDA_BASE + 0x04) 1271 * used to select FIR/SIR mode on the transceiver but as a GPIO. Instead a
1075#define IR_RING_BASE_ADDR_L (IRDA_BASE + 0x08) 1272 * CPLD has to be told about the mode.
1076#define IR_RING_SIZE (IRDA_BASE + 0x0C) 1273 */
1077#define IR_RING_PROMPT (IRDA_BASE + 0x10) 1274#define AU1000_IRDA_PHY_MODE_OFF 0
1078#define IR_RING_ADDR_CMPR (IRDA_BASE + 0x14) 1275#define AU1000_IRDA_PHY_MODE_SIR 1
1079#define IR_INT_CLEAR (IRDA_BASE + 0x18) 1276#define AU1000_IRDA_PHY_MODE_FIR 2
1080#define IR_CONFIG_1 (IRDA_BASE + 0x20) 1277
1081# define IR_RX_INVERT_LED (1 << 0) 1278struct au1k_irda_platform_data {
1082# define IR_TX_INVERT_LED (1 << 1) 1279 void(*set_phy_mode)(int mode);
1083# define IR_ST (1 << 2) 1280};
1084# define IR_SF (1 << 3) 1281
1085# define IR_SIR (1 << 4)
1086# define IR_MIR (1 << 5)
1087# define IR_FIR (1 << 6)
1088# define IR_16CRC (1 << 7)
1089# define IR_TD (1 << 8)
1090# define IR_RX_ALL (1 << 9)
1091# define IR_DMA_ENABLE (1 << 10)
1092# define IR_RX_ENABLE (1 << 11)
1093# define IR_TX_ENABLE (1 << 12)
1094# define IR_LOOPBACK (1 << 14)
1095# define IR_SIR_MODE (IR_SIR | IR_DMA_ENABLE | \
1096 IR_RX_ALL | IR_RX_ENABLE | IR_SF | IR_16CRC)
1097#define IR_SIR_FLAGS (IRDA_BASE + 0x24)
1098#define IR_ENABLE (IRDA_BASE + 0x28)
1099# define IR_RX_STATUS (1 << 9)
1100# define IR_TX_STATUS (1 << 10)
1101#define IR_READ_PHY_CONFIG (IRDA_BASE + 0x2C)
1102#define IR_WRITE_PHY_CONFIG (IRDA_BASE + 0x30)
1103#define IR_MAX_PKT_LEN (IRDA_BASE + 0x34)
1104#define IR_RX_BYTE_CNT (IRDA_BASE + 0x38)
1105#define IR_CONFIG_2 (IRDA_BASE + 0x3C)
1106# define IR_MODE_INV (1 << 0)
1107# define IR_ONE_PIN (1 << 1)
1108#define IR_INTERFACE_CONFIG (IRDA_BASE + 0x40)
1109 1282
1110/* GPIO */ 1283/* GPIO */
1111#define SYS_PINFUNC 0xB190002C 1284#define SYS_PINFUNC 0xB190002C
diff --git a/arch/mips/include/asm/mach-au1x00/au1100_mmc.h b/arch/mips/include/asm/mach-au1x00/au1100_mmc.h
index 94000a3b6f0b..e221659f1bca 100644
--- a/arch/mips/include/asm/mach-au1x00/au1100_mmc.h
+++ b/arch/mips/include/asm/mach-au1x00/au1100_mmc.h
@@ -130,8 +130,10 @@ struct au1xmmc_platform_data {
130#define SD_CONFIG2_DF (0x00000008) 130#define SD_CONFIG2_DF (0x00000008)
131#define SD_CONFIG2_DC (0x00000010) 131#define SD_CONFIG2_DC (0x00000010)
132#define SD_CONFIG2_xx2 (0x000000e0) 132#define SD_CONFIG2_xx2 (0x000000e0)
133#define SD_CONFIG2_BB (0x00000080)
133#define SD_CONFIG2_WB (0x00000100) 134#define SD_CONFIG2_WB (0x00000100)
134#define SD_CONFIG2_RW (0x00000200) 135#define SD_CONFIG2_RW (0x00000200)
136#define SD_CONFIG2_DP (0x00000400)
135 137
136 138
137/* 139/*
diff --git a/arch/mips/include/asm/mach-au1x00/au1200fb.h b/arch/mips/include/asm/mach-au1x00/au1200fb.h
new file mode 100644
index 000000000000..b3c87cc64bb9
--- /dev/null
+++ b/arch/mips/include/asm/mach-au1x00/au1200fb.h
@@ -0,0 +1,14 @@
1/*
2 * platform data for au1200fb driver.
3 */
4
5#ifndef _AU1200FB_PLAT_H_
6#define _AU1200FB_PLAT_H_
7
8struct au1200fb_platdata {
9 int (*panel_index)(void);
10 int (*panel_init)(void);
11 int (*panel_shutdown)(void);
12};
13
14#endif
diff --git a/arch/mips/include/asm/mach-au1x00/au1550nd.h b/arch/mips/include/asm/mach-au1x00/au1550nd.h
new file mode 100644
index 000000000000..ad4c0a03afef
--- /dev/null
+++ b/arch/mips/include/asm/mach-au1x00/au1550nd.h
@@ -0,0 +1,16 @@
1/*
2 * platform data for the Au1550 NAND driver
3 */
4
5#ifndef _AU1550ND_H_
6#define _AU1550ND_H_
7
8#include <linux/mtd/partitions.h>
9
10struct au1550nd_platdata {
11 struct mtd_partition *parts;
12 int num_parts;
13 int devwidth; /* 0 = 8bit device, 1 = 16bit device */
14};
15
16#endif
diff --git a/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h b/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h
index 323ce2d145f2..217810e18361 100644
--- a/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h
+++ b/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h
@@ -183,6 +183,37 @@ typedef volatile struct au1xxx_ddma_desc {
183#define AU1200_DSCR_CMD0_PSC1_SYNC 25 183#define AU1200_DSCR_CMD0_PSC1_SYNC 25
184#define AU1200_DSCR_CMD0_CIM_SYNC 26 184#define AU1200_DSCR_CMD0_CIM_SYNC 26
185 185
186#define AU1300_DSCR_CMD0_UART0_TX 0
187#define AU1300_DSCR_CMD0_UART0_RX 1
188#define AU1300_DSCR_CMD0_UART1_TX 2
189#define AU1300_DSCR_CMD0_UART1_RX 3
190#define AU1300_DSCR_CMD0_UART2_TX 4
191#define AU1300_DSCR_CMD0_UART2_RX 5
192#define AU1300_DSCR_CMD0_UART3_TX 6
193#define AU1300_DSCR_CMD0_UART3_RX 7
194#define AU1300_DSCR_CMD0_SDMS_TX0 8
195#define AU1300_DSCR_CMD0_SDMS_RX0 9
196#define AU1300_DSCR_CMD0_SDMS_TX1 10
197#define AU1300_DSCR_CMD0_SDMS_RX1 11
198#define AU1300_DSCR_CMD0_AES_TX 12
199#define AU1300_DSCR_CMD0_AES_RX 13
200#define AU1300_DSCR_CMD0_PSC0_TX 14
201#define AU1300_DSCR_CMD0_PSC0_RX 15
202#define AU1300_DSCR_CMD0_PSC1_TX 16
203#define AU1300_DSCR_CMD0_PSC1_RX 17
204#define AU1300_DSCR_CMD0_PSC2_TX 18
205#define AU1300_DSCR_CMD0_PSC2_RX 19
206#define AU1300_DSCR_CMD0_PSC3_TX 20
207#define AU1300_DSCR_CMD0_PSC3_RX 21
208#define AU1300_DSCR_CMD0_LCD 22
209#define AU1300_DSCR_CMD0_NAND_FLASH 23
210#define AU1300_DSCR_CMD0_SDMS_TX2 24
211#define AU1300_DSCR_CMD0_SDMS_RX2 25
212#define AU1300_DSCR_CMD0_CIM_SYNC 26
213#define AU1300_DSCR_CMD0_UDMA 27
214#define AU1300_DSCR_CMD0_DMA_REQ0 28
215#define AU1300_DSCR_CMD0_DMA_REQ1 29
216
186#define DSCR_CMD0_THROTTLE 30 217#define DSCR_CMD0_THROTTLE 30
187#define DSCR_CMD0_ALWAYS 31 218#define DSCR_CMD0_ALWAYS 31
188#define DSCR_NDEV_IDS 32 219#define DSCR_NDEV_IDS 32
diff --git a/arch/mips/include/asm/mach-au1x00/cpu-feature-overrides.h b/arch/mips/include/asm/mach-au1x00/cpu-feature-overrides.h
index d5df0cab9b87..3f741af37d47 100644
--- a/arch/mips/include/asm/mach-au1x00/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-au1x00/cpu-feature-overrides.h
@@ -13,12 +13,14 @@
13#define cpu_has_4k_cache 1 13#define cpu_has_4k_cache 1
14#define cpu_has_tx39_cache 0 14#define cpu_has_tx39_cache 0
15#define cpu_has_fpu 0 15#define cpu_has_fpu 0
16#define cpu_has_32fpr 0
16#define cpu_has_counter 1 17#define cpu_has_counter 1
17#define cpu_has_watch 1 18#define cpu_has_watch 1
18#define cpu_has_divec 1 19#define cpu_has_divec 1
19#define cpu_has_vce 0 20#define cpu_has_vce 0
20#define cpu_has_cache_cdex_p 0 21#define cpu_has_cache_cdex_p 0
21#define cpu_has_cache_cdex_s 0 22#define cpu_has_cache_cdex_s 0
23#define cpu_has_prefetch 1
22#define cpu_has_mcheck 1 24#define cpu_has_mcheck 1
23#define cpu_has_ejtag 1 25#define cpu_has_ejtag 1
24#define cpu_has_llsc 1 26#define cpu_has_llsc 1
@@ -29,6 +31,7 @@
29#define cpu_has_vtag_icache 0 31#define cpu_has_vtag_icache 0
30#define cpu_has_dc_aliases 0 32#define cpu_has_dc_aliases 0
31#define cpu_has_ic_fills_f_dc 1 33#define cpu_has_ic_fills_f_dc 1
34#define cpu_has_pindexed_dcache 0
32#define cpu_has_mips32r1 1 35#define cpu_has_mips32r1 1
33#define cpu_has_mips32r2 0 36#define cpu_has_mips32r2 0
34#define cpu_has_mips64r1 0 37#define cpu_has_mips64r1 0
diff --git a/arch/mips/include/asm/mach-au1x00/gpio-au1300.h b/arch/mips/include/asm/mach-au1x00/gpio-au1300.h
new file mode 100644
index 000000000000..556e1be20bf6
--- /dev/null
+++ b/arch/mips/include/asm/mach-au1x00/gpio-au1300.h
@@ -0,0 +1,241 @@
1/*
2 * gpio-au1300.h -- GPIO control for Au1300 GPIC and compatibles.
3 *
4 * Copyright (c) 2009-2011 Manuel Lauss <manuel.lauss@googlemail.com>
5 */
6
7#ifndef _GPIO_AU1300_H_
8#define _GPIO_AU1300_H_
9
10#include <asm/addrspace.h>
11#include <asm/io.h>
12#include <asm/mach-au1x00/au1000.h>
13
14/* with the current GPIC design, up to 128 GPIOs are possible.
15 * The only implementation so far is in the Au1300, which has 75 externally
16 * available GPIOs.
17 */
18#define AU1300_GPIO_BASE 0
19#define AU1300_GPIO_NUM 75
20#define AU1300_GPIO_MAX (AU1300_GPIO_BASE + AU1300_GPIO_NUM - 1)
21
22#define AU1300_GPIC_ADDR \
23 (void __iomem *)KSEG1ADDR(AU1300_GPIC_PHYS_ADDR)
24
25static inline int au1300_gpio_get_value(unsigned int gpio)
26{
27 void __iomem *roff = AU1300_GPIC_ADDR;
28 int bit;
29
30 gpio -= AU1300_GPIO_BASE;
31 roff += GPIC_GPIO_BANKOFF(gpio);
32 bit = GPIC_GPIO_TO_BIT(gpio);
33 return __raw_readl(roff + AU1300_GPIC_PINVAL) & bit;
34}
35
36static inline int au1300_gpio_direction_input(unsigned int gpio)
37{
38 void __iomem *roff = AU1300_GPIC_ADDR;
39 unsigned long bit;
40
41 gpio -= AU1300_GPIO_BASE;
42
43 roff += GPIC_GPIO_BANKOFF(gpio);
44 bit = GPIC_GPIO_TO_BIT(gpio);
45 __raw_writel(bit, roff + AU1300_GPIC_DEVCLR);
46 wmb();
47
48 return 0;
49}
50
51static inline int au1300_gpio_set_value(unsigned int gpio, int v)
52{
53 void __iomem *roff = AU1300_GPIC_ADDR;
54 unsigned long bit;
55
56 gpio -= AU1300_GPIO_BASE;
57
58 roff += GPIC_GPIO_BANKOFF(gpio);
59 bit = GPIC_GPIO_TO_BIT(gpio);
60 __raw_writel(bit, roff + (v ? AU1300_GPIC_PINVAL
61 : AU1300_GPIC_PINVALCLR));
62 wmb();
63
64 return 0;
65}
66
67static inline int au1300_gpio_direction_output(unsigned int gpio, int v)
68{
69 /* hw switches to output automatically */
70 return au1300_gpio_set_value(gpio, v);
71}
72
73static inline int au1300_gpio_to_irq(unsigned int gpio)
74{
75 return AU1300_FIRST_INT + (gpio - AU1300_GPIO_BASE);
76}
77
78static inline int au1300_irq_to_gpio(unsigned int irq)
79{
80 return (irq - AU1300_FIRST_INT) + AU1300_GPIO_BASE;
81}
82
83static inline int au1300_gpio_is_valid(unsigned int gpio)
84{
85 int ret;
86
87 switch (alchemy_get_cputype()) {
88 case ALCHEMY_CPU_AU1300:
89 ret = ((gpio >= AU1300_GPIO_BASE) && (gpio <= AU1300_GPIO_MAX));
90 break;
91 default:
92 ret = 0;
93 }
94 return ret;
95}
96
97static inline int au1300_gpio_cansleep(unsigned int gpio)
98{
99 return 0;
100}
101
102/* hardware remembers gpio 0-63 levels on powerup */
103static inline int au1300_gpio_getinitlvl(unsigned int gpio)
104{
105 void __iomem *roff = AU1300_GPIC_ADDR;
106 unsigned long v;
107
108 if (unlikely(gpio > 63))
109 return 0;
110 else if (gpio > 31) {
111 gpio -= 32;
112 roff += 4;
113 }
114
115 v = __raw_readl(roff + AU1300_GPIC_RSTVAL);
116 return (v >> gpio) & 1;
117}
118
119/**********************************************************************/
120
121/* Linux gpio framework integration.
122*
123* 4 use cases of Alchemy GPIOS:
124*(1) GPIOLIB=y, ALCHEMY_GPIO_INDIRECT=y:
125* Board must register gpiochips.
126*(2) GPIOLIB=y, ALCHEMY_GPIO_INDIRECT=n:
127* A gpiochip for the 75 GPIOs is registered.
128*
129*(3) GPIOLIB=n, ALCHEMY_GPIO_INDIRECT=y:
130* the boards' gpio.h must provide the linux gpio wrapper functions,
131*
132*(4) GPIOLIB=n, ALCHEMY_GPIO_INDIRECT=n:
133* inlinable gpio functions are provided which enable access to the
134* Au1300 gpios only by using the numbers straight out of the data-
135* sheets.
136
137* Cases 1 and 3 are intended for boards which want to provide their own
138* GPIO namespace and -operations (i.e. for example you have 8 GPIOs
139* which are in part provided by spare Au1300 GPIO pins and in part by
140* an external FPGA but you still want them to be accssible in linux
141* as gpio0-7. The board can of course use the alchemy_gpioX_* functions
142* as required).
143*/
144
145#ifndef CONFIG_GPIOLIB
146
147#ifdef CONFIG_ALCHEMY_GPIOINT_AU1300
148
149#ifndef CONFIG_ALCHEMY_GPIO_INDIRECT /* case (4) */
150
151static inline int gpio_direction_input(unsigned int gpio)
152{
153 return au1300_gpio_direction_input(gpio);
154}
155
156static inline int gpio_direction_output(unsigned int gpio, int v)
157{
158 return au1300_gpio_direction_output(gpio, v);
159}
160
161static inline int gpio_get_value(unsigned int gpio)
162{
163 return au1300_gpio_get_value(gpio);
164}
165
166static inline void gpio_set_value(unsigned int gpio, int v)
167{
168 au1300_gpio_set_value(gpio, v);
169}
170
171static inline int gpio_get_value_cansleep(unsigned gpio)
172{
173 return gpio_get_value(gpio);
174}
175
176static inline void gpio_set_value_cansleep(unsigned gpio, int value)
177{
178 gpio_set_value(gpio, value);
179}
180
181static inline int gpio_is_valid(unsigned int gpio)
182{
183 return au1300_gpio_is_valid(gpio);
184}
185
186static inline int gpio_cansleep(unsigned int gpio)
187{
188 return au1300_gpio_cansleep(gpio);
189}
190
191static inline int gpio_to_irq(unsigned int gpio)
192{
193 return au1300_gpio_to_irq(gpio);
194}
195
196static inline int irq_to_gpio(unsigned int irq)
197{
198 return au1300_irq_to_gpio(irq);
199}
200
201static inline int gpio_request(unsigned int gpio, const char *label)
202{
203 return 0;
204}
205
206static inline void gpio_free(unsigned int gpio)
207{
208}
209
210static inline int gpio_set_debounce(unsigned gpio, unsigned debounce)
211{
212 return -ENOSYS;
213}
214
215static inline void gpio_unexport(unsigned gpio)
216{
217}
218
219static inline int gpio_export(unsigned gpio, bool direction_may_change)
220{
221 return -ENOSYS;
222}
223
224static inline int gpio_sysfs_set_active_low(unsigned gpio, int value)
225{
226 return -ENOSYS;
227}
228
229static inline int gpio_export_link(struct device *dev, const char *name,
230 unsigned gpio)
231{
232 return -ENOSYS;
233}
234
235#endif /* !CONFIG_ALCHEMY_GPIO_INDIRECT */
236
237#endif /* CONFIG_ALCHEMY_GPIOINT_AU1300 */
238
239#endif /* CONFIG GPIOLIB */
240
241#endif /* _GPIO_AU1300_H_ */
diff --git a/arch/mips/include/asm/mach-au1x00/gpio.h b/arch/mips/include/asm/mach-au1x00/gpio.h
index fcdc8c4809db..22e7ff17fc48 100644
--- a/arch/mips/include/asm/mach-au1x00/gpio.h
+++ b/arch/mips/include/asm/mach-au1x00/gpio.h
@@ -12,6 +12,7 @@
12 12
13#include <asm/mach-au1x00/au1000.h> 13#include <asm/mach-au1x00/au1000.h>
14#include <asm/mach-au1x00/gpio-au1000.h> 14#include <asm/mach-au1x00/gpio-au1000.h>
15#include <asm/mach-au1x00/gpio-au1300.h>
15 16
16/* On Au1000, Au1500 and Au1100 GPIOs won't work as inputs before 17/* On Au1000, Au1500 and Au1100 GPIOs won't work as inputs before
17 * SYS_PININPUTEN is written to at least once. On Au1550/Au1200/Au1300 this 18 * SYS_PININPUTEN is written to at least once. On Au1550/Au1200/Au1300 this
@@ -58,6 +59,8 @@ static inline int __au_irq_to_gpio(unsigned int irq)
58 switch (alchemy_get_cputype()) { 59 switch (alchemy_get_cputype()) {
59 case ALCHEMY_CPU_AU1000...ALCHEMY_CPU_AU1200: 60 case ALCHEMY_CPU_AU1000...ALCHEMY_CPU_AU1200:
60 return alchemy_irq_to_gpio(irq); 61 return alchemy_irq_to_gpio(irq);
62 case ALCHEMY_CPU_AU1300:
63 return au1300_irq_to_gpio(irq);
61 } 64 }
62 return -EINVAL; 65 return -EINVAL;
63} 66}
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
index 96a2391ad85b..5b8d15bb5fe8 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
@@ -13,6 +13,7 @@
13#define BCM6345_CPU_ID 0x6345 13#define BCM6345_CPU_ID 0x6345
14#define BCM6348_CPU_ID 0x6348 14#define BCM6348_CPU_ID 0x6348
15#define BCM6358_CPU_ID 0x6358 15#define BCM6358_CPU_ID 0x6358
16#define BCM6368_CPU_ID 0x6368
16 17
17void __init bcm63xx_cpu_init(void); 18void __init bcm63xx_cpu_init(void);
18u16 __bcm63xx_get_cpu_id(void); 19u16 __bcm63xx_get_cpu_id(void);
@@ -71,6 +72,19 @@ unsigned int bcm63xx_get_cpu_freq(void);
71# define BCMCPU_IS_6358() (0) 72# define BCMCPU_IS_6358() (0)
72#endif 73#endif
73 74
75#ifdef CONFIG_BCM63XX_CPU_6368
76# ifdef bcm63xx_get_cpu_id
77# undef bcm63xx_get_cpu_id
78# define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
79# define BCMCPU_RUNTIME_DETECT
80# else
81# define bcm63xx_get_cpu_id() BCM6368_CPU_ID
82# endif
83# define BCMCPU_IS_6368() (bcm63xx_get_cpu_id() == BCM6368_CPU_ID)
84#else
85# define BCMCPU_IS_6368() (0)
86#endif
87
74#ifndef bcm63xx_get_cpu_id 88#ifndef bcm63xx_get_cpu_id
75#error "No CPU support configured" 89#error "No CPU support configured"
76#endif 90#endif
@@ -88,6 +102,7 @@ enum bcm63xx_regs_set {
88 RSET_UART1, 102 RSET_UART1,
89 RSET_GPIO, 103 RSET_GPIO,
90 RSET_SPI, 104 RSET_SPI,
105 RSET_SPI2,
91 RSET_UDC0, 106 RSET_UDC0,
92 RSET_OHCI0, 107 RSET_OHCI0,
93 RSET_OHCI_PRIV, 108 RSET_OHCI_PRIV,
@@ -98,10 +113,23 @@ enum bcm63xx_regs_set {
98 RSET_ENET0, 113 RSET_ENET0,
99 RSET_ENET1, 114 RSET_ENET1,
100 RSET_ENETDMA, 115 RSET_ENETDMA,
116 RSET_ENETDMAC,
117 RSET_ENETDMAS,
118 RSET_ENETSW,
101 RSET_EHCI0, 119 RSET_EHCI0,
102 RSET_SDRAM, 120 RSET_SDRAM,
103 RSET_MEMC, 121 RSET_MEMC,
104 RSET_DDR, 122 RSET_DDR,
123 RSET_M2M,
124 RSET_ATM,
125 RSET_XTM,
126 RSET_XTMDMA,
127 RSET_XTMDMAC,
128 RSET_XTMDMAS,
129 RSET_PCM,
130 RSET_PCMDMA,
131 RSET_PCMDMAC,
132 RSET_PCMDMAS,
105}; 133};
106 134
107#define RSET_DSL_LMEM_SIZE (64 * 1024 * 4) 135#define RSET_DSL_LMEM_SIZE (64 * 1024 * 4)
@@ -109,11 +137,18 @@ enum bcm63xx_regs_set {
109#define RSET_WDT_SIZE 12 137#define RSET_WDT_SIZE 12
110#define RSET_ENET_SIZE 2048 138#define RSET_ENET_SIZE 2048
111#define RSET_ENETDMA_SIZE 2048 139#define RSET_ENETDMA_SIZE 2048
140#define RSET_ENETSW_SIZE 65536
112#define RSET_UART_SIZE 24 141#define RSET_UART_SIZE 24
113#define RSET_UDC_SIZE 256 142#define RSET_UDC_SIZE 256
114#define RSET_OHCI_SIZE 256 143#define RSET_OHCI_SIZE 256
115#define RSET_EHCI_SIZE 256 144#define RSET_EHCI_SIZE 256
116#define RSET_PCMCIA_SIZE 12 145#define RSET_PCMCIA_SIZE 12
146#define RSET_M2M_SIZE 256
147#define RSET_ATM_SIZE 4096
148#define RSET_XTM_SIZE 10240
149#define RSET_XTMDMA_SIZE 256
150#define RSET_XTMDMAC_SIZE(chans) (16 * (chans))
151#define RSET_XTMDMAS_SIZE(chans) (16 * (chans))
117 152
118/* 153/*
119 * 6338 register sets base address 154 * 6338 register sets base address
@@ -127,6 +162,7 @@ enum bcm63xx_regs_set {
127#define BCM_6338_UART1_BASE (0xdeadbeef) 162#define BCM_6338_UART1_BASE (0xdeadbeef)
128#define BCM_6338_GPIO_BASE (0xfffe0400) 163#define BCM_6338_GPIO_BASE (0xfffe0400)
129#define BCM_6338_SPI_BASE (0xfffe0c00) 164#define BCM_6338_SPI_BASE (0xfffe0c00)
165#define BCM_6338_SPI2_BASE (0xdeadbeef)
130#define BCM_6338_UDC0_BASE (0xdeadbeef) 166#define BCM_6338_UDC0_BASE (0xdeadbeef)
131#define BCM_6338_USBDMA_BASE (0xfffe2400) 167#define BCM_6338_USBDMA_BASE (0xfffe2400)
132#define BCM_6338_OHCI0_BASE (0xdeadbeef) 168#define BCM_6338_OHCI0_BASE (0xdeadbeef)
@@ -136,15 +172,27 @@ enum bcm63xx_regs_set {
136#define BCM_6338_PCMCIA_BASE (0xdeadbeef) 172#define BCM_6338_PCMCIA_BASE (0xdeadbeef)
137#define BCM_6338_SDRAM_REGS_BASE (0xfffe3100) 173#define BCM_6338_SDRAM_REGS_BASE (0xfffe3100)
138#define BCM_6338_DSL_BASE (0xfffe1000) 174#define BCM_6338_DSL_BASE (0xfffe1000)
139#define BCM_6338_SAR_BASE (0xfffe2000)
140#define BCM_6338_UBUS_BASE (0xdeadbeef) 175#define BCM_6338_UBUS_BASE (0xdeadbeef)
141#define BCM_6338_ENET0_BASE (0xfffe2800) 176#define BCM_6338_ENET0_BASE (0xfffe2800)
142#define BCM_6338_ENET1_BASE (0xdeadbeef) 177#define BCM_6338_ENET1_BASE (0xdeadbeef)
143#define BCM_6338_ENETDMA_BASE (0xfffe2400) 178#define BCM_6338_ENETDMA_BASE (0xfffe2400)
179#define BCM_6338_ENETDMAC_BASE (0xfffe2500)
180#define BCM_6338_ENETDMAS_BASE (0xfffe2600)
181#define BCM_6338_ENETSW_BASE (0xdeadbeef)
144#define BCM_6338_EHCI0_BASE (0xdeadbeef) 182#define BCM_6338_EHCI0_BASE (0xdeadbeef)
145#define BCM_6338_SDRAM_BASE (0xfffe3100) 183#define BCM_6338_SDRAM_BASE (0xfffe3100)
146#define BCM_6338_MEMC_BASE (0xdeadbeef) 184#define BCM_6338_MEMC_BASE (0xdeadbeef)
147#define BCM_6338_DDR_BASE (0xdeadbeef) 185#define BCM_6338_DDR_BASE (0xdeadbeef)
186#define BCM_6338_M2M_BASE (0xdeadbeef)
187#define BCM_6338_ATM_BASE (0xfffe2000)
188#define BCM_6338_XTM_BASE (0xdeadbeef)
189#define BCM_6338_XTMDMA_BASE (0xdeadbeef)
190#define BCM_6338_XTMDMAC_BASE (0xdeadbeef)
191#define BCM_6338_XTMDMAS_BASE (0xdeadbeef)
192#define BCM_6338_PCM_BASE (0xdeadbeef)
193#define BCM_6338_PCMDMA_BASE (0xdeadbeef)
194#define BCM_6338_PCMDMAC_BASE (0xdeadbeef)
195#define BCM_6338_PCMDMAS_BASE (0xdeadbeef)
148 196
149/* 197/*
150 * 6345 register sets base address 198 * 6345 register sets base address
@@ -158,24 +206,37 @@ enum bcm63xx_regs_set {
158#define BCM_6345_UART1_BASE (0xdeadbeef) 206#define BCM_6345_UART1_BASE (0xdeadbeef)
159#define BCM_6345_GPIO_BASE (0xfffe0400) 207#define BCM_6345_GPIO_BASE (0xfffe0400)
160#define BCM_6345_SPI_BASE (0xdeadbeef) 208#define BCM_6345_SPI_BASE (0xdeadbeef)
209#define BCM_6345_SPI2_BASE (0xdeadbeef)
161#define BCM_6345_UDC0_BASE (0xdeadbeef) 210#define BCM_6345_UDC0_BASE (0xdeadbeef)
162#define BCM_6345_USBDMA_BASE (0xfffe2800) 211#define BCM_6345_USBDMA_BASE (0xfffe2800)
163#define BCM_6345_ENET0_BASE (0xfffe1800) 212#define BCM_6345_ENET0_BASE (0xfffe1800)
164#define BCM_6345_ENETDMA_BASE (0xfffe2800) 213#define BCM_6345_ENETDMA_BASE (0xfffe2800)
214#define BCM_6345_ENETDMAC_BASE (0xfffe2900)
215#define BCM_6345_ENETDMAS_BASE (0xfffe2a00)
216#define BCM_6345_ENETSW_BASE (0xdeadbeef)
165#define BCM_6345_PCMCIA_BASE (0xfffe2028) 217#define BCM_6345_PCMCIA_BASE (0xfffe2028)
166#define BCM_6345_MPI_BASE (0xdeadbeef) 218#define BCM_6345_MPI_BASE (0xfffe2000)
167#define BCM_6345_OHCI0_BASE (0xfffe2100) 219#define BCM_6345_OHCI0_BASE (0xfffe2100)
168#define BCM_6345_OHCI_PRIV_BASE (0xfffe2200) 220#define BCM_6345_OHCI_PRIV_BASE (0xfffe2200)
169#define BCM_6345_USBH_PRIV_BASE (0xdeadbeef) 221#define BCM_6345_USBH_PRIV_BASE (0xdeadbeef)
170#define BCM_6345_SDRAM_REGS_BASE (0xfffe2300) 222#define BCM_6345_SDRAM_REGS_BASE (0xfffe2300)
171#define BCM_6345_DSL_BASE (0xdeadbeef) 223#define BCM_6345_DSL_BASE (0xdeadbeef)
172#define BCM_6345_SAR_BASE (0xdeadbeef)
173#define BCM_6345_UBUS_BASE (0xdeadbeef) 224#define BCM_6345_UBUS_BASE (0xdeadbeef)
174#define BCM_6345_ENET1_BASE (0xdeadbeef) 225#define BCM_6345_ENET1_BASE (0xdeadbeef)
175#define BCM_6345_EHCI0_BASE (0xdeadbeef) 226#define BCM_6345_EHCI0_BASE (0xdeadbeef)
176#define BCM_6345_SDRAM_BASE (0xfffe2300) 227#define BCM_6345_SDRAM_BASE (0xfffe2300)
177#define BCM_6345_MEMC_BASE (0xdeadbeef) 228#define BCM_6345_MEMC_BASE (0xdeadbeef)
178#define BCM_6345_DDR_BASE (0xdeadbeef) 229#define BCM_6345_DDR_BASE (0xdeadbeef)
230#define BCM_6345_M2M_BASE (0xdeadbeef)
231#define BCM_6345_ATM_BASE (0xfffe4000)
232#define BCM_6345_XTM_BASE (0xdeadbeef)
233#define BCM_6345_XTMDMA_BASE (0xdeadbeef)
234#define BCM_6345_XTMDMAC_BASE (0xdeadbeef)
235#define BCM_6345_XTMDMAS_BASE (0xdeadbeef)
236#define BCM_6345_PCM_BASE (0xdeadbeef)
237#define BCM_6345_PCMDMA_BASE (0xdeadbeef)
238#define BCM_6345_PCMDMAC_BASE (0xdeadbeef)
239#define BCM_6345_PCMDMAS_BASE (0xdeadbeef)
179 240
180/* 241/*
181 * 6348 register sets base address 242 * 6348 register sets base address
@@ -188,6 +249,7 @@ enum bcm63xx_regs_set {
188#define BCM_6348_UART1_BASE (0xdeadbeef) 249#define BCM_6348_UART1_BASE (0xdeadbeef)
189#define BCM_6348_GPIO_BASE (0xfffe0400) 250#define BCM_6348_GPIO_BASE (0xfffe0400)
190#define BCM_6348_SPI_BASE (0xfffe0c00) 251#define BCM_6348_SPI_BASE (0xfffe0c00)
252#define BCM_6348_SPI2_BASE (0xdeadbeef)
191#define BCM_6348_UDC0_BASE (0xfffe1000) 253#define BCM_6348_UDC0_BASE (0xfffe1000)
192#define BCM_6348_OHCI0_BASE (0xfffe1b00) 254#define BCM_6348_OHCI0_BASE (0xfffe1b00)
193#define BCM_6348_OHCI_PRIV_BASE (0xfffe1c00) 255#define BCM_6348_OHCI_PRIV_BASE (0xfffe1c00)
@@ -195,14 +257,27 @@ enum bcm63xx_regs_set {
195#define BCM_6348_MPI_BASE (0xfffe2000) 257#define BCM_6348_MPI_BASE (0xfffe2000)
196#define BCM_6348_PCMCIA_BASE (0xfffe2054) 258#define BCM_6348_PCMCIA_BASE (0xfffe2054)
197#define BCM_6348_SDRAM_REGS_BASE (0xfffe2300) 259#define BCM_6348_SDRAM_REGS_BASE (0xfffe2300)
260#define BCM_6348_M2M_BASE (0xfffe2800)
198#define BCM_6348_DSL_BASE (0xfffe3000) 261#define BCM_6348_DSL_BASE (0xfffe3000)
199#define BCM_6348_ENET0_BASE (0xfffe6000) 262#define BCM_6348_ENET0_BASE (0xfffe6000)
200#define BCM_6348_ENET1_BASE (0xfffe6800) 263#define BCM_6348_ENET1_BASE (0xfffe6800)
201#define BCM_6348_ENETDMA_BASE (0xfffe7000) 264#define BCM_6348_ENETDMA_BASE (0xfffe7000)
265#define BCM_6348_ENETDMAC_BASE (0xfffe7100)
266#define BCM_6348_ENETDMAS_BASE (0xfffe7200)
267#define BCM_6348_ENETSW_BASE (0xdeadbeef)
202#define BCM_6348_EHCI0_BASE (0xdeadbeef) 268#define BCM_6348_EHCI0_BASE (0xdeadbeef)
203#define BCM_6348_SDRAM_BASE (0xfffe2300) 269#define BCM_6348_SDRAM_BASE (0xfffe2300)
204#define BCM_6348_MEMC_BASE (0xdeadbeef) 270#define BCM_6348_MEMC_BASE (0xdeadbeef)
205#define BCM_6348_DDR_BASE (0xdeadbeef) 271#define BCM_6348_DDR_BASE (0xdeadbeef)
272#define BCM_6348_ATM_BASE (0xfffe4000)
273#define BCM_6348_XTM_BASE (0xdeadbeef)
274#define BCM_6348_XTMDMA_BASE (0xdeadbeef)
275#define BCM_6348_XTMDMAC_BASE (0xdeadbeef)
276#define BCM_6348_XTMDMAS_BASE (0xdeadbeef)
277#define BCM_6348_PCM_BASE (0xdeadbeef)
278#define BCM_6348_PCMDMA_BASE (0xdeadbeef)
279#define BCM_6348_PCMDMAC_BASE (0xdeadbeef)
280#define BCM_6348_PCMDMAS_BASE (0xdeadbeef)
206 281
207/* 282/*
208 * 6358 register sets base address 283 * 6358 register sets base address
@@ -215,6 +290,7 @@ enum bcm63xx_regs_set {
215#define BCM_6358_UART1_BASE (0xfffe0120) 290#define BCM_6358_UART1_BASE (0xfffe0120)
216#define BCM_6358_GPIO_BASE (0xfffe0080) 291#define BCM_6358_GPIO_BASE (0xfffe0080)
217#define BCM_6358_SPI_BASE (0xdeadbeef) 292#define BCM_6358_SPI_BASE (0xdeadbeef)
293#define BCM_6358_SPI2_BASE (0xfffe0800)
218#define BCM_6358_UDC0_BASE (0xfffe0800) 294#define BCM_6358_UDC0_BASE (0xfffe0800)
219#define BCM_6358_OHCI0_BASE (0xfffe1400) 295#define BCM_6358_OHCI0_BASE (0xfffe1400)
220#define BCM_6358_OHCI_PRIV_BASE (0xdeadbeef) 296#define BCM_6358_OHCI_PRIV_BASE (0xdeadbeef)
@@ -222,214 +298,175 @@ enum bcm63xx_regs_set {
222#define BCM_6358_MPI_BASE (0xfffe1000) 298#define BCM_6358_MPI_BASE (0xfffe1000)
223#define BCM_6358_PCMCIA_BASE (0xfffe1054) 299#define BCM_6358_PCMCIA_BASE (0xfffe1054)
224#define BCM_6358_SDRAM_REGS_BASE (0xfffe2300) 300#define BCM_6358_SDRAM_REGS_BASE (0xfffe2300)
301#define BCM_6358_M2M_BASE (0xdeadbeef)
225#define BCM_6358_DSL_BASE (0xfffe3000) 302#define BCM_6358_DSL_BASE (0xfffe3000)
226#define BCM_6358_ENET0_BASE (0xfffe4000) 303#define BCM_6358_ENET0_BASE (0xfffe4000)
227#define BCM_6358_ENET1_BASE (0xfffe4800) 304#define BCM_6358_ENET1_BASE (0xfffe4800)
228#define BCM_6358_ENETDMA_BASE (0xfffe5000) 305#define BCM_6358_ENETDMA_BASE (0xfffe5000)
306#define BCM_6358_ENETDMAC_BASE (0xfffe5100)
307#define BCM_6358_ENETDMAS_BASE (0xfffe5200)
308#define BCM_6358_ENETSW_BASE (0xdeadbeef)
229#define BCM_6358_EHCI0_BASE (0xfffe1300) 309#define BCM_6358_EHCI0_BASE (0xfffe1300)
230#define BCM_6358_SDRAM_BASE (0xdeadbeef) 310#define BCM_6358_SDRAM_BASE (0xdeadbeef)
231#define BCM_6358_MEMC_BASE (0xfffe1200) 311#define BCM_6358_MEMC_BASE (0xfffe1200)
232#define BCM_6358_DDR_BASE (0xfffe12a0) 312#define BCM_6358_DDR_BASE (0xfffe12a0)
313#define BCM_6358_ATM_BASE (0xfffe2000)
314#define BCM_6358_XTM_BASE (0xdeadbeef)
315#define BCM_6358_XTMDMA_BASE (0xdeadbeef)
316#define BCM_6358_XTMDMAC_BASE (0xdeadbeef)
317#define BCM_6358_XTMDMAS_BASE (0xdeadbeef)
318#define BCM_6358_PCM_BASE (0xfffe1600)
319#define BCM_6358_PCMDMA_BASE (0xfffe1800)
320#define BCM_6358_PCMDMAC_BASE (0xfffe1900)
321#define BCM_6358_PCMDMAS_BASE (0xfffe1a00)
322
323
324/*
325 * 6368 register sets base address
326 */
327#define BCM_6368_DSL_LMEM_BASE (0xdeadbeef)
328#define BCM_6368_PERF_BASE (0xb0000000)
329#define BCM_6368_TIMER_BASE (0xb0000040)
330#define BCM_6368_WDT_BASE (0xb000005c)
331#define BCM_6368_UART0_BASE (0xb0000100)
332#define BCM_6368_UART1_BASE (0xb0000120)
333#define BCM_6368_GPIO_BASE (0xb0000080)
334#define BCM_6368_SPI_BASE (0xdeadbeef)
335#define BCM_6368_SPI2_BASE (0xb0000800)
336#define BCM_6368_UDC0_BASE (0xdeadbeef)
337#define BCM_6368_OHCI0_BASE (0xb0001600)
338#define BCM_6368_OHCI_PRIV_BASE (0xdeadbeef)
339#define BCM_6368_USBH_PRIV_BASE (0xb0001700)
340#define BCM_6368_MPI_BASE (0xb0001000)
341#define BCM_6368_PCMCIA_BASE (0xb0001054)
342#define BCM_6368_SDRAM_REGS_BASE (0xdeadbeef)
343#define BCM_6368_M2M_BASE (0xdeadbeef)
344#define BCM_6368_DSL_BASE (0xdeadbeef)
345#define BCM_6368_ENET0_BASE (0xdeadbeef)
346#define BCM_6368_ENET1_BASE (0xdeadbeef)
347#define BCM_6368_ENETDMA_BASE (0xb0006800)
348#define BCM_6368_ENETDMAC_BASE (0xb0006a00)
349#define BCM_6368_ENETDMAS_BASE (0xb0006c00)
350#define BCM_6368_ENETSW_BASE (0xb0f00000)
351#define BCM_6368_EHCI0_BASE (0xb0001500)
352#define BCM_6368_SDRAM_BASE (0xdeadbeef)
353#define BCM_6368_MEMC_BASE (0xb0001200)
354#define BCM_6368_DDR_BASE (0xb0001280)
355#define BCM_6368_ATM_BASE (0xdeadbeef)
356#define BCM_6368_XTM_BASE (0xb0001800)
357#define BCM_6368_XTMDMA_BASE (0xb0005000)
358#define BCM_6368_XTMDMAC_BASE (0xb0005200)
359#define BCM_6368_XTMDMAS_BASE (0xb0005400)
360#define BCM_6368_PCM_BASE (0xb0004000)
361#define BCM_6368_PCMDMA_BASE (0xb0005800)
362#define BCM_6368_PCMDMAC_BASE (0xb0005a00)
363#define BCM_6368_PCMDMAS_BASE (0xb0005c00)
233 364
234 365
235extern const unsigned long *bcm63xx_regs_base; 366extern const unsigned long *bcm63xx_regs_base;
236 367
368#define __GEN_RSET_BASE(__cpu, __rset) \
369 case RSET_## __rset : \
370 return BCM_## __cpu ##_## __rset ##_BASE;
371
372#define __GEN_RSET(__cpu) \
373 switch (set) { \
374 __GEN_RSET_BASE(__cpu, DSL_LMEM) \
375 __GEN_RSET_BASE(__cpu, PERF) \
376 __GEN_RSET_BASE(__cpu, TIMER) \
377 __GEN_RSET_BASE(__cpu, WDT) \
378 __GEN_RSET_BASE(__cpu, UART0) \
379 __GEN_RSET_BASE(__cpu, UART1) \
380 __GEN_RSET_BASE(__cpu, GPIO) \
381 __GEN_RSET_BASE(__cpu, SPI) \
382 __GEN_RSET_BASE(__cpu, SPI2) \
383 __GEN_RSET_BASE(__cpu, UDC0) \
384 __GEN_RSET_BASE(__cpu, OHCI0) \
385 __GEN_RSET_BASE(__cpu, OHCI_PRIV) \
386 __GEN_RSET_BASE(__cpu, USBH_PRIV) \
387 __GEN_RSET_BASE(__cpu, MPI) \
388 __GEN_RSET_BASE(__cpu, PCMCIA) \
389 __GEN_RSET_BASE(__cpu, DSL) \
390 __GEN_RSET_BASE(__cpu, ENET0) \
391 __GEN_RSET_BASE(__cpu, ENET1) \
392 __GEN_RSET_BASE(__cpu, ENETDMA) \
393 __GEN_RSET_BASE(__cpu, ENETDMAC) \
394 __GEN_RSET_BASE(__cpu, ENETDMAS) \
395 __GEN_RSET_BASE(__cpu, ENETSW) \
396 __GEN_RSET_BASE(__cpu, EHCI0) \
397 __GEN_RSET_BASE(__cpu, SDRAM) \
398 __GEN_RSET_BASE(__cpu, MEMC) \
399 __GEN_RSET_BASE(__cpu, DDR) \
400 __GEN_RSET_BASE(__cpu, M2M) \
401 __GEN_RSET_BASE(__cpu, ATM) \
402 __GEN_RSET_BASE(__cpu, XTM) \
403 __GEN_RSET_BASE(__cpu, XTMDMA) \
404 __GEN_RSET_BASE(__cpu, XTMDMAC) \
405 __GEN_RSET_BASE(__cpu, XTMDMAS) \
406 __GEN_RSET_BASE(__cpu, PCM) \
407 __GEN_RSET_BASE(__cpu, PCMDMA) \
408 __GEN_RSET_BASE(__cpu, PCMDMAC) \
409 __GEN_RSET_BASE(__cpu, PCMDMAS) \
410 }
411
412#define __GEN_CPU_REGS_TABLE(__cpu) \
413 [RSET_DSL_LMEM] = BCM_## __cpu ##_DSL_LMEM_BASE, \
414 [RSET_PERF] = BCM_## __cpu ##_PERF_BASE, \
415 [RSET_TIMER] = BCM_## __cpu ##_TIMER_BASE, \
416 [RSET_WDT] = BCM_## __cpu ##_WDT_BASE, \
417 [RSET_UART0] = BCM_## __cpu ##_UART0_BASE, \
418 [RSET_UART1] = BCM_## __cpu ##_UART1_BASE, \
419 [RSET_GPIO] = BCM_## __cpu ##_GPIO_BASE, \
420 [RSET_SPI] = BCM_## __cpu ##_SPI_BASE, \
421 [RSET_SPI2] = BCM_## __cpu ##_SPI2_BASE, \
422 [RSET_UDC0] = BCM_## __cpu ##_UDC0_BASE, \
423 [RSET_OHCI0] = BCM_## __cpu ##_OHCI0_BASE, \
424 [RSET_OHCI_PRIV] = BCM_## __cpu ##_OHCI_PRIV_BASE, \
425 [RSET_USBH_PRIV] = BCM_## __cpu ##_USBH_PRIV_BASE, \
426 [RSET_MPI] = BCM_## __cpu ##_MPI_BASE, \
427 [RSET_PCMCIA] = BCM_## __cpu ##_PCMCIA_BASE, \
428 [RSET_DSL] = BCM_## __cpu ##_DSL_BASE, \
429 [RSET_ENET0] = BCM_## __cpu ##_ENET0_BASE, \
430 [RSET_ENET1] = BCM_## __cpu ##_ENET1_BASE, \
431 [RSET_ENETDMA] = BCM_## __cpu ##_ENETDMA_BASE, \
432 [RSET_ENETDMAC] = BCM_## __cpu ##_ENETDMAC_BASE, \
433 [RSET_ENETDMAS] = BCM_## __cpu ##_ENETDMAS_BASE, \
434 [RSET_ENETSW] = BCM_## __cpu ##_ENETSW_BASE, \
435 [RSET_EHCI0] = BCM_## __cpu ##_EHCI0_BASE, \
436 [RSET_SDRAM] = BCM_## __cpu ##_SDRAM_BASE, \
437 [RSET_MEMC] = BCM_## __cpu ##_MEMC_BASE, \
438 [RSET_DDR] = BCM_## __cpu ##_DDR_BASE, \
439 [RSET_M2M] = BCM_## __cpu ##_M2M_BASE, \
440 [RSET_ATM] = BCM_## __cpu ##_ATM_BASE, \
441 [RSET_XTM] = BCM_## __cpu ##_XTM_BASE, \
442 [RSET_XTMDMA] = BCM_## __cpu ##_XTMDMA_BASE, \
443 [RSET_XTMDMAC] = BCM_## __cpu ##_XTMDMAC_BASE, \
444 [RSET_XTMDMAS] = BCM_## __cpu ##_XTMDMAS_BASE, \
445 [RSET_PCM] = BCM_## __cpu ##_PCM_BASE, \
446 [RSET_PCMDMA] = BCM_## __cpu ##_PCMDMA_BASE, \
447 [RSET_PCMDMAC] = BCM_## __cpu ##_PCMDMAC_BASE, \
448 [RSET_PCMDMAS] = BCM_## __cpu ##_PCMDMAS_BASE, \
449
450
237static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set) 451static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
238{ 452{
239#ifdef BCMCPU_RUNTIME_DETECT 453#ifdef BCMCPU_RUNTIME_DETECT
240 return bcm63xx_regs_base[set]; 454 return bcm63xx_regs_base[set];
241#else 455#else
242#ifdef CONFIG_BCM63XX_CPU_6338 456#ifdef CONFIG_BCM63XX_CPU_6338
243 switch (set) { 457 __GEN_RSET(6338)
244 case RSET_DSL_LMEM:
245 return BCM_6338_DSL_LMEM_BASE;
246 case RSET_PERF:
247 return BCM_6338_PERF_BASE;
248 case RSET_TIMER:
249 return BCM_6338_TIMER_BASE;
250 case RSET_WDT:
251 return BCM_6338_WDT_BASE;
252 case RSET_UART0:
253 return BCM_6338_UART0_BASE;
254 case RSET_UART1:
255 return BCM_6338_UART1_BASE;
256 case RSET_GPIO:
257 return BCM_6338_GPIO_BASE;
258 case RSET_SPI:
259 return BCM_6338_SPI_BASE;
260 case RSET_UDC0:
261 return BCM_6338_UDC0_BASE;
262 case RSET_OHCI0:
263 return BCM_6338_OHCI0_BASE;
264 case RSET_OHCI_PRIV:
265 return BCM_6338_OHCI_PRIV_BASE;
266 case RSET_USBH_PRIV:
267 return BCM_6338_USBH_PRIV_BASE;
268 case RSET_MPI:
269 return BCM_6338_MPI_BASE;
270 case RSET_PCMCIA:
271 return BCM_6338_PCMCIA_BASE;
272 case RSET_DSL:
273 return BCM_6338_DSL_BASE;
274 case RSET_ENET0:
275 return BCM_6338_ENET0_BASE;
276 case RSET_ENET1:
277 return BCM_6338_ENET1_BASE;
278 case RSET_ENETDMA:
279 return BCM_6338_ENETDMA_BASE;
280 case RSET_EHCI0:
281 return BCM_6338_EHCI0_BASE;
282 case RSET_SDRAM:
283 return BCM_6338_SDRAM_BASE;
284 case RSET_MEMC:
285 return BCM_6338_MEMC_BASE;
286 case RSET_DDR:
287 return BCM_6338_DDR_BASE;
288 }
289#endif 458#endif
290#ifdef CONFIG_BCM63XX_CPU_6345 459#ifdef CONFIG_BCM63XX_CPU_6345
291 switch (set) { 460 __GEN_RSET(6345)
292 case RSET_DSL_LMEM:
293 return BCM_6345_DSL_LMEM_BASE;
294 case RSET_PERF:
295 return BCM_6345_PERF_BASE;
296 case RSET_TIMER:
297 return BCM_6345_TIMER_BASE;
298 case RSET_WDT:
299 return BCM_6345_WDT_BASE;
300 case RSET_UART0:
301 return BCM_6345_UART0_BASE;
302 case RSET_UART1:
303 return BCM_6345_UART1_BASE;
304 case RSET_GPIO:
305 return BCM_6345_GPIO_BASE;
306 case RSET_SPI:
307 return BCM_6345_SPI_BASE;
308 case RSET_UDC0:
309 return BCM_6345_UDC0_BASE;
310 case RSET_OHCI0:
311 return BCM_6345_OHCI0_BASE;
312 case RSET_OHCI_PRIV:
313 return BCM_6345_OHCI_PRIV_BASE;
314 case RSET_USBH_PRIV:
315 return BCM_6345_USBH_PRIV_BASE;
316 case RSET_MPI:
317 return BCM_6345_MPI_BASE;
318 case RSET_PCMCIA:
319 return BCM_6345_PCMCIA_BASE;
320 case RSET_DSL:
321 return BCM_6345_DSL_BASE;
322 case RSET_ENET0:
323 return BCM_6345_ENET0_BASE;
324 case RSET_ENET1:
325 return BCM_6345_ENET1_BASE;
326 case RSET_ENETDMA:
327 return BCM_6345_ENETDMA_BASE;
328 case RSET_EHCI0:
329 return BCM_6345_EHCI0_BASE;
330 case RSET_SDRAM:
331 return BCM_6345_SDRAM_BASE;
332 case RSET_MEMC:
333 return BCM_6345_MEMC_BASE;
334 case RSET_DDR:
335 return BCM_6345_DDR_BASE;
336 }
337#endif 461#endif
338#ifdef CONFIG_BCM63XX_CPU_6348 462#ifdef CONFIG_BCM63XX_CPU_6348
339 switch (set) { 463 __GEN_RSET(6348)
340 case RSET_DSL_LMEM:
341 return BCM_6348_DSL_LMEM_BASE;
342 case RSET_PERF:
343 return BCM_6348_PERF_BASE;
344 case RSET_TIMER:
345 return BCM_6348_TIMER_BASE;
346 case RSET_WDT:
347 return BCM_6348_WDT_BASE;
348 case RSET_UART0:
349 return BCM_6348_UART0_BASE;
350 case RSET_UART1:
351 return BCM_6348_UART1_BASE;
352 case RSET_GPIO:
353 return BCM_6348_GPIO_BASE;
354 case RSET_SPI:
355 return BCM_6348_SPI_BASE;
356 case RSET_UDC0:
357 return BCM_6348_UDC0_BASE;
358 case RSET_OHCI0:
359 return BCM_6348_OHCI0_BASE;
360 case RSET_OHCI_PRIV:
361 return BCM_6348_OHCI_PRIV_BASE;
362 case RSET_USBH_PRIV:
363 return BCM_6348_USBH_PRIV_BASE;
364 case RSET_MPI:
365 return BCM_6348_MPI_BASE;
366 case RSET_PCMCIA:
367 return BCM_6348_PCMCIA_BASE;
368 case RSET_DSL:
369 return BCM_6348_DSL_BASE;
370 case RSET_ENET0:
371 return BCM_6348_ENET0_BASE;
372 case RSET_ENET1:
373 return BCM_6348_ENET1_BASE;
374 case RSET_ENETDMA:
375 return BCM_6348_ENETDMA_BASE;
376 case RSET_EHCI0:
377 return BCM_6348_EHCI0_BASE;
378 case RSET_SDRAM:
379 return BCM_6348_SDRAM_BASE;
380 case RSET_MEMC:
381 return BCM_6348_MEMC_BASE;
382 case RSET_DDR:
383 return BCM_6348_DDR_BASE;
384 }
385#endif 464#endif
386#ifdef CONFIG_BCM63XX_CPU_6358 465#ifdef CONFIG_BCM63XX_CPU_6358
387 switch (set) { 466 __GEN_RSET(6358)
388 case RSET_DSL_LMEM: 467#endif
389 return BCM_6358_DSL_LMEM_BASE; 468#ifdef CONFIG_BCM63XX_CPU_6368
390 case RSET_PERF: 469 __GEN_RSET(6368)
391 return BCM_6358_PERF_BASE;
392 case RSET_TIMER:
393 return BCM_6358_TIMER_BASE;
394 case RSET_WDT:
395 return BCM_6358_WDT_BASE;
396 case RSET_UART0:
397 return BCM_6358_UART0_BASE;
398 case RSET_UART1:
399 return BCM_6358_UART1_BASE;
400 case RSET_GPIO:
401 return BCM_6358_GPIO_BASE;
402 case RSET_SPI:
403 return BCM_6358_SPI_BASE;
404 case RSET_UDC0:
405 return BCM_6358_UDC0_BASE;
406 case RSET_OHCI0:
407 return BCM_6358_OHCI0_BASE;
408 case RSET_OHCI_PRIV:
409 return BCM_6358_OHCI_PRIV_BASE;
410 case RSET_USBH_PRIV:
411 return BCM_6358_USBH_PRIV_BASE;
412 case RSET_MPI:
413 return BCM_6358_MPI_BASE;
414 case RSET_PCMCIA:
415 return BCM_6358_PCMCIA_BASE;
416 case RSET_ENET0:
417 return BCM_6358_ENET0_BASE;
418 case RSET_ENET1:
419 return BCM_6358_ENET1_BASE;
420 case RSET_ENETDMA:
421 return BCM_6358_ENETDMA_BASE;
422 case RSET_DSL:
423 return BCM_6358_DSL_BASE;
424 case RSET_EHCI0:
425 return BCM_6358_EHCI0_BASE;
426 case RSET_SDRAM:
427 return BCM_6358_SDRAM_BASE;
428 case RSET_MEMC:
429 return BCM_6358_MEMC_BASE;
430 case RSET_DDR:
431 return BCM_6358_DDR_BASE;
432 }
433#endif 470#endif
434#endif 471#endif
435 /* unreached */ 472 /* unreached */
@@ -449,75 +486,114 @@ enum bcm63xx_irq {
449 IRQ_ENET_PHY, 486 IRQ_ENET_PHY,
450 IRQ_OHCI0, 487 IRQ_OHCI0,
451 IRQ_EHCI0, 488 IRQ_EHCI0,
452 IRQ_PCMCIA0,
453 IRQ_ENET0_RXDMA, 489 IRQ_ENET0_RXDMA,
454 IRQ_ENET0_TXDMA, 490 IRQ_ENET0_TXDMA,
455 IRQ_ENET1_RXDMA, 491 IRQ_ENET1_RXDMA,
456 IRQ_ENET1_TXDMA, 492 IRQ_ENET1_TXDMA,
457 IRQ_PCI, 493 IRQ_PCI,
458 IRQ_PCMCIA, 494 IRQ_PCMCIA,
495 IRQ_ATM,
496 IRQ_ENETSW_RXDMA0,
497 IRQ_ENETSW_RXDMA1,
498 IRQ_ENETSW_RXDMA2,
499 IRQ_ENETSW_RXDMA3,
500 IRQ_ENETSW_TXDMA0,
501 IRQ_ENETSW_TXDMA1,
502 IRQ_ENETSW_TXDMA2,
503 IRQ_ENETSW_TXDMA3,
504 IRQ_XTM,
505 IRQ_XTM_DMA0,
459}; 506};
460 507
461/* 508/*
462 * 6338 irqs 509 * 6338 irqs
463 */ 510 */
464#define BCM_6338_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) 511#define BCM_6338_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
465#define BCM_6338_SPI_IRQ (IRQ_INTERNAL_BASE + 1)
466#define BCM_6338_UART0_IRQ (IRQ_INTERNAL_BASE + 2) 512#define BCM_6338_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
467#define BCM_6338_DG_IRQ (IRQ_INTERNAL_BASE + 4) 513#define BCM_6338_UART1_IRQ 0
468#define BCM_6338_DSL_IRQ (IRQ_INTERNAL_BASE + 5) 514#define BCM_6338_DSL_IRQ (IRQ_INTERNAL_BASE + 5)
469#define BCM_6338_ATM_IRQ (IRQ_INTERNAL_BASE + 6)
470#define BCM_6338_UDC0_IRQ (IRQ_INTERNAL_BASE + 7)
471#define BCM_6338_ENET0_IRQ (IRQ_INTERNAL_BASE + 8) 515#define BCM_6338_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
516#define BCM_6338_ENET1_IRQ 0
472#define BCM_6338_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9) 517#define BCM_6338_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
473#define BCM_6338_SDRAM_IRQ (IRQ_INTERNAL_BASE + 10) 518#define BCM_6338_OHCI0_IRQ 0
474#define BCM_6338_USB_CNTL_RX_DMA_IRQ (IRQ_INTERNAL_BASE + 11) 519#define BCM_6338_EHCI0_IRQ 0
475#define BCM_6338_USB_CNTL_TX_DMA_IRQ (IRQ_INTERNAL_BASE + 12)
476#define BCM_6338_USB_BULK_RX_DMA_IRQ (IRQ_INTERNAL_BASE + 13)
477#define BCM_6338_USB_BULK_TX_DMA_IRQ (IRQ_INTERNAL_BASE + 14)
478#define BCM_6338_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15) 520#define BCM_6338_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15)
479#define BCM_6338_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16) 521#define BCM_6338_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16)
480#define BCM_6338_SDIO_IRQ (IRQ_INTERNAL_BASE + 17) 522#define BCM_6338_ENET1_RXDMA_IRQ 0
523#define BCM_6338_ENET1_TXDMA_IRQ 0
524#define BCM_6338_PCI_IRQ 0
525#define BCM_6338_PCMCIA_IRQ 0
526#define BCM_6338_ATM_IRQ 0
527#define BCM_6338_ENETSW_RXDMA0_IRQ 0
528#define BCM_6338_ENETSW_RXDMA1_IRQ 0
529#define BCM_6338_ENETSW_RXDMA2_IRQ 0
530#define BCM_6338_ENETSW_RXDMA3_IRQ 0
531#define BCM_6338_ENETSW_TXDMA0_IRQ 0
532#define BCM_6338_ENETSW_TXDMA1_IRQ 0
533#define BCM_6338_ENETSW_TXDMA2_IRQ 0
534#define BCM_6338_ENETSW_TXDMA3_IRQ 0
535#define BCM_6338_XTM_IRQ 0
536#define BCM_6338_XTM_DMA0_IRQ 0
481 537
482/* 538/*
483 * 6345 irqs 539 * 6345 irqs
484 */ 540 */
485#define BCM_6345_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) 541#define BCM_6345_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
486#define BCM_6345_UART0_IRQ (IRQ_INTERNAL_BASE + 2) 542#define BCM_6345_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
543#define BCM_6345_UART1_IRQ 0
487#define BCM_6345_DSL_IRQ (IRQ_INTERNAL_BASE + 3) 544#define BCM_6345_DSL_IRQ (IRQ_INTERNAL_BASE + 3)
488#define BCM_6345_ATM_IRQ (IRQ_INTERNAL_BASE + 4)
489#define BCM_6345_USB_IRQ (IRQ_INTERNAL_BASE + 5)
490#define BCM_6345_ENET0_IRQ (IRQ_INTERNAL_BASE + 8) 545#define BCM_6345_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
546#define BCM_6345_ENET1_IRQ 0
491#define BCM_6345_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12) 547#define BCM_6345_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12)
548#define BCM_6345_OHCI0_IRQ 0
549#define BCM_6345_EHCI0_IRQ 0
492#define BCM_6345_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 13 + 1) 550#define BCM_6345_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 13 + 1)
493#define BCM_6345_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 13 + 2) 551#define BCM_6345_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 13 + 2)
494#define BCM_6345_EBI_RX_IRQ (IRQ_INTERNAL_BASE + 13 + 5) 552#define BCM_6345_ENET1_RXDMA_IRQ 0
495#define BCM_6345_EBI_TX_IRQ (IRQ_INTERNAL_BASE + 13 + 6) 553#define BCM_6345_ENET1_TXDMA_IRQ 0
496#define BCM_6345_RESERVED_RX_IRQ (IRQ_INTERNAL_BASE + 13 + 9) 554#define BCM_6345_PCI_IRQ 0
497#define BCM_6345_RESERVED_TX_IRQ (IRQ_INTERNAL_BASE + 13 + 10) 555#define BCM_6345_PCMCIA_IRQ 0
498#define BCM_6345_USB_BULK_RX_DMA_IRQ (IRQ_INTERNAL_BASE + 13 + 13) 556#define BCM_6345_ATM_IRQ 0
499#define BCM_6345_USB_BULK_TX_DMA_IRQ (IRQ_INTERNAL_BASE + 13 + 14) 557#define BCM_6345_ENETSW_RXDMA0_IRQ 0
500#define BCM_6345_USB_CNTL_RX_DMA_IRQ (IRQ_INTERNAL_BASE + 13 + 15) 558#define BCM_6345_ENETSW_RXDMA1_IRQ 0
501#define BCM_6345_USB_CNTL_TX_DMA_IRQ (IRQ_INTERNAL_BASE + 13 + 16) 559#define BCM_6345_ENETSW_RXDMA2_IRQ 0
502#define BCM_6345_USB_ISO_RX_DMA_IRQ (IRQ_INTERNAL_BASE + 13 + 17) 560#define BCM_6345_ENETSW_RXDMA3_IRQ 0
503#define BCM_6345_USB_ISO_TX_DMA_IRQ (IRQ_INTERNAL_BASE + 13 + 18) 561#define BCM_6345_ENETSW_TXDMA0_IRQ 0
562#define BCM_6345_ENETSW_TXDMA1_IRQ 0
563#define BCM_6345_ENETSW_TXDMA2_IRQ 0
564#define BCM_6345_ENETSW_TXDMA3_IRQ 0
565#define BCM_6345_XTM_IRQ 0
566#define BCM_6345_XTM_DMA0_IRQ 0
504 567
505/* 568/*
506 * 6348 irqs 569 * 6348 irqs
507 */ 570 */
508#define BCM_6348_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) 571#define BCM_6348_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
509#define BCM_6348_UART0_IRQ (IRQ_INTERNAL_BASE + 2) 572#define BCM_6348_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
573#define BCM_6348_UART1_IRQ 0
510#define BCM_6348_DSL_IRQ (IRQ_INTERNAL_BASE + 4) 574#define BCM_6348_DSL_IRQ (IRQ_INTERNAL_BASE + 4)
511#define BCM_6348_ENET1_IRQ (IRQ_INTERNAL_BASE + 7)
512#define BCM_6348_ENET0_IRQ (IRQ_INTERNAL_BASE + 8) 575#define BCM_6348_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
576#define BCM_6348_ENET1_IRQ (IRQ_INTERNAL_BASE + 7)
513#define BCM_6348_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9) 577#define BCM_6348_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
514#define BCM_6348_OHCI0_IRQ (IRQ_INTERNAL_BASE + 12) 578#define BCM_6348_OHCI0_IRQ (IRQ_INTERNAL_BASE + 12)
579#define BCM_6348_EHCI0_IRQ 0
515#define BCM_6348_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 20) 580#define BCM_6348_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 20)
516#define BCM_6348_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 21) 581#define BCM_6348_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 21)
517#define BCM_6348_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 22) 582#define BCM_6348_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 22)
518#define BCM_6348_ENET1_TXDMA_IRQ (IRQ_INTERNAL_BASE + 23) 583#define BCM_6348_ENET1_TXDMA_IRQ (IRQ_INTERNAL_BASE + 23)
519#define BCM_6348_PCMCIA_IRQ (IRQ_INTERNAL_BASE + 24)
520#define BCM_6348_PCI_IRQ (IRQ_INTERNAL_BASE + 24) 584#define BCM_6348_PCI_IRQ (IRQ_INTERNAL_BASE + 24)
585#define BCM_6348_PCMCIA_IRQ (IRQ_INTERNAL_BASE + 24)
586#define BCM_6348_ATM_IRQ (IRQ_INTERNAL_BASE + 5)
587#define BCM_6348_ENETSW_RXDMA0_IRQ 0
588#define BCM_6348_ENETSW_RXDMA1_IRQ 0
589#define BCM_6348_ENETSW_RXDMA2_IRQ 0
590#define BCM_6348_ENETSW_RXDMA3_IRQ 0
591#define BCM_6348_ENETSW_TXDMA0_IRQ 0
592#define BCM_6348_ENETSW_TXDMA1_IRQ 0
593#define BCM_6348_ENETSW_TXDMA2_IRQ 0
594#define BCM_6348_ENETSW_TXDMA3_IRQ 0
595#define BCM_6348_XTM_IRQ 0
596#define BCM_6348_XTM_DMA0_IRQ 0
521 597
522/* 598/*
523 * 6358 irqs 599 * 6358 irqs
@@ -525,21 +601,108 @@ enum bcm63xx_irq {
525#define BCM_6358_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) 601#define BCM_6358_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
526#define BCM_6358_UART0_IRQ (IRQ_INTERNAL_BASE + 2) 602#define BCM_6358_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
527#define BCM_6358_UART1_IRQ (IRQ_INTERNAL_BASE + 3) 603#define BCM_6358_UART1_IRQ (IRQ_INTERNAL_BASE + 3)
528#define BCM_6358_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5) 604#define BCM_6358_DSL_IRQ (IRQ_INTERNAL_BASE + 29)
529#define BCM_6358_ENET1_IRQ (IRQ_INTERNAL_BASE + 6)
530#define BCM_6358_ENET0_IRQ (IRQ_INTERNAL_BASE + 8) 605#define BCM_6358_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
606#define BCM_6358_ENET1_IRQ (IRQ_INTERNAL_BASE + 6)
531#define BCM_6358_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9) 607#define BCM_6358_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
608#define BCM_6358_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5)
532#define BCM_6358_EHCI0_IRQ (IRQ_INTERNAL_BASE + 10) 609#define BCM_6358_EHCI0_IRQ (IRQ_INTERNAL_BASE + 10)
533#define BCM_6358_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15) 610#define BCM_6358_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15)
534#define BCM_6358_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16) 611#define BCM_6358_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16)
535#define BCM_6358_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 17) 612#define BCM_6358_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 17)
536#define BCM_6358_ENET1_TXDMA_IRQ (IRQ_INTERNAL_BASE + 18) 613#define BCM_6358_ENET1_TXDMA_IRQ (IRQ_INTERNAL_BASE + 18)
537#define BCM_6358_DSL_IRQ (IRQ_INTERNAL_BASE + 29)
538#define BCM_6358_PCI_IRQ (IRQ_INTERNAL_BASE + 31) 614#define BCM_6358_PCI_IRQ (IRQ_INTERNAL_BASE + 31)
539#define BCM_6358_PCMCIA_IRQ (IRQ_INTERNAL_BASE + 24) 615#define BCM_6358_PCMCIA_IRQ (IRQ_INTERNAL_BASE + 24)
616#define BCM_6358_ATM_IRQ (IRQ_INTERNAL_BASE + 19)
617#define BCM_6358_ENETSW_RXDMA0_IRQ 0
618#define BCM_6358_ENETSW_RXDMA1_IRQ 0
619#define BCM_6358_ENETSW_RXDMA2_IRQ 0
620#define BCM_6358_ENETSW_RXDMA3_IRQ 0
621#define BCM_6358_ENETSW_TXDMA0_IRQ 0
622#define BCM_6358_ENETSW_TXDMA1_IRQ 0
623#define BCM_6358_ENETSW_TXDMA2_IRQ 0
624#define BCM_6358_ENETSW_TXDMA3_IRQ 0
625#define BCM_6358_XTM_IRQ 0
626#define BCM_6358_XTM_DMA0_IRQ 0
627
628#define BCM_6358_PCM_DMA0_IRQ (IRQ_INTERNAL_BASE + 23)
629#define BCM_6358_PCM_DMA1_IRQ (IRQ_INTERNAL_BASE + 24)
630#define BCM_6358_EXT_IRQ0 (IRQ_INTERNAL_BASE + 25)
631#define BCM_6358_EXT_IRQ1 (IRQ_INTERNAL_BASE + 26)
632#define BCM_6358_EXT_IRQ2 (IRQ_INTERNAL_BASE + 27)
633#define BCM_6358_EXT_IRQ3 (IRQ_INTERNAL_BASE + 28)
634
635/*
636 * 6368 irqs
637 */
638#define BCM_6368_HIGH_IRQ_BASE (IRQ_INTERNAL_BASE + 32)
639
640#define BCM_6368_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
641#define BCM_6368_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
642#define BCM_6368_UART1_IRQ (IRQ_INTERNAL_BASE + 3)
643#define BCM_6368_DSL_IRQ (IRQ_INTERNAL_BASE + 4)
644#define BCM_6368_ENET0_IRQ 0
645#define BCM_6368_ENET1_IRQ 0
646#define BCM_6368_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 15)
647#define BCM_6368_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5)
648#define BCM_6368_EHCI0_IRQ (IRQ_INTERNAL_BASE + 7)
649#define BCM_6368_PCMCIA_IRQ 0
650#define BCM_6368_ENET0_RXDMA_IRQ 0
651#define BCM_6368_ENET0_TXDMA_IRQ 0
652#define BCM_6368_ENET1_RXDMA_IRQ 0
653#define BCM_6368_ENET1_TXDMA_IRQ 0
654#define BCM_6368_PCI_IRQ (IRQ_INTERNAL_BASE + 13)
655#define BCM_6368_ATM_IRQ 0
656#define BCM_6368_ENETSW_RXDMA0_IRQ (BCM_6368_HIGH_IRQ_BASE + 0)
657#define BCM_6368_ENETSW_RXDMA1_IRQ (BCM_6368_HIGH_IRQ_BASE + 1)
658#define BCM_6368_ENETSW_RXDMA2_IRQ (BCM_6368_HIGH_IRQ_BASE + 2)
659#define BCM_6368_ENETSW_RXDMA3_IRQ (BCM_6368_HIGH_IRQ_BASE + 3)
660#define BCM_6368_ENETSW_TXDMA0_IRQ (BCM_6368_HIGH_IRQ_BASE + 4)
661#define BCM_6368_ENETSW_TXDMA1_IRQ (BCM_6368_HIGH_IRQ_BASE + 5)
662#define BCM_6368_ENETSW_TXDMA2_IRQ (BCM_6368_HIGH_IRQ_BASE + 6)
663#define BCM_6368_ENETSW_TXDMA3_IRQ (BCM_6368_HIGH_IRQ_BASE + 7)
664#define BCM_6368_XTM_IRQ (IRQ_INTERNAL_BASE + 11)
665#define BCM_6368_XTM_DMA0_IRQ (BCM_6368_HIGH_IRQ_BASE + 8)
666
667#define BCM_6368_PCM_DMA0_IRQ (BCM_6368_HIGH_IRQ_BASE + 30)
668#define BCM_6368_PCM_DMA1_IRQ (BCM_6368_HIGH_IRQ_BASE + 31)
669#define BCM_6368_EXT_IRQ0 (IRQ_INTERNAL_BASE + 20)
670#define BCM_6368_EXT_IRQ1 (IRQ_INTERNAL_BASE + 21)
671#define BCM_6368_EXT_IRQ2 (IRQ_INTERNAL_BASE + 22)
672#define BCM_6368_EXT_IRQ3 (IRQ_INTERNAL_BASE + 23)
673#define BCM_6368_EXT_IRQ4 (IRQ_INTERNAL_BASE + 24)
674#define BCM_6368_EXT_IRQ5 (IRQ_INTERNAL_BASE + 25)
540 675
541extern const int *bcm63xx_irqs; 676extern const int *bcm63xx_irqs;
542 677
678#define __GEN_CPU_IRQ_TABLE(__cpu) \
679 [IRQ_TIMER] = BCM_## __cpu ##_TIMER_IRQ, \
680 [IRQ_UART0] = BCM_## __cpu ##_UART0_IRQ, \
681 [IRQ_UART1] = BCM_## __cpu ##_UART1_IRQ, \
682 [IRQ_DSL] = BCM_## __cpu ##_DSL_IRQ, \
683 [IRQ_ENET0] = BCM_## __cpu ##_ENET0_IRQ, \
684 [IRQ_ENET1] = BCM_## __cpu ##_ENET1_IRQ, \
685 [IRQ_ENET_PHY] = BCM_## __cpu ##_ENET_PHY_IRQ, \
686 [IRQ_OHCI0] = BCM_## __cpu ##_OHCI0_IRQ, \
687 [IRQ_EHCI0] = BCM_## __cpu ##_EHCI0_IRQ, \
688 [IRQ_ENET0_RXDMA] = BCM_## __cpu ##_ENET0_RXDMA_IRQ, \
689 [IRQ_ENET0_TXDMA] = BCM_## __cpu ##_ENET0_TXDMA_IRQ, \
690 [IRQ_ENET1_RXDMA] = BCM_## __cpu ##_ENET1_RXDMA_IRQ, \
691 [IRQ_ENET1_TXDMA] = BCM_## __cpu ##_ENET1_TXDMA_IRQ, \
692 [IRQ_PCI] = BCM_## __cpu ##_PCI_IRQ, \
693 [IRQ_PCMCIA] = BCM_## __cpu ##_PCMCIA_IRQ, \
694 [IRQ_ATM] = BCM_## __cpu ##_ATM_IRQ, \
695 [IRQ_ENETSW_RXDMA0] = BCM_## __cpu ##_ENETSW_RXDMA0_IRQ, \
696 [IRQ_ENETSW_RXDMA1] = BCM_## __cpu ##_ENETSW_RXDMA1_IRQ, \
697 [IRQ_ENETSW_RXDMA2] = BCM_## __cpu ##_ENETSW_RXDMA2_IRQ, \
698 [IRQ_ENETSW_RXDMA3] = BCM_## __cpu ##_ENETSW_RXDMA3_IRQ, \
699 [IRQ_ENETSW_TXDMA0] = BCM_## __cpu ##_ENETSW_TXDMA0_IRQ, \
700 [IRQ_ENETSW_TXDMA1] = BCM_## __cpu ##_ENETSW_TXDMA1_IRQ, \
701 [IRQ_ENETSW_TXDMA2] = BCM_## __cpu ##_ENETSW_TXDMA2_IRQ, \
702 [IRQ_ENETSW_TXDMA3] = BCM_## __cpu ##_ENETSW_TXDMA3_IRQ, \
703 [IRQ_XTM] = BCM_## __cpu ##_XTM_IRQ, \
704 [IRQ_XTM_DMA0] = BCM_## __cpu ##_XTM_DMA0_IRQ, \
705
543static inline int bcm63xx_get_irq_number(enum bcm63xx_irq irq) 706static inline int bcm63xx_get_irq_number(enum bcm63xx_irq irq)
544{ 707{
545 return bcm63xx_irqs[irq]; 708 return bcm63xx_irqs[irq];
@@ -550,4 +713,8 @@ static inline int bcm63xx_get_irq_number(enum bcm63xx_irq irq)
550 */ 713 */
551unsigned int bcm63xx_get_memory_size(void); 714unsigned int bcm63xx_get_memory_size(void);
552 715
716void bcm63xx_machine_halt(void);
717
718void bcm63xx_machine_reboot(void);
719
553#endif /* !BCM63XX_CPU_H_ */ 720#endif /* !BCM63XX_CPU_H_ */
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
index 3999ec0aa7f5..3d5de96d4036 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
@@ -14,6 +14,8 @@ static inline unsigned long bcm63xx_gpio_count(void)
14 return 8; 14 return 8;
15 case BCM6345_CPU_ID: 15 case BCM6345_CPU_ID:
16 return 16; 16 return 16;
17 case BCM6368_CPU_ID:
18 return 38;
17 case BCM6348_CPU_ID: 19 case BCM6348_CPU_ID:
18 default: 20 default:
19 return 37; 21 return 37;
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
index 91180fac6ed9..72477a6441dd 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
@@ -49,9 +49,11 @@
49#define bcm_readb(a) (*(volatile unsigned char *) BCM_REGS_VA(a)) 49#define bcm_readb(a) (*(volatile unsigned char *) BCM_REGS_VA(a))
50#define bcm_readw(a) (*(volatile unsigned short *) BCM_REGS_VA(a)) 50#define bcm_readw(a) (*(volatile unsigned short *) BCM_REGS_VA(a))
51#define bcm_readl(a) (*(volatile unsigned int *) BCM_REGS_VA(a)) 51#define bcm_readl(a) (*(volatile unsigned int *) BCM_REGS_VA(a))
52#define bcm_readq(a) (*(volatile u64 *) BCM_REGS_VA(a))
52#define bcm_writeb(v, a) (*(volatile unsigned char *) BCM_REGS_VA((a)) = (v)) 53#define bcm_writeb(v, a) (*(volatile unsigned char *) BCM_REGS_VA((a)) = (v))
53#define bcm_writew(v, a) (*(volatile unsigned short *) BCM_REGS_VA((a)) = (v)) 54#define bcm_writew(v, a) (*(volatile unsigned short *) BCM_REGS_VA((a)) = (v))
54#define bcm_writel(v, a) (*(volatile unsigned int *) BCM_REGS_VA((a)) = (v)) 55#define bcm_writel(v, a) (*(volatile unsigned int *) BCM_REGS_VA((a)) = (v))
56#define bcm_writeq(v, a) (*(volatile u64 *) BCM_REGS_VA((a)) = (v))
55 57
56/* 58/*
57 * IO helpers to access register set for current CPU 59 * IO helpers to access register set for current CPU
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_irq.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_irq.h
index 5f95577c8213..0c3074b871b8 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_irq.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_irq.h
@@ -3,13 +3,11 @@
3 3
4#include <bcm63xx_cpu.h> 4#include <bcm63xx_cpu.h>
5 5
6#define IRQ_MIPS_BASE 0
7#define IRQ_INTERNAL_BASE 8 6#define IRQ_INTERNAL_BASE 8
8 7#define IRQ_EXTERNAL_BASE 100
9#define IRQ_EXT_BASE (IRQ_MIPS_BASE + 3) 8#define IRQ_EXT_0 (IRQ_EXTERNAL_BASE + 0)
10#define IRQ_EXT_0 (IRQ_EXT_BASE + 0) 9#define IRQ_EXT_1 (IRQ_EXTERNAL_BASE + 1)
11#define IRQ_EXT_1 (IRQ_EXT_BASE + 1) 10#define IRQ_EXT_2 (IRQ_EXTERNAL_BASE + 2)
12#define IRQ_EXT_2 (IRQ_EXT_BASE + 2) 11#define IRQ_EXT_3 (IRQ_EXTERNAL_BASE + 3)
13#define IRQ_EXT_3 (IRQ_EXT_BASE + 3)
14 12
15#endif /* ! BCM63XX_IRQ_H_ */ 13#endif /* ! BCM63XX_IRQ_H_ */
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
index 0ed5230243c9..94d4faad29a1 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
@@ -83,30 +83,86 @@
83 CKCTL_6358_USBSU_EN | \ 83 CKCTL_6358_USBSU_EN | \
84 CKCTL_6358_EPHY_EN) 84 CKCTL_6358_EPHY_EN)
85 85
86#define CKCTL_6368_VDSL_QPROC_EN (1 << 2)
87#define CKCTL_6368_VDSL_AFE_EN (1 << 3)
88#define CKCTL_6368_VDSL_BONDING_EN (1 << 4)
89#define CKCTL_6368_VDSL_EN (1 << 5)
90#define CKCTL_6368_PHYMIPS_EN (1 << 6)
91#define CKCTL_6368_SWPKT_USB_EN (1 << 7)
92#define CKCTL_6368_SWPKT_SAR_EN (1 << 8)
93#define CKCTL_6368_SPI_CLK_EN (1 << 9)
94#define CKCTL_6368_USBD_CLK_EN (1 << 10)
95#define CKCTL_6368_SAR_CLK_EN (1 << 11)
96#define CKCTL_6368_ROBOSW_CLK_EN (1 << 12)
97#define CKCTL_6368_UTOPIA_CLK_EN (1 << 13)
98#define CKCTL_6368_PCM_CLK_EN (1 << 14)
99#define CKCTL_6368_USBH_CLK_EN (1 << 15)
100#define CKCTL_6368_DISABLE_GLESS_EN (1 << 16)
101#define CKCTL_6368_NAND_CLK_EN (1 << 17)
102#define CKCTL_6368_IPSEC_CLK_EN (1 << 17)
103
104#define CKCTL_6368_ALL_SAFE_EN (CKCTL_6368_SWPKT_USB_EN | \
105 CKCTL_6368_SWPKT_SAR_EN | \
106 CKCTL_6368_SPI_CLK_EN | \
107 CKCTL_6368_USBD_CLK_EN | \
108 CKCTL_6368_SAR_CLK_EN | \
109 CKCTL_6368_ROBOSW_CLK_EN | \
110 CKCTL_6368_UTOPIA_CLK_EN | \
111 CKCTL_6368_PCM_CLK_EN | \
112 CKCTL_6368_USBH_CLK_EN | \
113 CKCTL_6368_DISABLE_GLESS_EN | \
114 CKCTL_6368_NAND_CLK_EN | \
115 CKCTL_6368_IPSEC_CLK_EN)
116
86/* System PLL Control register */ 117/* System PLL Control register */
87#define PERF_SYS_PLL_CTL_REG 0x8 118#define PERF_SYS_PLL_CTL_REG 0x8
88#define SYS_PLL_SOFT_RESET 0x1 119#define SYS_PLL_SOFT_RESET 0x1
89 120
90/* Interrupt Mask register */ 121/* Interrupt Mask register */
91#define PERF_IRQMASK_REG 0xc 122#define PERF_IRQMASK_6338_REG 0xc
123#define PERF_IRQMASK_6345_REG 0xc
124#define PERF_IRQMASK_6348_REG 0xc
125#define PERF_IRQMASK_6358_REG 0xc
126#define PERF_IRQMASK_6368_REG 0x20
92 127
93/* Interrupt Status register */ 128/* Interrupt Status register */
94#define PERF_IRQSTAT_REG 0x10 129#define PERF_IRQSTAT_6338_REG 0x10
130#define PERF_IRQSTAT_6345_REG 0x10
131#define PERF_IRQSTAT_6348_REG 0x10
132#define PERF_IRQSTAT_6358_REG 0x10
133#define PERF_IRQSTAT_6368_REG 0x28
95 134
96/* External Interrupt Configuration register */ 135/* External Interrupt Configuration register */
97#define PERF_EXTIRQ_CFG_REG 0x14 136#define PERF_EXTIRQ_CFG_REG_6338 0x14
137#define PERF_EXTIRQ_CFG_REG_6348 0x14
138#define PERF_EXTIRQ_CFG_REG_6358 0x14
139#define PERF_EXTIRQ_CFG_REG_6368 0x18
140
141#define PERF_EXTIRQ_CFG_REG2_6368 0x1c
142
143/* for 6348 only */
144#define EXTIRQ_CFG_SENSE_6348(x) (1 << (x))
145#define EXTIRQ_CFG_STAT_6348(x) (1 << (x + 5))
146#define EXTIRQ_CFG_CLEAR_6348(x) (1 << (x + 10))
147#define EXTIRQ_CFG_MASK_6348(x) (1 << (x + 15))
148#define EXTIRQ_CFG_BOTHEDGE_6348(x) (1 << (x + 20))
149#define EXTIRQ_CFG_LEVELSENSE_6348(x) (1 << (x + 25))
150#define EXTIRQ_CFG_CLEAR_ALL_6348 (0xf << 10)
151#define EXTIRQ_CFG_MASK_ALL_6348 (0xf << 15)
152
153/* for all others */
98#define EXTIRQ_CFG_SENSE(x) (1 << (x)) 154#define EXTIRQ_CFG_SENSE(x) (1 << (x))
99#define EXTIRQ_CFG_STAT(x) (1 << (x + 5)) 155#define EXTIRQ_CFG_STAT(x) (1 << (x + 4))
100#define EXTIRQ_CFG_CLEAR(x) (1 << (x + 10)) 156#define EXTIRQ_CFG_CLEAR(x) (1 << (x + 8))
101#define EXTIRQ_CFG_MASK(x) (1 << (x + 15)) 157#define EXTIRQ_CFG_MASK(x) (1 << (x + 12))
102#define EXTIRQ_CFG_BOTHEDGE(x) (1 << (x + 20)) 158#define EXTIRQ_CFG_BOTHEDGE(x) (1 << (x + 16))
103#define EXTIRQ_CFG_LEVELSENSE(x) (1 << (x + 25)) 159#define EXTIRQ_CFG_LEVELSENSE(x) (1 << (x + 20))
104 160#define EXTIRQ_CFG_CLEAR_ALL (0xf << 8)
105#define EXTIRQ_CFG_CLEAR_ALL (0xf << 10) 161#define EXTIRQ_CFG_MASK_ALL (0xf << 12)
106#define EXTIRQ_CFG_MASK_ALL (0xf << 15)
107 162
108/* Soft Reset register */ 163/* Soft Reset register */
109#define PERF_SOFTRESET_REG 0x28 164#define PERF_SOFTRESET_REG 0x28
165#define PERF_SOFTRESET_6368_REG 0x10
110 166
111#define SOFTRESET_6338_SPI_MASK (1 << 0) 167#define SOFTRESET_6338_SPI_MASK (1 << 0)
112#define SOFTRESET_6338_ENET_MASK (1 << 2) 168#define SOFTRESET_6338_ENET_MASK (1 << 2)
@@ -147,6 +203,15 @@
147 SOFTRESET_6348_ACLC_MASK | \ 203 SOFTRESET_6348_ACLC_MASK | \
148 SOFTRESET_6348_ADSLMIPSPLL_MASK) 204 SOFTRESET_6348_ADSLMIPSPLL_MASK)
149 205
206#define SOFTRESET_6368_SPI_MASK (1 << 0)
207#define SOFTRESET_6368_MPI_MASK (1 << 3)
208#define SOFTRESET_6368_EPHY_MASK (1 << 6)
209#define SOFTRESET_6368_SAR_MASK (1 << 7)
210#define SOFTRESET_6368_ENETSW_MASK (1 << 10)
211#define SOFTRESET_6368_USBS_MASK (1 << 11)
212#define SOFTRESET_6368_USBH_MASK (1 << 12)
213#define SOFTRESET_6368_PCM_MASK (1 << 13)
214
150/* MIPS PLL control register */ 215/* MIPS PLL control register */
151#define PERF_MIPSPLLCTL_REG 0x34 216#define PERF_MIPSPLLCTL_REG 0x34
152#define MIPSPLLCTL_N1_SHIFT 20 217#define MIPSPLLCTL_N1_SHIFT 20
@@ -372,6 +437,7 @@
372#define GPIO_CTL_LO_REG 0x4 437#define GPIO_CTL_LO_REG 0x4
373#define GPIO_DATA_HI_REG 0x8 438#define GPIO_DATA_HI_REG 0x8
374#define GPIO_DATA_LO_REG 0xC 439#define GPIO_DATA_LO_REG 0xC
440#define GPIO_DATA_LO_REG_6345 0x8
375 441
376/* GPIO mux registers and constants */ 442/* GPIO mux registers and constants */
377#define GPIO_MODE_REG 0x18 443#define GPIO_MODE_REG 0x18
@@ -402,6 +468,44 @@
402#define GPIO_MODE_6358_SERIAL_LED (1 << 10) 468#define GPIO_MODE_6358_SERIAL_LED (1 << 10)
403#define GPIO_MODE_6358_UTOPIA (1 << 12) 469#define GPIO_MODE_6358_UTOPIA (1 << 12)
404 470
471#define GPIO_MODE_6368_ANALOG_AFE_0 (1 << 0)
472#define GPIO_MODE_6368_ANALOG_AFE_1 (1 << 1)
473#define GPIO_MODE_6368_SYS_IRQ (1 << 2)
474#define GPIO_MODE_6368_SERIAL_LED_DATA (1 << 3)
475#define GPIO_MODE_6368_SERIAL_LED_CLK (1 << 4)
476#define GPIO_MODE_6368_INET_LED (1 << 5)
477#define GPIO_MODE_6368_EPHY0_LED (1 << 6)
478#define GPIO_MODE_6368_EPHY1_LED (1 << 7)
479#define GPIO_MODE_6368_EPHY2_LED (1 << 8)
480#define GPIO_MODE_6368_EPHY3_LED (1 << 9)
481#define GPIO_MODE_6368_ROBOSW_LED_DAT (1 << 10)
482#define GPIO_MODE_6368_ROBOSW_LED_CLK (1 << 11)
483#define GPIO_MODE_6368_ROBOSW_LED0 (1 << 12)
484#define GPIO_MODE_6368_ROBOSW_LED1 (1 << 13)
485#define GPIO_MODE_6368_USBD_LED (1 << 14)
486#define GPIO_MODE_6368_NTR_PULSE (1 << 15)
487#define GPIO_MODE_6368_PCI_REQ1 (1 << 16)
488#define GPIO_MODE_6368_PCI_GNT1 (1 << 17)
489#define GPIO_MODE_6368_PCI_INTB (1 << 18)
490#define GPIO_MODE_6368_PCI_REQ0 (1 << 19)
491#define GPIO_MODE_6368_PCI_GNT0 (1 << 20)
492#define GPIO_MODE_6368_PCMCIA_CD1 (1 << 22)
493#define GPIO_MODE_6368_PCMCIA_CD2 (1 << 23)
494#define GPIO_MODE_6368_PCMCIA_VS1 (1 << 24)
495#define GPIO_MODE_6368_PCMCIA_VS2 (1 << 25)
496#define GPIO_MODE_6368_EBI_CS2 (1 << 26)
497#define GPIO_MODE_6368_EBI_CS3 (1 << 27)
498#define GPIO_MODE_6368_SPI_SSN2 (1 << 28)
499#define GPIO_MODE_6368_SPI_SSN3 (1 << 29)
500#define GPIO_MODE_6368_SPI_SSN4 (1 << 30)
501#define GPIO_MODE_6368_SPI_SSN5 (1 << 31)
502
503
504#define GPIO_BASEMODE_6368_REG 0x38
505#define GPIO_BASEMODE_6368_UART2 0x1
506#define GPIO_BASEMODE_6368_GPIO 0x0
507#define GPIO_BASEMODE_6368_MASK 0x7
508/* those bits must be kept as read in gpio basemode register*/
405 509
406/************************************************************************* 510/*************************************************************************
407 * _REG relative to RSET_ENET 511 * _REG relative to RSET_ENET
@@ -548,6 +652,56 @@
548 652
549 653
550/************************************************************************* 654/*************************************************************************
655 * _REG relative to RSET_ENETDMAC
656 *************************************************************************/
657
658/* Channel Configuration register */
659#define ENETDMAC_CHANCFG_REG(x) ((x) * 0x10)
660#define ENETDMAC_CHANCFG_EN_SHIFT 0
661#define ENETDMAC_CHANCFG_EN_MASK (1 << ENETDMA_CHANCFG_EN_SHIFT)
662#define ENETDMAC_CHANCFG_PKTHALT_SHIFT 1
663#define ENETDMAC_CHANCFG_PKTHALT_MASK (1 << ENETDMA_CHANCFG_PKTHALT_SHIFT)
664
665/* Interrupt Control/Status register */
666#define ENETDMAC_IR_REG(x) (0x4 + (x) * 0x10)
667#define ENETDMAC_IR_BUFDONE_MASK (1 << 0)
668#define ENETDMAC_IR_PKTDONE_MASK (1 << 1)
669#define ENETDMAC_IR_NOTOWNER_MASK (1 << 2)
670
671/* Interrupt Mask register */
672#define ENETDMAC_IRMASK_REG(x) (0x8 + (x) * 0x10)
673
674/* Maximum Burst Length */
675#define ENETDMAC_MAXBURST_REG(x) (0xc + (x) * 0x10)
676
677
678/*************************************************************************
679 * _REG relative to RSET_ENETDMAS
680 *************************************************************************/
681
682/* Ring Start Address register */
683#define ENETDMAS_RSTART_REG(x) ((x) * 0x10)
684
685/* State Ram Word 2 */
686#define ENETDMAS_SRAM2_REG(x) (0x4 + (x) * 0x10)
687
688/* State Ram Word 3 */
689#define ENETDMAS_SRAM3_REG(x) (0x8 + (x) * 0x10)
690
691/* State Ram Word 4 */
692#define ENETDMAS_SRAM4_REG(x) (0xc + (x) * 0x10)
693
694
695/*************************************************************************
696 * _REG relative to RSET_ENETSW
697 *************************************************************************/
698
699/* MIB register */
700#define ENETSW_MIB_REG(x) (0x2800 + (x) * 4)
701#define ENETSW_MIB_REG_COUNT 47
702
703
704/*************************************************************************
551 * _REG relative to RSET_OHCI_PRIV 705 * _REG relative to RSET_OHCI_PRIV
552 *************************************************************************/ 706 *************************************************************************/
553 707
@@ -562,7 +716,9 @@
562 * _REG relative to RSET_USBH_PRIV 716 * _REG relative to RSET_USBH_PRIV
563 *************************************************************************/ 717 *************************************************************************/
564 718
565#define USBH_PRIV_SWAP_REG 0x0 719#define USBH_PRIV_SWAP_6358_REG 0x0
720#define USBH_PRIV_SWAP_6368_REG 0x1c
721
566#define USBH_PRIV_SWAP_EHCI_ENDN_SHIFT 4 722#define USBH_PRIV_SWAP_EHCI_ENDN_SHIFT 4
567#define USBH_PRIV_SWAP_EHCI_ENDN_MASK (1 << USBH_PRIV_SWAP_EHCI_ENDN_SHIFT) 723#define USBH_PRIV_SWAP_EHCI_ENDN_MASK (1 << USBH_PRIV_SWAP_EHCI_ENDN_SHIFT)
568#define USBH_PRIV_SWAP_EHCI_DATA_SHIFT 3 724#define USBH_PRIV_SWAP_EHCI_DATA_SHIFT 3
@@ -572,7 +728,13 @@
572#define USBH_PRIV_SWAP_OHCI_DATA_SHIFT 0 728#define USBH_PRIV_SWAP_OHCI_DATA_SHIFT 0
573#define USBH_PRIV_SWAP_OHCI_DATA_MASK (1 << USBH_PRIV_SWAP_OHCI_DATA_SHIFT) 729#define USBH_PRIV_SWAP_OHCI_DATA_MASK (1 << USBH_PRIV_SWAP_OHCI_DATA_SHIFT)
574 730
575#define USBH_PRIV_TEST_REG 0x24 731#define USBH_PRIV_TEST_6358_REG 0x24
732#define USBH_PRIV_TEST_6368_REG 0x14
733
734#define USBH_PRIV_SETUP_6368_REG 0x28
735#define USBH_PRIV_SETUP_IOC_SHIFT 4
736#define USBH_PRIV_SETUP_IOC_MASK (1 << USBH_PRIV_SETUP_IOC_SHIFT)
737
576 738
577 739
578/************************************************************************* 740/*************************************************************************
@@ -734,6 +896,8 @@
734#define SDRAM_CFG_BANK_SHIFT 13 896#define SDRAM_CFG_BANK_SHIFT 13
735#define SDRAM_CFG_BANK_MASK (1 << SDRAM_CFG_BANK_SHIFT) 897#define SDRAM_CFG_BANK_MASK (1 << SDRAM_CFG_BANK_SHIFT)
736 898
899#define SDRAM_MBASE_REG 0xc
900
737#define SDRAM_PRIO_REG 0x2C 901#define SDRAM_PRIO_REG 0x2C
738#define SDRAM_PRIO_MIPS_SHIFT 29 902#define SDRAM_PRIO_MIPS_SHIFT 29
739#define SDRAM_PRIO_MIPS_MASK (1 << SDRAM_PRIO_MIPS_SHIFT) 903#define SDRAM_PRIO_MIPS_MASK (1 << SDRAM_PRIO_MIPS_SHIFT)
@@ -768,4 +932,45 @@
768#define DMIPSPLLCFG_N2_SHIFT 29 932#define DMIPSPLLCFG_N2_SHIFT 29
769#define DMIPSPLLCFG_N2_MASK (0x7 << DMIPSPLLCFG_N2_SHIFT) 933#define DMIPSPLLCFG_N2_MASK (0x7 << DMIPSPLLCFG_N2_SHIFT)
770 934
935#define DDR_DMIPSPLLCFG_6368_REG 0x20
936#define DMIPSPLLCFG_6368_P1_SHIFT 0
937#define DMIPSPLLCFG_6368_P1_MASK (0xf << DMIPSPLLCFG_6368_P1_SHIFT)
938#define DMIPSPLLCFG_6368_P2_SHIFT 4
939#define DMIPSPLLCFG_6368_P2_MASK (0xf << DMIPSPLLCFG_6368_P2_SHIFT)
940#define DMIPSPLLCFG_6368_NDIV_SHIFT 16
941#define DMIPSPLLCFG_6368_NDIV_MASK (0x1ff << DMIPSPLLCFG_6368_NDIV_SHIFT)
942
943#define DDR_DMIPSPLLDIV_6368_REG 0x24
944#define DMIPSPLLDIV_6368_MDIV_SHIFT 0
945#define DMIPSPLLDIV_6368_MDIV_MASK (0xff << DMIPSPLLDIV_6368_MDIV_SHIFT)
946
947
948/*************************************************************************
949 * _REG relative to RSET_M2M
950 *************************************************************************/
951
952#define M2M_RX 0
953#define M2M_TX 1
954
955#define M2M_SRC_REG(x) ((x) * 0x40 + 0x00)
956#define M2M_DST_REG(x) ((x) * 0x40 + 0x04)
957#define M2M_SIZE_REG(x) ((x) * 0x40 + 0x08)
958
959#define M2M_CTRL_REG(x) ((x) * 0x40 + 0x0c)
960#define M2M_CTRL_ENABLE_MASK (1 << 0)
961#define M2M_CTRL_IRQEN_MASK (1 << 1)
962#define M2M_CTRL_ERROR_CLR_MASK (1 << 6)
963#define M2M_CTRL_DONE_CLR_MASK (1 << 7)
964#define M2M_CTRL_NOINC_MASK (1 << 8)
965#define M2M_CTRL_PCMCIASWAP_MASK (1 << 9)
966#define M2M_CTRL_SWAPBYTE_MASK (1 << 10)
967#define M2M_CTRL_ENDIAN_MASK (1 << 11)
968
969#define M2M_STAT_REG(x) ((x) * 0x40 + 0x10)
970#define M2M_STAT_DONE (1 << 0)
971#define M2M_STAT_ERROR (1 << 1)
972
973#define M2M_SRCID_REG(x) ((x) * 0x40 + 0x14)
974#define M2M_DSTID_REG(x) ((x) * 0x40 + 0x18)
975
771#endif /* BCM63XX_REGS_H_ */ 976#endif /* BCM63XX_REGS_H_ */
diff --git a/arch/mips/include/asm/mach-bcm63xx/ioremap.h b/arch/mips/include/asm/mach-bcm63xx/ioremap.h
new file mode 100644
index 000000000000..ef94ba73646e
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm63xx/ioremap.h
@@ -0,0 +1,42 @@
1#ifndef BCM63XX_IOREMAP_H_
2#define BCM63XX_IOREMAP_H_
3
4#include <bcm63xx_cpu.h>
5
6static inline phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size)
7{
8 return phys_addr;
9}
10
11static inline int is_bcm63xx_internal_registers(phys_t offset)
12{
13 switch (bcm63xx_get_cpu_id()) {
14 case BCM6338_CPU_ID:
15 case BCM6345_CPU_ID:
16 case BCM6348_CPU_ID:
17 case BCM6358_CPU_ID:
18 if (offset >= 0xfff00000)
19 return 1;
20 break;
21 case BCM6368_CPU_ID:
22 if (offset >= 0xb0000000 && offset < 0xb1000000)
23 return 1;
24 break;
25 }
26 return 0;
27}
28
29static inline void __iomem *plat_ioremap(phys_t offset, unsigned long size,
30 unsigned long flags)
31{
32 if (is_bcm63xx_internal_registers(offset))
33 return (void __iomem *)offset;
34 return NULL;
35}
36
37static inline int plat_iounmap(const volatile void __iomem *addr)
38{
39 return is_bcm63xx_internal_registers((unsigned long)addr);
40}
41
42#endif /* BCM63XX_IOREMAP_H_ */
diff --git a/arch/mips/include/asm/mach-bcm63xx/irq.h b/arch/mips/include/asm/mach-bcm63xx/irq.h
new file mode 100644
index 000000000000..9332e788a5c9
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm63xx/irq.h
@@ -0,0 +1,7 @@
1#ifndef __ASM_MACH_BCM63XX_IRQ_H
2#define __ASM_MACH_BCM63XX_IRQ_H
3
4#define NR_IRQS 128
5#define MIPS_CPU_IRQ_BASE 0
6
7#endif
diff --git a/arch/mips/include/asm/mach-db1x00/bcsr.h b/arch/mips/include/asm/mach-db1x00/bcsr.h
index 618d2de02ed3..bb9fc23d853a 100644
--- a/arch/mips/include/asm/mach-db1x00/bcsr.h
+++ b/arch/mips/include/asm/mach-db1x00/bcsr.h
@@ -34,6 +34,8 @@
34#define PB1200_BCSR_PHYS_ADDR 0x0D800000 34#define PB1200_BCSR_PHYS_ADDR 0x0D800000
35#define PB1200_BCSR_HEXLED_OFS 0x00400000 35#define PB1200_BCSR_HEXLED_OFS 0x00400000
36 36
37#define DB1300_BCSR_PHYS_ADDR 0x19800000
38#define DB1300_BCSR_HEXLED_OFS 0x00400000
37 39
38enum bcsr_id { 40enum bcsr_id {
39 /* BCSR base 1 */ 41 /* BCSR base 1 */
@@ -105,6 +107,7 @@ enum bcsr_whoami_boards {
105 BCSR_WHOAMI_PB1200 = BCSR_WHOAMI_PB1200_DDR1, 107 BCSR_WHOAMI_PB1200 = BCSR_WHOAMI_PB1200_DDR1,
106 BCSR_WHOAMI_PB1200_DDR2, 108 BCSR_WHOAMI_PB1200_DDR2,
107 BCSR_WHOAMI_DB1200, 109 BCSR_WHOAMI_DB1200,
110 BCSR_WHOAMI_DB1300,
108}; 111};
109 112
110/* STATUS reg. Unless otherwise noted, they're valid on all boards. 113/* STATUS reg. Unless otherwise noted, they're valid on all boards.
@@ -118,12 +121,12 @@ enum bcsr_whoami_boards {
118#define BCSR_STATUS_SRAMWIDTH 0x0080 121#define BCSR_STATUS_SRAMWIDTH 0x0080
119#define BCSR_STATUS_FLASHBUSY 0x0100 122#define BCSR_STATUS_FLASHBUSY 0x0100
120#define BCSR_STATUS_ROMBUSY 0x0400 123#define BCSR_STATUS_ROMBUSY 0x0400
121#define BCSR_STATUS_SD0WP 0x0400 /* DB1200 */ 124#define BCSR_STATUS_SD0WP 0x0400 /* DB1200/DB1300:SD1 */
122#define BCSR_STATUS_SD1WP 0x0800 125#define BCSR_STATUS_SD1WP 0x0800
123#define BCSR_STATUS_USBOTGID 0x0800 /* PB/DB1550 */ 126#define BCSR_STATUS_USBOTGID 0x0800 /* PB/DB1550 */
124#define BCSR_STATUS_DB1000_SWAPBOOT 0x2000 127#define BCSR_STATUS_DB1000_SWAPBOOT 0x2000
125#define BCSR_STATUS_DB1200_SWAPBOOT 0x0040 /* DB1200 */ 128#define BCSR_STATUS_DB1200_SWAPBOOT 0x0040 /* DB1200/1300 */
126#define BCSR_STATUS_IDECBLID 0x0200 /* DB1200 */ 129#define BCSR_STATUS_IDECBLID 0x0200 /* DB1200/1300 */
127#define BCSR_STATUS_DB1200_U0RXD 0x1000 /* DB1200 */ 130#define BCSR_STATUS_DB1200_U0RXD 0x1000 /* DB1200 */
128#define BCSR_STATUS_DB1200_U1RXD 0x2000 /* DB1200 */ 131#define BCSR_STATUS_DB1200_U1RXD 0x2000 /* DB1200 */
129#define BCSR_STATUS_FLASHDEN 0xC000 132#define BCSR_STATUS_FLASHDEN 0xC000
@@ -133,6 +136,11 @@ enum bcsr_whoami_boards {
133#define BCSR_STATUS_PB1550_U1RXD 0x2000 /* PB1550 */ 136#define BCSR_STATUS_PB1550_U1RXD 0x2000 /* PB1550 */
134#define BCSR_STATUS_PB1550_U3RXD 0x8000 /* PB1550 */ 137#define BCSR_STATUS_PB1550_U3RXD 0x8000 /* PB1550 */
135 138
139#define BCSR_STATUS_CFWP 0x4000 /* DB1300 */
140#define BCSR_STATUS_USBOCn 0x2000 /* DB1300 */
141#define BCSR_STATUS_OTGOCn 0x1000 /* DB1300 */
142#define BCSR_STATUS_DCDMARQ 0x0010 /* DB1300 */
143#define BCSR_STATUS_IDEDMARQ 0x0020 /* DB1300 */
136 144
137/* DB/PB1000,1100,1500,1550 */ 145/* DB/PB1000,1100,1500,1550 */
138#define BCSR_RESETS_PHY0 0x0001 146#define BCSR_RESETS_PHY0 0x0001
@@ -155,17 +163,17 @@ enum bcsr_whoami_boards {
155#define BCSR_BOARD_GPIO200RST 0x0400 163#define BCSR_BOARD_GPIO200RST 0x0400
156#define BCSR_BOARD_PCICLKOUT 0x0800 164#define BCSR_BOARD_PCICLKOUT 0x0800
157#define BCSR_BOARD_PCICFG 0x1000 165#define BCSR_BOARD_PCICFG 0x1000
158#define BCSR_BOARD_SPISEL 0x4000 /* PB/DB1550 */ 166#define BCSR_BOARD_SPISEL 0x2000 /* PB/DB1550 */
159#define BCSR_BOARD_SD0WP 0x4000 /* DB1100 */ 167#define BCSR_BOARD_SD0WP 0x4000 /* DB1100 */
160#define BCSR_BOARD_SD1WP 0x8000 /* DB1100 */ 168#define BCSR_BOARD_SD1WP 0x8000 /* DB1100 */
161 169
162 170
163/* DB/PB1200 */ 171/* DB/PB1200/1300 */
164#define BCSR_RESETS_ETH 0x0001 172#define BCSR_RESETS_ETH 0x0001
165#define BCSR_RESETS_CAMERA 0x0002 173#define BCSR_RESETS_CAMERA 0x0002
166#define BCSR_RESETS_DC 0x0004 174#define BCSR_RESETS_DC 0x0004
167#define BCSR_RESETS_IDE 0x0008 175#define BCSR_RESETS_IDE 0x0008
168#define BCSR_RESETS_TV 0x0010 /* DB1200 */ 176#define BCSR_RESETS_TV 0x0010 /* DB1200/1300 */
169/* Not resets but in the same register */ 177/* Not resets but in the same register */
170#define BCSR_RESETS_PWMR1MUX 0x0800 /* DB1200 */ 178#define BCSR_RESETS_PWMR1MUX 0x0800 /* DB1200 */
171#define BCSR_RESETS_PB1200_WSCFSM 0x0800 /* PB1200 */ 179#define BCSR_RESETS_PB1200_WSCFSM 0x0800 /* PB1200 */
@@ -174,13 +182,22 @@ enum bcsr_whoami_boards {
174#define BCSR_RESETS_SPISEL 0x4000 182#define BCSR_RESETS_SPISEL 0x4000
175#define BCSR_RESETS_SD1MUX 0x8000 /* PB1200 */ 183#define BCSR_RESETS_SD1MUX 0x8000 /* PB1200 */
176 184
185#define BCSR_RESETS_VDDQSHDN 0x0200 /* DB1300 */
186#define BCSR_RESETS_OTPPGM 0x0400 /* DB1300 */
187#define BCSR_RESETS_OTPSCLK 0x0800 /* DB1300 */
188#define BCSR_RESETS_OTPWRPROT 0x1000 /* DB1300 */
189#define BCSR_RESETS_OTPCSB 0x2000 /* DB1300 */
190#define BCSR_RESETS_OTGPWR 0x4000 /* DB1300 */
191#define BCSR_RESETS_USBHPWR 0x8000 /* DB1300 */
192
177#define BCSR_BOARD_LCDVEE 0x0001 193#define BCSR_BOARD_LCDVEE 0x0001
178#define BCSR_BOARD_LCDVDD 0x0002 194#define BCSR_BOARD_LCDVDD 0x0002
179#define BCSR_BOARD_LCDBL 0x0004 195#define BCSR_BOARD_LCDBL 0x0004
180#define BCSR_BOARD_CAMSNAP 0x0010 196#define BCSR_BOARD_CAMSNAP 0x0010
181#define BCSR_BOARD_CAMPWR 0x0020 197#define BCSR_BOARD_CAMPWR 0x0020
182#define BCSR_BOARD_SD0PWR 0x0040 198#define BCSR_BOARD_SD0PWR 0x0040
183 199#define BCSR_BOARD_CAMCS 0x0010 /* DB1300 */
200#define BCSR_BOARD_HDMI_DE 0x0040 /* DB1300 */
184 201
185#define BCSR_SWITCHES_DIP 0x00FF 202#define BCSR_SWITCHES_DIP 0x00FF
186#define BCSR_SWITCHES_DIP_1 0x0080 203#define BCSR_SWITCHES_DIP_1 0x0080
@@ -214,7 +231,10 @@ enum bcsr_whoami_boards {
214#define BCSR_SYSTEM_RESET 0x8000 /* clear to reset */ 231#define BCSR_SYSTEM_RESET 0x8000 /* clear to reset */
215#define BCSR_SYSTEM_PWROFF 0x4000 /* set to power off */ 232#define BCSR_SYSTEM_PWROFF 0x4000 /* set to power off */
216#define BCSR_SYSTEM_VDDI 0x001F /* PB1xxx boards */ 233#define BCSR_SYSTEM_VDDI 0x001F /* PB1xxx boards */
217 234#define BCSR_SYSTEM_DEBUGCSMASK 0x003F /* DB1300 */
235#define BCSR_SYSTEM_UDMAMODE 0x0100 /* DB1300 */
236#define BCSR_SYSTEM_WAKEONIRQ 0x0200 /* DB1300 */
237#define BCSR_SYSTEM_VDDI1300 0x3C00 /* DB1300 */
218 238
219 239
220 240
diff --git a/arch/mips/include/asm/mach-db1x00/db1200.h b/arch/mips/include/asm/mach-db1x00/db1200.h
index 7a39657108c4..b2a8319521e5 100644
--- a/arch/mips/include/asm/mach-db1x00/db1200.h
+++ b/arch/mips/include/asm/mach-db1x00/db1200.h
@@ -43,15 +43,20 @@
43#define BCSR_INT_PC1EJECT 0x0800 43#define BCSR_INT_PC1EJECT 0x0800
44#define BCSR_INT_SD0INSERT 0x1000 44#define BCSR_INT_SD0INSERT 0x1000
45#define BCSR_INT_SD0EJECT 0x2000 45#define BCSR_INT_SD0EJECT 0x2000
46#define BCSR_INT_SD1INSERT 0x4000
47#define BCSR_INT_SD1EJECT 0x8000
46 48
47#define IDE_PHYS_ADDR 0x18800000
48#define IDE_REG_SHIFT 5 49#define IDE_REG_SHIFT 5
49 50
50#define DB1200_IDE_PHYS_ADDR IDE_PHYS_ADDR 51#define DB1200_IDE_PHYS_ADDR 0x18800000
51#define DB1200_IDE_PHYS_LEN (16 << IDE_REG_SHIFT) 52#define DB1200_IDE_PHYS_LEN (16 << IDE_REG_SHIFT)
52#define DB1200_ETH_PHYS_ADDR 0x19000300 53#define DB1200_ETH_PHYS_ADDR 0x19000300
53#define DB1200_NAND_PHYS_ADDR 0x20000000 54#define DB1200_NAND_PHYS_ADDR 0x20000000
54 55
56#define PB1200_IDE_PHYS_ADDR 0x0C800000
57#define PB1200_ETH_PHYS_ADDR 0x0D000300
58#define PB1200_NAND_PHYS_ADDR 0x1C000000
59
55/* 60/*
56 * External Interrupts for DBAu1200 as of 8/6/2004. 61 * External Interrupts for DBAu1200 as of 8/6/2004.
57 * Bit positions in the CPLD registers can be calculated by taking 62 * Bit positions in the CPLD registers can be calculated by taking
@@ -77,6 +82,8 @@ enum external_db1200_ints {
77 DB1200_PC1_EJECT_INT, 82 DB1200_PC1_EJECT_INT,
78 DB1200_SD0_INSERT_INT, 83 DB1200_SD0_INSERT_INT,
79 DB1200_SD0_EJECT_INT, 84 DB1200_SD0_EJECT_INT,
85 PB1200_SD1_INSERT_INT,
86 PB1200_SD1_EJECT_INT,
80 87
81 DB1200_INT_END = DB1200_INT_BEGIN + 15, 88 DB1200_INT_END = DB1200_INT_BEGIN + 15,
82}; 89};
diff --git a/arch/mips/include/asm/mach-db1x00/db1300.h b/arch/mips/include/asm/mach-db1x00/db1300.h
new file mode 100644
index 000000000000..7fe5fb3ba877
--- /dev/null
+++ b/arch/mips/include/asm/mach-db1x00/db1300.h
@@ -0,0 +1,40 @@
1/*
2 * NetLogic DB1300 board constants
3 */
4
5#ifndef _DB1300_H_
6#define _DB1300_H_
7
8/* FPGA (external mux) interrupt sources */
9#define DB1300_FIRST_INT (ALCHEMY_GPIC_INT_LAST + 1)
10#define DB1300_IDE_INT (DB1300_FIRST_INT + 0)
11#define DB1300_ETH_INT (DB1300_FIRST_INT + 1)
12#define DB1300_CF_INT (DB1300_FIRST_INT + 2)
13#define DB1300_VIDEO_INT (DB1300_FIRST_INT + 4)
14#define DB1300_HDMI_INT (DB1300_FIRST_INT + 5)
15#define DB1300_DC_INT (DB1300_FIRST_INT + 6)
16#define DB1300_FLASH_INT (DB1300_FIRST_INT + 7)
17#define DB1300_CF_INSERT_INT (DB1300_FIRST_INT + 8)
18#define DB1300_CF_EJECT_INT (DB1300_FIRST_INT + 9)
19#define DB1300_AC97_INT (DB1300_FIRST_INT + 10)
20#define DB1300_AC97_PEN_INT (DB1300_FIRST_INT + 11)
21#define DB1300_SD1_INSERT_INT (DB1300_FIRST_INT + 12)
22#define DB1300_SD1_EJECT_INT (DB1300_FIRST_INT + 13)
23#define DB1300_OTG_VBUS_OC_INT (DB1300_FIRST_INT + 14)
24#define DB1300_HOST_VBUS_OC_INT (DB1300_FIRST_INT + 15)
25#define DB1300_LAST_INT (DB1300_FIRST_INT + 15)
26
27/* SMSC9210 CS */
28#define DB1300_ETH_PHYS_ADDR 0x19000000
29#define DB1300_ETH_PHYS_END 0x197fffff
30
31/* ATA CS */
32#define DB1300_IDE_PHYS_ADDR 0x18800000
33#define DB1300_IDE_REG_SHIFT 5
34#define DB1300_IDE_PHYS_LEN (16 << DB1300_IDE_REG_SHIFT)
35
36/* NAND CS */
37#define DB1300_NAND_PHYS_ADDR 0x20000000
38#define DB1300_NAND_PHYS_END 0x20000fff
39
40#endif /* _DB1300_H_ */
diff --git a/arch/mips/include/asm/mach-db1x00/db1x00.h b/arch/mips/include/asm/mach-db1x00/db1x00.h
deleted file mode 100644
index a5affb0568ef..000000000000
--- a/arch/mips/include/asm/mach-db1x00/db1x00.h
+++ /dev/null
@@ -1,79 +0,0 @@
1/*
2 * AMD Alchemy DBAu1x00 Reference Boards
3 *
4 * Copyright 2001, 2008 MontaVista Software Inc.
5 * Author: MontaVista Software, Inc. <source@mvista.com>
6 * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
7 *
8 * ########################################################################
9 *
10 * This program is free software; you can distribute it and/or modify it
11 * under the terms of the GNU General Public License (Version 2) as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 * for more details.
18 *
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, write to the Free Software Foundation, Inc.,
21 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
22 *
23 * ########################################################################
24 *
25 *
26 */
27#ifndef __ASM_DB1X00_H
28#define __ASM_DB1X00_H
29
30#include <asm/mach-au1x00/au1xxx_psc.h>
31
32#ifdef CONFIG_MIPS_DB1550
33
34#define DBDMA_AC97_TX_CHAN AU1550_DSCR_CMD0_PSC1_TX
35#define DBDMA_AC97_RX_CHAN AU1550_DSCR_CMD0_PSC1_RX
36#define DBDMA_I2S_TX_CHAN AU1550_DSCR_CMD0_PSC3_TX
37#define DBDMA_I2S_RX_CHAN AU1550_DSCR_CMD0_PSC3_RX
38
39#define SPI_PSC_BASE AU1550_PSC0_PHYS_ADDR
40#define AC97_PSC_BASE AU1550_PSC1_PHYS_ADDR
41#define SMBUS_PSC_BASE AU1550_PSC2_PHYS_ADDR
42#define I2S_PSC_BASE AU1550_PSC3_PHYS_ADDR
43
44#define NAND_PHYS_ADDR 0x20000000
45
46#endif
47
48/*
49 * NAND defines
50 *
51 * Timing values as described in databook, * ns value stripped of the
52 * lower 2 bits.
53 * These defines are here rather than an Au1550 generic file because
54 * the parts chosen on another board may be different and may require
55 * different timings.
56 */
57#define NAND_T_H (18 >> 2)
58#define NAND_T_PUL (30 >> 2)
59#define NAND_T_SU (30 >> 2)
60#define NAND_T_WH (30 >> 2)
61
62/* Bitfield shift amounts */
63#define NAND_T_H_SHIFT 0
64#define NAND_T_PUL_SHIFT 4
65#define NAND_T_SU_SHIFT 8
66#define NAND_T_WH_SHIFT 12
67
68#define NAND_TIMING (((NAND_T_H & 0xF) << NAND_T_H_SHIFT) | \
69 ((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \
70 ((NAND_T_SU & 0xF) << NAND_T_SU_SHIFT) | \
71 ((NAND_T_WH & 0xF) << NAND_T_WH_SHIFT))
72#define NAND_CS 1
73
74/* Should be done by YAMON */
75#define NAND_STCFG 0x00400005 /* 8-bit NAND */
76#define NAND_STTIME 0x00007774 /* valid for 396 MHz SD=2 only */
77#define NAND_STADDR 0x12000FFF /* physical address 0x20000000 */
78
79#endif /* __ASM_DB1X00_H */
diff --git a/arch/mips/include/asm/mach-db1x00/irq.h b/arch/mips/include/asm/mach-db1x00/irq.h
new file mode 100644
index 000000000000..15b26693238f
--- /dev/null
+++ b/arch/mips/include/asm/mach-db1x00/irq.h
@@ -0,0 +1,23 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2003 by Ralf Baechle
7 */
8#ifndef __ASM_MACH_GENERIC_IRQ_H
9#define __ASM_MACH_GENERIC_IRQ_H
10
11
12#ifdef NR_IRQS
13#undef NR_IRQS
14#endif
15
16#ifndef MIPS_CPU_IRQ_BASE
17#define MIPS_CPU_IRQ_BASE 0
18#endif
19
20/* 8 (MIPS) + 128 (au1300) + 16 (cpld) */
21#define NR_IRQS 152
22
23#endif /* __ASM_MACH_GENERIC_IRQ_H */
diff --git a/arch/mips/include/asm/mach-generic/floppy.h b/arch/mips/include/asm/mach-generic/floppy.h
index 001a8ce17c17..a38f4d43e5e5 100644
--- a/arch/mips/include/asm/mach-generic/floppy.h
+++ b/arch/mips/include/asm/mach-generic/floppy.h
@@ -98,7 +98,7 @@ static inline void fd_disable_irq(void)
98static inline int fd_request_irq(void) 98static inline int fd_request_irq(void)
99{ 99{
100 return request_irq(FLOPPY_IRQ, floppy_interrupt, 100 return request_irq(FLOPPY_IRQ, floppy_interrupt,
101 IRQF_DISABLED, "floppy", NULL); 101 0, "floppy", NULL);
102} 102}
103 103
104static inline void fd_free_irq(void) 104static inline void fd_free_irq(void)
diff --git a/arch/mips/include/asm/mach-jazz/floppy.h b/arch/mips/include/asm/mach-jazz/floppy.h
index 56e9ca6ae426..88b5acb75145 100644
--- a/arch/mips/include/asm/mach-jazz/floppy.h
+++ b/arch/mips/include/asm/mach-jazz/floppy.h
@@ -90,7 +90,7 @@ static inline void fd_disable_irq(void)
90static inline int fd_request_irq(void) 90static inline int fd_request_irq(void)
91{ 91{
92 return request_irq(FLOPPY_IRQ, floppy_interrupt, 92 return request_irq(FLOPPY_IRQ, floppy_interrupt,
93 IRQF_DISABLED, "floppy", NULL); 93 0, "floppy", NULL);
94} 94}
95 95
96static inline void fd_free_irq(void) 96static inline void fd_free_irq(void)
diff --git a/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h b/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h
index 3b728275b9b0..d193fb68cf27 100644
--- a/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h
@@ -24,24 +24,33 @@
24 24
25#define cpu_has_llsc 1 25#define cpu_has_llsc 1
26#define cpu_has_vtag_icache 0 26#define cpu_has_vtag_icache 0
27#define cpu_has_dc_aliases 0 27#define cpu_has_ic_fills_f_dc 1
28#define cpu_has_ic_fills_f_dc 0
29#define cpu_has_dsp 0 28#define cpu_has_dsp 0
30#define cpu_has_mipsmt 0 29#define cpu_has_mipsmt 0
31#define cpu_has_userlocal 0 30#define cpu_icache_snoops_remote_store 1
32#define cpu_icache_snoops_remote_store 0
33 31
34#define cpu_has_nofpuex 0
35#define cpu_has_64bits 1 32#define cpu_has_64bits 1
36 33
37#define cpu_has_mips32r1 1 34#define cpu_has_mips32r1 1
38#define cpu_has_mips32r2 0
39#define cpu_has_mips64r1 1 35#define cpu_has_mips64r1 1
40#define cpu_has_mips64r2 0
41 36
42#define cpu_has_inclusive_pcaches 0 37#define cpu_has_inclusive_pcaches 0
43 38
44#define cpu_dcache_line_size() 32 39#define cpu_dcache_line_size() 32
45#define cpu_icache_line_size() 32 40#define cpu_icache_line_size() 32
46 41
42#if defined(CONFIG_CPU_XLR)
43#define cpu_has_userlocal 0
44#define cpu_has_dc_aliases 0
45#define cpu_has_mips32r2 0
46#define cpu_has_mips64r2 0
47#elif defined(CONFIG_CPU_XLP)
48#define cpu_has_userlocal 1
49#define cpu_has_mips32r2 1
50#define cpu_has_mips64r2 1
51#define cpu_has_dc_aliases 1
52#else
53#error "Unknown Netlogic CPU"
54#endif
55
47#endif /* __ASM_MACH_NETLOGIC_CPU_FEATURE_OVERRIDES_H */ 56#endif /* __ASM_MACH_NETLOGIC_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mach-pb1x00/mc146818rtc.h b/arch/mips/include/asm/mach-pb1x00/mc146818rtc.h
deleted file mode 100644
index 622c58710e5b..000000000000
--- a/arch/mips/include/asm/mach-pb1x00/mc146818rtc.h
+++ /dev/null
@@ -1,34 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1998, 2001, 03 by Ralf Baechle
7 *
8 * RTC routines for PC style attached Dallas chip.
9 */
10#ifndef __ASM_MACH_AU1XX_MC146818RTC_H
11#define __ASM_MACH_AU1XX_MC146818RTC_H
12
13#include <asm/io.h>
14#include <asm/mach-au1x00/au1000.h>
15
16#define RTC_PORT(x) (0x0c000000 + (x))
17#define RTC_IRQ 8
18#define PB1500_RTC_ADDR 0x0c000000
19
20static inline unsigned char CMOS_READ(unsigned long offset)
21{
22 offset <<= 2;
23 return (u8)(au_readl(offset + PB1500_RTC_ADDR) & 0xff);
24}
25
26static inline void CMOS_WRITE(unsigned char data, unsigned long offset)
27{
28 offset <<= 2;
29 au_writel(data, offset + PB1500_RTC_ADDR);
30}
31
32#define RTC_ALWAYS_BCD 1
33
34#endif /* __ASM_MACH_AU1XX_MC146818RTC_H */
diff --git a/arch/mips/include/asm/mach-pb1x00/pb1000.h b/arch/mips/include/asm/mach-pb1x00/pb1000.h
deleted file mode 100644
index 65059255dc1e..000000000000
--- a/arch/mips/include/asm/mach-pb1x00/pb1000.h
+++ /dev/null
@@ -1,87 +0,0 @@
1/*
2 * Alchemy Semi Pb1000 Reference Board
3 *
4 * Copyright 2001, 2008 MontaVista Software Inc.
5 * Author: MontaVista Software, Inc. <source@mvista.com>
6 *
7 * ########################################################################
8 *
9 * This program is free software; you can distribute it and/or modify it
10 * under the terms of the GNU General Public License (Version 2) as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * for more details.
17 *
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, write to the Free Software Foundation, Inc.,
20 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
21 *
22 * ########################################################################
23 *
24 *
25 */
26#ifndef __ASM_PB1000_H
27#define __ASM_PB1000_H
28
29/* PCMCIA PB1000 specific defines */
30#define PCMCIA_MAX_SOCK 1
31#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1)
32
33#define PB1000_PCR 0xBE000000
34# define PCR_SLOT_0_VPP0 (1 << 0)
35# define PCR_SLOT_0_VPP1 (1 << 1)
36# define PCR_SLOT_0_VCC0 (1 << 2)
37# define PCR_SLOT_0_VCC1 (1 << 3)
38# define PCR_SLOT_0_RST (1 << 4)
39# define PCR_SLOT_1_VPP0 (1 << 8)
40# define PCR_SLOT_1_VPP1 (1 << 9)
41# define PCR_SLOT_1_VCC0 (1 << 10)
42# define PCR_SLOT_1_VCC1 (1 << 11)
43# define PCR_SLOT_1_RST (1 << 12)
44
45#define PB1000_MDR 0xBE000004
46# define MDR_PI (1 << 5) /* PCMCIA int latch */
47# define MDR_EPI (1 << 14) /* enable PCMCIA int */
48# define MDR_CPI (1 << 15) /* clear PCMCIA int */
49
50#define PB1000_ACR1 0xBE000008
51# define ACR1_SLOT_0_CD1 (1 << 0) /* card detect 1 */
52# define ACR1_SLOT_0_CD2 (1 << 1) /* card detect 2 */
53# define ACR1_SLOT_0_READY (1 << 2) /* ready */
54# define ACR1_SLOT_0_STATUS (1 << 3) /* status change */
55# define ACR1_SLOT_0_VS1 (1 << 4) /* voltage sense 1 */
56# define ACR1_SLOT_0_VS2 (1 << 5) /* voltage sense 2 */
57# define ACR1_SLOT_0_INPACK (1 << 6) /* inpack pin status */
58# define ACR1_SLOT_1_CD1 (1 << 8) /* card detect 1 */
59# define ACR1_SLOT_1_CD2 (1 << 9) /* card detect 2 */
60# define ACR1_SLOT_1_READY (1 << 10) /* ready */
61# define ACR1_SLOT_1_STATUS (1 << 11) /* status change */
62# define ACR1_SLOT_1_VS1 (1 << 12) /* voltage sense 1 */
63# define ACR1_SLOT_1_VS2 (1 << 13) /* voltage sense 2 */
64# define ACR1_SLOT_1_INPACK (1 << 14) /* inpack pin status */
65
66#define CPLD_AUX0 0xBE00000C
67#define CPLD_AUX1 0xBE000010
68#define CPLD_AUX2 0xBE000014
69
70/* Voltage levels */
71
72/* VPPEN1 - VPPEN0 */
73#define VPP_GND ((0 << 1) | (0 << 0))
74#define VPP_5V ((1 << 1) | (0 << 0))
75#define VPP_3V ((0 << 1) | (1 << 0))
76#define VPP_12V ((0 << 1) | (1 << 0))
77#define VPP_HIZ ((1 << 1) | (1 << 0))
78
79/* VCCEN1 - VCCEN0 */
80#define VCC_3V ((0 << 1) | (1 << 0))
81#define VCC_5V ((1 << 1) | (0 << 0))
82#define VCC_HIZ ((0 << 1) | (0 << 0))
83
84/* VPP/VCC */
85#define SET_VCC_VPP(VCC, VPP, SLOT) \
86 ((((VCC) << 2) | ((VPP) << 0)) << ((SLOT) * 8))
87#endif /* __ASM_PB1000_H */
diff --git a/arch/mips/include/asm/mach-pb1x00/pb1200.h b/arch/mips/include/asm/mach-pb1x00/pb1200.h
deleted file mode 100644
index 374416adb65b..000000000000
--- a/arch/mips/include/asm/mach-pb1x00/pb1200.h
+++ /dev/null
@@ -1,139 +0,0 @@
1/*
2 * AMD Alchemy Pb1200 Reference Board
3 * Board Registers defines.
4 *
5 * ########################################################################
6 *
7 * This program is free software; you can distribute it and/or modify it
8 * under the terms of the GNU General Public License (Version 2) as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
19 *
20 * ########################################################################
21 *
22 *
23 */
24#ifndef __ASM_PB1200_H
25#define __ASM_PB1200_H
26
27#include <linux/types.h>
28#include <asm/mach-au1x00/au1000.h>
29#include <asm/mach-au1x00/au1xxx_psc.h>
30
31#define DBDMA_AC97_TX_CHAN AU1200_DSCR_CMD0_PSC1_TX
32#define DBDMA_AC97_RX_CHAN AU1200_DSCR_CMD0_PSC1_RX
33#define DBDMA_I2S_TX_CHAN AU1200_DSCR_CMD0_PSC1_TX
34#define DBDMA_I2S_RX_CHAN AU1200_DSCR_CMD0_PSC1_RX
35
36/*
37 * SPI and SMB are muxed on the Pb1200 board.
38 * Refer to board documentation.
39 */
40#define SPI_PSC_BASE AU1550_PSC0_PHYS_ADDR
41#define SMBUS_PSC_BASE AU1550_PSC0_PHYS_ADDR
42/*
43 * AC97 and I2S are muxed on the Pb1200 board.
44 * Refer to board documentation.
45 */
46#define AC97_PSC_BASE AU1550_PSC1_PHYS_ADDR
47#define I2S_PSC_BASE AU1550_PSC1_PHYS_ADDR
48
49
50#define BCSR_SYSTEM_VDDI 0x001F
51#define BCSR_SYSTEM_POWEROFF 0x4000
52#define BCSR_SYSTEM_RESET 0x8000
53
54/* Bit positions for the different interrupt sources */
55#define BCSR_INT_IDE 0x0001
56#define BCSR_INT_ETH 0x0002
57#define BCSR_INT_PC0 0x0004
58#define BCSR_INT_PC0STSCHG 0x0008
59#define BCSR_INT_PC1 0x0010
60#define BCSR_INT_PC1STSCHG 0x0020
61#define BCSR_INT_DC 0x0040
62#define BCSR_INT_FLASHBUSY 0x0080
63#define BCSR_INT_PC0INSERT 0x0100
64#define BCSR_INT_PC0EJECT 0x0200
65#define BCSR_INT_PC1INSERT 0x0400
66#define BCSR_INT_PC1EJECT 0x0800
67#define BCSR_INT_SD0INSERT 0x1000
68#define BCSR_INT_SD0EJECT 0x2000
69#define BCSR_INT_SD1INSERT 0x4000
70#define BCSR_INT_SD1EJECT 0x8000
71
72#define SMC91C111_PHYS_ADDR 0x0D000300
73#define SMC91C111_INT PB1200_ETH_INT
74
75#define IDE_PHYS_ADDR 0x0C800000
76#define IDE_REG_SHIFT 5
77#define IDE_PHYS_LEN (16 << IDE_REG_SHIFT)
78#define IDE_INT PB1200_IDE_INT
79
80#define NAND_PHYS_ADDR 0x1C000000
81
82/*
83 * Timing values as described in databook, * ns value stripped of
84 * lower 2 bits.
85 * These defines are here rather than an Au1200 generic file because
86 * the parts chosen on another board may be different and may require
87 * different timings.
88 */
89#define NAND_T_H (18 >> 2)
90#define NAND_T_PUL (30 >> 2)
91#define NAND_T_SU (30 >> 2)
92#define NAND_T_WH (30 >> 2)
93
94/* Bitfield shift amounts */
95#define NAND_T_H_SHIFT 0
96#define NAND_T_PUL_SHIFT 4
97#define NAND_T_SU_SHIFT 8
98#define NAND_T_WH_SHIFT 12
99
100#define NAND_TIMING (((NAND_T_H & 0xF) << NAND_T_H_SHIFT) | \
101 ((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \
102 ((NAND_T_SU & 0xF) << NAND_T_SU_SHIFT) | \
103 ((NAND_T_WH & 0xF) << NAND_T_WH_SHIFT))
104
105/*
106 * External Interrupts for Pb1200 as of 8/6/2004.
107 * Bit positions in the CPLD registers can be calculated by taking
108 * the interrupt define and subtracting the PB1200_INT_BEGIN value.
109 *
110 * Example: IDE bis pos is = 64 - 64
111 * ETH bit pos is = 65 - 64
112 */
113enum external_pb1200_ints {
114 PB1200_INT_BEGIN = AU1000_MAX_INTR + 1,
115
116 PB1200_IDE_INT = PB1200_INT_BEGIN,
117 PB1200_ETH_INT,
118 PB1200_PC0_INT,
119 PB1200_PC0_STSCHG_INT,
120 PB1200_PC1_INT,
121 PB1200_PC1_STSCHG_INT,
122 PB1200_DC_INT,
123 PB1200_FLASHBUSY_INT,
124 PB1200_PC0_INSERT_INT,
125 PB1200_PC0_EJECT_INT,
126 PB1200_PC1_INSERT_INT,
127 PB1200_PC1_EJECT_INT,
128 PB1200_SD0_INSERT_INT,
129 PB1200_SD0_EJECT_INT,
130 PB1200_SD1_INSERT_INT,
131 PB1200_SD1_EJECT_INT,
132
133 PB1200_INT_END = PB1200_INT_BEGIN + 15
134};
135
136/* NAND chip select */
137#define NAND_CS 1
138
139#endif /* __ASM_PB1200_H */
diff --git a/arch/mips/include/asm/mach-pb1x00/pb1550.h b/arch/mips/include/asm/mach-pb1x00/pb1550.h
deleted file mode 100644
index 443b88adebf1..000000000000
--- a/arch/mips/include/asm/mach-pb1x00/pb1550.h
+++ /dev/null
@@ -1,73 +0,0 @@
1/*
2 * AMD Alchemy Semi PB1550 Reference Board
3 * Board Registers defines.
4 *
5 * Copyright 2004 Embedded Edge LLC.
6 * Copyright 2005 Ralf Baechle (ralf@linux-mips.org)
7 *
8 * ########################################################################
9 *
10 * This program is free software; you can distribute it and/or modify it
11 * under the terms of the GNU General Public License (Version 2) as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 * for more details.
18 *
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, write to the Free Software Foundation, Inc.,
21 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
22 *
23 * ########################################################################
24 *
25 *
26 */
27#ifndef __ASM_PB1550_H
28#define __ASM_PB1550_H
29
30#include <linux/types.h>
31#include <asm/mach-au1x00/au1xxx_psc.h>
32
33#define DBDMA_AC97_TX_CHAN AU1550_DSCR_CMD0_PSC1_TX
34#define DBDMA_AC97_RX_CHAN AU1550_DSCR_CMD0_PSC1_RX
35#define DBDMA_I2S_TX_CHAN AU1550_DSCR_CMD0_PSC3_TX
36#define DBDMA_I2S_RX_CHAN AU1550_DSCR_CMD0_PSC3_RX
37
38#define SPI_PSC_BASE AU1550_PSC0_PHYS_ADDR
39#define AC97_PSC_BASE AU1550_PSC1_PHYS_ADDR
40#define SMBUS_PSC_BASE AU1550_PSC2_PHYS_ADDR
41#define I2S_PSC_BASE AU1550_PSC3_PHYS_ADDR
42
43/*
44 * Timing values as described in databook, * ns value stripped of
45 * lower 2 bits.
46 * These defines are here rather than an SOC1550 generic file because
47 * the parts chosen on another board may be different and may require
48 * different timings.
49 */
50#define NAND_T_H (18 >> 2)
51#define NAND_T_PUL (30 >> 2)
52#define NAND_T_SU (30 >> 2)
53#define NAND_T_WH (30 >> 2)
54
55/* Bitfield shift amounts */
56#define NAND_T_H_SHIFT 0
57#define NAND_T_PUL_SHIFT 4
58#define NAND_T_SU_SHIFT 8
59#define NAND_T_WH_SHIFT 12
60
61#define NAND_TIMING (((NAND_T_H & 0xF) << NAND_T_H_SHIFT) | \
62 ((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \
63 ((NAND_T_SU & 0xF) << NAND_T_SU_SHIFT) | \
64 ((NAND_T_WH & 0xF) << NAND_T_WH_SHIFT))
65
66#define NAND_CS 1
67
68/* Should be done by YAMON */
69#define NAND_STCFG 0x00400005 /* 8-bit NAND */
70#define NAND_STTIME 0x00007774 /* valid for 396 MHz SD=2 only */
71#define NAND_STADDR 0x12000FFF /* physical address 0x20000000 */
72
73#endif /* __ASM_PB1550_H */
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 2ea7b817feb8..7f87d824eeb0 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -1106,7 +1106,7 @@ do { \
1106#define read_c0_brcm_reset() __read_32bit_c0_register($22, 5) 1106#define read_c0_brcm_reset() __read_32bit_c0_register($22, 5)
1107#define write_c0_brcm_reset(val) __write_32bit_c0_register($22, 5, val) 1107#define write_c0_brcm_reset(val) __write_32bit_c0_register($22, 5, val)
1108 1108
1109/* BMIPS4380 */ 1109/* BMIPS43xx */
1110#define read_c0_brcm_cmt_intr() __read_32bit_c0_register($22, 1) 1110#define read_c0_brcm_cmt_intr() __read_32bit_c0_register($22, 1)
1111#define write_c0_brcm_cmt_intr(val) __write_32bit_c0_register($22, 1, val) 1111#define write_c0_brcm_cmt_intr(val) __write_32bit_c0_register($22, 1, val)
1112 1112
@@ -1667,6 +1667,13 @@ __BUILD_SET_C0(config)
1667__BUILD_SET_C0(intcontrol) 1667__BUILD_SET_C0(intcontrol)
1668__BUILD_SET_C0(intctl) 1668__BUILD_SET_C0(intctl)
1669__BUILD_SET_C0(srsmap) 1669__BUILD_SET_C0(srsmap)
1670__BUILD_SET_C0(brcm_config_0)
1671__BUILD_SET_C0(brcm_bus_pll)
1672__BUILD_SET_C0(brcm_reset)
1673__BUILD_SET_C0(brcm_cmt_intr)
1674__BUILD_SET_C0(brcm_cmt_ctrl)
1675__BUILD_SET_C0(brcm_config)
1676__BUILD_SET_C0(brcm_mode)
1670 1677
1671#endif /* !__ASSEMBLY__ */ 1678#endif /* !__ASSEMBLY__ */
1672 1679
diff --git a/arch/mips/include/asm/module.h b/arch/mips/include/asm/module.h
index bc01a02cacd8..7467d1d933d5 100644
--- a/arch/mips/include/asm/module.h
+++ b/arch/mips/include/asm/module.h
@@ -74,7 +74,9 @@ search_module_dbetables(unsigned long addr)
74} 74}
75#endif 75#endif
76 76
77#ifdef CONFIG_CPU_MIPS32_R1 77#ifdef CONFIG_CPU_BMIPS
78#define MODULE_PROC_FAMILY "BMIPS "
79#elif defined CONFIG_CPU_MIPS32_R1
78#define MODULE_PROC_FAMILY "MIPS32_R1 " 80#define MODULE_PROC_FAMILY "MIPS32_R1 "
79#elif defined CONFIG_CPU_MIPS32_R2 81#elif defined CONFIG_CPU_MIPS32_R2
80#define MODULE_PROC_FAMILY "MIPS32_R2 " 82#define MODULE_PROC_FAMILY "MIPS32_R2 "
@@ -120,6 +122,8 @@ search_module_dbetables(unsigned long addr)
120#define MODULE_PROC_FAMILY "OCTEON " 122#define MODULE_PROC_FAMILY "OCTEON "
121#elif defined CONFIG_CPU_XLR 123#elif defined CONFIG_CPU_XLR
122#define MODULE_PROC_FAMILY "XLR " 124#define MODULE_PROC_FAMILY "XLR "
125#elif defined CONFIG_CPU_XLP
126#define MODULE_PROC_FAMILY "XLP "
123#else 127#else
124#error MODULE_PROC_FAMILY undefined for your processor configuration 128#error MODULE_PROC_FAMILY undefined for your processor configuration
125#endif 129#endif
diff --git a/arch/mips/include/asm/netlogic/common.h b/arch/mips/include/asm/netlogic/common.h
new file mode 100644
index 000000000000..fdd2f44c7b59
--- /dev/null
+++ b/arch/mips/include/asm/netlogic/common.h
@@ -0,0 +1,76 @@
1/*
2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
3 * reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#ifndef _NETLOGIC_COMMON_H_
36#define _NETLOGIC_COMMON_H_
37
38/*
39 * Common SMP definitions
40 */
41#define RESET_VEC_PHYS 0x1fc00000
42#define RESET_DATA_PHYS (RESET_VEC_PHYS + (1<<10))
43#define BOOT_THREAD_MODE 0
44#define BOOT_NMI_LOCK 4
45#define BOOT_NMI_HANDLER 8
46
47#ifndef __ASSEMBLY__
48struct irq_desc;
49extern struct plat_smp_ops nlm_smp_ops;
50extern char nlm_reset_entry[], nlm_reset_entry_end[];
51void nlm_smp_function_ipi_handler(unsigned int irq, struct irq_desc *desc);
52void nlm_smp_resched_ipi_handler(unsigned int irq, struct irq_desc *desc);
53void nlm_smp_irq_init(void);
54void nlm_boot_secondary_cpus(void);
55int nlm_wakeup_secondary_cpus(u32 wakeup_mask);
56void nlm_rmiboot_preboot(void);
57
58static inline void
59nlm_set_nmi_handler(void *handler)
60{
61 char *reset_data;
62
63 reset_data = (char *)CKSEG1ADDR(RESET_DATA_PHYS);
64 *(int64_t *)(reset_data + BOOT_NMI_HANDLER) = (long)handler;
65}
66
67/*
68 * Misc.
69 */
70unsigned int nlm_get_cpu_frequency(void);
71
72extern unsigned long nlm_common_ebase;
73extern int nlm_threads_per_core;
74extern uint32_t nlm_cpumask, nlm_coremask;
75#endif
76#endif /* _NETLOGIC_COMMON_H_ */
diff --git a/arch/mips/include/asm/netlogic/haldefs.h b/arch/mips/include/asm/netlogic/haldefs.h
new file mode 100644
index 000000000000..72a0c788b472
--- /dev/null
+++ b/arch/mips/include/asm/netlogic/haldefs.h
@@ -0,0 +1,163 @@
1/*
2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
3 * reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#ifndef __NLM_HAL_HALDEFS_H__
36#define __NLM_HAL_HALDEFS_H__
37
38/*
39 * This file contains platform specific memory mapped IO implementation
40 * and will provide a way to read 32/64 bit memory mapped registers in
41 * all ABIs
42 */
43#if !defined(CONFIG_64BIT) && defined(CONFIG_CPU_XLP)
44#error "o32 compile not supported on XLP yet"
45#endif
46/*
47 * For o32 compilation, we have to disable interrupts and enable KX bit to
48 * access 64 bit addresses or data.
49 *
50 * We need to disable interrupts because we save just the lower 32 bits of
51 * registers in interrupt handling. So if we get hit by an interrupt while
52 * using the upper 32 bits of a register, we lose.
53 */
54static inline uint32_t nlm_save_flags_kx(void)
55{
56 return change_c0_status(ST0_KX | ST0_IE, ST0_KX);
57}
58
59static inline uint32_t nlm_save_flags_cop2(void)
60{
61 return change_c0_status(ST0_CU2 | ST0_IE, ST0_CU2);
62}
63
64static inline void nlm_restore_flags(uint32_t sr)
65{
66 write_c0_status(sr);
67}
68
69/*
70 * The n64 implementations are simple, the o32 implementations when they
71 * are added, will have to disable interrupts and enable KX before doing
72 * 64 bit ops.
73 */
74static inline uint32_t
75nlm_read_reg(uint64_t base, uint32_t reg)
76{
77 volatile uint32_t *addr = (volatile uint32_t *)(long)base + reg;
78
79 return *addr;
80}
81
82static inline void
83nlm_write_reg(uint64_t base, uint32_t reg, uint32_t val)
84{
85 volatile uint32_t *addr = (volatile uint32_t *)(long)base + reg;
86
87 *addr = val;
88}
89
90static inline uint64_t
91nlm_read_reg64(uint64_t base, uint32_t reg)
92{
93 uint64_t addr = base + (reg >> 1) * sizeof(uint64_t);
94 volatile uint64_t *ptr = (volatile uint64_t *)(long)addr;
95
96 return *ptr;
97}
98
99static inline void
100nlm_write_reg64(uint64_t base, uint32_t reg, uint64_t val)
101{
102 uint64_t addr = base + (reg >> 1) * sizeof(uint64_t);
103 volatile uint64_t *ptr = (volatile uint64_t *)(long)addr;
104
105 *ptr = val;
106}
107
108/*
109 * Routines to store 32/64 bit values to 64 bit addresses,
110 * used when going thru XKPHYS to access registers
111 */
112static inline uint32_t
113nlm_read_reg_xkphys(uint64_t base, uint32_t reg)
114{
115 return nlm_read_reg(base, reg);
116}
117
118static inline void
119nlm_write_reg_xkphys(uint64_t base, uint32_t reg, uint32_t val)
120{
121 nlm_write_reg(base, reg, val);
122}
123
124static inline uint64_t
125nlm_read_reg64_xkphys(uint64_t base, uint32_t reg)
126{
127 return nlm_read_reg64(base, reg);
128}
129
130static inline void
131nlm_write_reg64_xkphys(uint64_t base, uint32_t reg, uint64_t val)
132{
133 nlm_write_reg64(base, reg, val);
134}
135
136/* Location where IO base is mapped */
137extern uint64_t nlm_io_base;
138
139#if defined(CONFIG_CPU_XLP)
140static inline uint64_t
141nlm_pcicfg_base(uint32_t devoffset)
142{
143 return nlm_io_base + devoffset;
144}
145
146static inline uint64_t
147nlm_xkphys_map_pcibar0(uint64_t pcibase)
148{
149 uint64_t paddr;
150
151 paddr = nlm_read_reg(pcibase, 0x4) & ~0xfu;
152 return (uint64_t)0x9000000000000000 | paddr;
153}
154#elif defined(CONFIG_CPU_XLR)
155
156static inline uint64_t
157nlm_mmio_base(uint32_t devoffset)
158{
159 return nlm_io_base + devoffset;
160}
161#endif
162
163#endif
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/bridge.h b/arch/mips/include/asm/netlogic/xlp-hal/bridge.h
new file mode 100644
index 000000000000..ca95133f1ad1
--- /dev/null
+++ b/arch/mips/include/asm/netlogic/xlp-hal/bridge.h
@@ -0,0 +1,187 @@
1/*
2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
3 * reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#ifndef __NLM_HAL_BRIDGE_H__
36#define __NLM_HAL_BRIDGE_H__
37
38/**
39* @file_name mio.h
40* @author Netlogic Microsystems
41* @brief Basic definitions of XLP memory and io subsystem
42*/
43
44/*
45 * BRIDGE specific registers
46 *
47 * These registers start after the PCIe header, which has 0x40
48 * standard entries
49 */
50#define BRIDGE_MODE 0x00
51#define BRIDGE_PCI_CFG_BASE 0x01
52#define BRIDGE_PCI_CFG_LIMIT 0x02
53#define BRIDGE_PCIE_CFG_BASE 0x03
54#define BRIDGE_PCIE_CFG_LIMIT 0x04
55#define BRIDGE_BUSNUM_BAR0 0x05
56#define BRIDGE_BUSNUM_BAR1 0x06
57#define BRIDGE_BUSNUM_BAR2 0x07
58#define BRIDGE_BUSNUM_BAR3 0x08
59#define BRIDGE_BUSNUM_BAR4 0x09
60#define BRIDGE_BUSNUM_BAR5 0x0a
61#define BRIDGE_BUSNUM_BAR6 0x0b
62#define BRIDGE_FLASH_BAR0 0x0c
63#define BRIDGE_FLASH_BAR1 0x0d
64#define BRIDGE_FLASH_BAR2 0x0e
65#define BRIDGE_FLASH_BAR3 0x0f
66#define BRIDGE_FLASH_LIMIT0 0x10
67#define BRIDGE_FLASH_LIMIT1 0x11
68#define BRIDGE_FLASH_LIMIT2 0x12
69#define BRIDGE_FLASH_LIMIT3 0x13
70
71#define BRIDGE_DRAM_BAR(i) (0x14 + (i))
72#define BRIDGE_DRAM_BAR0 0x14
73#define BRIDGE_DRAM_BAR1 0x15
74#define BRIDGE_DRAM_BAR2 0x16
75#define BRIDGE_DRAM_BAR3 0x17
76#define BRIDGE_DRAM_BAR4 0x18
77#define BRIDGE_DRAM_BAR5 0x19
78#define BRIDGE_DRAM_BAR6 0x1a
79#define BRIDGE_DRAM_BAR7 0x1b
80
81#define BRIDGE_DRAM_LIMIT(i) (0x1c + (i))
82#define BRIDGE_DRAM_LIMIT0 0x1c
83#define BRIDGE_DRAM_LIMIT1 0x1d
84#define BRIDGE_DRAM_LIMIT2 0x1e
85#define BRIDGE_DRAM_LIMIT3 0x1f
86#define BRIDGE_DRAM_LIMIT4 0x20
87#define BRIDGE_DRAM_LIMIT5 0x21
88#define BRIDGE_DRAM_LIMIT6 0x22
89#define BRIDGE_DRAM_LIMIT7 0x23
90
91#define BRIDGE_DRAM_NODE_TRANSLN0 0x24
92#define BRIDGE_DRAM_NODE_TRANSLN1 0x25
93#define BRIDGE_DRAM_NODE_TRANSLN2 0x26
94#define BRIDGE_DRAM_NODE_TRANSLN3 0x27
95#define BRIDGE_DRAM_NODE_TRANSLN4 0x28
96#define BRIDGE_DRAM_NODE_TRANSLN5 0x29
97#define BRIDGE_DRAM_NODE_TRANSLN6 0x2a
98#define BRIDGE_DRAM_NODE_TRANSLN7 0x2b
99#define BRIDGE_DRAM_CHNL_TRANSLN0 0x2c
100#define BRIDGE_DRAM_CHNL_TRANSLN1 0x2d
101#define BRIDGE_DRAM_CHNL_TRANSLN2 0x2e
102#define BRIDGE_DRAM_CHNL_TRANSLN3 0x2f
103#define BRIDGE_DRAM_CHNL_TRANSLN4 0x30
104#define BRIDGE_DRAM_CHNL_TRANSLN5 0x31
105#define BRIDGE_DRAM_CHNL_TRANSLN6 0x32
106#define BRIDGE_DRAM_CHNL_TRANSLN7 0x33
107#define BRIDGE_PCIEMEM_BASE0 0x34
108#define BRIDGE_PCIEMEM_BASE1 0x35
109#define BRIDGE_PCIEMEM_BASE2 0x36
110#define BRIDGE_PCIEMEM_BASE3 0x37
111#define BRIDGE_PCIEMEM_LIMIT0 0x38
112#define BRIDGE_PCIEMEM_LIMIT1 0x39
113#define BRIDGE_PCIEMEM_LIMIT2 0x3a
114#define BRIDGE_PCIEMEM_LIMIT3 0x3b
115#define BRIDGE_PCIEIO_BASE0 0x3c
116#define BRIDGE_PCIEIO_BASE1 0x3d
117#define BRIDGE_PCIEIO_BASE2 0x3e
118#define BRIDGE_PCIEIO_BASE3 0x3f
119#define BRIDGE_PCIEIO_LIMIT0 0x40
120#define BRIDGE_PCIEIO_LIMIT1 0x41
121#define BRIDGE_PCIEIO_LIMIT2 0x42
122#define BRIDGE_PCIEIO_LIMIT3 0x43
123#define BRIDGE_PCIEMEM_BASE4 0x44
124#define BRIDGE_PCIEMEM_BASE5 0x45
125#define BRIDGE_PCIEMEM_BASE6 0x46
126#define BRIDGE_PCIEMEM_LIMIT4 0x47
127#define BRIDGE_PCIEMEM_LIMIT5 0x48
128#define BRIDGE_PCIEMEM_LIMIT6 0x49
129#define BRIDGE_PCIEIO_BASE4 0x4a
130#define BRIDGE_PCIEIO_BASE5 0x4b
131#define BRIDGE_PCIEIO_BASE6 0x4c
132#define BRIDGE_PCIEIO_LIMIT4 0x4d
133#define BRIDGE_PCIEIO_LIMIT5 0x4e
134#define BRIDGE_PCIEIO_LIMIT6 0x4f
135#define BRIDGE_NBU_EVENT_CNT_CTL 0x50
136#define BRIDGE_EVNTCTR1_LOW 0x51
137#define BRIDGE_EVNTCTR1_HI 0x52
138#define BRIDGE_EVNT_CNT_CTL2 0x53
139#define BRIDGE_EVNTCTR2_LOW 0x54
140#define BRIDGE_EVNTCTR2_HI 0x55
141#define BRIDGE_TRACEBUF_MATCH0 0x56
142#define BRIDGE_TRACEBUF_MATCH1 0x57
143#define BRIDGE_TRACEBUF_MATCH_LOW 0x58
144#define BRIDGE_TRACEBUF_MATCH_HI 0x59
145#define BRIDGE_TRACEBUF_CTRL 0x5a
146#define BRIDGE_TRACEBUF_INIT 0x5b
147#define BRIDGE_TRACEBUF_ACCESS 0x5c
148#define BRIDGE_TRACEBUF_READ_DATA0 0x5d
149#define BRIDGE_TRACEBUF_READ_DATA1 0x5d
150#define BRIDGE_TRACEBUF_READ_DATA2 0x5f
151#define BRIDGE_TRACEBUF_READ_DATA3 0x60
152#define BRIDGE_TRACEBUF_STATUS 0x61
153#define BRIDGE_ADDRESS_ERROR0 0x62
154#define BRIDGE_ADDRESS_ERROR1 0x63
155#define BRIDGE_ADDRESS_ERROR2 0x64
156#define BRIDGE_TAG_ECC_ADDR_ERROR0 0x65
157#define BRIDGE_TAG_ECC_ADDR_ERROR1 0x66
158#define BRIDGE_TAG_ECC_ADDR_ERROR2 0x67
159#define BRIDGE_LINE_FLUSH0 0x68
160#define BRIDGE_LINE_FLUSH1 0x69
161#define BRIDGE_NODE_ID 0x6a
162#define BRIDGE_ERROR_INTERRUPT_EN 0x6b
163#define BRIDGE_PCIE0_WEIGHT 0x2c0
164#define BRIDGE_PCIE1_WEIGHT 0x2c1
165#define BRIDGE_PCIE2_WEIGHT 0x2c2
166#define BRIDGE_PCIE3_WEIGHT 0x2c3
167#define BRIDGE_USB_WEIGHT 0x2c4
168#define BRIDGE_NET_WEIGHT 0x2c5
169#define BRIDGE_POE_WEIGHT 0x2c6
170#define BRIDGE_CMS_WEIGHT 0x2c7
171#define BRIDGE_DMAENG_WEIGHT 0x2c8
172#define BRIDGE_SEC_WEIGHT 0x2c9
173#define BRIDGE_COMP_WEIGHT 0x2ca
174#define BRIDGE_GIO_WEIGHT 0x2cb
175#define BRIDGE_FLASH_WEIGHT 0x2cc
176
177#ifndef __ASSEMBLY__
178
179#define nlm_read_bridge_reg(b, r) nlm_read_reg(b, r)
180#define nlm_write_bridge_reg(b, r, v) nlm_write_reg(b, r, v)
181#define nlm_get_bridge_pcibase(node) \
182 nlm_pcicfg_base(XLP_IO_BRIDGE_OFFSET(node))
183#define nlm_get_bridge_regbase(node) \
184 (nlm_get_bridge_pcibase(node) + XLP_IO_PCI_HDRSZ)
185
186#endif /* __ASSEMBLY__ */
187#endif /* __NLM_HAL_BRIDGE_H__ */
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h b/arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h
new file mode 100644
index 000000000000..bf7d41deb9be
--- /dev/null
+++ b/arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h
@@ -0,0 +1,83 @@
1/*
2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
3 * reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#ifndef __NLM_HAL_CPUCONTROL_H__
36#define __NLM_HAL_CPUCONTROL_H__
37
38#define CPU_BLOCKID_IFU 0
39#define CPU_BLOCKID_ICU 1
40#define CPU_BLOCKID_IEU 2
41#define CPU_BLOCKID_LSU 3
42#define CPU_BLOCKID_MMU 4
43#define CPU_BLOCKID_PRF 5
44#define CPU_BLOCKID_SCH 7
45#define CPU_BLOCKID_SCU 8
46#define CPU_BLOCKID_FPU 9
47#define CPU_BLOCKID_MAP 10
48
49#define LSU_DEFEATURE 0x304
50#define LSU_CERRLOG_REGID 0x09
51#define SCHED_DEFEATURE 0x700
52
53/* Offsets of interest from the 'MAP' Block */
54#define MAP_THREADMODE 0x00
55#define MAP_EXT_EBASE_ENABLE 0x04
56#define MAP_CCDI_CONFIG 0x08
57#define MAP_THRD0_CCDI_STATUS 0x0c
58#define MAP_THRD1_CCDI_STATUS 0x10
59#define MAP_THRD2_CCDI_STATUS 0x14
60#define MAP_THRD3_CCDI_STATUS 0x18
61#define MAP_THRD0_DEBUG_MODE 0x1c
62#define MAP_THRD1_DEBUG_MODE 0x20
63#define MAP_THRD2_DEBUG_MODE 0x24
64#define MAP_THRD3_DEBUG_MODE 0x28
65#define MAP_MISC_STATE 0x60
66#define MAP_DEBUG_READ_CTL 0x64
67#define MAP_DEBUG_READ_REG0 0x68
68#define MAP_DEBUG_READ_REG1 0x6c
69
70#define MMU_SETUP 0x400
71#define MMU_LFSRSEED 0x401
72#define MMU_HPW_NUM_PAGE_LVL 0x410
73#define MMU_PGWKR_PGDBASE 0x411
74#define MMU_PGWKR_PGDSHFT 0x412
75#define MMU_PGWKR_PGDMASK 0x413
76#define MMU_PGWKR_PUDSHFT 0x414
77#define MMU_PGWKR_PUDMASK 0x415
78#define MMU_PGWKR_PMDSHFT 0x416
79#define MMU_PGWKR_PMDMASK 0x417
80#define MMU_PGWKR_PTESHFT 0x418
81#define MMU_PGWKR_PTEMASK 0x419
82
83#endif /* __NLM_CPUCONTROL_H__ */
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/iomap.h b/arch/mips/include/asm/netlogic/xlp-hal/iomap.h
new file mode 100644
index 000000000000..86cc3391e50c
--- /dev/null
+++ b/arch/mips/include/asm/netlogic/xlp-hal/iomap.h
@@ -0,0 +1,153 @@
1/*
2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
3 * reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#ifndef __NLM_HAL_IOMAP_H__
36#define __NLM_HAL_IOMAP_H__
37
38#define XLP_DEFAULT_IO_BASE 0x18000000
39#define NMI_BASE 0xbfc00000
40#define XLP_IO_CLK 133333333
41
42#define XLP_PCIE_CFG_SIZE 0x1000 /* 4K */
43#define XLP_PCIE_DEV_BLK_SIZE (8 * XLP_PCIE_CFG_SIZE)
44#define XLP_PCIE_BUS_BLK_SIZE (256 * XLP_PCIE_DEV_BLK_SIZE)
45#define XLP_IO_SIZE (64 << 20) /* ECFG space size */
46#define XLP_IO_PCI_HDRSZ 0x100
47#define XLP_IO_DEV(node, dev) ((dev) + (node) * 8)
48#define XLP_HDR_OFFSET(node, bus, dev, fn) (((bus) << 20) | \
49 ((XLP_IO_DEV(node, dev)) << 15) | ((fn) << 12))
50
51#define XLP_IO_BRIDGE_OFFSET(node) XLP_HDR_OFFSET(node, 0, 0, 0)
52/* coherent inter chip */
53#define XLP_IO_CIC0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 0, 1)
54#define XLP_IO_CIC1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 0, 2)
55#define XLP_IO_CIC2_OFFSET(node) XLP_HDR_OFFSET(node, 0, 0, 3)
56#define XLP_IO_PIC_OFFSET(node) XLP_HDR_OFFSET(node, 0, 0, 4)
57
58#define XLP_IO_PCIE_OFFSET(node, i) XLP_HDR_OFFSET(node, 0, 1, i)
59#define XLP_IO_PCIE0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 1, 0)
60#define XLP_IO_PCIE1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 1, 1)
61#define XLP_IO_PCIE2_OFFSET(node) XLP_HDR_OFFSET(node, 0, 1, 2)
62#define XLP_IO_PCIE3_OFFSET(node) XLP_HDR_OFFSET(node, 0, 1, 3)
63
64#define XLP_IO_USB_OFFSET(node, i) XLP_HDR_OFFSET(node, 0, 2, i)
65#define XLP_IO_USB_EHCI0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 0)
66#define XLP_IO_USB_OHCI0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 1)
67#define XLP_IO_USB_OHCI1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 2)
68#define XLP_IO_USB_EHCI1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 3)
69#define XLP_IO_USB_OHCI2_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 4)
70#define XLP_IO_USB_OHCI3_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 5)
71
72#define XLP_IO_NAE_OFFSET(node) XLP_HDR_OFFSET(node, 0, 3, 0)
73#define XLP_IO_POE_OFFSET(node) XLP_HDR_OFFSET(node, 0, 3, 1)
74
75#define XLP_IO_CMS_OFFSET(node) XLP_HDR_OFFSET(node, 0, 4, 0)
76
77#define XLP_IO_DMA_OFFSET(node) XLP_HDR_OFFSET(node, 0, 5, 1)
78#define XLP_IO_SEC_OFFSET(node) XLP_HDR_OFFSET(node, 0, 5, 2)
79#define XLP_IO_CMP_OFFSET(node) XLP_HDR_OFFSET(node, 0, 5, 3)
80
81#define XLP_IO_UART_OFFSET(node, i) XLP_HDR_OFFSET(node, 0, 6, i)
82#define XLP_IO_UART0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 0)
83#define XLP_IO_UART1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 1)
84#define XLP_IO_I2C_OFFSET(node, i) XLP_HDR_OFFSET(node, 0, 6, 2 + i)
85#define XLP_IO_I2C0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 2)
86#define XLP_IO_I2C1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 3)
87#define XLP_IO_GPIO_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 4)
88/* system management */
89#define XLP_IO_SYS_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 5)
90#define XLP_IO_JTAG_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 6)
91
92#define XLP_IO_NOR_OFFSET(node) XLP_HDR_OFFSET(node, 0, 7, 0)
93#define XLP_IO_NAND_OFFSET(node) XLP_HDR_OFFSET(node, 0, 7, 1)
94#define XLP_IO_SPI_OFFSET(node) XLP_HDR_OFFSET(node, 0, 7, 2)
95/* SD flash */
96#define XLP_IO_SD_OFFSET(node) XLP_HDR_OFFSET(node, 0, 7, 3)
97#define XLP_IO_MMC_OFFSET(node, slot) \
98 ((XLP_IO_SD_OFFSET(node))+(slot*0x100)+XLP_IO_PCI_HDRSZ)
99
100/* PCI config header register id's */
101#define XLP_PCI_CFGREG0 0x00
102#define XLP_PCI_CFGREG1 0x01
103#define XLP_PCI_CFGREG2 0x02
104#define XLP_PCI_CFGREG3 0x03
105#define XLP_PCI_CFGREG4 0x04
106#define XLP_PCI_CFGREG5 0x05
107#define XLP_PCI_DEVINFO_REG0 0x30
108#define XLP_PCI_DEVINFO_REG1 0x31
109#define XLP_PCI_DEVINFO_REG2 0x32
110#define XLP_PCI_DEVINFO_REG3 0x33
111#define XLP_PCI_DEVINFO_REG4 0x34
112#define XLP_PCI_DEVINFO_REG5 0x35
113#define XLP_PCI_DEVINFO_REG6 0x36
114#define XLP_PCI_DEVINFO_REG7 0x37
115#define XLP_PCI_DEVSCRATCH_REG0 0x38
116#define XLP_PCI_DEVSCRATCH_REG1 0x39
117#define XLP_PCI_DEVSCRATCH_REG2 0x3a
118#define XLP_PCI_DEVSCRATCH_REG3 0x3b
119#define XLP_PCI_MSGSTN_REG 0x3c
120#define XLP_PCI_IRTINFO_REG 0x3d
121#define XLP_PCI_UCODEINFO_REG 0x3e
122#define XLP_PCI_SBB_WT_REG 0x3f
123
124/* PCI IDs for SoC device */
125#define PCI_VENDOR_NETLOGIC 0x184e
126
127#define PCI_DEVICE_ID_NLM_ROOT 0x1001
128#define PCI_DEVICE_ID_NLM_ICI 0x1002
129#define PCI_DEVICE_ID_NLM_PIC 0x1003
130#define PCI_DEVICE_ID_NLM_PCIE 0x1004
131#define PCI_DEVICE_ID_NLM_EHCI 0x1007
132#define PCI_DEVICE_ID_NLM_ILK 0x1008
133#define PCI_DEVICE_ID_NLM_NAE 0x1009
134#define PCI_DEVICE_ID_NLM_POE 0x100A
135#define PCI_DEVICE_ID_NLM_FMN 0x100B
136#define PCI_DEVICE_ID_NLM_RAID 0x100D
137#define PCI_DEVICE_ID_NLM_SAE 0x100D
138#define PCI_DEVICE_ID_NLM_RSA 0x100E
139#define PCI_DEVICE_ID_NLM_CMP 0x100F
140#define PCI_DEVICE_ID_NLM_UART 0x1010
141#define PCI_DEVICE_ID_NLM_I2C 0x1011
142#define PCI_DEVICE_ID_NLM_NOR 0x1015
143#define PCI_DEVICE_ID_NLM_NAND 0x1016
144#define PCI_DEVICE_ID_NLM_MMC 0x1018
145
146#ifndef __ASSEMBLY__
147
148#define nlm_read_pci_reg(b, r) nlm_read_reg(b, r)
149#define nlm_write_pci_reg(b, r, v) nlm_write_reg(b, r, v)
150
151#endif /* !__ASSEMBLY */
152
153#endif /* __NLM_HAL_IOMAP_H__ */
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/pic.h b/arch/mips/include/asm/netlogic/xlp-hal/pic.h
new file mode 100644
index 000000000000..b6628f7ccf74
--- /dev/null
+++ b/arch/mips/include/asm/netlogic/xlp-hal/pic.h
@@ -0,0 +1,411 @@
1/*
2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
3 * reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#ifndef _NLM_HAL_PIC_H
36#define _NLM_HAL_PIC_H
37
38/* PIC Specific registers */
39#define PIC_CTRL 0x00
40
41/* PIC control register defines */
42#define PIC_CTRL_ITV 32 /* interrupt timeout value */
43#define PIC_CTRL_ICI 19 /* ICI interrupt timeout enable */
44#define PIC_CTRL_ITE 18 /* interrupt timeout enable */
45#define PIC_CTRL_STE 10 /* system timer interrupt enable */
46#define PIC_CTRL_WWR1 8 /* watchdog 1 wraparound count for reset */
47#define PIC_CTRL_WWR0 6 /* watchdog 0 wraparound count for reset */
48#define PIC_CTRL_WWN1 4 /* watchdog 1 wraparound count for NMI */
49#define PIC_CTRL_WWN0 2 /* watchdog 0 wraparound count for NMI */
50#define PIC_CTRL_WTE 0 /* watchdog timer enable */
51
52/* PIC Status register defines */
53#define PIC_ICI_STATUS 33 /* ICI interrupt timeout status */
54#define PIC_ITE_STATUS 32 /* interrupt timeout status */
55#define PIC_STS_STATUS 4 /* System timer interrupt status */
56#define PIC_WNS_STATUS 2 /* NMI status for watchdog timers */
57#define PIC_WIS_STATUS 0 /* Interrupt status for watchdog timers */
58
59/* PIC IPI control register offsets */
60#define PIC_IPICTRL_NMI 32
61#define PIC_IPICTRL_RIV 20 /* received interrupt vector */
62#define PIC_IPICTRL_IDB 16 /* interrupt destination base */
63#define PIC_IPICTRL_DTE 0 /* interrupt destination thread enables */
64
65/* PIC IRT register offsets */
66#define PIC_IRT_ENABLE 31
67#define PIC_IRT_NMI 29
68#define PIC_IRT_SCH 28 /* Scheduling scheme */
69#define PIC_IRT_RVEC 20 /* Interrupt receive vectors */
70#define PIC_IRT_DT 19 /* Destination type */
71#define PIC_IRT_DB 16 /* Destination base */
72#define PIC_IRT_DTE 0 /* Destination thread enables */
73
74#define PIC_BYTESWAP 0x02
75#define PIC_STATUS 0x04
76#define PIC_INTR_TIMEOUT 0x06
77#define PIC_ICI0_INTR_TIMEOUT 0x08
78#define PIC_ICI1_INTR_TIMEOUT 0x0a
79#define PIC_ICI2_INTR_TIMEOUT 0x0c
80#define PIC_IPI_CTL 0x0e
81#define PIC_INT_ACK 0x10
82#define PIC_INT_PENDING0 0x12
83#define PIC_INT_PENDING1 0x14
84#define PIC_INT_PENDING2 0x16
85
86#define PIC_WDOG0_MAXVAL 0x18
87#define PIC_WDOG0_COUNT 0x1a
88#define PIC_WDOG0_ENABLE0 0x1c
89#define PIC_WDOG0_ENABLE1 0x1e
90#define PIC_WDOG0_BEATCMD 0x20
91#define PIC_WDOG0_BEAT0 0x22
92#define PIC_WDOG0_BEAT1 0x24
93
94#define PIC_WDOG1_MAXVAL 0x26
95#define PIC_WDOG1_COUNT 0x28
96#define PIC_WDOG1_ENABLE0 0x2a
97#define PIC_WDOG1_ENABLE1 0x2c
98#define PIC_WDOG1_BEATCMD 0x2e
99#define PIC_WDOG1_BEAT0 0x30
100#define PIC_WDOG1_BEAT1 0x32
101
102#define PIC_WDOG_MAXVAL(i) (PIC_WDOG0_MAXVAL + ((i) ? 7 : 0))
103#define PIC_WDOG_COUNT(i) (PIC_WDOG0_COUNT + ((i) ? 7 : 0))
104#define PIC_WDOG_ENABLE0(i) (PIC_WDOG0_ENABLE0 + ((i) ? 7 : 0))
105#define PIC_WDOG_ENABLE1(i) (PIC_WDOG0_ENABLE1 + ((i) ? 7 : 0))
106#define PIC_WDOG_BEATCMD(i) (PIC_WDOG0_BEATCMD + ((i) ? 7 : 0))
107#define PIC_WDOG_BEAT0(i) (PIC_WDOG0_BEAT0 + ((i) ? 7 : 0))
108#define PIC_WDOG_BEAT1(i) (PIC_WDOG0_BEAT1 + ((i) ? 7 : 0))
109
110#define PIC_TIMER0_MAXVAL 0x34
111#define PIC_TIMER1_MAXVAL 0x36
112#define PIC_TIMER2_MAXVAL 0x38
113#define PIC_TIMER3_MAXVAL 0x3a
114#define PIC_TIMER4_MAXVAL 0x3c
115#define PIC_TIMER5_MAXVAL 0x3e
116#define PIC_TIMER6_MAXVAL 0x40
117#define PIC_TIMER7_MAXVAL 0x42
118#define PIC_TIMER_MAXVAL(i) (PIC_TIMER0_MAXVAL + ((i) * 2))
119
120#define PIC_TIMER0_COUNT 0x44
121#define PIC_TIMER1_COUNT 0x46
122#define PIC_TIMER2_COUNT 0x48
123#define PIC_TIMER3_COUNT 0x4a
124#define PIC_TIMER4_COUNT 0x4c
125#define PIC_TIMER5_COUNT 0x4e
126#define PIC_TIMER6_COUNT 0x50
127#define PIC_TIMER7_COUNT 0x52
128#define PIC_TIMER_COUNT(i) (PIC_TIMER0_COUNT + ((i) * 2))
129
130#define PIC_ITE0_N0_N1 0x54
131#define PIC_ITE1_N0_N1 0x58
132#define PIC_ITE2_N0_N1 0x5c
133#define PIC_ITE3_N0_N1 0x60
134#define PIC_ITE4_N0_N1 0x64
135#define PIC_ITE5_N0_N1 0x68
136#define PIC_ITE6_N0_N1 0x6c
137#define PIC_ITE7_N0_N1 0x70
138#define PIC_ITE_N0_N1(i) (PIC_ITE0_N0_N1 + ((i) * 4))
139
140#define PIC_ITE0_N2_N3 0x56
141#define PIC_ITE1_N2_N3 0x5a
142#define PIC_ITE2_N2_N3 0x5e
143#define PIC_ITE3_N2_N3 0x62
144#define PIC_ITE4_N2_N3 0x66
145#define PIC_ITE5_N2_N3 0x6a
146#define PIC_ITE6_N2_N3 0x6e
147#define PIC_ITE7_N2_N3 0x72
148#define PIC_ITE_N2_N3(i) (PIC_ITE0_N2_N3 + ((i) * 4))
149
150#define PIC_IRT0 0x74
151#define PIC_IRT(i) (PIC_IRT0 + ((i) * 2))
152
153#define TIMER_CYCLES_MAXVAL 0xffffffffffffffffULL
154
155/*
156 * IRT Map
157 */
158#define PIC_NUM_IRTS 160
159
160#define PIC_IRT_WD_0_INDEX 0
161#define PIC_IRT_WD_1_INDEX 1
162#define PIC_IRT_WD_NMI_0_INDEX 2
163#define PIC_IRT_WD_NMI_1_INDEX 3
164#define PIC_IRT_TIMER_0_INDEX 4
165#define PIC_IRT_TIMER_1_INDEX 5
166#define PIC_IRT_TIMER_2_INDEX 6
167#define PIC_IRT_TIMER_3_INDEX 7
168#define PIC_IRT_TIMER_4_INDEX 8
169#define PIC_IRT_TIMER_5_INDEX 9
170#define PIC_IRT_TIMER_6_INDEX 10
171#define PIC_IRT_TIMER_7_INDEX 11
172#define PIC_IRT_CLOCK_INDEX PIC_IRT_TIMER_7_INDEX
173#define PIC_IRT_TIMER_INDEX(num) ((num) + PIC_IRT_TIMER_0_INDEX)
174
175
176/* 11 and 12 */
177#define PIC_NUM_MSG_Q_IRTS 32
178#define PIC_IRT_MSG_Q0_INDEX 12
179#define PIC_IRT_MSG_Q_INDEX(qid) ((qid) + PIC_IRT_MSG_Q0_INDEX)
180/* 12 to 43 */
181#define PIC_IRT_MSG_0_INDEX 44
182#define PIC_IRT_MSG_1_INDEX 45
183/* 44 and 45 */
184#define PIC_NUM_PCIE_MSIX_IRTS 32
185#define PIC_IRT_PCIE_MSIX_0_INDEX 46
186#define PIC_IRT_PCIE_MSIX_INDEX(num) ((num) + PIC_IRT_PCIE_MSIX_0_INDEX)
187/* 46 to 77 */
188#define PIC_NUM_PCIE_LINK_IRTS 4
189#define PIC_IRT_PCIE_LINK_0_INDEX 78
190#define PIC_IRT_PCIE_LINK_1_INDEX 79
191#define PIC_IRT_PCIE_LINK_2_INDEX 80
192#define PIC_IRT_PCIE_LINK_3_INDEX 81
193#define PIC_IRT_PCIE_LINK_INDEX(num) ((num) + PIC_IRT_PCIE_LINK_0_INDEX)
194/* 78 to 81 */
195#define PIC_NUM_NA_IRTS 32
196/* 82 to 113 */
197#define PIC_IRT_NA_0_INDEX 82
198#define PIC_IRT_NA_INDEX(num) ((num) + PIC_IRT_NA_0_INDEX)
199#define PIC_IRT_POE_INDEX 114
200
201#define PIC_NUM_USB_IRTS 6
202#define PIC_IRT_USB_0_INDEX 115
203#define PIC_IRT_EHCI_0_INDEX 115
204#define PIC_IRT_EHCI_1_INDEX 118
205#define PIC_IRT_USB_INDEX(num) ((num) + PIC_IRT_USB_0_INDEX)
206/* 115 to 120 */
207#define PIC_IRT_GDX_INDEX 121
208#define PIC_IRT_SEC_INDEX 122
209#define PIC_IRT_RSA_INDEX 123
210
211#define PIC_NUM_COMP_IRTS 4
212#define PIC_IRT_COMP_0_INDEX 124
213#define PIC_IRT_COMP_INDEX(num) ((num) + PIC_IRT_COMP_0_INDEX)
214/* 124 to 127 */
215#define PIC_IRT_GBU_INDEX 128
216#define PIC_IRT_ICC_0_INDEX 129 /* ICC - Inter Chip Coherency */
217#define PIC_IRT_ICC_1_INDEX 130
218#define PIC_IRT_ICC_2_INDEX 131
219#define PIC_IRT_CAM_INDEX 132
220#define PIC_IRT_UART_0_INDEX 133
221#define PIC_IRT_UART_1_INDEX 134
222#define PIC_IRT_I2C_0_INDEX 135
223#define PIC_IRT_I2C_1_INDEX 136
224#define PIC_IRT_SYS_0_INDEX 137
225#define PIC_IRT_SYS_1_INDEX 138
226#define PIC_IRT_JTAG_INDEX 139
227#define PIC_IRT_PIC_INDEX 140
228#define PIC_IRT_NBU_INDEX 141
229#define PIC_IRT_TCU_INDEX 142
230#define PIC_IRT_GCU_INDEX 143 /* GBC - Global Coherency */
231#define PIC_IRT_DMC_0_INDEX 144
232#define PIC_IRT_DMC_1_INDEX 145
233
234#define PIC_NUM_GPIO_IRTS 4
235#define PIC_IRT_GPIO_0_INDEX 146
236#define PIC_IRT_GPIO_INDEX(num) ((num) + PIC_IRT_GPIO_0_INDEX)
237
238/* 146 to 149 */
239#define PIC_IRT_NOR_INDEX 150
240#define PIC_IRT_NAND_INDEX 151
241#define PIC_IRT_SPI_INDEX 152
242#define PIC_IRT_MMC_INDEX 153
243
244#define PIC_CLOCK_TIMER 7
245#define PIC_IRQ_BASE 8
246
247#if !defined(LOCORE) && !defined(__ASSEMBLY__)
248
249#define PIC_IRT_FIRST_IRQ (PIC_IRQ_BASE)
250#define PIC_IRT_LAST_IRQ 63
251#define PIC_IRQ_IS_IRT(irq) ((irq) >= PIC_IRT_FIRST_IRQ)
252
253/*
254 * Misc
255 */
256#define PIC_IRT_VALID 1
257#define PIC_LOCAL_SCHEDULING 1
258#define PIC_GLOBAL_SCHEDULING 0
259
260#define nlm_read_pic_reg(b, r) nlm_read_reg64(b, r)
261#define nlm_write_pic_reg(b, r, v) nlm_write_reg64(b, r, v)
262#define nlm_get_pic_pcibase(node) nlm_pcicfg_base(XLP_IO_PIC_OFFSET(node))
263#define nlm_get_pic_regbase(node) (nlm_get_pic_pcibase(node) + XLP_IO_PCI_HDRSZ)
264
265/* IRT and h/w interrupt routines */
266static inline int
267nlm_pic_read_irt(uint64_t base, int irt_index)
268{
269 return nlm_read_pic_reg(base, PIC_IRT(irt_index));
270}
271
272static inline uint64_t
273nlm_pic_read_control(uint64_t base)
274{
275 return nlm_read_pic_reg(base, PIC_CTRL);
276}
277
278static inline void
279nlm_pic_write_control(uint64_t base, uint64_t control)
280{
281 nlm_write_pic_reg(base, PIC_CTRL, control);
282}
283
284static inline void
285nlm_pic_update_control(uint64_t base, uint64_t control)
286{
287 uint64_t val;
288
289 val = nlm_read_pic_reg(base, PIC_CTRL);
290 nlm_write_pic_reg(base, PIC_CTRL, control | val);
291}
292
293static inline void
294nlm_set_irt_to_cpu(uint64_t base, int irt, int cpu)
295{
296 uint64_t val;
297
298 val = nlm_read_pic_reg(base, PIC_IRT(irt));
299 val |= cpu & 0xf;
300 if (cpu > 15)
301 val |= 1 << 16;
302 nlm_write_pic_reg(base, PIC_IRT(irt), val);
303}
304
305static inline void
306nlm_pic_write_irt(uint64_t base, int irt_num, int en, int nmi,
307 int sch, int vec, int dt, int db, int dte)
308{
309 uint64_t val;
310
311 val = (((uint64_t)en & 0x1) << 31) | ((nmi & 0x1) << 29) |
312 ((sch & 0x1) << 28) | ((vec & 0x3f) << 20) |
313 ((dt & 0x1) << 19) | ((db & 0x7) << 16) |
314 (dte & 0xffff);
315
316 nlm_write_pic_reg(base, PIC_IRT(irt_num), val);
317}
318
319static inline void
320nlm_pic_write_irt_direct(uint64_t base, int irt_num, int en, int nmi,
321 int sch, int vec, int cpu)
322{
323 nlm_pic_write_irt(base, irt_num, en, nmi, sch, vec, 1,
324 (cpu >> 4), /* thread group */
325 1 << (cpu & 0xf)); /* thread mask */
326}
327
328static inline uint64_t
329nlm_pic_read_timer(uint64_t base, int timer)
330{
331 return nlm_read_pic_reg(base, PIC_TIMER_COUNT(timer));
332}
333
334static inline void
335nlm_pic_write_timer(uint64_t base, int timer, uint64_t value)
336{
337 nlm_write_pic_reg(base, PIC_TIMER_COUNT(timer), value);
338}
339
340static inline void
341nlm_pic_set_timer(uint64_t base, int timer, uint64_t value, int irq, int cpu)
342{
343 uint64_t pic_ctrl = nlm_read_pic_reg(base, PIC_CTRL);
344 int en;
345
346 en = (irq > 0);
347 nlm_write_pic_reg(base, PIC_TIMER_MAXVAL(timer), value);
348 nlm_pic_write_irt_direct(base, PIC_IRT_TIMER_INDEX(timer),
349 en, 0, 0, irq, cpu);
350
351 /* enable the timer */
352 pic_ctrl |= (1 << (PIC_CTRL_STE + timer));
353 nlm_write_pic_reg(base, PIC_CTRL, pic_ctrl);
354}
355
356static inline void
357nlm_pic_enable_irt(uint64_t base, int irt)
358{
359 uint64_t reg;
360
361 reg = nlm_read_pic_reg(base, PIC_IRT(irt));
362 nlm_write_pic_reg(base, PIC_IRT(irt), reg | (1u << 31));
363}
364
365static inline void
366nlm_pic_disable_irt(uint64_t base, int irt)
367{
368 uint32_t reg;
369
370 reg = nlm_read_pic_reg(base, PIC_IRT(irt));
371 nlm_write_pic_reg(base, PIC_IRT(irt), reg & ~((uint64_t)1 << 31));
372}
373
374static inline void
375nlm_pic_send_ipi(uint64_t base, int hwt, int irq, int nmi)
376{
377 uint64_t ipi;
378 int node, ncpu;
379
380 node = hwt / 32;
381 ncpu = hwt & 0x1f;
382 ipi = ((uint64_t)nmi << 31) | (irq << 20) | (node << 17) |
383 (1 << (ncpu & 0xf));
384 if (ncpu > 15)
385 ipi |= 0x10000; /* Setting bit 16 to select cpus 16-31 */
386
387 nlm_write_pic_reg(base, PIC_IPI_CTL, ipi);
388}
389
390static inline void
391nlm_pic_ack(uint64_t base, int irt_num)
392{
393 nlm_write_pic_reg(base, PIC_INT_ACK, irt_num);
394
395 /* Ack the Status register for Watchdog & System timers */
396 if (irt_num < 12)
397 nlm_write_pic_reg(base, PIC_STATUS, (1 << irt_num));
398}
399
400static inline void
401nlm_pic_init_irt(uint64_t base, int irt, int irq, int hwt)
402{
403 nlm_pic_write_irt_direct(base, irt, 0, 0, 0, irq, 0);
404}
405
406extern uint64_t nlm_pic_base;
407int nlm_irq_to_irt(int irq);
408int nlm_irt_to_irq(int irt);
409
410#endif /* __ASSEMBLY__ */
411#endif /* _NLM_HAL_PIC_H */
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/sys.h b/arch/mips/include/asm/netlogic/xlp-hal/sys.h
new file mode 100644
index 000000000000..21432f7d89b9
--- /dev/null
+++ b/arch/mips/include/asm/netlogic/xlp-hal/sys.h
@@ -0,0 +1,129 @@
1/*
2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
3 * reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#ifndef __NLM_HAL_SYS_H__
36#define __NLM_HAL_SYS_H__
37
38/**
39* @file_name sys.h
40* @author Netlogic Microsystems
41* @brief HAL for System configuration registers
42*/
43#define SYS_CHIP_RESET 0x00
44#define SYS_POWER_ON_RESET_CFG 0x01
45#define SYS_EFUSE_DEVICE_CFG_STATUS0 0x02
46#define SYS_EFUSE_DEVICE_CFG_STATUS1 0x03
47#define SYS_EFUSE_DEVICE_CFG_STATUS2 0x04
48#define SYS_EFUSE_DEVICE_CFG3 0x05
49#define SYS_EFUSE_DEVICE_CFG4 0x06
50#define SYS_EFUSE_DEVICE_CFG5 0x07
51#define SYS_EFUSE_DEVICE_CFG6 0x08
52#define SYS_EFUSE_DEVICE_CFG7 0x09
53#define SYS_PLL_CTRL 0x0a
54#define SYS_CPU_RESET 0x0b
55#define SYS_CPU_NONCOHERENT_MODE 0x0d
56#define SYS_CORE_DFS_DIS_CTRL 0x0e
57#define SYS_CORE_DFS_RST_CTRL 0x0f
58#define SYS_CORE_DFS_BYP_CTRL 0x10
59#define SYS_CORE_DFS_PHA_CTRL 0x11
60#define SYS_CORE_DFS_DIV_INC_CTRL 0x12
61#define SYS_CORE_DFS_DIV_DEC_CTRL 0x13
62#define SYS_CORE_DFS_DIV_VALUE 0x14
63#define SYS_RESET 0x15
64#define SYS_DFS_DIS_CTRL 0x16
65#define SYS_DFS_RST_CTRL 0x17
66#define SYS_DFS_BYP_CTRL 0x18
67#define SYS_DFS_DIV_INC_CTRL 0x19
68#define SYS_DFS_DIV_DEC_CTRL 0x1a
69#define SYS_DFS_DIV_VALUE0 0x1b
70#define SYS_DFS_DIV_VALUE1 0x1c
71#define SYS_SENSE_AMP_DLY 0x1d
72#define SYS_SOC_SENSE_AMP_DLY 0x1e
73#define SYS_CTRL0 0x1f
74#define SYS_CTRL1 0x20
75#define SYS_TIMEOUT_BS1 0x21
76#define SYS_BYTE_SWAP 0x22
77#define SYS_VRM_VID 0x23
78#define SYS_PWR_RAM_CMD 0x24
79#define SYS_PWR_RAM_ADDR 0x25
80#define SYS_PWR_RAM_DATA0 0x26
81#define SYS_PWR_RAM_DATA1 0x27
82#define SYS_PWR_RAM_DATA2 0x28
83#define SYS_PWR_UCODE 0x29
84#define SYS_CPU0_PWR_STATUS 0x2a
85#define SYS_CPU1_PWR_STATUS 0x2b
86#define SYS_CPU2_PWR_STATUS 0x2c
87#define SYS_CPU3_PWR_STATUS 0x2d
88#define SYS_CPU4_PWR_STATUS 0x2e
89#define SYS_CPU5_PWR_STATUS 0x2f
90#define SYS_CPU6_PWR_STATUS 0x30
91#define SYS_CPU7_PWR_STATUS 0x31
92#define SYS_STATUS 0x32
93#define SYS_INT_POL 0x33
94#define SYS_INT_TYPE 0x34
95#define SYS_INT_STATUS 0x35
96#define SYS_INT_MASK0 0x36
97#define SYS_INT_MASK1 0x37
98#define SYS_UCO_S_ECC 0x38
99#define SYS_UCO_M_ECC 0x39
100#define SYS_UCO_ADDR 0x3a
101#define SYS_UCO_INSTR 0x3b
102#define SYS_MEM_BIST0 0x3c
103#define SYS_MEM_BIST1 0x3d
104#define SYS_MEM_BIST2 0x3e
105#define SYS_MEM_BIST3 0x3f
106#define SYS_MEM_BIST4 0x40
107#define SYS_MEM_BIST5 0x41
108#define SYS_MEM_BIST6 0x42
109#define SYS_MEM_BIST7 0x43
110#define SYS_MEM_BIST8 0x44
111#define SYS_MEM_BIST9 0x45
112#define SYS_MEM_BIST10 0x46
113#define SYS_MEM_BIST11 0x47
114#define SYS_MEM_BIST12 0x48
115#define SYS_SCRTCH0 0x49
116#define SYS_SCRTCH1 0x4a
117#define SYS_SCRTCH2 0x4b
118#define SYS_SCRTCH3 0x4c
119
120#ifndef __ASSEMBLY__
121
122#define nlm_read_sys_reg(b, r) nlm_read_reg(b, r)
123#define nlm_write_sys_reg(b, r, v) nlm_write_reg(b, r, v)
124#define nlm_get_sys_pcibase(node) nlm_pcicfg_base(XLP_IO_SYS_OFFSET(node))
125#define nlm_get_sys_regbase(node) (nlm_get_sys_pcibase(node) + XLP_IO_PCI_HDRSZ)
126
127extern uint64_t nlm_sys_base;
128#endif
129#endif
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/uart.h b/arch/mips/include/asm/netlogic/xlp-hal/uart.h
new file mode 100644
index 000000000000..6a7046ca094d
--- /dev/null
+++ b/arch/mips/include/asm/netlogic/xlp-hal/uart.h
@@ -0,0 +1,191 @@
1/*
2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
3 * reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#ifndef __XLP_HAL_UART_H__
36#define __XLP_HAL_UART_H__
37
38/* UART Specific registers */
39#define UART_RX_DATA 0x00
40#define UART_TX_DATA 0x00
41
42#define UART_INT_EN 0x01
43#define UART_INT_ID 0x02
44#define UART_FIFO_CTL 0x02
45#define UART_LINE_CTL 0x03
46#define UART_MODEM_CTL 0x04
47#define UART_LINE_STS 0x05
48#define UART_MODEM_STS 0x06
49
50#define UART_DIVISOR0 0x00
51#define UART_DIVISOR1 0x01
52
53#define BASE_BAUD (XLP_IO_CLK/16)
54#define BAUD_DIVISOR(baud) (BASE_BAUD / baud)
55
56/* LCR mask values */
57#define LCR_5BITS 0x00
58#define LCR_6BITS 0x01
59#define LCR_7BITS 0x02
60#define LCR_8BITS 0x03
61#define LCR_STOPB 0x04
62#define LCR_PENAB 0x08
63#define LCR_PODD 0x00
64#define LCR_PEVEN 0x10
65#define LCR_PONE 0x20
66#define LCR_PZERO 0x30
67#define LCR_SBREAK 0x40
68#define LCR_EFR_ENABLE 0xbf
69#define LCR_DLAB 0x80
70
71/* MCR mask values */
72#define MCR_DTR 0x01
73#define MCR_RTS 0x02
74#define MCR_DRS 0x04
75#define MCR_IE 0x08
76#define MCR_LOOPBACK 0x10
77
78/* FCR mask values */
79#define FCR_RCV_RST 0x02
80#define FCR_XMT_RST 0x04
81#define FCR_RX_LOW 0x00
82#define FCR_RX_MEDL 0x40
83#define FCR_RX_MEDH 0x80
84#define FCR_RX_HIGH 0xc0
85
86/* IER mask values */
87#define IER_ERXRDY 0x1
88#define IER_ETXRDY 0x2
89#define IER_ERLS 0x4
90#define IER_EMSC 0x8
91
92#if !defined(LOCORE) && !defined(__ASSEMBLY__)
93
94#define nlm_read_uart_reg(b, r) nlm_read_reg(b, r)
95#define nlm_write_uart_reg(b, r, v) nlm_write_reg(b, r, v)
96#define nlm_get_uart_pcibase(node, inst) \
97 nlm_pcicfg_base(XLP_IO_UART_OFFSET(node, inst))
98#define nlm_get_uart_regbase(node, inst) \
99 (nlm_get_uart_pcibase(node, inst) + XLP_IO_PCI_HDRSZ)
100
101static inline void
102nlm_uart_set_baudrate(uint64_t base, int baud)
103{
104 uint32_t lcr;
105
106 lcr = nlm_read_uart_reg(base, UART_LINE_CTL);
107
108 /* enable divisor register, and write baud values */
109 nlm_write_uart_reg(base, UART_LINE_CTL, lcr | (1 << 7));
110 nlm_write_uart_reg(base, UART_DIVISOR0,
111 (BAUD_DIVISOR(baud) & 0xff));
112 nlm_write_uart_reg(base, UART_DIVISOR1,
113 ((BAUD_DIVISOR(baud) >> 8) & 0xff));
114
115 /* restore default lcr */
116 nlm_write_uart_reg(base, UART_LINE_CTL, lcr);
117}
118
119static inline void
120nlm_uart_outbyte(uint64_t base, char c)
121{
122 uint32_t lsr;
123
124 for (;;) {
125 lsr = nlm_read_uart_reg(base, UART_LINE_STS);
126 if (lsr & 0x20)
127 break;
128 }
129
130 nlm_write_uart_reg(base, UART_TX_DATA, (int)c);
131}
132
133static inline char
134nlm_uart_inbyte(uint64_t base)
135{
136 int data, lsr;
137
138 for (;;) {
139 lsr = nlm_read_uart_reg(base, UART_LINE_STS);
140 if (lsr & 0x80) { /* parity/frame/break-error - push a zero */
141 data = 0;
142 break;
143 }
144 if (lsr & 0x01) { /* Rx data */
145 data = nlm_read_uart_reg(base, UART_RX_DATA);
146 break;
147 }
148 }
149
150 return (char)data;
151}
152
153static inline int
154nlm_uart_init(uint64_t base, int baud, int databits, int stopbits,
155 int parity, int int_en, int loopback)
156{
157 uint32_t lcr;
158
159 lcr = 0;
160 if (databits >= 8)
161 lcr |= LCR_8BITS;
162 else if (databits == 7)
163 lcr |= LCR_7BITS;
164 else if (databits == 6)
165 lcr |= LCR_6BITS;
166 else
167 lcr |= LCR_5BITS;
168
169 if (stopbits > 1)
170 lcr |= LCR_STOPB;
171
172 lcr |= parity << 3;
173
174 /* setup default lcr */
175 nlm_write_uart_reg(base, UART_LINE_CTL, lcr);
176
177 /* Reset the FIFOs */
178 nlm_write_uart_reg(base, UART_LINE_CTL, FCR_RCV_RST | FCR_XMT_RST);
179
180 nlm_uart_set_baudrate(base, baud);
181
182 if (loopback)
183 nlm_write_uart_reg(base, UART_MODEM_CTL, 0x1f);
184
185 if (int_en)
186 nlm_write_uart_reg(base, UART_INT_EN, IER_ERXRDY | IER_ETXRDY);
187
188 return 0;
189}
190#endif /* !LOCORE && !__ASSEMBLY__ */
191#endif /* __XLP_HAL_UART_H__ */
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/xlp.h b/arch/mips/include/asm/netlogic/xlp-hal/xlp.h
new file mode 100644
index 000000000000..1540588e396d
--- /dev/null
+++ b/arch/mips/include/asm/netlogic/xlp-hal/xlp.h
@@ -0,0 +1,51 @@
1/*
2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
3 * reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#ifndef _NLM_HAL_XLP_H
36#define _NLM_HAL_XLP_H
37
38#define PIC_UART_0_IRQ 17
39#define PIC_UART_1_IRQ 18
40
41#ifndef __ASSEMBLY__
42
43/* SMP support functions */
44void xlp_boot_core0_siblings(void);
45void xlp_wakeup_secondary_cpus(void);
46
47void xlp_mmu_init(void);
48void nlm_hal_init(void);
49
50#endif /* !__ASSEMBLY__ */
51#endif /* _ASM_NLM_XLP_H */
diff --git a/arch/mips/include/asm/netlogic/xlr/iomap.h b/arch/mips/include/asm/netlogic/xlr/iomap.h
index 2e3a4dd53045..2e768f032e83 100644
--- a/arch/mips/include/asm/netlogic/xlr/iomap.h
+++ b/arch/mips/include/asm/netlogic/xlr/iomap.h
@@ -106,26 +106,4 @@
106#define DEFAULT_HT_TYPE0_CFG_BASE 0x16000000 106#define DEFAULT_HT_TYPE0_CFG_BASE 0x16000000
107#define DEFAULT_HT_TYPE1_CFG_BASE 0x17000000 107#define DEFAULT_HT_TYPE1_CFG_BASE 0x17000000
108 108
109#ifndef __ASSEMBLY__
110#include <linux/types.h>
111#include <asm/byteorder.h>
112
113typedef volatile __u32 nlm_reg_t;
114extern unsigned long netlogic_io_base;
115
116/* FIXME read once in write_reg */
117#ifdef CONFIG_CPU_LITTLE_ENDIAN
118#define netlogic_read_reg(base, offset) ((base)[(offset)])
119#define netlogic_write_reg(base, offset, value) ((base)[(offset)] = (value))
120#else
121#define netlogic_read_reg(base, offset) (be32_to_cpu((base)[(offset)]))
122#define netlogic_write_reg(base, offset, value) \
123 ((base)[(offset)] = cpu_to_be32((value)))
124#endif
125
126#define netlogic_read_reg_le32(base, offset) (le32_to_cpu((base)[(offset)]))
127#define netlogic_write_reg_le32(base, offset, value) \
128 ((base)[(offset)] = cpu_to_le32((value)))
129#define netlogic_io_mmio(offset) ((nlm_reg_t *)(netlogic_io_base+(offset)))
130#endif /* __ASSEMBLY__ */
131#endif 109#endif
diff --git a/arch/mips/include/asm/netlogic/xlr/msidef.h b/arch/mips/include/asm/netlogic/xlr/msidef.h
new file mode 100644
index 000000000000..7e39d40be4f5
--- /dev/null
+++ b/arch/mips/include/asm/netlogic/xlr/msidef.h
@@ -0,0 +1,84 @@
1/*
2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
3 * reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#ifndef ASM_RMI_MSIDEF_H
36#define ASM_RMI_MSIDEF_H
37
38/*
39 * Constants for Intel APIC based MSI messages.
40 * Adapted for the RMI XLR using identical defines
41 */
42
43/*
44 * Shifts for MSI data
45 */
46
47#define MSI_DATA_VECTOR_SHIFT 0
48#define MSI_DATA_VECTOR_MASK 0x000000ff
49#define MSI_DATA_VECTOR(v) (((v) << MSI_DATA_VECTOR_SHIFT) & \
50 MSI_DATA_VECTOR_MASK)
51
52#define MSI_DATA_DELIVERY_MODE_SHIFT 8
53#define MSI_DATA_DELIVERY_FIXED (0 << MSI_DATA_DELIVERY_MODE_SHIFT)
54#define MSI_DATA_DELIVERY_LOWPRI (1 << MSI_DATA_DELIVERY_MODE_SHIFT)
55
56#define MSI_DATA_LEVEL_SHIFT 14
57#define MSI_DATA_LEVEL_DEASSERT (0 << MSI_DATA_LEVEL_SHIFT)
58#define MSI_DATA_LEVEL_ASSERT (1 << MSI_DATA_LEVEL_SHIFT)
59
60#define MSI_DATA_TRIGGER_SHIFT 15
61#define MSI_DATA_TRIGGER_EDGE (0 << MSI_DATA_TRIGGER_SHIFT)
62#define MSI_DATA_TRIGGER_LEVEL (1 << MSI_DATA_TRIGGER_SHIFT)
63
64/*
65 * Shift/mask fields for msi address
66 */
67
68#define MSI_ADDR_BASE_HI 0
69#define MSI_ADDR_BASE_LO 0xfee00000
70
71#define MSI_ADDR_DEST_MODE_SHIFT 2
72#define MSI_ADDR_DEST_MODE_PHYSICAL (0 << MSI_ADDR_DEST_MODE_SHIFT)
73#define MSI_ADDR_DEST_MODE_LOGICAL (1 << MSI_ADDR_DEST_MODE_SHIFT)
74
75#define MSI_ADDR_REDIRECTION_SHIFT 3
76#define MSI_ADDR_REDIRECTION_CPU (0 << MSI_ADDR_REDIRECTION_SHIFT)
77#define MSI_ADDR_REDIRECTION_LOWPRI (1 << MSI_ADDR_REDIRECTION_SHIFT)
78
79#define MSI_ADDR_DEST_ID_SHIFT 12
80#define MSI_ADDR_DEST_ID_MASK 0x00ffff0
81#define MSI_ADDR_DEST_ID(dest) (((dest) << MSI_ADDR_DEST_ID_SHIFT) & \
82 MSI_ADDR_DEST_ID_MASK)
83
84#endif /* ASM_RMI_MSIDEF_H */
diff --git a/arch/mips/include/asm/netlogic/xlr/pic.h b/arch/mips/include/asm/netlogic/xlr/pic.h
index 5cceb746f080..868013e62f32 100644
--- a/arch/mips/include/asm/netlogic/xlr/pic.h
+++ b/arch/mips/include/asm/netlogic/xlr/pic.h
@@ -193,39 +193,72 @@
193/* end XLS */ 193/* end XLS */
194 194
195#ifndef __ASSEMBLY__ 195#ifndef __ASSEMBLY__
196static inline void pic_send_ipi(u32 ipi) 196
197#define PIC_IRQ_IS_EDGE_TRIGGERED(irq) (((irq) >= PIC_TIMER_0_IRQ) && \
198 ((irq) <= PIC_TIMER_7_IRQ))
199#define PIC_IRQ_IS_IRT(irq) (((irq) >= PIC_IRT_FIRST_IRQ) && \
200 ((irq) <= PIC_IRT_LAST_IRQ))
201
202static inline int
203nlm_irq_to_irt(int irq)
197{ 204{
198 nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET); 205 if (PIC_IRQ_IS_IRT(irq) == 0)
206 return -1;
199 207
200 netlogic_write_reg(mmio, PIC_IPI, ipi); 208 return PIC_IRQ_TO_INTR(irq);
201} 209}
202 210
203static inline u32 pic_read_control(void) 211static inline int
212nlm_irt_to_irq(int irt)
204{ 213{
205 nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET);
206 214
207 return netlogic_read_reg(mmio, PIC_CTRL); 215 return PIC_INTR_TO_IRQ(irt);
208} 216}
209 217
210static inline void pic_write_control(u32 control) 218static inline void
219nlm_pic_enable_irt(uint64_t base, int irt)
211{ 220{
212 nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET); 221 uint32_t reg;
213 222
214 netlogic_write_reg(mmio, PIC_CTRL, control); 223 reg = nlm_read_reg(base, PIC_IRT_1(irt));
224 nlm_write_reg(base, PIC_IRT_1(irt), reg | (1u << 31));
215} 225}
216 226
217static inline void pic_update_control(u32 control) 227static inline void
228nlm_pic_disable_irt(uint64_t base, int irt)
218{ 229{
219 nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET); 230 uint32_t reg;
220 231
221 netlogic_write_reg(mmio, PIC_CTRL, 232 reg = nlm_read_reg(base, PIC_IRT_1(irt));
222 (control | netlogic_read_reg(mmio, PIC_CTRL))); 233 nlm_write_reg(base, PIC_IRT_1(irt), reg & ~(1u << 31));
223} 234}
224 235
225#define PIC_IRQ_IS_EDGE_TRIGGERED(irq) (((irq) >= PIC_TIMER_0_IRQ) && \ 236static inline void
226 ((irq) <= PIC_TIMER_7_IRQ)) 237nlm_pic_send_ipi(uint64_t base, int hwt, int irq, int nmi)
227#define PIC_IRQ_IS_IRT(irq) (((irq) >= PIC_IRT_FIRST_IRQ) && \ 238{
228 ((irq) <= PIC_IRT_LAST_IRQ)) 239 unsigned int tid, pid;
229#endif 240
241 tid = hwt & 0x3;
242 pid = (hwt >> 2) & 0x07;
243 nlm_write_reg(base, PIC_IPI,
244 (pid << 20) | (tid << 16) | (nmi << 8) | irq);
245}
246
247static inline void
248nlm_pic_ack(uint64_t base, int irt)
249{
250 nlm_write_reg(base, PIC_INT_ACK, 1u << irt);
251}
230 252
253static inline void
254nlm_pic_init_irt(uint64_t base, int irt, int irq, int hwt)
255{
256 nlm_write_reg(base, PIC_IRT_0(irt), (1u << hwt));
257 /* local scheduling, invalid, level by default */
258 nlm_write_reg(base, PIC_IRT_1(irt),
259 (1 << 30) | (1 << 6) | irq);
260}
261
262extern uint64_t nlm_pic_base;
263#endif
231#endif /* _ASM_NLM_XLR_PIC_H */ 264#endif /* _ASM_NLM_XLR_PIC_H */
diff --git a/arch/mips/include/asm/netlogic/xlr/xlr.h b/arch/mips/include/asm/netlogic/xlr/xlr.h
index 3e6372692a04..ff4a17b0bf78 100644
--- a/arch/mips/include/asm/netlogic/xlr/xlr.h
+++ b/arch/mips/include/asm/netlogic/xlr/xlr.h
@@ -40,17 +40,8 @@ struct uart_port;
40unsigned int nlm_xlr_uart_in(struct uart_port *, int); 40unsigned int nlm_xlr_uart_in(struct uart_port *, int);
41void nlm_xlr_uart_out(struct uart_port *, int, int); 41void nlm_xlr_uart_out(struct uart_port *, int, int);
42 42
43/* SMP support functions */ 43/* SMP helpers */
44struct irq_desc; 44void xlr_wakeup_secondary_cpus(void);
45void nlm_smp_function_ipi_handler(unsigned int irq, struct irq_desc *desc);
46void nlm_smp_resched_ipi_handler(unsigned int irq, struct irq_desc *desc);
47int nlm_wakeup_secondary_cpus(u32 wakeup_mask);
48void nlm_smp_irq_init(void);
49void nlm_boot_smp_nmi(void);
50void prom_pre_boot_secondary_cpus(void);
51
52extern struct plat_smp_ops nlm_smp_ops;
53extern unsigned long nlm_common_ebase;
54 45
55/* XLS B silicon "Rook" */ 46/* XLS B silicon "Rook" */
56static inline unsigned int nlm_chip_is_xls_b(void) 47static inline unsigned int nlm_chip_is_xls_b(void)
diff --git a/arch/mips/include/asm/page.h b/arch/mips/include/asm/page.h
index e59cd1ac09c2..d41790928c64 100644
--- a/arch/mips/include/asm/page.h
+++ b/arch/mips/include/asm/page.h
@@ -38,6 +38,14 @@
38#define HPAGE_SIZE (_AC(1,UL) << HPAGE_SHIFT) 38#define HPAGE_SIZE (_AC(1,UL) << HPAGE_SHIFT)
39#define HPAGE_MASK (~(HPAGE_SIZE - 1)) 39#define HPAGE_MASK (~(HPAGE_SIZE - 1))
40#define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT) 40#define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT)
41#else /* !CONFIG_HUGETLB_PAGE */
42# ifndef BUILD_BUG
43# define BUILD_BUG() do { extern void __build_bug(void); __build_bug(); } while (0)
44# endif
45#define HPAGE_SHIFT ({BUILD_BUG(); 0; })
46#define HPAGE_SIZE ({BUILD_BUG(); 0; })
47#define HPAGE_MASK ({BUILD_BUG(); 0; })
48#define HUGETLB_PAGE_ORDER ({BUILD_BUG(); 0; })
41#endif /* CONFIG_HUGETLB_PAGE */ 49#endif /* CONFIG_HUGETLB_PAGE */
42 50
43#ifndef __ASSEMBLY__ 51#ifndef __ASSEMBLY__
diff --git a/arch/mips/include/asm/pgtable-32.h b/arch/mips/include/asm/pgtable-32.h
index 8a153d2fa62a..5d56bb230345 100644
--- a/arch/mips/include/asm/pgtable-32.h
+++ b/arch/mips/include/asm/pgtable-32.h
@@ -19,23 +19,7 @@
19#include <asm-generic/pgtable-nopmd.h> 19#include <asm-generic/pgtable-nopmd.h>
20 20
21/* 21/*
22 * - add_wired_entry() add a fixed TLB entry, and move wired register 22 * Basically we have the same two-level (which is the logical three level
23 */
24extern void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1,
25 unsigned long entryhi, unsigned long pagemask);
26
27/*
28 * - add_temporary_entry() add a temporary TLB entry. We use TLB entries
29 * starting at the top and working down. This is for populating the
30 * TLB before trap_init() puts the TLB miss handler in place. It
31 * should be used only for entries matching the actual page tables,
32 * to prevent inconsistencies.
33 */
34extern int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1,
35 unsigned long entryhi, unsigned long pagemask);
36
37
38/* Basically we have the same two-level (which is the logical three level
39 * Linux page table layout folded) page tables as the i386. Some day 23 * Linux page table layout folded) page tables as the i386. Some day
40 * when we have proper page coloring support we can have a 1% quicker 24 * when we have proper page coloring support we can have a 1% quicker
41 * tlb refill handling mechanism, but for now it is a bit slower but 25 * tlb refill handling mechanism, but for now it is a bit slower but
diff --git a/arch/mips/include/asm/tlbmisc.h b/arch/mips/include/asm/tlbmisc.h
new file mode 100644
index 000000000000..3a452282cba0
--- /dev/null
+++ b/arch/mips/include/asm/tlbmisc.h
@@ -0,0 +1,10 @@
1#ifndef __ASM_TLBMISC_H
2#define __ASM_TLBMISC_H
3
4/*
5 * - add_wired_entry() add a fixed TLB entry, and move wired register
6 */
7extern void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1,
8 unsigned long entryhi, unsigned long pagemask);
9
10#endif /* __ASM_TLBMISC_H */
diff --git a/arch/mips/include/asm/traps.h b/arch/mips/include/asm/traps.h
index 90ff2f497c50..ff74aec3561a 100644
--- a/arch/mips/include/asm/traps.h
+++ b/arch/mips/include/asm/traps.h
@@ -24,5 +24,18 @@ extern int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
24extern void (*board_nmi_handler_setup)(void); 24extern void (*board_nmi_handler_setup)(void);
25extern void (*board_ejtag_handler_setup)(void); 25extern void (*board_ejtag_handler_setup)(void);
26extern void (*board_bind_eic_interrupt)(int irq, int regset); 26extern void (*board_bind_eic_interrupt)(int irq, int regset);
27extern void (*board_ebase_setup)(void);
28
29extern int register_nmi_notifier(struct notifier_block *nb);
30
31#define nmi_notifier(fn, pri) \
32({ \
33 static struct notifier_block fn##_nb = { \
34 .notifier_call = fn, \
35 .priority = pri \
36 }; \
37 \
38 register_nmi_notifier(&fn##_nb); \
39})
27 40
28#endif /* _ASM_TRAPS_H */ 41#endif /* _ASM_TRAPS_H */
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