aboutsummaryrefslogtreecommitdiffstats
path: root/arch/mips/include
diff options
context:
space:
mode:
Diffstat (limited to 'arch/mips/include')
-rw-r--r--arch/mips/include/asm/atomic.h16
-rw-r--r--arch/mips/include/asm/barrier.h60
-rw-r--r--arch/mips/include/asm/bitops.h8
-rw-r--r--arch/mips/include/asm/cmpxchg.h10
-rw-r--r--arch/mips/include/asm/cpu-features.h10
-rw-r--r--arch/mips/include/asm/cpu-info.h3
-rw-r--r--arch/mips/include/asm/cpu.h2
-rw-r--r--arch/mips/include/asm/current.h24
-rw-r--r--arch/mips/include/asm/dec/kn01.h1
-rw-r--r--arch/mips/include/asm/device.h1
-rw-r--r--arch/mips/include/asm/elf.h14
-rw-r--r--arch/mips/include/asm/ftrace.h2
-rw-r--r--arch/mips/include/asm/i8259.h6
-rw-r--r--arch/mips/include/asm/io.h18
-rw-r--r--arch/mips/include/asm/mach-ar7/ar7.h23
-rw-r--r--arch/mips/include/asm/mach-ar7/gpio.h86
-rw-r--r--arch/mips/include/asm/mach-au1x00/au1000.h876
-rw-r--r--arch/mips/include/asm/mach-au1x00/au1100_mmc.h2
-rw-r--r--arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h24
-rw-r--r--arch/mips/include/asm/mach-au1x00/au1xxx_eth.h17
-rw-r--r--arch/mips/include/asm/mach-au1x00/gpio-au1000.h164
-rw-r--r--arch/mips/include/asm/mach-au1x00/gpio.h2
-rw-r--r--arch/mips/include/asm/mach-au1x00/ioremap.h2
-rw-r--r--arch/mips/include/asm/mach-au1x00/prom.h1
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h1
-rw-r--r--arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h3
-rw-r--r--arch/mips/include/asm/mach-db1x00/bcsr.h238
-rw-r--r--arch/mips/include/asm/mach-db1x00/db1200.h156
-rw-r--r--arch/mips/include/asm/mach-db1x00/db1x00.h100
-rw-r--r--arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h2
-rw-r--r--arch/mips/include/asm/mach-loongson/cs5536/cs5536_vsm.h2
-rw-r--r--arch/mips/include/asm/mach-loongson/loongson.h5
-rw-r--r--arch/mips/include/asm/mach-loongson/machine.h4
-rw-r--r--arch/mips/include/asm/mach-loongson/mem.h2
-rw-r--r--arch/mips/include/asm/mach-loongson/pci.h13
-rw-r--r--arch/mips/include/asm/mach-pb1x00/pb1100.h85
-rw-r--r--arch/mips/include/asm/mach-pb1x00/pb1200.h122
-rw-r--r--arch/mips/include/asm/mach-pb1x00/pb1500.h49
-rw-r--r--arch/mips/include/asm/mach-pb1x00/pb1550.h96
-rw-r--r--arch/mips/include/asm/mach-pnx833x/irq-mapping.h1
-rw-r--r--arch/mips/include/asm/mach-powertv/interrupts.h1
-rw-r--r--arch/mips/include/asm/mipsregs.h15
-rw-r--r--arch/mips/include/asm/msc01_ic.h1
-rw-r--r--arch/mips/include/asm/nile4.h1
-rw-r--r--arch/mips/include/asm/octeon/octeon-feature.h8
-rw-r--r--arch/mips/include/asm/octeon/octeon.h5
-rw-r--r--arch/mips/include/asm/page.h12
-rw-r--r--arch/mips/include/asm/param.h17
-rw-r--r--arch/mips/include/asm/parport.h16
-rw-r--r--arch/mips/include/asm/pgalloc.h4
-rw-r--r--arch/mips/include/asm/pgtable-32.h4
-rw-r--r--arch/mips/include/asm/pgtable-64.h44
-rw-r--r--arch/mips/include/asm/pgtable-bits.h120
-rw-r--r--arch/mips/include/asm/pgtable.h31
-rw-r--r--arch/mips/include/asm/pmc-sierra/msp71xx/msp_prom.h1
-rw-r--r--arch/mips/include/asm/serial.h23
-rw-r--r--arch/mips/include/asm/sgialib.h45
-rw-r--r--arch/mips/include/asm/sibyte/bigsur.h1
-rw-r--r--arch/mips/include/asm/sibyte/sb1250_ldt.h1
-rw-r--r--arch/mips/include/asm/sn/klkernvars.h1
-rw-r--r--arch/mips/include/asm/sparsemem.h1
-rw-r--r--arch/mips/include/asm/spinlock.h120
-rw-r--r--arch/mips/include/asm/spinlock_types.h24
-rw-r--r--arch/mips/include/asm/system.h4
-rw-r--r--arch/mips/include/asm/txx9/generic.h1
-rw-r--r--arch/mips/include/asm/uasm.h195
-rw-r--r--arch/mips/include/asm/ucontext.h22
67 files changed, 1312 insertions, 1657 deletions
diff --git a/arch/mips/include/asm/atomic.h b/arch/mips/include/asm/atomic.h
index dd75d673447e..519197ede089 100644
--- a/arch/mips/include/asm/atomic.h
+++ b/arch/mips/include/asm/atomic.h
@@ -137,7 +137,7 @@ static __inline__ int atomic_add_return(int i, atomic_t * v)
137{ 137{
138 int result; 138 int result;
139 139
140 smp_llsc_mb(); 140 smp_mb__before_llsc();
141 141
142 if (kernel_uses_llsc && R10000_LLSC_WAR) { 142 if (kernel_uses_llsc && R10000_LLSC_WAR) {
143 int temp; 143 int temp;
@@ -189,7 +189,7 @@ static __inline__ int atomic_sub_return(int i, atomic_t * v)
189{ 189{
190 int result; 190 int result;
191 191
192 smp_llsc_mb(); 192 smp_mb__before_llsc();
193 193
194 if (kernel_uses_llsc && R10000_LLSC_WAR) { 194 if (kernel_uses_llsc && R10000_LLSC_WAR) {
195 int temp; 195 int temp;
@@ -249,7 +249,7 @@ static __inline__ int atomic_sub_if_positive(int i, atomic_t * v)
249{ 249{
250 int result; 250 int result;
251 251
252 smp_llsc_mb(); 252 smp_mb__before_llsc();
253 253
254 if (kernel_uses_llsc && R10000_LLSC_WAR) { 254 if (kernel_uses_llsc && R10000_LLSC_WAR) {
255 int temp; 255 int temp;
@@ -516,7 +516,7 @@ static __inline__ long atomic64_add_return(long i, atomic64_t * v)
516{ 516{
517 long result; 517 long result;
518 518
519 smp_llsc_mb(); 519 smp_mb__before_llsc();
520 520
521 if (kernel_uses_llsc && R10000_LLSC_WAR) { 521 if (kernel_uses_llsc && R10000_LLSC_WAR) {
522 long temp; 522 long temp;
@@ -568,7 +568,7 @@ static __inline__ long atomic64_sub_return(long i, atomic64_t * v)
568{ 568{
569 long result; 569 long result;
570 570
571 smp_llsc_mb(); 571 smp_mb__before_llsc();
572 572
573 if (kernel_uses_llsc && R10000_LLSC_WAR) { 573 if (kernel_uses_llsc && R10000_LLSC_WAR) {
574 long temp; 574 long temp;
@@ -628,7 +628,7 @@ static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v)
628{ 628{
629 long result; 629 long result;
630 630
631 smp_llsc_mb(); 631 smp_mb__before_llsc();
632 632
633 if (kernel_uses_llsc && R10000_LLSC_WAR) { 633 if (kernel_uses_llsc && R10000_LLSC_WAR) {
634 long temp; 634 long temp;
@@ -788,9 +788,9 @@ static __inline__ int atomic64_add_unless(atomic64_t *v, long a, long u)
788 * atomic*_return operations are serializing but not the non-*_return 788 * atomic*_return operations are serializing but not the non-*_return
789 * versions. 789 * versions.
790 */ 790 */
791#define smp_mb__before_atomic_dec() smp_llsc_mb() 791#define smp_mb__before_atomic_dec() smp_mb__before_llsc()
792#define smp_mb__after_atomic_dec() smp_llsc_mb() 792#define smp_mb__after_atomic_dec() smp_llsc_mb()
793#define smp_mb__before_atomic_inc() smp_llsc_mb() 793#define smp_mb__before_atomic_inc() smp_mb__before_llsc()
794#define smp_mb__after_atomic_inc() smp_llsc_mb() 794#define smp_mb__after_atomic_inc() smp_llsc_mb()
795 795
796#include <asm-generic/atomic-long.h> 796#include <asm-generic/atomic-long.h>
diff --git a/arch/mips/include/asm/barrier.h b/arch/mips/include/asm/barrier.h
index 8e9ac313ca3b..c0884f02d3a6 100644
--- a/arch/mips/include/asm/barrier.h
+++ b/arch/mips/include/asm/barrier.h
@@ -88,12 +88,20 @@
88 : /* no output */ \ 88 : /* no output */ \
89 : "m" (*(int *)CKSEG1) \ 89 : "m" (*(int *)CKSEG1) \
90 : "memory") 90 : "memory")
91 91#ifdef CONFIG_CPU_CAVIUM_OCTEON
92#define fast_wmb() __sync() 92# define OCTEON_SYNCW_STR ".set push\n.set arch=octeon\nsyncw\nsyncw\n.set pop\n"
93#define fast_rmb() __sync() 93# define __syncw() __asm__ __volatile__(OCTEON_SYNCW_STR : : : "memory")
94#define fast_mb() __sync() 94
95#ifdef CONFIG_SGI_IP28 95# define fast_wmb() __syncw()
96#define fast_iob() \ 96# define fast_rmb() barrier()
97# define fast_mb() __sync()
98# define fast_iob() do { } while (0)
99#else /* ! CONFIG_CPU_CAVIUM_OCTEON */
100# define fast_wmb() __sync()
101# define fast_rmb() __sync()
102# define fast_mb() __sync()
103# ifdef CONFIG_SGI_IP28
104# define fast_iob() \
97 __asm__ __volatile__( \ 105 __asm__ __volatile__( \
98 ".set push\n\t" \ 106 ".set push\n\t" \
99 ".set noreorder\n\t" \ 107 ".set noreorder\n\t" \
@@ -104,13 +112,14 @@
104 : /* no output */ \ 112 : /* no output */ \
105 : "m" (*(int *)CKSEG1ADDR(0x1fa00004)) \ 113 : "m" (*(int *)CKSEG1ADDR(0x1fa00004)) \
106 : "memory") 114 : "memory")
107#else 115# else
108#define fast_iob() \ 116# define fast_iob() \
109 do { \ 117 do { \
110 __sync(); \ 118 __sync(); \
111 __fast_iob(); \ 119 __fast_iob(); \
112 } while (0) 120 } while (0)
113#endif 121# endif
122#endif /* CONFIG_CPU_CAVIUM_OCTEON */
114 123
115#ifdef CONFIG_CPU_HAS_WB 124#ifdef CONFIG_CPU_HAS_WB
116 125
@@ -131,25 +140,42 @@
131#endif /* !CONFIG_CPU_HAS_WB */ 140#endif /* !CONFIG_CPU_HAS_WB */
132 141
133#if defined(CONFIG_WEAK_ORDERING) && defined(CONFIG_SMP) 142#if defined(CONFIG_WEAK_ORDERING) && defined(CONFIG_SMP)
134#define __WEAK_ORDERING_MB " sync \n" 143# ifdef CONFIG_CPU_CAVIUM_OCTEON
144# define smp_mb() __sync()
145# define smp_rmb() barrier()
146# define smp_wmb() __syncw()
147# else
148# define smp_mb() __asm__ __volatile__("sync" : : :"memory")
149# define smp_rmb() __asm__ __volatile__("sync" : : :"memory")
150# define smp_wmb() __asm__ __volatile__("sync" : : :"memory")
151# endif
135#else 152#else
136#define __WEAK_ORDERING_MB " \n" 153#define smp_mb() barrier()
154#define smp_rmb() barrier()
155#define smp_wmb() barrier()
137#endif 156#endif
157
138#if defined(CONFIG_WEAK_REORDERING_BEYOND_LLSC) && defined(CONFIG_SMP) 158#if defined(CONFIG_WEAK_REORDERING_BEYOND_LLSC) && defined(CONFIG_SMP)
139#define __WEAK_LLSC_MB " sync \n" 159#define __WEAK_LLSC_MB " sync \n"
140#else 160#else
141#define __WEAK_LLSC_MB " \n" 161#define __WEAK_LLSC_MB " \n"
142#endif 162#endif
143 163
144#define smp_mb() __asm__ __volatile__(__WEAK_ORDERING_MB : : :"memory")
145#define smp_rmb() __asm__ __volatile__(__WEAK_ORDERING_MB : : :"memory")
146#define smp_wmb() __asm__ __volatile__(__WEAK_ORDERING_MB : : :"memory")
147
148#define set_mb(var, value) \ 164#define set_mb(var, value) \
149 do { var = value; smp_mb(); } while (0) 165 do { var = value; smp_mb(); } while (0)
150 166
151#define smp_llsc_mb() __asm__ __volatile__(__WEAK_LLSC_MB : : :"memory") 167#define smp_llsc_mb() __asm__ __volatile__(__WEAK_LLSC_MB : : :"memory")
152#define smp_llsc_rmb() __asm__ __volatile__(__WEAK_LLSC_MB : : :"memory") 168
153#define smp_llsc_wmb() __asm__ __volatile__(__WEAK_LLSC_MB : : :"memory") 169#ifdef CONFIG_CPU_CAVIUM_OCTEON
170#define smp_mb__before_llsc() smp_wmb()
171/* Cause previous writes to become visible on all CPUs as soon as possible */
172#define nudge_writes() __asm__ __volatile__(".set push\n\t" \
173 ".set arch=octeon\n\t" \
174 "syncw\n\t" \
175 ".set pop" : : : "memory")
176#else
177#define smp_mb__before_llsc() smp_llsc_mb()
178#define nudge_writes() mb()
179#endif
154 180
155#endif /* __ASM_BARRIER_H */ 181#endif /* __ASM_BARRIER_H */
diff --git a/arch/mips/include/asm/bitops.h b/arch/mips/include/asm/bitops.h
index 84a383806b2c..9255cfbee459 100644
--- a/arch/mips/include/asm/bitops.h
+++ b/arch/mips/include/asm/bitops.h
@@ -42,7 +42,7 @@
42/* 42/*
43 * clear_bit() doesn't provide any barrier for the compiler. 43 * clear_bit() doesn't provide any barrier for the compiler.
44 */ 44 */
45#define smp_mb__before_clear_bit() smp_llsc_mb() 45#define smp_mb__before_clear_bit() smp_mb__before_llsc()
46#define smp_mb__after_clear_bit() smp_llsc_mb() 46#define smp_mb__after_clear_bit() smp_llsc_mb()
47 47
48/* 48/*
@@ -258,7 +258,7 @@ static inline int test_and_set_bit(unsigned long nr,
258 unsigned short bit = nr & SZLONG_MASK; 258 unsigned short bit = nr & SZLONG_MASK;
259 unsigned long res; 259 unsigned long res;
260 260
261 smp_llsc_mb(); 261 smp_mb__before_llsc();
262 262
263 if (kernel_uses_llsc && R10000_LLSC_WAR) { 263 if (kernel_uses_llsc && R10000_LLSC_WAR) {
264 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); 264 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
@@ -395,7 +395,7 @@ static inline int test_and_clear_bit(unsigned long nr,
395 unsigned short bit = nr & SZLONG_MASK; 395 unsigned short bit = nr & SZLONG_MASK;
396 unsigned long res; 396 unsigned long res;
397 397
398 smp_llsc_mb(); 398 smp_mb__before_llsc();
399 399
400 if (kernel_uses_llsc && R10000_LLSC_WAR) { 400 if (kernel_uses_llsc && R10000_LLSC_WAR) {
401 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); 401 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
@@ -485,7 +485,7 @@ static inline int test_and_change_bit(unsigned long nr,
485 unsigned short bit = nr & SZLONG_MASK; 485 unsigned short bit = nr & SZLONG_MASK;
486 unsigned long res; 486 unsigned long res;
487 487
488 smp_llsc_mb(); 488 smp_mb__before_llsc();
489 489
490 if (kernel_uses_llsc && R10000_LLSC_WAR) { 490 if (kernel_uses_llsc && R10000_LLSC_WAR) {
491 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); 491 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
diff --git a/arch/mips/include/asm/cmpxchg.h b/arch/mips/include/asm/cmpxchg.h
index 815a438a268d..ed9aaaaf0749 100644
--- a/arch/mips/include/asm/cmpxchg.h
+++ b/arch/mips/include/asm/cmpxchg.h
@@ -72,14 +72,14 @@
72 */ 72 */
73extern void __cmpxchg_called_with_bad_pointer(void); 73extern void __cmpxchg_called_with_bad_pointer(void);
74 74
75#define __cmpxchg(ptr, old, new, barrier) \ 75#define __cmpxchg(ptr, old, new, pre_barrier, post_barrier) \
76({ \ 76({ \
77 __typeof__(ptr) __ptr = (ptr); \ 77 __typeof__(ptr) __ptr = (ptr); \
78 __typeof__(*(ptr)) __old = (old); \ 78 __typeof__(*(ptr)) __old = (old); \
79 __typeof__(*(ptr)) __new = (new); \ 79 __typeof__(*(ptr)) __new = (new); \
80 __typeof__(*(ptr)) __res = 0; \ 80 __typeof__(*(ptr)) __res = 0; \
81 \ 81 \
82 barrier; \ 82 pre_barrier; \
83 \ 83 \
84 switch (sizeof(*(__ptr))) { \ 84 switch (sizeof(*(__ptr))) { \
85 case 4: \ 85 case 4: \
@@ -96,13 +96,13 @@ extern void __cmpxchg_called_with_bad_pointer(void);
96 break; \ 96 break; \
97 } \ 97 } \
98 \ 98 \
99 barrier; \ 99 post_barrier; \
100 \ 100 \
101 __res; \ 101 __res; \
102}) 102})
103 103
104#define cmpxchg(ptr, old, new) __cmpxchg(ptr, old, new, smp_llsc_mb()) 104#define cmpxchg(ptr, old, new) __cmpxchg(ptr, old, new, smp_mb__before_llsc(), smp_llsc_mb())
105#define cmpxchg_local(ptr, old, new) __cmpxchg(ptr, old, new, ) 105#define cmpxchg_local(ptr, old, new) __cmpxchg(ptr, old, new, , )
106 106
107#define cmpxchg64(ptr, o, n) \ 107#define cmpxchg64(ptr, o, n) \
108 ({ \ 108 ({ \
diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
index 1f4df647c384..ac73cede3a0a 100644
--- a/arch/mips/include/asm/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
@@ -95,6 +95,9 @@
95#ifndef cpu_has_smartmips 95#ifndef cpu_has_smartmips
96#define cpu_has_smartmips (cpu_data[0].ases & MIPS_ASE_SMARTMIPS) 96#define cpu_has_smartmips (cpu_data[0].ases & MIPS_ASE_SMARTMIPS)
97#endif 97#endif
98#ifndef kernel_uses_smartmips_rixi
99#define kernel_uses_smartmips_rixi 0
100#endif
98#ifndef cpu_has_vtag_icache 101#ifndef cpu_has_vtag_icache
99#define cpu_has_vtag_icache (cpu_data[0].icache.flags & MIPS_CACHE_VTAG) 102#define cpu_has_vtag_icache (cpu_data[0].icache.flags & MIPS_CACHE_VTAG)
100#endif 103#endif
@@ -191,6 +194,9 @@
191# ifndef cpu_has_64bit_addresses 194# ifndef cpu_has_64bit_addresses
192# define cpu_has_64bit_addresses 0 195# define cpu_has_64bit_addresses 0
193# endif 196# endif
197# ifndef cpu_vmbits
198# define cpu_vmbits 31
199# endif
194#endif 200#endif
195 201
196#ifdef CONFIG_64BIT 202#ifdef CONFIG_64BIT
@@ -209,6 +215,10 @@
209# ifndef cpu_has_64bit_addresses 215# ifndef cpu_has_64bit_addresses
210# define cpu_has_64bit_addresses 1 216# define cpu_has_64bit_addresses 1
211# endif 217# endif
218# ifndef cpu_vmbits
219# define cpu_vmbits cpu_data[0].vmbits
220# define __NEED_VMBITS_PROBE
221# endif
212#endif 222#endif
213 223
214#if defined(CONFIG_CPU_MIPSR2_IRQ_VI) && !defined(cpu_has_vint) 224#if defined(CONFIG_CPU_MIPSR2_IRQ_VI) && !defined(cpu_has_vint)
diff --git a/arch/mips/include/asm/cpu-info.h b/arch/mips/include/asm/cpu-info.h
index 126044308dec..b39def3f6e03 100644
--- a/arch/mips/include/asm/cpu-info.h
+++ b/arch/mips/include/asm/cpu-info.h
@@ -58,6 +58,9 @@ struct cpuinfo_mips {
58 struct cache_desc tcache; /* Tertiary/split secondary cache */ 58 struct cache_desc tcache; /* Tertiary/split secondary cache */
59 int srsets; /* Shadow register sets */ 59 int srsets; /* Shadow register sets */
60 int core; /* physical core number */ 60 int core; /* physical core number */
61#ifdef CONFIG_64BIT
62 int vmbits; /* Virtual memory size in bits */
63#endif
61#if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_MIPS_MT_SMTC) 64#if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_MIPS_MT_SMTC)
62 /* 65 /*
63 * In the MIPS MT "SMTC" model, each TC is considered 66 * In the MIPS MT "SMTC" model, each TC is considered
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index cf373a95fe4a..a5acda416946 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -224,7 +224,7 @@ enum cpu_type_enum {
224 * MIPS64 class processors 224 * MIPS64 class processors
225 */ 225 */
226 CPU_5KC, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2, 226 CPU_5KC, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2,
227 CPU_CAVIUM_OCTEON, 227 CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS,
228 228
229 CPU_LAST 229 CPU_LAST
230}; 230};
diff --git a/arch/mips/include/asm/current.h b/arch/mips/include/asm/current.h
index 559db66b9790..4c51401b5537 100644
--- a/arch/mips/include/asm/current.h
+++ b/arch/mips/include/asm/current.h
@@ -1,23 +1 @@
1/* #include <asm-generic/current.h>
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1998, 2002 Ralf Baechle
7 * Copyright (C) 1999 Silicon Graphics, Inc.
8 */
9#ifndef _ASM_CURRENT_H
10#define _ASM_CURRENT_H
11
12#include <linux/thread_info.h>
13
14struct task_struct;
15
16static inline struct task_struct * get_current(void)
17{
18 return current_thread_info()->task;
19}
20
21#define current get_current()
22
23#endif /* _ASM_CURRENT_H */
diff --git a/arch/mips/include/asm/dec/kn01.h b/arch/mips/include/asm/dec/kn01.h
index 28fa717ac423..88d9ffd74258 100644
--- a/arch/mips/include/asm/dec/kn01.h
+++ b/arch/mips/include/asm/dec/kn01.h
@@ -80,7 +80,6 @@
80struct pt_regs; 80struct pt_regs;
81 81
82extern u16 cached_kn01_csr; 82extern u16 cached_kn01_csr;
83extern spinlock_t kn01_lock;
84 83
85extern void dec_kn01_be_init(void); 84extern void dec_kn01_be_init(void);
86extern int dec_kn01_be_handler(struct pt_regs *regs, int is_fixup); 85extern int dec_kn01_be_handler(struct pt_regs *regs, int is_fixup);
diff --git a/arch/mips/include/asm/device.h b/arch/mips/include/asm/device.h
index d8f9872b0e2d..06746c5e8099 100644
--- a/arch/mips/include/asm/device.h
+++ b/arch/mips/include/asm/device.h
@@ -4,4 +4,3 @@
4 * This file is released under the GPLv2 4 * This file is released under the GPLv2
5 */ 5 */
6#include <asm-generic/device.h> 6#include <asm-generic/device.h>
7
diff --git a/arch/mips/include/asm/elf.h b/arch/mips/include/asm/elf.h
index 7a6a35dbe529..e53d7bed5cda 100644
--- a/arch/mips/include/asm/elf.h
+++ b/arch/mips/include/asm/elf.h
@@ -334,14 +334,14 @@ extern int dump_task_fpu(struct task_struct *, elf_fpregset_t *);
334 334
335#define ELF_HWCAP (0) 335#define ELF_HWCAP (0)
336 336
337/* This yields a string that ld.so will use to load implementation 337/*
338 specific libraries for optimization. This is more specific in 338 * This yields a string that ld.so will use to load implementation
339 intent than poking at uname or /proc/cpuinfo. 339 * specific libraries for optimization. This is more specific in
340 340 * intent than poking at uname or /proc/cpuinfo.
341 For the moment, we have only optimizations for the Intel generations, 341 */
342 but that could change... */
343 342
344#define ELF_PLATFORM (NULL) 343#define ELF_PLATFORM __elf_platform
344extern const char *__elf_platform;
345 345
346/* 346/*
347 * See comments in asm-alpha/elf.h, this is the same thing 347 * See comments in asm-alpha/elf.h, this is the same thing
diff --git a/arch/mips/include/asm/ftrace.h b/arch/mips/include/asm/ftrace.h
index 3986cd8704f3..ce35c9af0c28 100644
--- a/arch/mips/include/asm/ftrace.h
+++ b/arch/mips/include/asm/ftrace.h
@@ -4,7 +4,7 @@
4 * more details. 4 * more details.
5 * 5 *
6 * Copyright (C) 2009 DSLab, Lanzhou University, China 6 * Copyright (C) 2009 DSLab, Lanzhou University, China
7 * Author: Wu Zhangjin <wuzj@lemote.com> 7 * Author: Wu Zhangjin <wuzhangjin@gmail.com>
8 */ 8 */
9 9
10#ifndef _ASM_MIPS_FTRACE_H 10#ifndef _ASM_MIPS_FTRACE_H
diff --git a/arch/mips/include/asm/i8259.h b/arch/mips/include/asm/i8259.h
index 8572a2d90484..c7e278447c0a 100644
--- a/arch/mips/include/asm/i8259.h
+++ b/arch/mips/include/asm/i8259.h
@@ -35,7 +35,7 @@
35#define SLAVE_ICW4_DEFAULT 0x01 35#define SLAVE_ICW4_DEFAULT 0x01
36#define PIC_ICW4_AEOI 2 36#define PIC_ICW4_AEOI 2
37 37
38extern spinlock_t i8259A_lock; 38extern raw_spinlock_t i8259A_lock;
39 39
40extern int i8259A_irq_pending(unsigned int irq); 40extern int i8259A_irq_pending(unsigned int irq);
41extern void make_8259A_irq(unsigned int irq); 41extern void make_8259A_irq(unsigned int irq);
@@ -51,7 +51,7 @@ static inline int i8259_irq(void)
51{ 51{
52 int irq; 52 int irq;
53 53
54 spin_lock(&i8259A_lock); 54 raw_spin_lock(&i8259A_lock);
55 55
56 /* Perform an interrupt acknowledge cycle on controller 1. */ 56 /* Perform an interrupt acknowledge cycle on controller 1. */
57 outb(0x0C, PIC_MASTER_CMD); /* prepare for poll */ 57 outb(0x0C, PIC_MASTER_CMD); /* prepare for poll */
@@ -78,7 +78,7 @@ static inline int i8259_irq(void)
78 irq = -1; 78 irq = -1;
79 } 79 }
80 80
81 spin_unlock(&i8259A_lock); 81 raw_spin_unlock(&i8259A_lock);
82 82
83 return likely(irq >= 0) ? irq + I8259A_IRQ_BASE : irq; 83 return likely(irq >= 0) ? irq + I8259A_IRQ_BASE : irq;
84} 84}
diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
index 436878e4e063..c98bf514ec7d 100644
--- a/arch/mips/include/asm/io.h
+++ b/arch/mips/include/asm/io.h
@@ -447,6 +447,24 @@ __BUILDIO(q, u64)
447#define readl_relaxed readl 447#define readl_relaxed readl
448#define readq_relaxed readq 448#define readq_relaxed readq
449 449
450#define readb_be(addr) \
451 __raw_readb((__force unsigned *)(addr))
452#define readw_be(addr) \
453 be16_to_cpu(__raw_readw((__force unsigned *)(addr)))
454#define readl_be(addr) \
455 be32_to_cpu(__raw_readl((__force unsigned *)(addr)))
456#define readq_be(addr) \
457 be64_to_cpu(__raw_readq((__force unsigned *)(addr)))
458
459#define writeb_be(val, addr) \
460 __raw_writeb((val), (__force unsigned *)(addr))
461#define writew_be(val, addr) \
462 __raw_writew(cpu_to_be16((val)), (__force unsigned *)(addr))
463#define writel_be(val, addr) \
464 __raw_writel(cpu_to_be32((val)), (__force unsigned *)(addr))
465#define writeq_be(val, addr) \
466 __raw_writeq(cpu_to_be64((val)), (__force unsigned *)(addr))
467
450/* 468/*
451 * Some code tests for these symbols 469 * Some code tests for these symbols
452 */ 470 */
diff --git a/arch/mips/include/asm/mach-ar7/ar7.h b/arch/mips/include/asm/mach-ar7/ar7.h
index 21cbbc706448..f1cf38943497 100644
--- a/arch/mips/include/asm/mach-ar7/ar7.h
+++ b/arch/mips/include/asm/mach-ar7/ar7.h
@@ -105,26 +105,9 @@ static inline u8 ar7_chip_rev(void)
105 return (readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x14)) >> 16) & 0xff; 105 return (readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x14)) >> 16) & 0xff;
106} 106}
107 107
108static inline int ar7_cpu_freq(void) 108struct clk {
109{ 109 unsigned int rate;
110 return ar7_cpu_clock; 110};
111}
112
113static inline int ar7_bus_freq(void)
114{
115 return ar7_bus_clock;
116}
117
118static inline int ar7_vbus_freq(void)
119{
120 return ar7_bus_clock / 2;
121}
122#define ar7_cpmac_freq ar7_vbus_freq
123
124static inline int ar7_dsp_freq(void)
125{
126 return ar7_dsp_clock;
127}
128 111
129static inline int ar7_has_high_cpmac(void) 112static inline int ar7_has_high_cpmac(void)
130{ 113{
diff --git a/arch/mips/include/asm/mach-ar7/gpio.h b/arch/mips/include/asm/mach-ar7/gpio.h
index cbe9c4f126df..73f9b162c970 100644
--- a/arch/mips/include/asm/mach-ar7/gpio.h
+++ b/arch/mips/include/asm/mach-ar7/gpio.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (C) 2007 Florian Fainelli <florian@openwrt.org> 2 * Copyright (C) 2007-2009 Florian Fainelli <florian@openwrt.org>
3 * 3 *
4 * This program is free software; you can redistribute it and/or modify 4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by 5 * it under the terms of the GNU General Public License as published by
@@ -22,88 +22,18 @@
22#include <asm/mach-ar7/ar7.h> 22#include <asm/mach-ar7/ar7.h>
23 23
24#define AR7_GPIO_MAX 32 24#define AR7_GPIO_MAX 32
25#define NR_BUILTIN_GPIO AR7_GPIO_MAX
25 26
26extern int gpio_request(unsigned gpio, const char *label); 27#define gpio_to_irq(gpio) NULL
27extern void gpio_free(unsigned gpio);
28 28
29/* Common GPIO layer */ 29#define gpio_get_value __gpio_get_value
30static inline int gpio_get_value(unsigned gpio) 30#define gpio_set_value __gpio_set_value
31{
32 void __iomem *gpio_in =
33 (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + AR7_GPIO_INPUT);
34 31
35 return readl(gpio_in) & (1 << gpio); 32#define gpio_cansleep __gpio_cansleep
36}
37
38static inline void gpio_set_value(unsigned gpio, int value)
39{
40 void __iomem *gpio_out =
41 (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + AR7_GPIO_OUTPUT);
42 unsigned tmp;
43
44 tmp = readl(gpio_out) & ~(1 << gpio);
45 if (value)
46 tmp |= 1 << gpio;
47 writel(tmp, gpio_out);
48}
49
50static inline int gpio_direction_input(unsigned gpio)
51{
52 void __iomem *gpio_dir =
53 (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + AR7_GPIO_DIR);
54
55 if (gpio >= AR7_GPIO_MAX)
56 return -EINVAL;
57
58 writel(readl(gpio_dir) | (1 << gpio), gpio_dir);
59
60 return 0;
61}
62
63static inline int gpio_direction_output(unsigned gpio, int value)
64{
65 void __iomem *gpio_dir =
66 (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + AR7_GPIO_DIR);
67
68 if (gpio >= AR7_GPIO_MAX)
69 return -EINVAL;
70
71 gpio_set_value(gpio, value);
72 writel(readl(gpio_dir) & ~(1 << gpio), gpio_dir);
73
74 return 0;
75}
76
77static inline int gpio_to_irq(unsigned gpio)
78{
79 return -EINVAL;
80}
81
82static inline int irq_to_gpio(unsigned irq)
83{
84 return -EINVAL;
85}
86 33
87/* Board specific GPIO functions */ 34/* Board specific GPIO functions */
88static inline int ar7_gpio_enable(unsigned gpio) 35int ar7_gpio_enable(unsigned gpio);
89{ 36int ar7_gpio_disable(unsigned gpio);
90 void __iomem *gpio_en =
91 (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + AR7_GPIO_ENABLE);
92
93 writel(readl(gpio_en) | (1 << gpio), gpio_en);
94
95 return 0;
96}
97
98static inline int ar7_gpio_disable(unsigned gpio)
99{
100 void __iomem *gpio_en =
101 (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + AR7_GPIO_ENABLE);
102
103 writel(readl(gpio_en) & ~(1 << gpio), gpio_en);
104
105 return 0;
106}
107 37
108#include <asm-generic/gpio.h> 38#include <asm-generic/gpio.h>
109 39
diff --git a/arch/mips/include/asm/mach-au1x00/au1000.h b/arch/mips/include/asm/mach-au1x00/au1000.h
index 854e95f1b07c..ae07423e6e82 100644
--- a/arch/mips/include/asm/mach-au1x00/au1000.h
+++ b/arch/mips/include/asm/mach-au1x00/au1000.h
@@ -130,6 +130,56 @@ static inline int au1xxx_cpu_needs_config_od(void)
130 return 0; 130 return 0;
131} 131}
132 132
133#define ALCHEMY_CPU_UNKNOWN -1
134#define ALCHEMY_CPU_AU1000 0
135#define ALCHEMY_CPU_AU1500 1
136#define ALCHEMY_CPU_AU1100 2
137#define ALCHEMY_CPU_AU1550 3
138#define ALCHEMY_CPU_AU1200 4
139
140static inline int alchemy_get_cputype(void)
141{
142 switch (read_c0_prid() & 0xffff0000) {
143 case 0x00030000:
144 return ALCHEMY_CPU_AU1000;
145 break;
146 case 0x01030000:
147 return ALCHEMY_CPU_AU1500;
148 break;
149 case 0x02030000:
150 return ALCHEMY_CPU_AU1100;
151 break;
152 case 0x03030000:
153 return ALCHEMY_CPU_AU1550;
154 break;
155 case 0x04030000:
156 case 0x05030000:
157 return ALCHEMY_CPU_AU1200;
158 break;
159 }
160
161 return ALCHEMY_CPU_UNKNOWN;
162}
163
164static inline void alchemy_uart_putchar(u32 uart_phys, u8 c)
165{
166 void __iomem *base = (void __iomem *)KSEG1ADDR(uart_phys);
167 int timeout, i;
168
169 /* check LSR TX_EMPTY bit */
170 timeout = 0xffffff;
171 do {
172 if (__raw_readl(base + 0x1c) & 0x20)
173 break;
174 /* slow down */
175 for (i = 10000; i; i--)
176 asm volatile ("nop");
177 } while (--timeout);
178
179 __raw_writel(c, base + 0x04); /* tx */
180 wmb();
181}
182
133/* arch/mips/au1000/common/clocks.c */ 183/* arch/mips/au1000/common/clocks.c */
134extern void set_au1x00_speed(unsigned int new_freq); 184extern void set_au1x00_speed(unsigned int new_freq);
135extern unsigned int get_au1x00_speed(void); 185extern unsigned int get_au1x00_speed(void);
@@ -143,20 +193,332 @@ void au_sleep(void);
143void save_au1xxx_intctl(void); 193void save_au1xxx_intctl(void);
144void restore_au1xxx_intctl(void); 194void restore_au1xxx_intctl(void);
145 195
146/* 196
147 * Every board describes its IRQ mapping with this table. 197/* SOC Interrupt numbers */
148 */ 198
149struct au1xxx_irqmap { 199#define AU1000_INTC0_INT_BASE (MIPS_CPU_IRQ_BASE + 8)
150 int im_irq; 200#define AU1000_INTC0_INT_LAST (AU1000_INTC0_INT_BASE + 31)
151 int im_type; 201#define AU1000_INTC1_INT_BASE (AU1000_INTC0_INT_LAST + 1)
152 int im_request; 202#define AU1000_INTC1_INT_LAST (AU1000_INTC1_INT_BASE + 31)
203#define AU1000_MAX_INTR AU1000_INTC1_INT_LAST
204
205enum soc_au1000_ints {
206 AU1000_FIRST_INT = AU1000_INTC0_INT_BASE,
207 AU1000_UART0_INT = AU1000_FIRST_INT,
208 AU1000_UART1_INT,
209 AU1000_UART2_INT,
210 AU1000_UART3_INT,
211 AU1000_SSI0_INT,
212 AU1000_SSI1_INT,
213 AU1000_DMA_INT_BASE,
214
215 AU1000_TOY_INT = AU1000_FIRST_INT + 14,
216 AU1000_TOY_MATCH0_INT,
217 AU1000_TOY_MATCH1_INT,
218 AU1000_TOY_MATCH2_INT,
219 AU1000_RTC_INT,
220 AU1000_RTC_MATCH0_INT,
221 AU1000_RTC_MATCH1_INT,
222 AU1000_RTC_MATCH2_INT,
223 AU1000_IRDA_TX_INT,
224 AU1000_IRDA_RX_INT,
225 AU1000_USB_DEV_REQ_INT,
226 AU1000_USB_DEV_SUS_INT,
227 AU1000_USB_HOST_INT,
228 AU1000_ACSYNC_INT,
229 AU1000_MAC0_DMA_INT,
230 AU1000_MAC1_DMA_INT,
231 AU1000_I2S_UO_INT,
232 AU1000_AC97C_INT,
233 AU1000_GPIO0_INT,
234 AU1000_GPIO1_INT,
235 AU1000_GPIO2_INT,
236 AU1000_GPIO3_INT,
237 AU1000_GPIO4_INT,
238 AU1000_GPIO5_INT,
239 AU1000_GPIO6_INT,
240 AU1000_GPIO7_INT,
241 AU1000_GPIO8_INT,
242 AU1000_GPIO9_INT,
243 AU1000_GPIO10_INT,
244 AU1000_GPIO11_INT,
245 AU1000_GPIO12_INT,
246 AU1000_GPIO13_INT,
247 AU1000_GPIO14_INT,
248 AU1000_GPIO15_INT,
249 AU1000_GPIO16_INT,
250 AU1000_GPIO17_INT,
251 AU1000_GPIO18_INT,
252 AU1000_GPIO19_INT,
253 AU1000_GPIO20_INT,
254 AU1000_GPIO21_INT,
255 AU1000_GPIO22_INT,
256 AU1000_GPIO23_INT,
257 AU1000_GPIO24_INT,
258 AU1000_GPIO25_INT,
259 AU1000_GPIO26_INT,
260 AU1000_GPIO27_INT,
261 AU1000_GPIO28_INT,
262 AU1000_GPIO29_INT,
263 AU1000_GPIO30_INT,
264 AU1000_GPIO31_INT,
153}; 265};
154 266
155/* core calls this function to let boards initialize other IRQ sources */ 267enum soc_au1100_ints {
156void board_init_irq(void); 268 AU1100_FIRST_INT = AU1000_INTC0_INT_BASE,
269 AU1100_UART0_INT = AU1100_FIRST_INT,
270 AU1100_UART1_INT,
271 AU1100_SD_INT,
272 AU1100_UART3_INT,
273 AU1100_SSI0_INT,
274 AU1100_SSI1_INT,
275 AU1100_DMA_INT_BASE,
276
277 AU1100_TOY_INT = AU1100_FIRST_INT + 14,
278 AU1100_TOY_MATCH0_INT,
279 AU1100_TOY_MATCH1_INT,
280 AU1100_TOY_MATCH2_INT,
281 AU1100_RTC_INT,
282 AU1100_RTC_MATCH0_INT,
283 AU1100_RTC_MATCH1_INT,
284 AU1100_RTC_MATCH2_INT,
285 AU1100_IRDA_TX_INT,
286 AU1100_IRDA_RX_INT,
287 AU1100_USB_DEV_REQ_INT,
288 AU1100_USB_DEV_SUS_INT,
289 AU1100_USB_HOST_INT,
290 AU1100_ACSYNC_INT,
291 AU1100_MAC0_DMA_INT,
292 AU1100_GPIO208_215_INT,
293 AU1100_LCD_INT,
294 AU1100_AC97C_INT,
295 AU1100_GPIO0_INT,
296 AU1100_GPIO1_INT,
297 AU1100_GPIO2_INT,
298 AU1100_GPIO3_INT,
299 AU1100_GPIO4_INT,
300 AU1100_GPIO5_INT,
301 AU1100_GPIO6_INT,
302 AU1100_GPIO7_INT,
303 AU1100_GPIO8_INT,
304 AU1100_GPIO9_INT,
305 AU1100_GPIO10_INT,
306 AU1100_GPIO11_INT,
307 AU1100_GPIO12_INT,
308 AU1100_GPIO13_INT,
309 AU1100_GPIO14_INT,
310 AU1100_GPIO15_INT,
311 AU1100_GPIO16_INT,
312 AU1100_GPIO17_INT,
313 AU1100_GPIO18_INT,
314 AU1100_GPIO19_INT,
315 AU1100_GPIO20_INT,
316 AU1100_GPIO21_INT,
317 AU1100_GPIO22_INT,
318 AU1100_GPIO23_INT,
319 AU1100_GPIO24_INT,
320 AU1100_GPIO25_INT,
321 AU1100_GPIO26_INT,
322 AU1100_GPIO27_INT,
323 AU1100_GPIO28_INT,
324 AU1100_GPIO29_INT,
325 AU1100_GPIO30_INT,
326 AU1100_GPIO31_INT,
327};
157 328
158/* boards call this to register additional (GPIO) interrupts */ 329enum soc_au1500_ints {
159void au1xxx_setup_irqmap(struct au1xxx_irqmap *map, int count); 330 AU1500_FIRST_INT = AU1000_INTC0_INT_BASE,
331 AU1500_UART0_INT = AU1500_FIRST_INT,
332 AU1500_PCI_INTA,
333 AU1500_PCI_INTB,
334 AU1500_UART3_INT,
335 AU1500_PCI_INTC,
336 AU1500_PCI_INTD,
337 AU1500_DMA_INT_BASE,
338
339 AU1500_TOY_INT = AU1500_FIRST_INT + 14,
340 AU1500_TOY_MATCH0_INT,
341 AU1500_TOY_MATCH1_INT,
342 AU1500_TOY_MATCH2_INT,
343 AU1500_RTC_INT,
344 AU1500_RTC_MATCH0_INT,
345 AU1500_RTC_MATCH1_INT,
346 AU1500_RTC_MATCH2_INT,
347 AU1500_PCI_ERR_INT,
348 AU1500_RESERVED_INT,
349 AU1500_USB_DEV_REQ_INT,
350 AU1500_USB_DEV_SUS_INT,
351 AU1500_USB_HOST_INT,
352 AU1500_ACSYNC_INT,
353 AU1500_MAC0_DMA_INT,
354 AU1500_MAC1_DMA_INT,
355 AU1500_AC97C_INT = AU1500_FIRST_INT + 31,
356 AU1500_GPIO0_INT,
357 AU1500_GPIO1_INT,
358 AU1500_GPIO2_INT,
359 AU1500_GPIO3_INT,
360 AU1500_GPIO4_INT,
361 AU1500_GPIO5_INT,
362 AU1500_GPIO6_INT,
363 AU1500_GPIO7_INT,
364 AU1500_GPIO8_INT,
365 AU1500_GPIO9_INT,
366 AU1500_GPIO10_INT,
367 AU1500_GPIO11_INT,
368 AU1500_GPIO12_INT,
369 AU1500_GPIO13_INT,
370 AU1500_GPIO14_INT,
371 AU1500_GPIO15_INT,
372 AU1500_GPIO200_INT,
373 AU1500_GPIO201_INT,
374 AU1500_GPIO202_INT,
375 AU1500_GPIO203_INT,
376 AU1500_GPIO20_INT,
377 AU1500_GPIO204_INT,
378 AU1500_GPIO205_INT,
379 AU1500_GPIO23_INT,
380 AU1500_GPIO24_INT,
381 AU1500_GPIO25_INT,
382 AU1500_GPIO26_INT,
383 AU1500_GPIO27_INT,
384 AU1500_GPIO28_INT,
385 AU1500_GPIO206_INT,
386 AU1500_GPIO207_INT,
387 AU1500_GPIO208_215_INT,
388};
389
390enum soc_au1550_ints {
391 AU1550_FIRST_INT = AU1000_INTC0_INT_BASE,
392 AU1550_UART0_INT = AU1550_FIRST_INT,
393 AU1550_PCI_INTA,
394 AU1550_PCI_INTB,
395 AU1550_DDMA_INT,
396 AU1550_CRYPTO_INT,
397 AU1550_PCI_INTC,
398 AU1550_PCI_INTD,
399 AU1550_PCI_RST_INT,
400 AU1550_UART1_INT,
401 AU1550_UART3_INT,
402 AU1550_PSC0_INT,
403 AU1550_PSC1_INT,
404 AU1550_PSC2_INT,
405 AU1550_PSC3_INT,
406 AU1550_TOY_INT,
407 AU1550_TOY_MATCH0_INT,
408 AU1550_TOY_MATCH1_INT,
409 AU1550_TOY_MATCH2_INT,
410 AU1550_RTC_INT,
411 AU1550_RTC_MATCH0_INT,
412 AU1550_RTC_MATCH1_INT,
413 AU1550_RTC_MATCH2_INT,
414
415 AU1550_NAND_INT = AU1550_FIRST_INT + 23,
416 AU1550_USB_DEV_REQ_INT,
417 AU1550_USB_DEV_SUS_INT,
418 AU1550_USB_HOST_INT,
419 AU1550_MAC0_DMA_INT,
420 AU1550_MAC1_DMA_INT,
421 AU1550_GPIO0_INT = AU1550_FIRST_INT + 32,
422 AU1550_GPIO1_INT,
423 AU1550_GPIO2_INT,
424 AU1550_GPIO3_INT,
425 AU1550_GPIO4_INT,
426 AU1550_GPIO5_INT,
427 AU1550_GPIO6_INT,
428 AU1550_GPIO7_INT,
429 AU1550_GPIO8_INT,
430 AU1550_GPIO9_INT,
431 AU1550_GPIO10_INT,
432 AU1550_GPIO11_INT,
433 AU1550_GPIO12_INT,
434 AU1550_GPIO13_INT,
435 AU1550_GPIO14_INT,
436 AU1550_GPIO15_INT,
437 AU1550_GPIO200_INT,
438 AU1550_GPIO201_205_INT, /* Logical or of GPIO201:205 */
439 AU1550_GPIO16_INT,
440 AU1550_GPIO17_INT,
441 AU1550_GPIO20_INT,
442 AU1550_GPIO21_INT,
443 AU1550_GPIO22_INT,
444 AU1550_GPIO23_INT,
445 AU1550_GPIO24_INT,
446 AU1550_GPIO25_INT,
447 AU1550_GPIO26_INT,
448 AU1550_GPIO27_INT,
449 AU1550_GPIO28_INT,
450 AU1550_GPIO206_INT,
451 AU1550_GPIO207_INT,
452 AU1550_GPIO208_215_INT, /* Logical or of GPIO208:215 */
453};
454
455enum soc_au1200_ints {
456 AU1200_FIRST_INT = AU1000_INTC0_INT_BASE,
457 AU1200_UART0_INT = AU1200_FIRST_INT,
458 AU1200_SWT_INT,
459 AU1200_SD_INT,
460 AU1200_DDMA_INT,
461 AU1200_MAE_BE_INT,
462 AU1200_GPIO200_INT,
463 AU1200_GPIO201_INT,
464 AU1200_GPIO202_INT,
465 AU1200_UART1_INT,
466 AU1200_MAE_FE_INT,
467 AU1200_PSC0_INT,
468 AU1200_PSC1_INT,
469 AU1200_AES_INT,
470 AU1200_CAMERA_INT,
471 AU1200_TOY_INT,
472 AU1200_TOY_MATCH0_INT,
473 AU1200_TOY_MATCH1_INT,
474 AU1200_TOY_MATCH2_INT,
475 AU1200_RTC_INT,
476 AU1200_RTC_MATCH0_INT,
477 AU1200_RTC_MATCH1_INT,
478 AU1200_RTC_MATCH2_INT,
479 AU1200_GPIO203_INT,
480 AU1200_NAND_INT,
481 AU1200_GPIO204_INT,
482 AU1200_GPIO205_INT,
483 AU1200_GPIO206_INT,
484 AU1200_GPIO207_INT,
485 AU1200_GPIO208_215_INT, /* Logical OR of 208:215 */
486 AU1200_USB_INT,
487 AU1200_LCD_INT,
488 AU1200_MAE_BOTH_INT,
489 AU1200_GPIO0_INT,
490 AU1200_GPIO1_INT,
491 AU1200_GPIO2_INT,
492 AU1200_GPIO3_INT,
493 AU1200_GPIO4_INT,
494 AU1200_GPIO5_INT,
495 AU1200_GPIO6_INT,
496 AU1200_GPIO7_INT,
497 AU1200_GPIO8_INT,
498 AU1200_GPIO9_INT,
499 AU1200_GPIO10_INT,
500 AU1200_GPIO11_INT,
501 AU1200_GPIO12_INT,
502 AU1200_GPIO13_INT,
503 AU1200_GPIO14_INT,
504 AU1200_GPIO15_INT,
505 AU1200_GPIO16_INT,
506 AU1200_GPIO17_INT,
507 AU1200_GPIO18_INT,
508 AU1200_GPIO19_INT,
509 AU1200_GPIO20_INT,
510 AU1200_GPIO21_INT,
511 AU1200_GPIO22_INT,
512 AU1200_GPIO23_INT,
513 AU1200_GPIO24_INT,
514 AU1200_GPIO25_INT,
515 AU1200_GPIO26_INT,
516 AU1200_GPIO27_INT,
517 AU1200_GPIO28_INT,
518 AU1200_GPIO29_INT,
519 AU1200_GPIO30_INT,
520 AU1200_GPIO31_INT,
521};
160 522
161#endif /* !defined (_LANGUAGE_ASSEMBLY) */ 523#endif /* !defined (_LANGUAGE_ASSEMBLY) */
162 524
@@ -549,78 +911,16 @@ void au1xxx_setup_irqmap(struct au1xxx_irqmap *map, int count);
549 911
550#define IC1_TESTBIT 0xB1800080 912#define IC1_TESTBIT 0xB1800080
551 913
552/* Interrupt Numbers */ 914
553/* Au1000 */ 915/* Au1000 */
554#ifdef CONFIG_SOC_AU1000 916#ifdef CONFIG_SOC_AU1000
555enum soc_au1000_ints {
556 AU1000_FIRST_INT = MIPS_CPU_IRQ_BASE + 8,
557 AU1000_UART0_INT = AU1000_FIRST_INT,
558 AU1000_UART1_INT, /* au1000 */
559 AU1000_UART2_INT, /* au1000 */
560 AU1000_UART3_INT,
561 AU1000_SSI0_INT, /* au1000 */
562 AU1000_SSI1_INT, /* au1000 */
563 AU1000_DMA_INT_BASE,
564
565 AU1000_TOY_INT = AU1000_FIRST_INT + 14,
566 AU1000_TOY_MATCH0_INT,
567 AU1000_TOY_MATCH1_INT,
568 AU1000_TOY_MATCH2_INT,
569 AU1000_RTC_INT,
570 AU1000_RTC_MATCH0_INT,
571 AU1000_RTC_MATCH1_INT,
572 AU1000_RTC_MATCH2_INT,
573 AU1000_IRDA_TX_INT, /* au1000 */
574 AU1000_IRDA_RX_INT, /* au1000 */
575 AU1000_USB_DEV_REQ_INT,
576 AU1000_USB_DEV_SUS_INT,
577 AU1000_USB_HOST_INT,
578 AU1000_ACSYNC_INT,
579 AU1000_MAC0_DMA_INT,
580 AU1000_MAC1_DMA_INT,
581 AU1000_I2S_UO_INT, /* au1000 */
582 AU1000_AC97C_INT,
583 AU1000_GPIO_0,
584 AU1000_GPIO_1,
585 AU1000_GPIO_2,
586 AU1000_GPIO_3,
587 AU1000_GPIO_4,
588 AU1000_GPIO_5,
589 AU1000_GPIO_6,
590 AU1000_GPIO_7,
591 AU1000_GPIO_8,
592 AU1000_GPIO_9,
593 AU1000_GPIO_10,
594 AU1000_GPIO_11,
595 AU1000_GPIO_12,
596 AU1000_GPIO_13,
597 AU1000_GPIO_14,
598 AU1000_GPIO_15,
599 AU1000_GPIO_16,
600 AU1000_GPIO_17,
601 AU1000_GPIO_18,
602 AU1000_GPIO_19,
603 AU1000_GPIO_20,
604 AU1000_GPIO_21,
605 AU1000_GPIO_22,
606 AU1000_GPIO_23,
607 AU1000_GPIO_24,
608 AU1000_GPIO_25,
609 AU1000_GPIO_26,
610 AU1000_GPIO_27,
611 AU1000_GPIO_28,
612 AU1000_GPIO_29,
613 AU1000_GPIO_30,
614 AU1000_GPIO_31,
615};
616 917
617#define UART0_ADDR 0xB1100000 918#define UART0_ADDR 0xB1100000
618#define UART1_ADDR 0xB1200000
619#define UART2_ADDR 0xB1300000
620#define UART3_ADDR 0xB1400000 919#define UART3_ADDR 0xB1400000
621 920
622#define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */ 921#define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */
623#define USB_HOST_CONFIG 0xB017FFFC 922#define USB_HOST_CONFIG 0xB017FFFC
923#define FOR_PLATFORM_C_USB_HOST_INT AU1000_USB_HOST_INT
624 924
625#define AU1000_ETH0_BASE 0xB0500000 925#define AU1000_ETH0_BASE 0xB0500000
626#define AU1000_ETH1_BASE 0xB0510000 926#define AU1000_ETH1_BASE 0xB0510000
@@ -631,78 +931,13 @@ enum soc_au1000_ints {
631 931
632/* Au1500 */ 932/* Au1500 */
633#ifdef CONFIG_SOC_AU1500 933#ifdef CONFIG_SOC_AU1500
634enum soc_au1500_ints {
635 AU1500_FIRST_INT = MIPS_CPU_IRQ_BASE + 8,
636 AU1500_UART0_INT = AU1500_FIRST_INT,
637 AU1000_PCI_INTA, /* au1500 */
638 AU1000_PCI_INTB, /* au1500 */
639 AU1500_UART3_INT,
640 AU1000_PCI_INTC, /* au1500 */
641 AU1000_PCI_INTD, /* au1500 */
642 AU1000_DMA_INT_BASE,
643
644 AU1000_TOY_INT = AU1500_FIRST_INT + 14,
645 AU1000_TOY_MATCH0_INT,
646 AU1000_TOY_MATCH1_INT,
647 AU1000_TOY_MATCH2_INT,
648 AU1000_RTC_INT,
649 AU1000_RTC_MATCH0_INT,
650 AU1000_RTC_MATCH1_INT,
651 AU1000_RTC_MATCH2_INT,
652 AU1500_PCI_ERR_INT,
653 AU1500_RESERVED_INT,
654 AU1000_USB_DEV_REQ_INT,
655 AU1000_USB_DEV_SUS_INT,
656 AU1000_USB_HOST_INT,
657 AU1000_ACSYNC_INT,
658 AU1500_MAC0_DMA_INT,
659 AU1500_MAC1_DMA_INT,
660 AU1000_AC97C_INT = AU1500_FIRST_INT + 31,
661 AU1000_GPIO_0,
662 AU1000_GPIO_1,
663 AU1000_GPIO_2,
664 AU1000_GPIO_3,
665 AU1000_GPIO_4,
666 AU1000_GPIO_5,
667 AU1000_GPIO_6,
668 AU1000_GPIO_7,
669 AU1000_GPIO_8,
670 AU1000_GPIO_9,
671 AU1000_GPIO_10,
672 AU1000_GPIO_11,
673 AU1000_GPIO_12,
674 AU1000_GPIO_13,
675 AU1000_GPIO_14,
676 AU1000_GPIO_15,
677 AU1500_GPIO_200,
678 AU1500_GPIO_201,
679 AU1500_GPIO_202,
680 AU1500_GPIO_203,
681 AU1500_GPIO_20,
682 AU1500_GPIO_204,
683 AU1500_GPIO_205,
684 AU1500_GPIO_23,
685 AU1500_GPIO_24,
686 AU1500_GPIO_25,
687 AU1500_GPIO_26,
688 AU1500_GPIO_27,
689 AU1500_GPIO_28,
690 AU1500_GPIO_206,
691 AU1500_GPIO_207,
692 AU1500_GPIO_208_215,
693};
694
695/* shortcuts */
696#define INTA AU1000_PCI_INTA
697#define INTB AU1000_PCI_INTB
698#define INTC AU1000_PCI_INTC
699#define INTD AU1000_PCI_INTD
700 934
701#define UART0_ADDR 0xB1100000 935#define UART0_ADDR 0xB1100000
702#define UART3_ADDR 0xB1400000 936#define UART3_ADDR 0xB1400000
703 937
704#define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */ 938#define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */
705#define USB_HOST_CONFIG 0xB017fffc 939#define USB_HOST_CONFIG 0xB017fffc
940#define FOR_PLATFORM_C_USB_HOST_INT AU1500_USB_HOST_INT
706 941
707#define AU1500_ETH0_BASE 0xB1500000 942#define AU1500_ETH0_BASE 0xB1500000
708#define AU1500_ETH1_BASE 0xB1510000 943#define AU1500_ETH1_BASE 0xB1510000
@@ -713,74 +948,13 @@ enum soc_au1500_ints {
713 948
714/* Au1100 */ 949/* Au1100 */
715#ifdef CONFIG_SOC_AU1100 950#ifdef CONFIG_SOC_AU1100
716enum soc_au1100_ints {
717 AU1100_FIRST_INT = MIPS_CPU_IRQ_BASE + 8,
718 AU1100_UART0_INT = AU1100_FIRST_INT,
719 AU1100_UART1_INT,
720 AU1100_SD_INT,
721 AU1100_UART3_INT,
722 AU1000_SSI0_INT,
723 AU1000_SSI1_INT,
724 AU1000_DMA_INT_BASE,
725
726 AU1000_TOY_INT = AU1100_FIRST_INT + 14,
727 AU1000_TOY_MATCH0_INT,
728 AU1000_TOY_MATCH1_INT,
729 AU1000_TOY_MATCH2_INT,
730 AU1000_RTC_INT,
731 AU1000_RTC_MATCH0_INT,
732 AU1000_RTC_MATCH1_INT,
733 AU1000_RTC_MATCH2_INT,
734 AU1000_IRDA_TX_INT,
735 AU1000_IRDA_RX_INT,
736 AU1000_USB_DEV_REQ_INT,
737 AU1000_USB_DEV_SUS_INT,
738 AU1000_USB_HOST_INT,
739 AU1000_ACSYNC_INT,
740 AU1100_MAC0_DMA_INT,
741 AU1100_GPIO_208_215,
742 AU1100_LCD_INT,
743 AU1000_AC97C_INT,
744 AU1000_GPIO_0,
745 AU1000_GPIO_1,
746 AU1000_GPIO_2,
747 AU1000_GPIO_3,
748 AU1000_GPIO_4,
749 AU1000_GPIO_5,
750 AU1000_GPIO_6,
751 AU1000_GPIO_7,
752 AU1000_GPIO_8,
753 AU1000_GPIO_9,
754 AU1000_GPIO_10,
755 AU1000_GPIO_11,
756 AU1000_GPIO_12,
757 AU1000_GPIO_13,
758 AU1000_GPIO_14,
759 AU1000_GPIO_15,
760 AU1000_GPIO_16,
761 AU1000_GPIO_17,
762 AU1000_GPIO_18,
763 AU1000_GPIO_19,
764 AU1000_GPIO_20,
765 AU1000_GPIO_21,
766 AU1000_GPIO_22,
767 AU1000_GPIO_23,
768 AU1000_GPIO_24,
769 AU1000_GPIO_25,
770 AU1000_GPIO_26,
771 AU1000_GPIO_27,
772 AU1000_GPIO_28,
773 AU1000_GPIO_29,
774 AU1000_GPIO_30,
775 AU1000_GPIO_31,
776};
777 951
778#define UART0_ADDR 0xB1100000 952#define UART0_ADDR 0xB1100000
779#define UART1_ADDR 0xB1200000
780#define UART3_ADDR 0xB1400000 953#define UART3_ADDR 0xB1400000
781 954
782#define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */ 955#define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */
783#define USB_HOST_CONFIG 0xB017FFFC 956#define USB_HOST_CONFIG 0xB017FFFC
957#define FOR_PLATFORM_C_USB_HOST_INT AU1100_USB_HOST_INT
784 958
785#define AU1100_ETH0_BASE 0xB0500000 959#define AU1100_ETH0_BASE 0xB0500000
786#define AU1100_MAC0_ENABLE 0xB0520000 960#define AU1100_MAC0_ENABLE 0xB0520000
@@ -788,87 +962,12 @@ enum soc_au1100_ints {
788#endif /* CONFIG_SOC_AU1100 */ 962#endif /* CONFIG_SOC_AU1100 */
789 963
790#ifdef CONFIG_SOC_AU1550 964#ifdef CONFIG_SOC_AU1550
791enum soc_au1550_ints {
792 AU1550_FIRST_INT = MIPS_CPU_IRQ_BASE + 8,
793 AU1550_UART0_INT = AU1550_FIRST_INT,
794 AU1550_PCI_INTA,
795 AU1550_PCI_INTB,
796 AU1550_DDMA_INT,
797 AU1550_CRYPTO_INT,
798 AU1550_PCI_INTC,
799 AU1550_PCI_INTD,
800 AU1550_PCI_RST_INT,
801 AU1550_UART1_INT,
802 AU1550_UART3_INT,
803 AU1550_PSC0_INT,
804 AU1550_PSC1_INT,
805 AU1550_PSC2_INT,
806 AU1550_PSC3_INT,
807 AU1000_TOY_INT,
808 AU1000_TOY_MATCH0_INT,
809 AU1000_TOY_MATCH1_INT,
810 AU1000_TOY_MATCH2_INT,
811 AU1000_RTC_INT,
812 AU1000_RTC_MATCH0_INT,
813 AU1000_RTC_MATCH1_INT,
814 AU1000_RTC_MATCH2_INT,
815
816 AU1550_NAND_INT = AU1550_FIRST_INT + 23,
817 AU1550_USB_DEV_REQ_INT,
818 AU1000_USB_DEV_REQ_INT = AU1550_USB_DEV_REQ_INT,
819 AU1550_USB_DEV_SUS_INT,
820 AU1000_USB_DEV_SUS_INT = AU1550_USB_DEV_SUS_INT,
821 AU1550_USB_HOST_INT,
822 AU1000_USB_HOST_INT = AU1550_USB_HOST_INT,
823 AU1550_MAC0_DMA_INT,
824 AU1550_MAC1_DMA_INT,
825 AU1000_GPIO_0 = AU1550_FIRST_INT + 32,
826 AU1000_GPIO_1,
827 AU1000_GPIO_2,
828 AU1000_GPIO_3,
829 AU1000_GPIO_4,
830 AU1000_GPIO_5,
831 AU1000_GPIO_6,
832 AU1000_GPIO_7,
833 AU1000_GPIO_8,
834 AU1000_GPIO_9,
835 AU1000_GPIO_10,
836 AU1000_GPIO_11,
837 AU1000_GPIO_12,
838 AU1000_GPIO_13,
839 AU1000_GPIO_14,
840 AU1000_GPIO_15,
841 AU1550_GPIO_200,
842 AU1500_GPIO_201_205, /* Logical or of GPIO201:205 */
843 AU1500_GPIO_16,
844 AU1500_GPIO_17,
845 AU1500_GPIO_20,
846 AU1500_GPIO_21,
847 AU1500_GPIO_22,
848 AU1500_GPIO_23,
849 AU1500_GPIO_24,
850 AU1500_GPIO_25,
851 AU1500_GPIO_26,
852 AU1500_GPIO_27,
853 AU1500_GPIO_28,
854 AU1500_GPIO_206,
855 AU1500_GPIO_207,
856 AU1500_GPIO_208_218, /* Logical or of GPIO208:218 */
857};
858
859/* shortcuts */
860#define INTA AU1550_PCI_INTA
861#define INTB AU1550_PCI_INTB
862#define INTC AU1550_PCI_INTC
863#define INTD AU1550_PCI_INTD
864
865#define UART0_ADDR 0xB1100000 965#define UART0_ADDR 0xB1100000
866#define UART1_ADDR 0xB1200000
867#define UART3_ADDR 0xB1400000
868 966
869#define USB_OHCI_BASE 0x14020000 /* phys addr for ioremap */ 967#define USB_OHCI_BASE 0x14020000 /* phys addr for ioremap */
870#define USB_OHCI_LEN 0x00060000 968#define USB_OHCI_LEN 0x00060000
871#define USB_HOST_CONFIG 0xB4027ffc 969#define USB_HOST_CONFIG 0xB4027ffc
970#define FOR_PLATFORM_C_USB_HOST_INT AU1550_USB_HOST_INT
872 971
873#define AU1550_ETH0_BASE 0xB0500000 972#define AU1550_ETH0_BASE 0xB0500000
874#define AU1550_ETH1_BASE 0xB0510000 973#define AU1550_ETH1_BASE 0xB0510000
@@ -877,78 +976,10 @@ enum soc_au1550_ints {
877#define NUM_ETH_INTERFACES 2 976#define NUM_ETH_INTERFACES 2
878#endif /* CONFIG_SOC_AU1550 */ 977#endif /* CONFIG_SOC_AU1550 */
879 978
979
880#ifdef CONFIG_SOC_AU1200 980#ifdef CONFIG_SOC_AU1200
881enum soc_au1200_ints {
882 AU1200_FIRST_INT = MIPS_CPU_IRQ_BASE + 8,
883 AU1200_UART0_INT = AU1200_FIRST_INT,
884 AU1200_SWT_INT,
885 AU1200_SD_INT,
886 AU1200_DDMA_INT,
887 AU1200_MAE_BE_INT,
888 AU1200_GPIO_200,
889 AU1200_GPIO_201,
890 AU1200_GPIO_202,
891 AU1200_UART1_INT,
892 AU1200_MAE_FE_INT,
893 AU1200_PSC0_INT,
894 AU1200_PSC1_INT,
895 AU1200_AES_INT,
896 AU1200_CAMERA_INT,
897 AU1000_TOY_INT,
898 AU1000_TOY_MATCH0_INT,
899 AU1000_TOY_MATCH1_INT,
900 AU1000_TOY_MATCH2_INT,
901 AU1000_RTC_INT,
902 AU1000_RTC_MATCH0_INT,
903 AU1000_RTC_MATCH1_INT,
904 AU1000_RTC_MATCH2_INT,
905 AU1200_GPIO_203,
906 AU1200_NAND_INT,
907 AU1200_GPIO_204,
908 AU1200_GPIO_205,
909 AU1200_GPIO_206,
910 AU1200_GPIO_207,
911 AU1200_GPIO_208_215, /* Logical OR of 208:215 */
912 AU1200_USB_INT,
913 AU1000_USB_HOST_INT = AU1200_USB_INT,
914 AU1200_LCD_INT,
915 AU1200_MAE_BOTH_INT,
916 AU1000_GPIO_0,
917 AU1000_GPIO_1,
918 AU1000_GPIO_2,
919 AU1000_GPIO_3,
920 AU1000_GPIO_4,
921 AU1000_GPIO_5,
922 AU1000_GPIO_6,
923 AU1000_GPIO_7,
924 AU1000_GPIO_8,
925 AU1000_GPIO_9,
926 AU1000_GPIO_10,
927 AU1000_GPIO_11,
928 AU1000_GPIO_12,
929 AU1000_GPIO_13,
930 AU1000_GPIO_14,
931 AU1000_GPIO_15,
932 AU1000_GPIO_16,
933 AU1000_GPIO_17,
934 AU1000_GPIO_18,
935 AU1000_GPIO_19,
936 AU1000_GPIO_20,
937 AU1000_GPIO_21,
938 AU1000_GPIO_22,
939 AU1000_GPIO_23,
940 AU1000_GPIO_24,
941 AU1000_GPIO_25,
942 AU1000_GPIO_26,
943 AU1000_GPIO_27,
944 AU1000_GPIO_28,
945 AU1000_GPIO_29,
946 AU1000_GPIO_30,
947 AU1000_GPIO_31,
948};
949 981
950#define UART0_ADDR 0xB1100000 982#define UART0_ADDR 0xB1100000
951#define UART1_ADDR 0xB1200000
952 983
953#define USB_UOC_BASE 0x14020020 984#define USB_UOC_BASE 0x14020020
954#define USB_UOC_LEN 0x20 985#define USB_UOC_LEN 0x20
@@ -974,15 +1005,9 @@ enum soc_au1200_ints {
974#define USBMSRMCFG_RDCOMB 30 1005#define USBMSRMCFG_RDCOMB 30
975#define USBMSRMCFG_PFEN 31 1006#define USBMSRMCFG_PFEN 31
976 1007
977#endif /* CONFIG_SOC_AU1200 */ 1008#define FOR_PLATFORM_C_USB_HOST_INT AU1200_USB_INT
978
979#define AU1000_INTC0_INT_BASE (MIPS_CPU_IRQ_BASE + 8)
980#define AU1000_INTC0_INT_LAST (AU1000_INTC0_INT_BASE + 31)
981#define AU1000_INTC1_INT_BASE (AU1000_INTC0_INT_BASE + 32)
982#define AU1000_INTC1_INT_LAST (AU1000_INTC1_INT_BASE + 31)
983 1009
984#define AU1000_MAX_INTR AU1000_INTC1_INT_LAST 1010#endif /* CONFIG_SOC_AU1200 */
985#define INTX 0xFF /* not valid */
986 1011
987/* Programmable Counters 0 and 1 */ 1012/* Programmable Counters 0 and 1 */
988#define SYS_BASE 0xB1900000 1013#define SYS_BASE 0xB1900000
@@ -1231,14 +1256,6 @@ enum soc_au1200_ints {
1231#define MAC_RX_BUFF3_STATUS 0x30 1256#define MAC_RX_BUFF3_STATUS 0x30
1232#define MAC_RX_BUFF3_ADDR 0x34 1257#define MAC_RX_BUFF3_ADDR 0x34
1233 1258
1234/* UARTS 0-3 */
1235#define UART_BASE UART0_ADDR
1236#ifdef CONFIG_SOC_AU1200
1237#define UART_DEBUG_BASE UART1_ADDR
1238#else
1239#define UART_DEBUG_BASE UART3_ADDR
1240#endif
1241
1242#define UART_RX 0 /* Receive buffer */ 1259#define UART_RX 0 /* Receive buffer */
1243#define UART_TX 4 /* Transmit buffer */ 1260#define UART_TX 4 /* Transmit buffer */
1244#define UART_IER 8 /* Interrupt Enable Register */ 1261#define UART_IER 8 /* Interrupt Enable Register */
@@ -1251,84 +1268,6 @@ enum soc_au1200_ints {
1251#define UART_CLK 0x28 /* Baud Rate Clock Divider */ 1268#define UART_CLK 0x28 /* Baud Rate Clock Divider */
1252#define UART_MOD_CNTRL 0x100 /* Module Control */ 1269#define UART_MOD_CNTRL 0x100 /* Module Control */
1253 1270
1254#define UART_FCR_ENABLE_FIFO 0x01 /* Enable the FIFO */
1255#define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */
1256#define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */
1257#define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */
1258#define UART_FCR_TRIGGER_MASK 0xF0 /* Mask for the FIFO trigger range */
1259#define UART_FCR_R_TRIGGER_1 0x00 /* Mask for receive trigger set at 1 */
1260#define UART_FCR_R_TRIGGER_4 0x40 /* Mask for receive trigger set at 4 */
1261#define UART_FCR_R_TRIGGER_8 0x80 /* Mask for receive trigger set at 8 */
1262#define UART_FCR_R_TRIGGER_14 0xA0 /* Mask for receive trigger set at 14 */
1263#define UART_FCR_T_TRIGGER_0 0x00 /* Mask for transmit trigger set at 0 */
1264#define UART_FCR_T_TRIGGER_4 0x10 /* Mask for transmit trigger set at 4 */
1265#define UART_FCR_T_TRIGGER_8 0x20 /* Mask for transmit trigger set at 8 */
1266#define UART_FCR_T_TRIGGER_12 0x30 /* Mask for transmit trigger set at 12 */
1267
1268/*
1269 * These are the definitions for the Line Control Register
1270 */
1271#define UART_LCR_SBC 0x40 /* Set break control */
1272#define UART_LCR_SPAR 0x20 /* Stick parity (?) */
1273#define UART_LCR_EPAR 0x10 /* Even parity select */
1274#define UART_LCR_PARITY 0x08 /* Parity Enable */
1275#define UART_LCR_STOP 0x04 /* Stop bits: 0=1 stop bit, 1= 2 stop bits */
1276#define UART_LCR_WLEN5 0x00 /* Wordlength: 5 bits */
1277#define UART_LCR_WLEN6 0x01 /* Wordlength: 6 bits */
1278#define UART_LCR_WLEN7 0x02 /* Wordlength: 7 bits */
1279#define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */
1280
1281/*
1282 * These are the definitions for the Line Status Register
1283 */
1284#define UART_LSR_TEMT 0x40 /* Transmitter empty */
1285#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
1286#define UART_LSR_BI 0x10 /* Break interrupt indicator */
1287#define UART_LSR_FE 0x08 /* Frame error indicator */
1288#define UART_LSR_PE 0x04 /* Parity error indicator */
1289#define UART_LSR_OE 0x02 /* Overrun error indicator */
1290#define UART_LSR_DR 0x01 /* Receiver data ready */
1291
1292/*
1293 * These are the definitions for the Interrupt Identification Register
1294 */
1295#define UART_IIR_NO_INT 0x01 /* No interrupts pending */
1296#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
1297#define UART_IIR_MSI 0x00 /* Modem status interrupt */
1298#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
1299#define UART_IIR_RDI 0x04 /* Receiver data interrupt */
1300#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
1301
1302/*
1303 * These are the definitions for the Interrupt Enable Register
1304 */
1305#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
1306#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
1307#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
1308#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
1309
1310/*
1311 * These are the definitions for the Modem Control Register
1312 */
1313#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
1314#define UART_MCR_OUT2 0x08 /* Out2 complement */
1315#define UART_MCR_OUT1 0x04 /* Out1 complement */
1316#define UART_MCR_RTS 0x02 /* RTS complement */
1317#define UART_MCR_DTR 0x01 /* DTR complement */
1318
1319/*
1320 * These are the definitions for the Modem Status Register
1321 */
1322#define UART_MSR_DCD 0x80 /* Data Carrier Detect */
1323#define UART_MSR_RI 0x40 /* Ring Indicator */
1324#define UART_MSR_DSR 0x20 /* Data Set Ready */
1325#define UART_MSR_CTS 0x10 /* Clear to Send */
1326#define UART_MSR_DDCD 0x08 /* Delta DCD */
1327#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
1328#define UART_MSR_DDSR 0x02 /* Delta DSR */
1329#define UART_MSR_DCTS 0x01 /* Delta CTS */
1330#define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
1331
1332/* SSIO */ 1271/* SSIO */
1333#define SSI0_STATUS 0xB1600000 1272#define SSI0_STATUS 0xB1600000
1334# define SSI_STATUS_BF (1 << 4) 1273# define SSI_STATUS_BF (1 << 4)
@@ -1720,7 +1659,7 @@ enum soc_au1200_ints {
1720#define IOPORT_RESOURCE_START 0x00001000 /* skip legacy probing */ 1659#define IOPORT_RESOURCE_START 0x00001000 /* skip legacy probing */
1721#define IOPORT_RESOURCE_END 0xffffffff 1660#define IOPORT_RESOURCE_END 0xffffffff
1722#define IOMEM_RESOURCE_START 0x10000000 1661#define IOMEM_RESOURCE_START 0x10000000
1723#define IOMEM_RESOURCE_END 0xffffffff 1662#define IOMEM_RESOURCE_END 0xfffffffffULL
1724 1663
1725#else /* Au1000 and Au1100 and Au1200 */ 1664#else /* Au1000 and Au1100 and Au1200 */
1726 1665
@@ -1728,7 +1667,7 @@ enum soc_au1200_ints {
1728#define IOPORT_RESOURCE_START 0x10000000 1667#define IOPORT_RESOURCE_START 0x10000000
1729#define IOPORT_RESOURCE_END 0xffffffff 1668#define IOPORT_RESOURCE_END 0xffffffff
1730#define IOMEM_RESOURCE_START 0x10000000 1669#define IOMEM_RESOURCE_START 0x10000000
1731#define IOMEM_RESOURCE_END 0xffffffff 1670#define IOMEM_RESOURCE_END 0xfffffffffULL
1732 1671
1733#define PCI_IO_START 0 1672#define PCI_IO_START 0
1734#define PCI_IO_END 0 1673#define PCI_IO_END 0
@@ -1739,53 +1678,4 @@ enum soc_au1200_ints {
1739 1678
1740#endif 1679#endif
1741 1680
1742#ifndef _LANGUAGE_ASSEMBLY
1743typedef volatile struct {
1744 /* 0x0000 */ u32 toytrim;
1745 /* 0x0004 */ u32 toywrite;
1746 /* 0x0008 */ u32 toymatch0;
1747 /* 0x000C */ u32 toymatch1;
1748 /* 0x0010 */ u32 toymatch2;
1749 /* 0x0014 */ u32 cntrctrl;
1750 /* 0x0018 */ u32 scratch0;
1751 /* 0x001C */ u32 scratch1;
1752 /* 0x0020 */ u32 freqctrl0;
1753 /* 0x0024 */ u32 freqctrl1;
1754 /* 0x0028 */ u32 clksrc;
1755 /* 0x002C */ u32 pinfunc;
1756 /* 0x0030 */ u32 reserved0;
1757 /* 0x0034 */ u32 wakemsk;
1758 /* 0x0038 */ u32 endian;
1759 /* 0x003C */ u32 powerctrl;
1760 /* 0x0040 */ u32 toyread;
1761 /* 0x0044 */ u32 rtctrim;
1762 /* 0x0048 */ u32 rtcwrite;
1763 /* 0x004C */ u32 rtcmatch0;
1764 /* 0x0050 */ u32 rtcmatch1;
1765 /* 0x0054 */ u32 rtcmatch2;
1766 /* 0x0058 */ u32 rtcread;
1767 /* 0x005C */ u32 wakesrc;
1768 /* 0x0060 */ u32 cpupll;
1769 /* 0x0064 */ u32 auxpll;
1770 /* 0x0068 */ u32 reserved1;
1771 /* 0x006C */ u32 reserved2;
1772 /* 0x0070 */ u32 reserved3;
1773 /* 0x0074 */ u32 reserved4;
1774 /* 0x0078 */ u32 slppwr;
1775 /* 0x007C */ u32 sleep;
1776 /* 0x0080 */ u32 reserved5[32];
1777 /* 0x0100 */ u32 trioutrd;
1778#define trioutclr trioutrd
1779 /* 0x0104 */ u32 reserved6;
1780 /* 0x0108 */ u32 outputrd;
1781#define outputset outputrd
1782 /* 0x010C */ u32 outputclr;
1783 /* 0x0110 */ u32 pinstaterd;
1784#define pininputen pinstaterd
1785} AU1X00_SYS;
1786
1787static AU1X00_SYS * const sys = (AU1X00_SYS *)SYS_BASE;
1788
1789#endif
1790
1791#endif 1681#endif
diff --git a/arch/mips/include/asm/mach-au1x00/au1100_mmc.h b/arch/mips/include/asm/mach-au1x00/au1100_mmc.h
index c35e20918490..94000a3b6f0b 100644
--- a/arch/mips/include/asm/mach-au1x00/au1100_mmc.h
+++ b/arch/mips/include/asm/mach-au1x00/au1100_mmc.h
@@ -46,6 +46,7 @@ struct au1xmmc_platform_data {
46 int(*card_readonly)(void *mmc_host); 46 int(*card_readonly)(void *mmc_host);
47 void(*set_power)(void *mmc_host, int state); 47 void(*set_power)(void *mmc_host, int state);
48 struct led_classdev *led; 48 struct led_classdev *led;
49 unsigned long mask_host_caps;
49}; 50};
50 51
51#define SD0_BASE 0xB0600000 52#define SD0_BASE 0xB0600000
@@ -205,4 +206,3 @@ struct au1xmmc_platform_data {
205 206
206 207
207#endif /* __ASM_AU1100_MMC_H */ 208#endif /* __ASM_AU1100_MMC_H */
208
diff --git a/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h b/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h
index 06f68f43800a..8c6b1105ce0b 100644
--- a/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h
+++ b/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h
@@ -305,6 +305,7 @@ typedef struct dbdma_chan_config {
305 dbdev_tab_t *chan_dest; 305 dbdev_tab_t *chan_dest;
306 au1x_dma_chan_t *chan_ptr; 306 au1x_dma_chan_t *chan_ptr;
307 au1x_ddma_desc_t *chan_desc_base; 307 au1x_ddma_desc_t *chan_desc_base;
308 u32 cdb_membase; /* kmalloc base of above */
308 au1x_ddma_desc_t *get_ptr, *put_ptr, *cur_ptr; 309 au1x_ddma_desc_t *get_ptr, *put_ptr, *cur_ptr;
309 void *chan_callparam; 310 void *chan_callparam;
310 void (*chan_callback)(int, void *); 311 void (*chan_callback)(int, void *);
@@ -338,8 +339,8 @@ u32 au1xxx_dbdma_set_devwidth(u32 chanid, int bits);
338u32 au1xxx_dbdma_ring_alloc(u32 chanid, int entries); 339u32 au1xxx_dbdma_ring_alloc(u32 chanid, int entries);
339 340
340/* Put buffers on source/destination descriptors. */ 341/* Put buffers on source/destination descriptors. */
341u32 _au1xxx_dbdma_put_source(u32 chanid, void *buf, int nbytes, u32 flags); 342u32 au1xxx_dbdma_put_source(u32 chanid, dma_addr_t buf, int nbytes, u32 flags);
342u32 _au1xxx_dbdma_put_dest(u32 chanid, void *buf, int nbytes, u32 flags); 343u32 au1xxx_dbdma_put_dest(u32 chanid, dma_addr_t buf, int nbytes, u32 flags);
343 344
344/* Get a buffer from the destination descriptor. */ 345/* Get a buffer from the destination descriptor. */
345u32 au1xxx_dbdma_get_dest(u32 chanid, void **buf, int *nbytes); 346u32 au1xxx_dbdma_get_dest(u32 chanid, void **buf, int *nbytes);
@@ -362,25 +363,6 @@ void au1xxx_dbdma_suspend(void);
362void au1xxx_dbdma_resume(void); 363void au1xxx_dbdma_resume(void);
363#endif 364#endif
364 365
365
366/*
367 * Some compatibilty macros -- needed to make changes to API
368 * without breaking existing drivers.
369 */
370#define au1xxx_dbdma_put_source(chanid, buf, nbytes) \
371 _au1xxx_dbdma_put_source(chanid, buf, nbytes, DDMA_FLAGS_IE)
372#define au1xxx_dbdma_put_source_flags(chanid, buf, nbytes, flags) \
373 _au1xxx_dbdma_put_source(chanid, buf, nbytes, flags)
374#define put_source_flags(chanid, buf, nbytes, flags) \
375 au1xxx_dbdma_put_source_flags(chanid, buf, nbytes, flags)
376
377#define au1xxx_dbdma_put_dest(chanid, buf, nbytes) \
378 _au1xxx_dbdma_put_dest(chanid, buf, nbytes, DDMA_FLAGS_IE)
379#define au1xxx_dbdma_put_dest_flags(chanid, buf, nbytes, flags) \
380 _au1xxx_dbdma_put_dest(chanid, buf, nbytes, flags)
381#define put_dest_flags(chanid, buf, nbytes, flags) \
382 au1xxx_dbdma_put_dest_flags(chanid, buf, nbytes, flags)
383
384/* 366/*
385 * Flags for the put_source/put_dest functions. 367 * Flags for the put_source/put_dest functions.
386 */ 368 */
diff --git a/arch/mips/include/asm/mach-au1x00/au1xxx_eth.h b/arch/mips/include/asm/mach-au1x00/au1xxx_eth.h
new file mode 100644
index 000000000000..bae9b758fcde
--- /dev/null
+++ b/arch/mips/include/asm/mach-au1x00/au1xxx_eth.h
@@ -0,0 +1,17 @@
1#ifndef __AU1X00_ETH_DATA_H
2#define __AU1X00_ETH_DATA_H
3
4/* Platform specific PHY configuration passed to the MAC driver */
5struct au1000_eth_platform_data {
6 int phy_static_config;
7 int phy_search_highest_addr;
8 int phy1_search_mac0;
9 int phy_addr;
10 int phy_busid;
11 int phy_irq;
12};
13
14void __init au1xxx_override_eth_cfg(unsigned port,
15 struct au1000_eth_platform_data *eth_data);
16
17#endif /* __AU1X00_ETH_DATA_H */
diff --git a/arch/mips/include/asm/mach-au1x00/gpio-au1000.h b/arch/mips/include/asm/mach-au1x00/gpio-au1000.h
index 91595fa89034..62d2f136d941 100644
--- a/arch/mips/include/asm/mach-au1x00/gpio-au1000.h
+++ b/arch/mips/include/asm/mach-au1x00/gpio-au1000.h
@@ -35,15 +35,13 @@ static inline int au1000_gpio2_to_irq(int gpio)
35 return -ENXIO; 35 return -ENXIO;
36} 36}
37 37
38#ifdef CONFIG_SOC_AU1000
39static inline int au1000_irq_to_gpio(int irq) 38static inline int au1000_irq_to_gpio(int irq)
40{ 39{
41 if ((irq >= AU1000_GPIO_0) && (irq <= AU1000_GPIO_31)) 40 if ((irq >= AU1000_GPIO0_INT) && (irq <= AU1000_GPIO31_INT))
42 return ALCHEMY_GPIO1_BASE + (irq - AU1000_GPIO_0) + 0; 41 return ALCHEMY_GPIO1_BASE + (irq - AU1000_GPIO0_INT) + 0;
43 42
44 return -ENXIO; 43 return -ENXIO;
45} 44}
46#endif
47 45
48static inline int au1500_gpio1_to_irq(int gpio) 46static inline int au1500_gpio1_to_irq(int gpio)
49{ 47{
@@ -71,27 +69,25 @@ static inline int au1500_gpio2_to_irq(int gpio)
71 return -ENXIO; 69 return -ENXIO;
72} 70}
73 71
74#ifdef CONFIG_SOC_AU1500
75static inline int au1500_irq_to_gpio(int irq) 72static inline int au1500_irq_to_gpio(int irq)
76{ 73{
77 switch (irq) { 74 switch (irq) {
78 case AU1000_GPIO_0 ... AU1000_GPIO_15: 75 case AU1500_GPIO0_INT ... AU1500_GPIO15_INT:
79 case AU1500_GPIO_20: 76 case AU1500_GPIO20_INT:
80 case AU1500_GPIO_23 ... AU1500_GPIO_28: 77 case AU1500_GPIO23_INT ... AU1500_GPIO28_INT:
81 return ALCHEMY_GPIO1_BASE + (irq - AU1000_GPIO_0) + 0; 78 return ALCHEMY_GPIO1_BASE + (irq - AU1500_GPIO0_INT) + 0;
82 case AU1500_GPIO_200 ... AU1500_GPIO_203: 79 case AU1500_GPIO200_INT ... AU1500_GPIO203_INT:
83 return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO_200) + 0; 80 return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO200_INT) + 0;
84 case AU1500_GPIO_204 ... AU1500_GPIO_205: 81 case AU1500_GPIO204_INT ... AU1500_GPIO205_INT:
85 return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO_204) + 4; 82 return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO204_INT) + 4;
86 case AU1500_GPIO_206 ... AU1500_GPIO_207: 83 case AU1500_GPIO206_INT ... AU1500_GPIO207_INT:
87 return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO_206) + 6; 84 return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO206_INT) + 6;
88 case AU1500_GPIO_208_215: 85 case AU1500_GPIO208_215_INT:
89 return ALCHEMY_GPIO2_BASE + 8; 86 return ALCHEMY_GPIO2_BASE + 8;
90 } 87 }
91 88
92 return -ENXIO; 89 return -ENXIO;
93} 90}
94#endif
95 91
96static inline int au1100_gpio1_to_irq(int gpio) 92static inline int au1100_gpio1_to_irq(int gpio)
97{ 93{
@@ -108,19 +104,17 @@ static inline int au1100_gpio2_to_irq(int gpio)
108 return -ENXIO; 104 return -ENXIO;
109} 105}
110 106
111#ifdef CONFIG_SOC_AU1100
112static inline int au1100_irq_to_gpio(int irq) 107static inline int au1100_irq_to_gpio(int irq)
113{ 108{
114 switch (irq) { 109 switch (irq) {
115 case AU1000_GPIO_0 ... AU1000_GPIO_31: 110 case AU1100_GPIO0_INT ... AU1100_GPIO31_INT:
116 return ALCHEMY_GPIO1_BASE + (irq - AU1000_GPIO_0) + 0; 111 return ALCHEMY_GPIO1_BASE + (irq - AU1100_GPIO0_INT) + 0;
117 case AU1100_GPIO_208_215: 112 case AU1100_GPIO208_215_INT:
118 return ALCHEMY_GPIO2_BASE + 8; 113 return ALCHEMY_GPIO2_BASE + 8;
119 } 114 }
120 115
121 return -ENXIO; 116 return -ENXIO;
122} 117}
123#endif
124 118
125static inline int au1550_gpio1_to_irq(int gpio) 119static inline int au1550_gpio1_to_irq(int gpio)
126{ 120{
@@ -149,24 +143,22 @@ static inline int au1550_gpio2_to_irq(int gpio)
149 return -ENXIO; 143 return -ENXIO;
150} 144}
151 145
152#ifdef CONFIG_SOC_AU1550
153static inline int au1550_irq_to_gpio(int irq) 146static inline int au1550_irq_to_gpio(int irq)
154{ 147{
155 switch (irq) { 148 switch (irq) {
156 case AU1000_GPIO_0 ... AU1000_GPIO_15: 149 case AU1550_GPIO0_INT ... AU1550_GPIO15_INT:
157 return ALCHEMY_GPIO1_BASE + (irq - AU1000_GPIO_0) + 0; 150 return ALCHEMY_GPIO1_BASE + (irq - AU1550_GPIO0_INT) + 0;
158 case AU1550_GPIO_200: 151 case AU1550_GPIO200_INT:
159 case AU1500_GPIO_201_205: 152 case AU1550_GPIO201_205_INT:
160 return ALCHEMY_GPIO2_BASE + (irq - AU1550_GPIO_200) + 0; 153 return ALCHEMY_GPIO2_BASE + (irq - AU1550_GPIO200_INT) + 0;
161 case AU1500_GPIO_16 ... AU1500_GPIO_28: 154 case AU1550_GPIO16_INT ... AU1550_GPIO28_INT:
162 return ALCHEMY_GPIO1_BASE + (irq - AU1500_GPIO_16) + 16; 155 return ALCHEMY_GPIO1_BASE + (irq - AU1550_GPIO16_INT) + 16;
163 case AU1500_GPIO_206 ... AU1500_GPIO_208_218: 156 case AU1550_GPIO206_INT ... AU1550_GPIO208_215_INT:
164 return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO_206) + 6; 157 return ALCHEMY_GPIO2_BASE + (irq - AU1550_GPIO206_INT) + 6;
165 } 158 }
166 159
167 return -ENXIO; 160 return -ENXIO;
168} 161}
169#endif
170 162
171static inline int au1200_gpio1_to_irq(int gpio) 163static inline int au1200_gpio1_to_irq(int gpio)
172{ 164{
@@ -187,23 +179,21 @@ static inline int au1200_gpio2_to_irq(int gpio)
187 return -ENXIO; 179 return -ENXIO;
188} 180}
189 181
190#ifdef CONFIG_SOC_AU1200
191static inline int au1200_irq_to_gpio(int irq) 182static inline int au1200_irq_to_gpio(int irq)
192{ 183{
193 switch (irq) { 184 switch (irq) {
194 case AU1000_GPIO_0 ... AU1000_GPIO_31: 185 case AU1200_GPIO0_INT ... AU1200_GPIO31_INT:
195 return ALCHEMY_GPIO1_BASE + (irq - AU1000_GPIO_0) + 0; 186 return ALCHEMY_GPIO1_BASE + (irq - AU1200_GPIO0_INT) + 0;
196 case AU1200_GPIO_200 ... AU1200_GPIO_202: 187 case AU1200_GPIO200_INT ... AU1200_GPIO202_INT:
197 return ALCHEMY_GPIO2_BASE + (irq - AU1200_GPIO_200) + 0; 188 return ALCHEMY_GPIO2_BASE + (irq - AU1200_GPIO200_INT) + 0;
198 case AU1200_GPIO_203: 189 case AU1200_GPIO203_INT:
199 return ALCHEMY_GPIO2_BASE + 3; 190 return ALCHEMY_GPIO2_BASE + 3;
200 case AU1200_GPIO_204 ... AU1200_GPIO_208_215: 191 case AU1200_GPIO204_INT ... AU1200_GPIO208_215_INT:
201 return ALCHEMY_GPIO2_BASE + (irq - AU1200_GPIO_204) + 4; 192 return ALCHEMY_GPIO2_BASE + (irq - AU1200_GPIO204_INT) + 4;
202 } 193 }
203 194
204 return -ENXIO; 195 return -ENXIO;
205} 196}
206#endif
207 197
208/* 198/*
209 * GPIO1 block macros for common linux gpio functions. 199 * GPIO1 block macros for common linux gpio functions.
@@ -246,19 +236,19 @@ static inline int alchemy_gpio1_is_valid(int gpio)
246 236
247static inline int alchemy_gpio1_to_irq(int gpio) 237static inline int alchemy_gpio1_to_irq(int gpio)
248{ 238{
249#if defined(CONFIG_SOC_AU1000) 239 switch (alchemy_get_cputype()) {
250 return au1000_gpio1_to_irq(gpio); 240 case ALCHEMY_CPU_AU1000:
251#elif defined(CONFIG_SOC_AU1100) 241 return au1000_gpio1_to_irq(gpio);
252 return au1100_gpio1_to_irq(gpio); 242 case ALCHEMY_CPU_AU1100:
253#elif defined(CONFIG_SOC_AU1500) 243 return au1100_gpio1_to_irq(gpio);
254 return au1500_gpio1_to_irq(gpio); 244 case ALCHEMY_CPU_AU1500:
255#elif defined(CONFIG_SOC_AU1550) 245 return au1500_gpio1_to_irq(gpio);
256 return au1550_gpio1_to_irq(gpio); 246 case ALCHEMY_CPU_AU1550:
257#elif defined(CONFIG_SOC_AU1200) 247 return au1550_gpio1_to_irq(gpio);
258 return au1200_gpio1_to_irq(gpio); 248 case ALCHEMY_CPU_AU1200:
259#else 249 return au1200_gpio1_to_irq(gpio);
250 }
260 return -ENXIO; 251 return -ENXIO;
261#endif
262} 252}
263 253
264/* 254/*
@@ -316,19 +306,19 @@ static inline int alchemy_gpio2_is_valid(int gpio)
316 306
317static inline int alchemy_gpio2_to_irq(int gpio) 307static inline int alchemy_gpio2_to_irq(int gpio)
318{ 308{
319#if defined(CONFIG_SOC_AU1000) 309 switch (alchemy_get_cputype()) {
320 return au1000_gpio2_to_irq(gpio); 310 case ALCHEMY_CPU_AU1000:
321#elif defined(CONFIG_SOC_AU1100) 311 return au1000_gpio2_to_irq(gpio);
322 return au1100_gpio2_to_irq(gpio); 312 case ALCHEMY_CPU_AU1100:
323#elif defined(CONFIG_SOC_AU1500) 313 return au1100_gpio2_to_irq(gpio);
324 return au1500_gpio2_to_irq(gpio); 314 case ALCHEMY_CPU_AU1500:
325#elif defined(CONFIG_SOC_AU1550) 315 return au1500_gpio2_to_irq(gpio);
326 return au1550_gpio2_to_irq(gpio); 316 case ALCHEMY_CPU_AU1550:
327#elif defined(CONFIG_SOC_AU1200) 317 return au1550_gpio2_to_irq(gpio);
328 return au1200_gpio2_to_irq(gpio); 318 case ALCHEMY_CPU_AU1200:
329#else 319 return au1200_gpio2_to_irq(gpio);
320 }
330 return -ENXIO; 321 return -ENXIO;
331#endif
332} 322}
333 323
334/**********************************************************************/ 324/**********************************************************************/
@@ -384,10 +374,13 @@ static inline void alchemy_gpio2_enable_int(int gpio2)
384 374
385 gpio2 -= ALCHEMY_GPIO2_BASE; 375 gpio2 -= ALCHEMY_GPIO2_BASE;
386 376
387#if defined(CONFIG_SOC_AU1100) || defined(CONFIG_SOC_AU1500)
388 /* Au1100/Au1500 have GPIO208-215 enable bits at 0..7 */ 377 /* Au1100/Au1500 have GPIO208-215 enable bits at 0..7 */
389 gpio2 -= 8; 378 switch (alchemy_get_cputype()) {
390#endif 379 case ALCHEMY_CPU_AU1100:
380 case ALCHEMY_CPU_AU1500:
381 gpio2 -= 8;
382 }
383
391 local_irq_save(flags); 384 local_irq_save(flags);
392 __alchemy_gpio2_mod_int(gpio2, 1); 385 __alchemy_gpio2_mod_int(gpio2, 1);
393 local_irq_restore(flags); 386 local_irq_restore(flags);
@@ -405,10 +398,13 @@ static inline void alchemy_gpio2_disable_int(int gpio2)
405 398
406 gpio2 -= ALCHEMY_GPIO2_BASE; 399 gpio2 -= ALCHEMY_GPIO2_BASE;
407 400
408#if defined(CONFIG_SOC_AU1100) || defined(CONFIG_SOC_AU1500)
409 /* Au1100/Au1500 have GPIO208-215 enable bits at 0..7 */ 401 /* Au1100/Au1500 have GPIO208-215 enable bits at 0..7 */
410 gpio2 -= 8; 402 switch (alchemy_get_cputype()) {
411#endif 403 case ALCHEMY_CPU_AU1100:
404 case ALCHEMY_CPU_AU1500:
405 gpio2 -= 8;
406 }
407
412 local_irq_save(flags); 408 local_irq_save(flags);
413 __alchemy_gpio2_mod_int(gpio2, 0); 409 __alchemy_gpio2_mod_int(gpio2, 0);
414 local_irq_restore(flags); 410 local_irq_restore(flags);
@@ -494,19 +490,19 @@ static inline int alchemy_gpio_to_irq(int gpio)
494 490
495static inline int alchemy_irq_to_gpio(int irq) 491static inline int alchemy_irq_to_gpio(int irq)
496{ 492{
497#if defined(CONFIG_SOC_AU1000) 493 switch (alchemy_get_cputype()) {
498 return au1000_irq_to_gpio(irq); 494 case ALCHEMY_CPU_AU1000:
499#elif defined(CONFIG_SOC_AU1100) 495 return au1000_irq_to_gpio(irq);
500 return au1100_irq_to_gpio(irq); 496 case ALCHEMY_CPU_AU1100:
501#elif defined(CONFIG_SOC_AU1500) 497 return au1100_irq_to_gpio(irq);
502 return au1500_irq_to_gpio(irq); 498 case ALCHEMY_CPU_AU1500:
503#elif defined(CONFIG_SOC_AU1550) 499 return au1500_irq_to_gpio(irq);
504 return au1550_irq_to_gpio(irq); 500 case ALCHEMY_CPU_AU1550:
505#elif defined(CONFIG_SOC_AU1200) 501 return au1550_irq_to_gpio(irq);
506 return au1200_irq_to_gpio(irq); 502 case ALCHEMY_CPU_AU1200:
507#else 503 return au1200_irq_to_gpio(irq);
504 }
508 return -ENXIO; 505 return -ENXIO;
509#endif
510} 506}
511 507
512/**********************************************************************/ 508/**********************************************************************/
diff --git a/arch/mips/include/asm/mach-au1x00/gpio.h b/arch/mips/include/asm/mach-au1x00/gpio.h
index f9b7d41c659a..c3f60cdc3203 100644
--- a/arch/mips/include/asm/mach-au1x00/gpio.h
+++ b/arch/mips/include/asm/mach-au1x00/gpio.h
@@ -1,7 +1,7 @@
1#ifndef _ALCHEMY_GPIO_H_ 1#ifndef _ALCHEMY_GPIO_H_
2#define _ALCHEMY_GPIO_H_ 2#define _ALCHEMY_GPIO_H_
3 3
4#if defined(CONFIG_ALCHEMY_GPIO_AU1000) 4#if defined(CONFIG_ALCHEMY_GPIOINT_AU1000)
5 5
6#include <asm/mach-au1x00/gpio-au1000.h> 6#include <asm/mach-au1x00/gpio-au1000.h>
7 7
diff --git a/arch/mips/include/asm/mach-au1x00/ioremap.h b/arch/mips/include/asm/mach-au1x00/ioremap.h
index 364cea2dc71f..75a94ad3ac91 100644
--- a/arch/mips/include/asm/mach-au1x00/ioremap.h
+++ b/arch/mips/include/asm/mach-au1x00/ioremap.h
@@ -11,7 +11,7 @@
11 11
12#include <linux/types.h> 12#include <linux/types.h>
13 13
14#ifdef CONFIG_64BIT_PHYS_ADDR 14#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_PCI)
15extern phys_t __fixup_bigphys_addr(phys_t, phys_t); 15extern phys_t __fixup_bigphys_addr(phys_t, phys_t);
16#else 16#else
17static inline phys_t __fixup_bigphys_addr(phys_t phys_addr, phys_t size) 17static inline phys_t __fixup_bigphys_addr(phys_t phys_addr, phys_t size)
diff --git a/arch/mips/include/asm/mach-au1x00/prom.h b/arch/mips/include/asm/mach-au1x00/prom.h
index e38715577c51..4c0e09cf1735 100644
--- a/arch/mips/include/asm/mach-au1x00/prom.h
+++ b/arch/mips/include/asm/mach-au1x00/prom.h
@@ -6,7 +6,6 @@ extern char **prom_argv;
6extern char **prom_envp; 6extern char **prom_envp;
7 7
8extern void prom_init_cmdline(void); 8extern void prom_init_cmdline(void);
9extern char *prom_getcmdline(void);
10extern char *prom_getenv(char *envname); 9extern char *prom_getenv(char *envname);
11extern int prom_get_ethernet_addr(char *ethernet_addr); 10extern int prom_get_ethernet_addr(char *ethernet_addr);
12 11
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
index ed4ccec87dd4..85fd27509aac 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
@@ -770,4 +770,3 @@
770#define DMIPSPLLCFG_N2_MASK (0x7 << DMIPSPLLCFG_N2_SHIFT) 770#define DMIPSPLLCFG_N2_MASK (0x7 << DMIPSPLLCFG_N2_SHIFT)
771 771
772#endif /* BCM63XX_REGS_H_ */ 772#endif /* BCM63XX_REGS_H_ */
773
diff --git a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
index 425e708d4fb9..bbf054042395 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
@@ -58,6 +58,9 @@
58#define cpu_has_vint 0 58#define cpu_has_vint 0
59#define cpu_has_veic 0 59#define cpu_has_veic 0
60#define cpu_hwrena_impl_bits 0xc0000000 60#define cpu_hwrena_impl_bits 0xc0000000
61
62#define kernel_uses_smartmips_rixi (cpu_data[0].cputype == CPU_CAVIUM_OCTEON_PLUS)
63
61#define ARCH_HAS_READ_CURRENT_TIMER 1 64#define ARCH_HAS_READ_CURRENT_TIMER 1
62#define ARCH_HAS_IRQ_PER_CPU 1 65#define ARCH_HAS_IRQ_PER_CPU 1
63#define ARCH_HAS_SPINLOCK_PREFETCH 1 66#define ARCH_HAS_SPINLOCK_PREFETCH 1
diff --git a/arch/mips/include/asm/mach-db1x00/bcsr.h b/arch/mips/include/asm/mach-db1x00/bcsr.h
new file mode 100644
index 000000000000..618d2de02ed3
--- /dev/null
+++ b/arch/mips/include/asm/mach-db1x00/bcsr.h
@@ -0,0 +1,238 @@
1/*
2 * bcsr.h -- Db1xxx/Pb1xxx Devboard CPLD registers ("BCSR") abstraction.
3 *
4 * All Alchemy development boards (except, of course, the weird PB1000)
5 * have a few registers in a CPLD with standardised layout; they mostly
6 * only differ in base address and bit meanings in the RESETS and BOARD
7 * registers.
8 *
9 * All data taken from the official AMD board documentation sheets.
10 */
11
12#ifndef _DB1XXX_BCSR_H_
13#define _DB1XXX_BCSR_H_
14
15
16/* BCSR base addresses on various boards. BCSR base 2 refers to the
17 * physical address of the first HEXLEDS register, which is usually
18 * a variable offset from the WHOAMI register.
19 */
20
21/* DB1000, DB1100, DB1500, PB1100, PB1500 */
22#define DB1000_BCSR_PHYS_ADDR 0x0E000000
23#define DB1000_BCSR_HEXLED_OFS 0x01000000
24
25#define DB1550_BCSR_PHYS_ADDR 0x0F000000
26#define DB1550_BCSR_HEXLED_OFS 0x00400000
27
28#define PB1550_BCSR_PHYS_ADDR 0x0F000000
29#define PB1550_BCSR_HEXLED_OFS 0x00800000
30
31#define DB1200_BCSR_PHYS_ADDR 0x19800000
32#define DB1200_BCSR_HEXLED_OFS 0x00400000
33
34#define PB1200_BCSR_PHYS_ADDR 0x0D800000
35#define PB1200_BCSR_HEXLED_OFS 0x00400000
36
37
38enum bcsr_id {
39 /* BCSR base 1 */
40 BCSR_WHOAMI = 0,
41 BCSR_STATUS,
42 BCSR_SWITCHES,
43 BCSR_RESETS,
44 BCSR_PCMCIA,
45 BCSR_BOARD,
46 BCSR_LEDS,
47 BCSR_SYSTEM,
48 /* Au1200/1300 based boards */
49 BCSR_INTCLR,
50 BCSR_INTSET,
51 BCSR_MASKCLR,
52 BCSR_MASKSET,
53 BCSR_SIGSTAT,
54 BCSR_INTSTAT,
55
56 /* BCSR base 2 */
57 BCSR_HEXLEDS,
58 BCSR_RSVD1,
59 BCSR_HEXCLEAR,
60
61 BCSR_CNT,
62};
63
64/* register offsets, valid for all Db1xxx/Pb1xxx boards */
65#define BCSR_REG_WHOAMI 0x00
66#define BCSR_REG_STATUS 0x04
67#define BCSR_REG_SWITCHES 0x08
68#define BCSR_REG_RESETS 0x0c
69#define BCSR_REG_PCMCIA 0x10
70#define BCSR_REG_BOARD 0x14
71#define BCSR_REG_LEDS 0x18
72#define BCSR_REG_SYSTEM 0x1c
73/* Au1200/Au1300 based boards: CPLD IRQ muxer */
74#define BCSR_REG_INTCLR 0x20
75#define BCSR_REG_INTSET 0x24
76#define BCSR_REG_MASKCLR 0x28
77#define BCSR_REG_MASKSET 0x2c
78#define BCSR_REG_SIGSTAT 0x30
79#define BCSR_REG_INTSTAT 0x34
80
81/* hexled control, offset from BCSR base 2 */
82#define BCSR_REG_HEXLEDS 0x00
83#define BCSR_REG_HEXCLEAR 0x08
84
85/*
86 * Register Bits and Pieces.
87 */
88#define BCSR_WHOAMI_DCID(x) ((x) & 0xf)
89#define BCSR_WHOAMI_CPLD(x) (((x) >> 4) & 0xf)
90#define BCSR_WHOAMI_BOARD(x) (((x) >> 8) & 0xf)
91
92/* register "WHOAMI" bits 11:8 identify the board */
93enum bcsr_whoami_boards {
94 BCSR_WHOAMI_PB1500 = 1,
95 BCSR_WHOAMI_PB1500R2,
96 BCSR_WHOAMI_PB1100,
97 BCSR_WHOAMI_DB1000,
98 BCSR_WHOAMI_DB1100,
99 BCSR_WHOAMI_DB1500,
100 BCSR_WHOAMI_DB1550,
101 BCSR_WHOAMI_PB1550_DDR,
102 BCSR_WHOAMI_PB1550 = BCSR_WHOAMI_PB1550_DDR,
103 BCSR_WHOAMI_PB1550_SDR,
104 BCSR_WHOAMI_PB1200_DDR1,
105 BCSR_WHOAMI_PB1200 = BCSR_WHOAMI_PB1200_DDR1,
106 BCSR_WHOAMI_PB1200_DDR2,
107 BCSR_WHOAMI_DB1200,
108};
109
110/* STATUS reg. Unless otherwise noted, they're valid on all boards.
111 * PB1200 = DB1200.
112 */
113#define BCSR_STATUS_PC0VS 0x0003
114#define BCSR_STATUS_PC1VS 0x000C
115#define BCSR_STATUS_PC0FI 0x0010
116#define BCSR_STATUS_PC1FI 0x0020
117#define BCSR_STATUS_PB1550_SWAPBOOT 0x0040
118#define BCSR_STATUS_SRAMWIDTH 0x0080
119#define BCSR_STATUS_FLASHBUSY 0x0100
120#define BCSR_STATUS_ROMBUSY 0x0400
121#define BCSR_STATUS_SD0WP 0x0400 /* DB1200 */
122#define BCSR_STATUS_SD1WP 0x0800
123#define BCSR_STATUS_USBOTGID 0x0800 /* PB/DB1550 */
124#define BCSR_STATUS_DB1000_SWAPBOOT 0x2000
125#define BCSR_STATUS_DB1200_SWAPBOOT 0x0040 /* DB1200 */
126#define BCSR_STATUS_IDECBLID 0x0200 /* DB1200 */
127#define BCSR_STATUS_DB1200_U0RXD 0x1000 /* DB1200 */
128#define BCSR_STATUS_DB1200_U1RXD 0x2000 /* DB1200 */
129#define BCSR_STATUS_FLASHDEN 0xC000
130#define BCSR_STATUS_DB1550_U0RXD 0x1000 /* DB1550 */
131#define BCSR_STATUS_DB1550_U3RXD 0x2000 /* DB1550 */
132#define BCSR_STATUS_PB1550_U0RXD 0x1000 /* PB1550 */
133#define BCSR_STATUS_PB1550_U1RXD 0x2000 /* PB1550 */
134#define BCSR_STATUS_PB1550_U3RXD 0x8000 /* PB1550 */
135
136
137/* DB/PB1000,1100,1500,1550 */
138#define BCSR_RESETS_PHY0 0x0001
139#define BCSR_RESETS_PHY1 0x0002
140#define BCSR_RESETS_DC 0x0004
141#define BCSR_RESETS_FIR_SEL 0x2000
142#define BCSR_RESETS_IRDA_MODE_MASK 0xC000
143#define BCSR_RESETS_IRDA_MODE_FULL 0x0000
144#define BCSR_RESETS_PB1550_WSCFSM 0x2000
145#define BCSR_RESETS_IRDA_MODE_OFF 0x4000
146#define BCSR_RESETS_IRDA_MODE_2_3 0x8000
147#define BCSR_RESETS_IRDA_MODE_1_3 0xC000
148#define BCSR_RESETS_DMAREQ 0x8000 /* PB1550 */
149
150#define BCSR_BOARD_PCIM66EN 0x0001
151#define BCSR_BOARD_SD0PWR 0x0040
152#define BCSR_BOARD_SD1PWR 0x0080
153#define BCSR_BOARD_PCIM33 0x0100
154#define BCSR_BOARD_PCIEXTARB 0x0200
155#define BCSR_BOARD_GPIO200RST 0x0400
156#define BCSR_BOARD_PCICLKOUT 0x0800
157#define BCSR_BOARD_PCICFG 0x1000
158#define BCSR_BOARD_SPISEL 0x4000 /* PB/DB1550 */
159#define BCSR_BOARD_SD0WP 0x4000 /* DB1100 */
160#define BCSR_BOARD_SD1WP 0x8000 /* DB1100 */
161
162
163/* DB/PB1200 */
164#define BCSR_RESETS_ETH 0x0001
165#define BCSR_RESETS_CAMERA 0x0002
166#define BCSR_RESETS_DC 0x0004
167#define BCSR_RESETS_IDE 0x0008
168#define BCSR_RESETS_TV 0x0010 /* DB1200 */
169/* Not resets but in the same register */
170#define BCSR_RESETS_PWMR1MUX 0x0800 /* DB1200 */
171#define BCSR_RESETS_PB1200_WSCFSM 0x0800 /* PB1200 */
172#define BCSR_RESETS_PSC0MUX 0x1000
173#define BCSR_RESETS_PSC1MUX 0x2000
174#define BCSR_RESETS_SPISEL 0x4000
175#define BCSR_RESETS_SD1MUX 0x8000 /* PB1200 */
176
177#define BCSR_BOARD_LCDVEE 0x0001
178#define BCSR_BOARD_LCDVDD 0x0002
179#define BCSR_BOARD_LCDBL 0x0004
180#define BCSR_BOARD_CAMSNAP 0x0010
181#define BCSR_BOARD_CAMPWR 0x0020
182#define BCSR_BOARD_SD0PWR 0x0040
183
184
185#define BCSR_SWITCHES_DIP 0x00FF
186#define BCSR_SWITCHES_DIP_1 0x0080
187#define BCSR_SWITCHES_DIP_2 0x0040
188#define BCSR_SWITCHES_DIP_3 0x0020
189#define BCSR_SWITCHES_DIP_4 0x0010
190#define BCSR_SWITCHES_DIP_5 0x0008
191#define BCSR_SWITCHES_DIP_6 0x0004
192#define BCSR_SWITCHES_DIP_7 0x0002
193#define BCSR_SWITCHES_DIP_8 0x0001
194#define BCSR_SWITCHES_ROTARY 0x0F00
195
196
197#define BCSR_PCMCIA_PC0VPP 0x0003
198#define BCSR_PCMCIA_PC0VCC 0x000C
199#define BCSR_PCMCIA_PC0DRVEN 0x0010
200#define BCSR_PCMCIA_PC0RST 0x0080
201#define BCSR_PCMCIA_PC1VPP 0x0300
202#define BCSR_PCMCIA_PC1VCC 0x0C00
203#define BCSR_PCMCIA_PC1DRVEN 0x1000
204#define BCSR_PCMCIA_PC1RST 0x8000
205
206
207#define BCSR_LEDS_DECIMALS 0x0003
208#define BCSR_LEDS_LED0 0x0100
209#define BCSR_LEDS_LED1 0x0200
210#define BCSR_LEDS_LED2 0x0400
211#define BCSR_LEDS_LED3 0x0800
212
213
214#define BCSR_SYSTEM_RESET 0x8000 /* clear to reset */
215#define BCSR_SYSTEM_PWROFF 0x4000 /* set to power off */
216#define BCSR_SYSTEM_VDDI 0x001F /* PB1xxx boards */
217
218
219
220
221/* initialize BCSR for a board. Provide the PHYSICAL addresses of both
222 * BCSR spaces.
223 */
224void __init bcsr_init(unsigned long bcsr1_phys, unsigned long bcsr2_phys);
225
226/* read a board register */
227unsigned short bcsr_read(enum bcsr_id reg);
228
229/* write to a board register */
230void bcsr_write(enum bcsr_id reg, unsigned short val);
231
232/* modify a register. clear bits set in 'clr', set bits set in 'set' */
233void bcsr_mod(enum bcsr_id reg, unsigned short clr, unsigned short set);
234
235/* install CPLD IRQ demuxer (DB1200/PB1200) */
236void __init bcsr_init_irq(int csc_start, int csc_end, int hook_irq);
237
238#endif
diff --git a/arch/mips/include/asm/mach-db1x00/db1200.h b/arch/mips/include/asm/mach-db1x00/db1200.h
index 27f26102b1bb..3404248f5094 100644
--- a/arch/mips/include/asm/mach-db1x00/db1200.h
+++ b/arch/mips/include/asm/mach-db1x00/db1200.h
@@ -25,133 +25,9 @@
25#define __ASM_DB1200_H 25#define __ASM_DB1200_H
26 26
27#include <linux/types.h> 27#include <linux/types.h>
28#include <asm/mach-au1x00/au1000.h>
28#include <asm/mach-au1x00/au1xxx_psc.h> 29#include <asm/mach-au1x00/au1xxx_psc.h>
29 30
30#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
31#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
32#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC1_TX
33#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC1_RX
34
35/*
36 * SPI and SMB are muxed on the DBAu1200 board.
37 * Refer to board documentation.
38 */
39#define SPI_PSC_BASE PSC0_BASE_ADDR
40#define SMBUS_PSC_BASE PSC0_BASE_ADDR
41/*
42 * AC'97 and I2S are muxed on the DBAu1200 board.
43 * Refer to board documentation.
44 */
45#define AC97_PSC_BASE PSC1_BASE_ADDR
46#define I2S_PSC_BASE PSC1_BASE_ADDR
47
48#define BCSR_KSEG1_ADDR 0xB9800000
49
50typedef volatile struct
51{
52 /*00*/ u16 whoami;
53 u16 reserved0;
54 /*04*/ u16 status;
55 u16 reserved1;
56 /*08*/ u16 switches;
57 u16 reserved2;
58 /*0C*/ u16 resets;
59 u16 reserved3;
60
61 /*10*/ u16 pcmcia;
62 u16 reserved4;
63 /*14*/ u16 board;
64 u16 reserved5;
65 /*18*/ u16 disk_leds;
66 u16 reserved6;
67 /*1C*/ u16 system;
68 u16 reserved7;
69
70 /*20*/ u16 intclr;
71 u16 reserved8;
72 /*24*/ u16 intset;
73 u16 reserved9;
74 /*28*/ u16 intclr_mask;
75 u16 reserved10;
76 /*2C*/ u16 intset_mask;
77 u16 reserved11;
78
79 /*30*/ u16 sig_status;
80 u16 reserved12;
81 /*34*/ u16 int_status;
82 u16 reserved13;
83 /*38*/ u16 reserved14;
84 u16 reserved15;
85 /*3C*/ u16 reserved16;
86 u16 reserved17;
87
88} BCSR;
89
90static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
91
92/*
93 * Register bit definitions for the BCSRs
94 */
95#define BCSR_WHOAMI_DCID 0x000F
96#define BCSR_WHOAMI_CPLD 0x00F0
97#define BCSR_WHOAMI_BOARD 0x0F00
98
99#define BCSR_STATUS_PCMCIA0VS 0x0003
100#define BCSR_STATUS_PCMCIA1VS 0x000C
101#define BCSR_STATUS_SWAPBOOT 0x0040
102#define BCSR_STATUS_FLASHBUSY 0x0100
103#define BCSR_STATUS_IDECBLID 0x0200
104#define BCSR_STATUS_SD0WP 0x0400
105#define BCSR_STATUS_U0RXD 0x1000
106#define BCSR_STATUS_U1RXD 0x2000
107
108#define BCSR_SWITCHES_OCTAL 0x00FF
109#define BCSR_SWITCHES_DIP_1 0x0080
110#define BCSR_SWITCHES_DIP_2 0x0040
111#define BCSR_SWITCHES_DIP_3 0x0020
112#define BCSR_SWITCHES_DIP_4 0x0010
113#define BCSR_SWITCHES_DIP_5 0x0008
114#define BCSR_SWITCHES_DIP_6 0x0004
115#define BCSR_SWITCHES_DIP_7 0x0002
116#define BCSR_SWITCHES_DIP_8 0x0001
117#define BCSR_SWITCHES_ROTARY 0x0F00
118
119#define BCSR_RESETS_ETH 0x0001
120#define BCSR_RESETS_CAMERA 0x0002
121#define BCSR_RESETS_DC 0x0004
122#define BCSR_RESETS_IDE 0x0008
123#define BCSR_RESETS_TV 0x0010
124/* Not resets but in the same register */
125#define BCSR_RESETS_PWMR1MUX 0x0800
126#define BCSR_RESETS_PCS0MUX 0x1000
127#define BCSR_RESETS_PCS1MUX 0x2000
128#define BCSR_RESETS_SPISEL 0x4000
129
130#define BCSR_PCMCIA_PC0VPP 0x0003
131#define BCSR_PCMCIA_PC0VCC 0x000C
132#define BCSR_PCMCIA_PC0DRVEN 0x0010
133#define BCSR_PCMCIA_PC0RST 0x0080
134#define BCSR_PCMCIA_PC1VPP 0x0300
135#define BCSR_PCMCIA_PC1VCC 0x0C00
136#define BCSR_PCMCIA_PC1DRVEN 0x1000
137#define BCSR_PCMCIA_PC1RST 0x8000
138
139#define BCSR_BOARD_LCDVEE 0x0001
140#define BCSR_BOARD_LCDVDD 0x0002
141#define BCSR_BOARD_LCDBL 0x0004
142#define BCSR_BOARD_CAMSNAP 0x0010
143#define BCSR_BOARD_CAMPWR 0x0020
144#define BCSR_BOARD_SD0PWR 0x0040
145
146#define BCSR_LEDS_DECIMALS 0x0003
147#define BCSR_LEDS_LED0 0x0100
148#define BCSR_LEDS_LED1 0x0200
149#define BCSR_LEDS_LED2 0x0400
150#define BCSR_LEDS_LED3 0x0800
151
152#define BCSR_SYSTEM_POWEROFF 0x4000
153#define BCSR_SYSTEM_RESET 0x8000
154
155/* Bit positions for the different interrupt sources */ 31/* Bit positions for the different interrupt sources */
156#define BCSR_INT_IDE 0x0001 32#define BCSR_INT_IDE 0x0001
157#define BCSR_INT_ETH 0x0002 33#define BCSR_INT_ETH 0x0002
@@ -168,17 +44,15 @@ static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
168#define BCSR_INT_SD0INSERT 0x1000 44#define BCSR_INT_SD0INSERT 0x1000
169#define BCSR_INT_SD0EJECT 0x2000 45#define BCSR_INT_SD0EJECT 0x2000
170 46
171#define SMC91C111_PHYS_ADDR 0x19000300
172#define SMC91C111_INT DB1200_ETH_INT
173
174#define IDE_PHYS_ADDR 0x18800000 47#define IDE_PHYS_ADDR 0x18800000
175#define IDE_REG_SHIFT 5 48#define IDE_REG_SHIFT 5
176#define IDE_PHYS_LEN (16 << IDE_REG_SHIFT)
177#define IDE_INT DB1200_IDE_INT
178#define IDE_DDMA_REQ DSCR_CMD0_DMA_REQ1 49#define IDE_DDMA_REQ DSCR_CMD0_DMA_REQ1
179#define IDE_RQSIZE 128 50#define IDE_RQSIZE 128
180 51
181#define NAND_PHYS_ADDR 0x20000000 52#define DB1200_IDE_PHYS_ADDR IDE_PHYS_ADDR
53#define DB1200_IDE_PHYS_LEN (16 << IDE_REG_SHIFT)
54#define DB1200_ETH_PHYS_ADDR 0x19000300
55#define DB1200_NAND_PHYS_ADDR 0x20000000
182 56
183/* 57/*
184 * External Interrupts for DBAu1200 as of 8/6/2004. 58 * External Interrupts for DBAu1200 as of 8/6/2004.
@@ -188,7 +62,7 @@ static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
188 * Example: IDE bis pos is = 64 - 64 62 * Example: IDE bis pos is = 64 - 64
189 * ETH bit pos is = 65 - 64 63 * ETH bit pos is = 65 - 64
190 */ 64 */
191enum external_pb1200_ints { 65enum external_db1200_ints {
192 DB1200_INT_BEGIN = AU1000_MAX_INTR + 1, 66 DB1200_INT_BEGIN = AU1000_MAX_INTR + 1,
193 67
194 DB1200_IDE_INT = DB1200_INT_BEGIN, 68 DB1200_IDE_INT = DB1200_INT_BEGIN,
@@ -209,22 +83,4 @@ enum external_pb1200_ints {
209 DB1200_INT_END = DB1200_INT_BEGIN + 15, 83 DB1200_INT_END = DB1200_INT_BEGIN + 15,
210}; 84};
211 85
212
213/*
214 * DBAu1200 specific PCMCIA defines for drivers/pcmcia/au1000_db1x00.c
215 */
216#define PCMCIA_MAX_SOCK 1
217#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1)
218
219/* VPP/VCC */
220#define SET_VCC_VPP(VCC, VPP, SLOT) \
221 ((((VCC) << 2) | ((VPP) << 0)) << ((SLOT) * 8))
222
223#define BOARD_PC0_INT DB1200_PC0_INT
224#define BOARD_PC1_INT DB1200_PC1_INT
225#define BOARD_CARD_INSERTED(SOCKET) bcsr->sig_status & (1 << (8 + (2 * SOCKET)))
226
227/* NAND chip select */
228#define NAND_CS 1
229
230#endif /* __ASM_DB1200_H */ 86#endif /* __ASM_DB1200_H */
diff --git a/arch/mips/include/asm/mach-db1x00/db1x00.h b/arch/mips/include/asm/mach-db1x00/db1x00.h
index 1a515b8c870f..a919dac525a1 100644
--- a/arch/mips/include/asm/mach-db1x00/db1x00.h
+++ b/arch/mips/include/asm/mach-db1x00/db1x00.h
@@ -41,111 +41,11 @@
41#define SMBUS_PSC_BASE PSC2_BASE_ADDR 41#define SMBUS_PSC_BASE PSC2_BASE_ADDR
42#define I2S_PSC_BASE PSC3_BASE_ADDR 42#define I2S_PSC_BASE PSC3_BASE_ADDR
43 43
44#define BCSR_KSEG1_ADDR 0xAF000000
45#define NAND_PHYS_ADDR 0x20000000 44#define NAND_PHYS_ADDR 0x20000000
46 45
47#else
48#define BCSR_KSEG1_ADDR 0xAE000000
49#endif 46#endif
50 47
51/* 48/*
52 * Overlay data structure of the DBAu1x00 board registers.
53 * Registers are located at physical 0E0000xx, KSEG1 0xAE0000xx.
54 */
55typedef volatile struct
56{
57 /*00*/ unsigned short whoami;
58 unsigned short reserved0;
59 /*04*/ unsigned short status;
60 unsigned short reserved1;
61 /*08*/ unsigned short switches;
62 unsigned short reserved2;
63 /*0C*/ unsigned short resets;
64 unsigned short reserved3;
65 /*10*/ unsigned short pcmcia;
66 unsigned short reserved4;
67 /*14*/ unsigned short specific;
68 unsigned short reserved5;
69 /*18*/ unsigned short leds;
70 unsigned short reserved6;
71 /*1C*/ unsigned short swreset;
72 unsigned short reserved7;
73
74} BCSR;
75
76
77/*
78 * Register/mask bit definitions for the BCSRs
79 */
80#define BCSR_WHOAMI_DCID 0x000F
81#define BCSR_WHOAMI_CPLD 0x00F0
82#define BCSR_WHOAMI_BOARD 0x0F00
83
84#define BCSR_STATUS_PC0VS 0x0003
85#define BCSR_STATUS_PC1VS 0x000C
86#define BCSR_STATUS_PC0FI 0x0010
87#define BCSR_STATUS_PC1FI 0x0020
88#define BCSR_STATUS_FLASHBUSY 0x0100
89#define BCSR_STATUS_ROMBUSY 0x0400
90#define BCSR_STATUS_SWAPBOOT 0x2000
91#define BCSR_STATUS_FLASHDEN 0xC000
92
93#define BCSR_SWITCHES_DIP 0x00FF
94#define BCSR_SWITCHES_DIP_1 0x0080
95#define BCSR_SWITCHES_DIP_2 0x0040
96#define BCSR_SWITCHES_DIP_3 0x0020
97#define BCSR_SWITCHES_DIP_4 0x0010
98#define BCSR_SWITCHES_DIP_5 0x0008
99#define BCSR_SWITCHES_DIP_6 0x0004
100#define BCSR_SWITCHES_DIP_7 0x0002
101#define BCSR_SWITCHES_DIP_8 0x0001
102#define BCSR_SWITCHES_ROTARY 0x0F00
103
104#define BCSR_RESETS_PHY0 0x0001
105#define BCSR_RESETS_PHY1 0x0002
106#define BCSR_RESETS_DC 0x0004
107#define BCSR_RESETS_FIR_SEL 0x2000
108#define BCSR_RESETS_IRDA_MODE_MASK 0xC000
109#define BCSR_RESETS_IRDA_MODE_FULL 0x0000
110#define BCSR_RESETS_IRDA_MODE_OFF 0x4000
111#define BCSR_RESETS_IRDA_MODE_2_3 0x8000
112#define BCSR_RESETS_IRDA_MODE_1_3 0xC000
113
114#define BCSR_PCMCIA_PC0VPP 0x0003
115#define BCSR_PCMCIA_PC0VCC 0x000C
116#define BCSR_PCMCIA_PC0DRVEN 0x0010
117#define BCSR_PCMCIA_PC0RST 0x0080
118#define BCSR_PCMCIA_PC1VPP 0x0300
119#define BCSR_PCMCIA_PC1VCC 0x0C00
120#define BCSR_PCMCIA_PC1DRVEN 0x1000
121#define BCSR_PCMCIA_PC1RST 0x8000
122
123#define BCSR_BOARD_PCIM66EN 0x0001
124#define BCSR_BOARD_SD0_PWR 0x0040
125#define BCSR_BOARD_SD1_PWR 0x0080
126#define BCSR_BOARD_PCIM33 0x0100
127#define BCSR_BOARD_GPIO200RST 0x0400
128#define BCSR_BOARD_PCICFG 0x1000
129#define BCSR_BOARD_SD0_WP 0x4000
130#define BCSR_BOARD_SD1_WP 0x8000
131
132#define BCSR_LEDS_DECIMALS 0x0003
133#define BCSR_LEDS_LED0 0x0100
134#define BCSR_LEDS_LED1 0x0200
135#define BCSR_LEDS_LED2 0x0400
136#define BCSR_LEDS_LED3 0x0800
137
138#define BCSR_SWRESET_RESET 0x0080
139
140/* PCMCIA DBAu1x00 specific defines */
141#define PCMCIA_MAX_SOCK 1
142#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1)
143
144/* VPP/VCC */
145#define SET_VCC_VPP(VCC, VPP, SLOT)\
146 ((((VCC) << 2) | ((VPP) << 0)) << ((SLOT) * 8))
147
148/*
149 * NAND defines 49 * NAND defines
150 * 50 *
151 * Timing values as described in databook, * ns value stripped of the 51 * Timing values as described in databook, * ns value stripped of the
diff --git a/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h b/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h
index 9947e57c91de..16210cedd929 100644
--- a/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h
@@ -3,7 +3,7 @@
3 * License. See the file "COPYING" in the main directory of this archive 3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details. 4 * for more details.
5 * 5 *
6 * Copyright (C) 2009 Wu Zhangjin <wuzj@lemote.com> 6 * Copyright (C) 2009 Wu Zhangjin <wuzhangjin@gmail.com>
7 * Copyright (C) 2009 Philippe Vachon <philippe@cowpig.ca> 7 * Copyright (C) 2009 Philippe Vachon <philippe@cowpig.ca>
8 * Copyright (C) 2009 Zhang Le <r0bertz@gentoo.org> 8 * Copyright (C) 2009 Zhang Le <r0bertz@gentoo.org>
9 * 9 *
diff --git a/arch/mips/include/asm/mach-loongson/cs5536/cs5536_vsm.h b/arch/mips/include/asm/mach-loongson/cs5536/cs5536_vsm.h
index 6305bea7e18e..21c4ecedebe7 100644
--- a/arch/mips/include/asm/mach-loongson/cs5536/cs5536_vsm.h
+++ b/arch/mips/include/asm/mach-loongson/cs5536/cs5536_vsm.h
@@ -2,7 +2,7 @@
2 * the read/write interfaces for Virtual Support Module(VSM) 2 * the read/write interfaces for Virtual Support Module(VSM)
3 * 3 *
4 * Copyright (C) 2009 Lemote, Inc. 4 * Copyright (C) 2009 Lemote, Inc.
5 * Author: Wu Zhangjin <wuzj@lemote.com> 5 * Author: Wu Zhangjin <wuzhangjin@gmail.com>
6 */ 6 */
7 7
8#ifndef _CS5536_VSM_H 8#ifndef _CS5536_VSM_H
diff --git a/arch/mips/include/asm/mach-loongson/loongson.h b/arch/mips/include/asm/mach-loongson/loongson.h
index ee8bc8376972..1cf7b1401ee4 100644
--- a/arch/mips/include/asm/mach-loongson/loongson.h
+++ b/arch/mips/include/asm/mach-loongson/loongson.h
@@ -1,12 +1,11 @@
1/* 1/*
2 * Copyright (C) 2009 Lemote, Inc. 2 * Copyright (C) 2009 Lemote, Inc.
3 * Author: Wu Zhangjin <wuzj@lemote.com> 3 * Author: Wu Zhangjin <wuzhangjin@gmail.com>
4 * 4 *
5 * This program is free software; you can redistribute it and/or modify it 5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the 6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your 7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version. 8 * option) any later version.
9 *
10 */ 9 */
11 10
12#ifndef __ASM_MACH_LOONGSON_LOONGSON_H 11#ifndef __ASM_MACH_LOONGSON_LOONGSON_H
@@ -23,7 +22,7 @@ extern void mach_prepare_reboot(void);
23extern void mach_prepare_shutdown(void); 22extern void mach_prepare_shutdown(void);
24 23
25/* environment arguments from bootloader */ 24/* environment arguments from bootloader */
26extern unsigned long bus_clock, cpu_clock_freq; 25extern unsigned long cpu_clock_freq;
27extern unsigned long memsize, highmemsize; 26extern unsigned long memsize, highmemsize;
28 27
29/* loongson-specific command line, env and memory initialization */ 28/* loongson-specific command line, env and memory initialization */
diff --git a/arch/mips/include/asm/mach-loongson/machine.h b/arch/mips/include/asm/mach-loongson/machine.h
index acf8359cb135..43213388c174 100644
--- a/arch/mips/include/asm/mach-loongson/machine.h
+++ b/arch/mips/include/asm/mach-loongson/machine.h
@@ -1,6 +1,6 @@
1/* 1/*
2 * Copyright (C) 2009 Lemote, Inc. & Institute of Computing Technology 2 * Copyright (C) 2009 Lemote, Inc.
3 * Author: Wu Zhangjin <wuzj@lemote.com> 3 * Author: Wu Zhangjin <wuzhangjin@gmail.com>
4 * 4 *
5 * This program is free software; you can redistribute it and/or modify it 5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the 6 * under the terms of the GNU General Public License as published by the
diff --git a/arch/mips/include/asm/mach-loongson/mem.h b/arch/mips/include/asm/mach-loongson/mem.h
index e9960f341b96..3b23ee8647d6 100644
--- a/arch/mips/include/asm/mach-loongson/mem.h
+++ b/arch/mips/include/asm/mach-loongson/mem.h
@@ -1,6 +1,6 @@
1/* 1/*
2 * Copyright (C) 2009 Lemote, Inc. 2 * Copyright (C) 2009 Lemote, Inc.
3 * Author: Wu Zhangjin <wuzj@lemote.com> 3 * Author: Wu Zhangjin <wuzhangjin@gmail.com>
4 * 4 *
5 * This program is free software; you can redistribute it and/or modify it 5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the 6 * under the terms of the GNU General Public License as published by the
diff --git a/arch/mips/include/asm/mach-loongson/pci.h b/arch/mips/include/asm/mach-loongson/pci.h
index a199a4f6de4e..bc99dab4ef63 100644
--- a/arch/mips/include/asm/mach-loongson/pci.h
+++ b/arch/mips/include/asm/mach-loongson/pci.h
@@ -1,23 +1,12 @@
1/* 1/*
2 * Copyright (c) 2008 Zhang Le <r0bertz@gentoo.org> 2 * Copyright (c) 2008 Zhang Le <r0bertz@gentoo.org>
3 * Copyright (c) 2009 Wu Zhangjin <wuzj@lemote.com> 3 * Copyright (c) 2009 Wu Zhangjin <wuzhangjin@gmail.com>
4 * 4 *
5 * This program is free software; you can redistribute it 5 * This program is free software; you can redistribute it
6 * and/or modify it under the terms of the GNU General 6 * and/or modify it under the terms of the GNU General
7 * Public License as published by the Free Software 7 * Public License as published by the Free Software
8 * Foundation; either version 2 of the License, or (at your 8 * Foundation; either version 2 of the License, or (at your
9 * option) any later version. 9 * option) any later version.
10 *
11 * This program is distributed in the hope that it will be
12 * useful, but WITHOUT ANY WARRANTY; without even the implied
13 * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
14 * PURPOSE. See the GNU General Public License for more
15 * details.
16 *
17 * You should have received a copy of the GNU General Public
18 * License along with this program; if not, write to the Free
19 * Software Foundation, Inc., 675 Mass Ave, Cambridge, MA
20 * 02139, USA.
21 */ 10 */
22 11
23#ifndef __ASM_MACH_LOONGSON_PCI_H_ 12#ifndef __ASM_MACH_LOONGSON_PCI_H_
diff --git a/arch/mips/include/asm/mach-pb1x00/pb1100.h b/arch/mips/include/asm/mach-pb1x00/pb1100.h
deleted file mode 100644
index b1a60f1cbd02..000000000000
--- a/arch/mips/include/asm/mach-pb1x00/pb1100.h
+++ /dev/null
@@ -1,85 +0,0 @@
1/*
2 * Alchemy Semi Pb1100 Referrence Board
3 *
4 * Copyright 2001, 2008 MontaVista Software Inc.
5 * Author: MontaVista Software, Inc. <source@mvista.com>
6 *
7 * ########################################################################
8 *
9 * This program is free software; you can distribute it and/or modify it
10 * under the terms of the GNU General Public License (Version 2) as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * for more details.
17 *
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, write to the Free Software Foundation, Inc.,
20 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
21 *
22 * ########################################################################
23 *
24 *
25 */
26#ifndef __ASM_PB1100_H
27#define __ASM_PB1100_H
28
29#define PB1100_IDENT 0xAE000000
30#define BOARD_STATUS_REG 0xAE000004
31# define PB1100_ROM_SEL (1 << 15)
32# define PB1100_ROM_SIZ (1 << 14)
33# define PB1100_SWAP_BOOT (1 << 13)
34# define PB1100_FLASH_WP (1 << 12)
35# define PB1100_ROM_H_STS (1 << 11)
36# define PB1100_ROM_L_STS (1 << 10)
37# define PB1100_FLASH_H_STS (1 << 9)
38# define PB1100_FLASH_L_STS (1 << 8)
39# define PB1100_SRAM_SIZ (1 << 7)
40# define PB1100_TSC_BUSY (1 << 6)
41# define PB1100_PCMCIA_VS_MASK (3 << 4)
42# define PB1100_RS232_CD (1 << 3)
43# define PB1100_RS232_CTS (1 << 2)
44# define PB1100_RS232_DSR (1 << 1)
45# define PB1100_RS232_RI (1 << 0)
46
47#define PB1100_IRDA_RS232 0xAE00000C
48# define PB1100_IRDA_FULL (0 << 14) /* full power */
49# define PB1100_IRDA_SHUTDOWN (1 << 14)
50# define PB1100_IRDA_TT (2 << 14) /* 2/3 power */
51# define PB1100_IRDA_OT (3 << 14) /* 1/3 power */
52# define PB1100_IRDA_FIR (1 << 13)
53
54#define PCMCIA_BOARD_REG 0xAE000010
55# define PB1100_SD_WP1_RO (1 << 15) /* read only */
56# define PB1100_SD_WP0_RO (1 << 14) /* read only */
57# define PB1100_SD_PWR1 (1 << 11) /* applies power to SD1 */
58# define PB1100_SD_PWR0 (1 << 10) /* applies power to SD0 */
59# define PB1100_SEL_SD_CONN1 (1 << 9)
60# define PB1100_SEL_SD_CONN0 (1 << 8)
61# define PC_DEASSERT_RST (1 << 7)
62# define PC_DRV_EN (1 << 4)
63
64#define PB1100_G_CONTROL 0xAE000014 /* graphics control */
65
66#define PB1100_RST_VDDI 0xAE00001C
67# define PB1100_SOFT_RESET (1 << 15) /* clear to reset the board */
68# define PB1100_VDDI_MASK 0x1F
69
70#define PB1100_LEDS 0xAE000018
71
72/*
73 * 11:8 is 4 discreet LEDs. Clearing a bit illuminates the LED.
74 * 7:0 is the LED Display's decimal points.
75 */
76#define PB1100_HEX_LED 0xAE000018
77
78/* PCMCIA Pb1100 specific defines */
79#define PCMCIA_MAX_SOCK 0
80#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1)
81
82/* VPP/VCC */
83#define SET_VCC_VPP(VCC, VPP) (((VCC) << 2) | ((VPP) << 0))
84
85#endif /* __ASM_PB1100_H */
diff --git a/arch/mips/include/asm/mach-pb1x00/pb1200.h b/arch/mips/include/asm/mach-pb1x00/pb1200.h
index c8618df88cb5..962eb55dc880 100644
--- a/arch/mips/include/asm/mach-pb1x00/pb1200.h
+++ b/arch/mips/include/asm/mach-pb1x00/pb1200.h
@@ -25,6 +25,7 @@
25#define __ASM_PB1200_H 25#define __ASM_PB1200_H
26 26
27#include <linux/types.h> 27#include <linux/types.h>
28#include <asm/mach-au1x00/au1000.h>
28#include <asm/mach-au1x00/au1xxx_psc.h> 29#include <asm/mach-au1x00/au1xxx_psc.h>
29 30
30#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX 31#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
@@ -43,113 +44,8 @@
43 * Refer to board documentation. 44 * Refer to board documentation.
44 */ 45 */
45#define AC97_PSC_BASE PSC1_BASE_ADDR 46#define AC97_PSC_BASE PSC1_BASE_ADDR
46#define I2S_PSC_BASE PSC1_BASE_ADDR 47#define I2S_PSC_BASE PSC1_BASE_ADDR
47 48
48#define BCSR_KSEG1_ADDR 0xAD800000
49
50typedef volatile struct
51{
52 /*00*/ u16 whoami;
53 u16 reserved0;
54 /*04*/ u16 status;
55 u16 reserved1;
56 /*08*/ u16 switches;
57 u16 reserved2;
58 /*0C*/ u16 resets;
59 u16 reserved3;
60
61 /*10*/ u16 pcmcia;
62 u16 reserved4;
63 /*14*/ u16 board;
64 u16 reserved5;
65 /*18*/ u16 disk_leds;
66 u16 reserved6;
67 /*1C*/ u16 system;
68 u16 reserved7;
69
70 /*20*/ u16 intclr;
71 u16 reserved8;
72 /*24*/ u16 intset;
73 u16 reserved9;
74 /*28*/ u16 intclr_mask;
75 u16 reserved10;
76 /*2C*/ u16 intset_mask;
77 u16 reserved11;
78
79 /*30*/ u16 sig_status;
80 u16 reserved12;
81 /*34*/ u16 int_status;
82 u16 reserved13;
83 /*38*/ u16 reserved14;
84 u16 reserved15;
85 /*3C*/ u16 reserved16;
86 u16 reserved17;
87
88} BCSR;
89
90static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
91
92/*
93 * Register bit definitions for the BCSRs
94 */
95#define BCSR_WHOAMI_DCID 0x000F
96#define BCSR_WHOAMI_CPLD 0x00F0
97#define BCSR_WHOAMI_BOARD 0x0F00
98
99#define BCSR_STATUS_PCMCIA0VS 0x0003
100#define BCSR_STATUS_PCMCIA1VS 0x000C
101#define BCSR_STATUS_SWAPBOOT 0x0040
102#define BCSR_STATUS_FLASHBUSY 0x0100
103#define BCSR_STATUS_IDECBLID 0x0200
104#define BCSR_STATUS_SD0WP 0x0400
105#define BCSR_STATUS_SD1WP 0x0800
106#define BCSR_STATUS_U0RXD 0x1000
107#define BCSR_STATUS_U1RXD 0x2000
108
109#define BCSR_SWITCHES_OCTAL 0x00FF
110#define BCSR_SWITCHES_DIP_1 0x0080
111#define BCSR_SWITCHES_DIP_2 0x0040
112#define BCSR_SWITCHES_DIP_3 0x0020
113#define BCSR_SWITCHES_DIP_4 0x0010
114#define BCSR_SWITCHES_DIP_5 0x0008
115#define BCSR_SWITCHES_DIP_6 0x0004
116#define BCSR_SWITCHES_DIP_7 0x0002
117#define BCSR_SWITCHES_DIP_8 0x0001
118#define BCSR_SWITCHES_ROTARY 0x0F00
119
120#define BCSR_RESETS_ETH 0x0001
121#define BCSR_RESETS_CAMERA 0x0002
122#define BCSR_RESETS_DC 0x0004
123#define BCSR_RESETS_IDE 0x0008
124/* not resets but in the same register */
125#define BCSR_RESETS_WSCFSM 0x0800
126#define BCSR_RESETS_PCS0MUX 0x1000
127#define BCSR_RESETS_PCS1MUX 0x2000
128#define BCSR_RESETS_SPISEL 0x4000
129#define BCSR_RESETS_SD1MUX 0x8000
130
131#define BCSR_PCMCIA_PC0VPP 0x0003
132#define BCSR_PCMCIA_PC0VCC 0x000C
133#define BCSR_PCMCIA_PC0DRVEN 0x0010
134#define BCSR_PCMCIA_PC0RST 0x0080
135#define BCSR_PCMCIA_PC1VPP 0x0300
136#define BCSR_PCMCIA_PC1VCC 0x0C00
137#define BCSR_PCMCIA_PC1DRVEN 0x1000
138#define BCSR_PCMCIA_PC1RST 0x8000
139
140#define BCSR_BOARD_LCDVEE 0x0001
141#define BCSR_BOARD_LCDVDD 0x0002
142#define BCSR_BOARD_LCDBL 0x0004
143#define BCSR_BOARD_CAMSNAP 0x0010
144#define BCSR_BOARD_CAMPWR 0x0020
145#define BCSR_BOARD_SD0PWR 0x0040
146#define BCSR_BOARD_SD1PWR 0x0080
147
148#define BCSR_LEDS_DECIMALS 0x00FF
149#define BCSR_LEDS_LED0 0x0100
150#define BCSR_LEDS_LED1 0x0200
151#define BCSR_LEDS_LED2 0x0400
152#define BCSR_LEDS_LED3 0x0800
153 49
154#define BCSR_SYSTEM_VDDI 0x001F 50#define BCSR_SYSTEM_VDDI 0x001F
155#define BCSR_SYSTEM_POWEROFF 0x4000 51#define BCSR_SYSTEM_POWEROFF 0x4000
@@ -239,20 +135,6 @@ enum external_pb1200_ints {
239 PB1200_INT_END = PB1200_INT_BEGIN + 15 135 PB1200_INT_END = PB1200_INT_BEGIN + 15
240}; 136};
241 137
242/*
243 * Pb1200 specific PCMCIA defines for drivers/pcmcia/au1000_db1x00.c
244 */
245#define PCMCIA_MAX_SOCK 1
246#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1)
247
248/* VPP/VCC */
249#define SET_VCC_VPP(VCC, VPP, SLOT) \
250 ((((VCC) << 2) | ((VPP) << 0)) << ((SLOT) * 8))
251
252#define BOARD_PC0_INT PB1200_PC0_INT
253#define BOARD_PC1_INT PB1200_PC1_INT
254#define BOARD_CARD_INSERTED(SOCKET) bcsr->sig_status & (1 << (8 + (2 * SOCKET)))
255
256/* NAND chip select */ 138/* NAND chip select */
257#define NAND_CS 1 139#define NAND_CS 1
258 140
diff --git a/arch/mips/include/asm/mach-pb1x00/pb1500.h b/arch/mips/include/asm/mach-pb1x00/pb1500.h
deleted file mode 100644
index da51a2eb7b82..000000000000
--- a/arch/mips/include/asm/mach-pb1x00/pb1500.h
+++ /dev/null
@@ -1,49 +0,0 @@
1/*
2 * Alchemy Semi Pb1500 Referrence Board
3 *
4 * Copyright 2001, 2008 MontaVista Software Inc.
5 * Author: MontaVista Software, Inc. <source@mvista.com>
6 *
7 * ########################################################################
8 *
9 * This program is free software; you can distribute it and/or modify it
10 * under the terms of the GNU General Public License (Version 2) as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * for more details.
17 *
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, write to the Free Software Foundation, Inc.,
20 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
21 *
22 * ########################################################################
23 *
24 *
25 */
26#ifndef __ASM_PB1500_H
27#define __ASM_PB1500_H
28
29#define IDENT_BOARD_REG 0xAE000000
30#define BOARD_STATUS_REG 0xAE000004
31#define PCI_BOARD_REG 0xAE000010
32#define PCMCIA_BOARD_REG 0xAE000010
33# define PC_DEASSERT_RST 0x80
34# define PC_DRV_EN 0x10
35#define PB1500_G_CONTROL 0xAE000014
36#define PB1500_RST_VDDI 0xAE00001C
37#define PB1500_LEDS 0xAE000018
38
39#define PB1500_HEX_LED 0xAF000004
40#define PB1500_HEX_LED_BLANK 0xAF000008
41
42/* PCMCIA Pb1500 specific defines */
43#define PCMCIA_MAX_SOCK 0
44#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1)
45
46/* VPP/VCC */
47#define SET_VCC_VPP(VCC, VPP) (((VCC) << 2) | ((VPP) << 0))
48
49#endif /* __ASM_PB1500_H */
diff --git a/arch/mips/include/asm/mach-pb1x00/pb1550.h b/arch/mips/include/asm/mach-pb1x00/pb1550.h
index 6704a11497db..58796410bd6e 100644
--- a/arch/mips/include/asm/mach-pb1x00/pb1550.h
+++ b/arch/mips/include/asm/mach-pb1x00/pb1550.h
@@ -40,102 +40,6 @@
40#define SMBUS_PSC_BASE PSC2_BASE_ADDR 40#define SMBUS_PSC_BASE PSC2_BASE_ADDR
41#define I2S_PSC_BASE PSC3_BASE_ADDR 41#define I2S_PSC_BASE PSC3_BASE_ADDR
42 42
43#define BCSR_PHYS_ADDR 0xAF000000
44
45typedef volatile struct
46{
47 /*00*/ u16 whoami;
48 u16 reserved0;
49 /*04*/ u16 status;
50 u16 reserved1;
51 /*08*/ u16 switches;
52 u16 reserved2;
53 /*0C*/ u16 resets;
54 u16 reserved3;
55 /*10*/ u16 pcmcia;
56 u16 reserved4;
57 /*14*/ u16 pci;
58 u16 reserved5;
59 /*18*/ u16 leds;
60 u16 reserved6;
61 /*1C*/ u16 system;
62 u16 reserved7;
63
64} BCSR;
65
66static BCSR * const bcsr = (BCSR *)BCSR_PHYS_ADDR;
67
68/*
69 * Register bit definitions for the BCSRs
70 */
71#define BCSR_WHOAMI_DCID 0x000F
72#define BCSR_WHOAMI_CPLD 0x00F0
73#define BCSR_WHOAMI_BOARD 0x0F00
74
75#define BCSR_STATUS_PCMCIA0VS 0x0003
76#define BCSR_STATUS_PCMCIA1VS 0x000C
77#define BCSR_STATUS_PCMCIA0FI 0x0010
78#define BCSR_STATUS_PCMCIA1FI 0x0020
79#define BCSR_STATUS_SWAPBOOT 0x0040
80#define BCSR_STATUS_SRAMWIDTH 0x0080
81#define BCSR_STATUS_FLASHBUSY 0x0100
82#define BCSR_STATUS_ROMBUSY 0x0200
83#define BCSR_STATUS_USBOTGID 0x0800
84#define BCSR_STATUS_U0RXD 0x1000
85#define BCSR_STATUS_U1RXD 0x2000
86#define BCSR_STATUS_U3RXD 0x8000
87
88#define BCSR_SWITCHES_OCTAL 0x00FF
89#define BCSR_SWITCHES_DIP_1 0x0080
90#define BCSR_SWITCHES_DIP_2 0x0040
91#define BCSR_SWITCHES_DIP_3 0x0020
92#define BCSR_SWITCHES_DIP_4 0x0010
93#define BCSR_SWITCHES_DIP_5 0x0008
94#define BCSR_SWITCHES_DIP_6 0x0004
95#define BCSR_SWITCHES_DIP_7 0x0002
96#define BCSR_SWITCHES_DIP_8 0x0001
97#define BCSR_SWITCHES_ROTARY 0x0F00
98
99#define BCSR_RESETS_PHY0 0x0001
100#define BCSR_RESETS_PHY1 0x0002
101#define BCSR_RESETS_DC 0x0004
102#define BCSR_RESETS_WSC 0x2000
103#define BCSR_RESETS_SPISEL 0x4000
104#define BCSR_RESETS_DMAREQ 0x8000
105
106#define BCSR_PCMCIA_PC0VPP 0x0003
107#define BCSR_PCMCIA_PC0VCC 0x000C
108#define BCSR_PCMCIA_PC0DRVEN 0x0010
109#define BCSR_PCMCIA_PC0RST 0x0080
110#define BCSR_PCMCIA_PC1VPP 0x0300
111#define BCSR_PCMCIA_PC1VCC 0x0C00
112#define BCSR_PCMCIA_PC1DRVEN 0x1000
113#define BCSR_PCMCIA_PC1RST 0x8000
114
115#define BCSR_PCI_M66EN 0x0001
116#define BCSR_PCI_M33 0x0100
117#define BCSR_PCI_EXTERNARB 0x0200
118#define BCSR_PCI_GPIO200RST 0x0400
119#define BCSR_PCI_CLKOUT 0x0800
120#define BCSR_PCI_CFGHOST 0x1000
121
122#define BCSR_LEDS_DECIMALS 0x00FF
123#define BCSR_LEDS_LED0 0x0100
124#define BCSR_LEDS_LED1 0x0200
125#define BCSR_LEDS_LED2 0x0400
126#define BCSR_LEDS_LED3 0x0800
127
128#define BCSR_SYSTEM_VDDI 0x001F
129#define BCSR_SYSTEM_POWEROFF 0x4000
130#define BCSR_SYSTEM_RESET 0x8000
131
132#define PCMCIA_MAX_SOCK 1
133#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1)
134
135/* VPP/VCC */
136#define SET_VCC_VPP(VCC, VPP, SLOT) \
137 ((((VCC) << 2) | ((VPP) << 0)) << ((SLOT) * 8))
138
139#if defined(CONFIG_MTD_PB1550_BOOT) && defined(CONFIG_MTD_PB1550_USER) 43#if defined(CONFIG_MTD_PB1550_BOOT) && defined(CONFIG_MTD_PB1550_USER)
140#define PB1550_BOTH_BANKS 44#define PB1550_BOTH_BANKS
141#elif defined(CONFIG_MTD_PB1550_BOOT) && !defined(CONFIG_MTD_PB1550_USER) 45#elif defined(CONFIG_MTD_PB1550_BOOT) && !defined(CONFIG_MTD_PB1550_USER)
diff --git a/arch/mips/include/asm/mach-pnx833x/irq-mapping.h b/arch/mips/include/asm/mach-pnx833x/irq-mapping.h
index 657f089b1724..6d70264557b2 100644
--- a/arch/mips/include/asm/mach-pnx833x/irq-mapping.h
+++ b/arch/mips/include/asm/mach-pnx833x/irq-mapping.h
@@ -123,4 +123,3 @@
123#define PNX833X_GPIO_15_INT (PNX833X_GPIO_IRQ_BASE + 15) 123#define PNX833X_GPIO_15_INT (PNX833X_GPIO_IRQ_BASE + 15)
124 124
125#endif 125#endif
126
diff --git a/arch/mips/include/asm/mach-powertv/interrupts.h b/arch/mips/include/asm/mach-powertv/interrupts.h
index 629a57413657..4fd652ceb52a 100644
--- a/arch/mips/include/asm/mach-powertv/interrupts.h
+++ b/arch/mips/include/asm/mach-powertv/interrupts.h
@@ -251,4 +251,3 @@
251 * channel 3. */ 251 * channel 3. */
252#define irq_mpeg_d (ibase+0) /* MPEG Decoder Interrupt */ 252#define irq_mpeg_d (ibase+0) /* MPEG Decoder Interrupt */
253#endif /* _ASM_MACH_POWERTV_INTERRUPTS_H_ */ 253#endif /* _ASM_MACH_POWERTV_INTERRUPTS_H_ */
254
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index f4ab3139d737..49382d5e891a 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -251,6 +251,14 @@
251#define PL_256M 28 251#define PL_256M 28
252 252
253/* 253/*
254 * PageGrain bits
255 */
256#define PG_RIE (_ULCAST_(1) << 31)
257#define PG_XIE (_ULCAST_(1) << 30)
258#define PG_ELPA (_ULCAST_(1) << 29)
259#define PG_ESP (_ULCAST_(1) << 28)
260
261/*
254 * R4x00 interrupt enable / cause bits 262 * R4x00 interrupt enable / cause bits
255 */ 263 */
256#define IE_SW0 (_ULCAST_(1) << 8) 264#define IE_SW0 (_ULCAST_(1) << 8)
@@ -576,6 +584,10 @@
576#define MIPS_CONF3_DSP (_ULCAST_(1) << 10) 584#define MIPS_CONF3_DSP (_ULCAST_(1) << 10)
577#define MIPS_CONF3_ULRI (_ULCAST_(1) << 13) 585#define MIPS_CONF3_ULRI (_ULCAST_(1) << 13)
578 586
587#define MIPS_CONF4_MMUSIZEEXT (_ULCAST_(255) << 0)
588#define MIPS_CONF4_MMUEXTDEF (_ULCAST_(3) << 14)
589#define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14)
590
579#define MIPS_CONF7_WII (_ULCAST_(1) << 31) 591#define MIPS_CONF7_WII (_ULCAST_(1) << 31)
580 592
581#define MIPS_CONF7_RPS (_ULCAST_(1) << 2) 593#define MIPS_CONF7_RPS (_ULCAST_(1) << 2)
@@ -826,6 +838,9 @@ do { \
826#define read_c0_pagemask() __read_32bit_c0_register($5, 0) 838#define read_c0_pagemask() __read_32bit_c0_register($5, 0)
827#define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val) 839#define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val)
828 840
841#define read_c0_pagegrain() __read_32bit_c0_register($5, 1)
842#define write_c0_pagegrain(val) __write_32bit_c0_register($5, 1, val)
843
829#define read_c0_wired() __read_32bit_c0_register($6, 0) 844#define read_c0_wired() __read_32bit_c0_register($6, 0)
830#define write_c0_wired(val) __write_32bit_c0_register($6, 0, val) 845#define write_c0_wired(val) __write_32bit_c0_register($6, 0, val)
831 846
diff --git a/arch/mips/include/asm/msc01_ic.h b/arch/mips/include/asm/msc01_ic.h
index 7989b9ffc1d2..d92406ae2841 100644
--- a/arch/mips/include/asm/msc01_ic.h
+++ b/arch/mips/include/asm/msc01_ic.h
@@ -145,4 +145,3 @@ extern void __init init_msc_irqs(unsigned long icubase, unsigned int base, msc_i
145extern void ll_msc_irq(void); 145extern void ll_msc_irq(void);
146 146
147#endif /* __ASM_MIPS_BOARDS_MSC01_IC_H */ 147#endif /* __ASM_MIPS_BOARDS_MSC01_IC_H */
148
diff --git a/arch/mips/include/asm/nile4.h b/arch/mips/include/asm/nile4.h
index c3ca959aa4d9..af0e51a9f68a 100644
--- a/arch/mips/include/asm/nile4.h
+++ b/arch/mips/include/asm/nile4.h
@@ -307,4 +307,3 @@ extern u8 nile4_i8259_iack(void);
307extern void nile4_dump_irq_status(void); /* Debug */ 307extern void nile4_dump_irq_status(void); /* Debug */
308 308
309#endif 309#endif
310
diff --git a/arch/mips/include/asm/octeon/octeon-feature.h b/arch/mips/include/asm/octeon/octeon-feature.h
index ef24a7b4ea57..cba6fbed9f43 100644
--- a/arch/mips/include/asm/octeon/octeon-feature.h
+++ b/arch/mips/include/asm/octeon/octeon-feature.h
@@ -99,6 +99,8 @@ static inline int octeon_has_feature(enum octeon_feature feature)
99 return !cvmx_fuse_read(90); 99 return !cvmx_fuse_read(90);
100 100
101 case OCTEON_FEATURE_PCIE: 101 case OCTEON_FEATURE_PCIE:
102 case OCTEON_FEATURE_MGMT_PORT:
103 case OCTEON_FEATURE_RAID:
102 return OCTEON_IS_MODEL(OCTEON_CN56XX) 104 return OCTEON_IS_MODEL(OCTEON_CN56XX)
103 || OCTEON_IS_MODEL(OCTEON_CN52XX); 105 || OCTEON_IS_MODEL(OCTEON_CN52XX);
104 106
@@ -110,12 +112,6 @@ static inline int octeon_has_feature(enum octeon_feature feature)
110 case OCTEON_FEATURE_TRA: 112 case OCTEON_FEATURE_TRA:
111 return !(OCTEON_IS_MODEL(OCTEON_CN30XX) 113 return !(OCTEON_IS_MODEL(OCTEON_CN30XX)
112 || OCTEON_IS_MODEL(OCTEON_CN50XX)); 114 || OCTEON_IS_MODEL(OCTEON_CN50XX));
113 case OCTEON_FEATURE_MGMT_PORT:
114 return OCTEON_IS_MODEL(OCTEON_CN56XX)
115 || OCTEON_IS_MODEL(OCTEON_CN52XX);
116 case OCTEON_FEATURE_RAID:
117 return OCTEON_IS_MODEL(OCTEON_CN56XX)
118 || OCTEON_IS_MODEL(OCTEON_CN52XX);
119 case OCTEON_FEATURE_USB: 115 case OCTEON_FEATURE_USB:
120 return !(OCTEON_IS_MODEL(OCTEON_CN38XX) 116 return !(OCTEON_IS_MODEL(OCTEON_CN38XX)
121 || OCTEON_IS_MODEL(OCTEON_CN58XX)); 117 || OCTEON_IS_MODEL(OCTEON_CN58XX));
diff --git a/arch/mips/include/asm/octeon/octeon.h b/arch/mips/include/asm/octeon/octeon.h
index 4d0a8c61fc3e..ca6214b5ccb9 100644
--- a/arch/mips/include/asm/octeon/octeon.h
+++ b/arch/mips/include/asm/octeon/octeon.h
@@ -213,6 +213,11 @@ struct octeon_cf_data {
213 int dma_engine; /* -1 for no DMA */ 213 int dma_engine; /* -1 for no DMA */
214}; 214};
215 215
216struct octeon_i2c_data {
217 unsigned int sys_freq;
218 unsigned int i2c_freq;
219};
220
216extern void octeon_write_lcd(const char *s); 221extern void octeon_write_lcd(const char *s);
217extern void octeon_check_cpu_bist(void); 222extern void octeon_check_cpu_bist(void);
218extern int octeon_get_boot_debug_flag(void); 223extern int octeon_get_boot_debug_flag(void);
diff --git a/arch/mips/include/asm/page.h b/arch/mips/include/asm/page.h
index f266295cce51..ac32572430f4 100644
--- a/arch/mips/include/asm/page.h
+++ b/arch/mips/include/asm/page.h
@@ -107,18 +107,6 @@ typedef struct { unsigned long pte; } pte_t;
107typedef struct page *pgtable_t; 107typedef struct page *pgtable_t;
108 108
109/* 109/*
110 * For 3-level pagetables we defines these ourselves, for 2-level the
111 * definitions are supplied by <asm-generic/pgtable-nopmd.h>.
112 */
113#ifdef CONFIG_64BIT
114
115typedef struct { unsigned long pmd; } pmd_t;
116#define pmd_val(x) ((x).pmd)
117#define __pmd(x) ((pmd_t) { (x) } )
118
119#endif
120
121/*
122 * Right now we don't support 4-level pagetables, so all pud-related 110 * Right now we don't support 4-level pagetables, so all pud-related
123 * definitions come from <asm-generic/pgtable-nopud.h>. 111 * definitions come from <asm-generic/pgtable-nopud.h>.
124 */ 112 */
diff --git a/arch/mips/include/asm/param.h b/arch/mips/include/asm/param.h
index 1d9bb8c5ab24..da3920fce9ad 100644
--- a/arch/mips/include/asm/param.h
+++ b/arch/mips/include/asm/param.h
@@ -9,23 +9,8 @@
9#ifndef _ASM_PARAM_H 9#ifndef _ASM_PARAM_H
10#define _ASM_PARAM_H 10#define _ASM_PARAM_H
11 11
12#ifdef __KERNEL__
13
14# define HZ CONFIG_HZ /* Internal kernel timer frequency */
15# define USER_HZ 100 /* .. some user interfaces are in "ticks" */
16# define CLOCKS_PER_SEC (USER_HZ) /* like times() */
17#endif
18
19#ifndef HZ
20#define HZ 100
21#endif
22
23#define EXEC_PAGESIZE 65536 12#define EXEC_PAGESIZE 65536
24 13
25#ifndef NOGROUP 14#include <asm-generic/param.h>
26#define NOGROUP (-1)
27#endif
28
29#define MAXHOSTNAMELEN 64 /* max length of hostname */
30 15
31#endif /* _ASM_PARAM_H */ 16#endif /* _ASM_PARAM_H */
diff --git a/arch/mips/include/asm/parport.h b/arch/mips/include/asm/parport.h
index f52656826cce..cf252af64590 100644
--- a/arch/mips/include/asm/parport.h
+++ b/arch/mips/include/asm/parport.h
@@ -1,15 +1 @@
1/* #include <asm-generic/parport.h>
2 * Copyright (C) 1999, 2000 Tim Waugh <tim@cyberelk.demon.co.uk>
3 *
4 * This file should only be included by drivers/parport/parport_pc.c.
5 */
6#ifndef _ASM_PARPORT_H
7#define _ASM_PARPORT_H
8
9static int __devinit parport_pc_find_isa_ports(int autoirq, int autodma);
10static int __devinit parport_pc_find_nonpci_ports(int autoirq, int autodma)
11{
12 return parport_pc_find_isa_ports(autoirq, autodma);
13}
14
15#endif /* _ASM_PARPORT_H */
diff --git a/arch/mips/include/asm/pgalloc.h b/arch/mips/include/asm/pgalloc.h
index 3738f4b48cbd..881d18b4e298 100644
--- a/arch/mips/include/asm/pgalloc.h
+++ b/arch/mips/include/asm/pgalloc.h
@@ -31,7 +31,7 @@ static inline void pmd_populate(struct mm_struct *mm, pmd_t *pmd,
31 */ 31 */
32extern void pmd_init(unsigned long page, unsigned long pagetable); 32extern void pmd_init(unsigned long page, unsigned long pagetable);
33 33
34#ifdef CONFIG_64BIT 34#ifndef __PAGETABLE_PMD_FOLDED
35 35
36static inline void pud_populate(struct mm_struct *mm, pud_t *pud, pmd_t *pmd) 36static inline void pud_populate(struct mm_struct *mm, pud_t *pud, pmd_t *pmd)
37{ 37{
@@ -104,7 +104,7 @@ do { \
104 tlb_remove_page((tlb), pte); \ 104 tlb_remove_page((tlb), pte); \
105} while (0) 105} while (0)
106 106
107#ifdef CONFIG_64BIT 107#ifndef __PAGETABLE_PMD_FOLDED
108 108
109static inline pmd_t *pmd_alloc_one(struct mm_struct *mm, unsigned long address) 109static inline pmd_t *pmd_alloc_one(struct mm_struct *mm, unsigned long address)
110{ 110{
diff --git a/arch/mips/include/asm/pgtable-32.h b/arch/mips/include/asm/pgtable-32.h
index 55813d6150c7..ae90412556d0 100644
--- a/arch/mips/include/asm/pgtable-32.h
+++ b/arch/mips/include/asm/pgtable-32.h
@@ -127,8 +127,8 @@ pfn_pte(unsigned long pfn, pgprot_t prot)
127#define pte_pfn(x) ((unsigned long)((x).pte >> (PAGE_SHIFT + 2))) 127#define pte_pfn(x) ((unsigned long)((x).pte >> (PAGE_SHIFT + 2)))
128#define pfn_pte(pfn, prot) __pte(((pfn) << (PAGE_SHIFT + 2)) | pgprot_val(prot)) 128#define pfn_pte(pfn, prot) __pte(((pfn) << (PAGE_SHIFT + 2)) | pgprot_val(prot))
129#else 129#else
130#define pte_pfn(x) ((unsigned long)((x).pte >> PAGE_SHIFT)) 130#define pte_pfn(x) ((unsigned long)((x).pte >> _PFN_SHIFT))
131#define pfn_pte(pfn, prot) __pte(((unsigned long long)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) 131#define pfn_pte(pfn, prot) __pte(((unsigned long long)(pfn) << _PFN_SHIFT) | pgprot_val(prot))
132#endif 132#endif
133#endif /* defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) */ 133#endif /* defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) */
134 134
diff --git a/arch/mips/include/asm/pgtable-64.h b/arch/mips/include/asm/pgtable-64.h
index 9cd508993956..26dc69d792a6 100644
--- a/arch/mips/include/asm/pgtable-64.h
+++ b/arch/mips/include/asm/pgtable-64.h
@@ -16,7 +16,11 @@
16#include <asm/cachectl.h> 16#include <asm/cachectl.h>
17#include <asm/fixmap.h> 17#include <asm/fixmap.h>
18 18
19#ifdef CONFIG_PAGE_SIZE_64KB
20#include <asm-generic/pgtable-nopmd.h>
21#else
19#include <asm-generic/pgtable-nopud.h> 22#include <asm-generic/pgtable-nopud.h>
23#endif
20 24
21/* 25/*
22 * Each address space has 2 4K pages as its page directory, giving 1024 26 * Each address space has 2 4K pages as its page directory, giving 1024
@@ -37,13 +41,20 @@
37 * fault address - VMALLOC_START. 41 * fault address - VMALLOC_START.
38 */ 42 */
39 43
44
45/* PGDIR_SHIFT determines what a third-level page table entry can map */
46#ifdef __PAGETABLE_PMD_FOLDED
47#define PGDIR_SHIFT (PAGE_SHIFT + PAGE_SHIFT + PTE_ORDER - 3)
48#else
49
40/* PMD_SHIFT determines the size of the area a second-level page table can map */ 50/* PMD_SHIFT determines the size of the area a second-level page table can map */
41#define PMD_SHIFT (PAGE_SHIFT + (PAGE_SHIFT + PTE_ORDER - 3)) 51#define PMD_SHIFT (PAGE_SHIFT + (PAGE_SHIFT + PTE_ORDER - 3))
42#define PMD_SIZE (1UL << PMD_SHIFT) 52#define PMD_SIZE (1UL << PMD_SHIFT)
43#define PMD_MASK (~(PMD_SIZE-1)) 53#define PMD_MASK (~(PMD_SIZE-1))
44 54
45/* PGDIR_SHIFT determines what a third-level page table entry can map */ 55
46#define PGDIR_SHIFT (PMD_SHIFT + (PAGE_SHIFT + PMD_ORDER - 3)) 56#define PGDIR_SHIFT (PMD_SHIFT + (PAGE_SHIFT + PMD_ORDER - 3))
57#endif
47#define PGDIR_SIZE (1UL << PGDIR_SHIFT) 58#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
48#define PGDIR_MASK (~(PGDIR_SIZE-1)) 59#define PGDIR_MASK (~(PGDIR_SIZE-1))
49 60
@@ -92,12 +103,14 @@
92#ifdef CONFIG_PAGE_SIZE_64KB 103#ifdef CONFIG_PAGE_SIZE_64KB
93#define PGD_ORDER 0 104#define PGD_ORDER 0
94#define PUD_ORDER aieeee_attempt_to_allocate_pud 105#define PUD_ORDER aieeee_attempt_to_allocate_pud
95#define PMD_ORDER 0 106#define PMD_ORDER aieeee_attempt_to_allocate_pmd
96#define PTE_ORDER 0 107#define PTE_ORDER 0
97#endif 108#endif
98 109
99#define PTRS_PER_PGD ((PAGE_SIZE << PGD_ORDER) / sizeof(pgd_t)) 110#define PTRS_PER_PGD ((PAGE_SIZE << PGD_ORDER) / sizeof(pgd_t))
111#ifndef __PAGETABLE_PMD_FOLDED
100#define PTRS_PER_PMD ((PAGE_SIZE << PMD_ORDER) / sizeof(pmd_t)) 112#define PTRS_PER_PMD ((PAGE_SIZE << PMD_ORDER) / sizeof(pmd_t))
113#endif
101#define PTRS_PER_PTE ((PAGE_SIZE << PTE_ORDER) / sizeof(pte_t)) 114#define PTRS_PER_PTE ((PAGE_SIZE << PTE_ORDER) / sizeof(pte_t))
102 115
103#if PGDIR_SIZE >= TASK_SIZE 116#if PGDIR_SIZE >= TASK_SIZE
@@ -110,7 +123,9 @@
110#define VMALLOC_START MAP_BASE 123#define VMALLOC_START MAP_BASE
111#define VMALLOC_END \ 124#define VMALLOC_END \
112 (VMALLOC_START + \ 125 (VMALLOC_START + \
113 PTRS_PER_PGD * PTRS_PER_PMD * PTRS_PER_PTE * PAGE_SIZE - (1UL << 32)) 126 min(PTRS_PER_PGD * PTRS_PER_PMD * PTRS_PER_PTE * PAGE_SIZE, \
127 (1UL << cpu_vmbits)) - (1UL << 32))
128
114#if defined(CONFIG_MODULES) && defined(KBUILD_64BIT_SYM32) && \ 129#if defined(CONFIG_MODULES) && defined(KBUILD_64BIT_SYM32) && \
115 VMALLOC_START != CKSSEG 130 VMALLOC_START != CKSSEG
116/* Load modules into 32bit-compatible segment. */ 131/* Load modules into 32bit-compatible segment. */
@@ -120,15 +135,30 @@
120 135
121#define pte_ERROR(e) \ 136#define pte_ERROR(e) \
122 printk("%s:%d: bad pte %016lx.\n", __FILE__, __LINE__, pte_val(e)) 137 printk("%s:%d: bad pte %016lx.\n", __FILE__, __LINE__, pte_val(e))
138#ifndef __PAGETABLE_PMD_FOLDED
123#define pmd_ERROR(e) \ 139#define pmd_ERROR(e) \
124 printk("%s:%d: bad pmd %016lx.\n", __FILE__, __LINE__, pmd_val(e)) 140 printk("%s:%d: bad pmd %016lx.\n", __FILE__, __LINE__, pmd_val(e))
141#endif
125#define pgd_ERROR(e) \ 142#define pgd_ERROR(e) \
126 printk("%s:%d: bad pgd %016lx.\n", __FILE__, __LINE__, pgd_val(e)) 143 printk("%s:%d: bad pgd %016lx.\n", __FILE__, __LINE__, pgd_val(e))
127 144
128extern pte_t invalid_pte_table[PTRS_PER_PTE]; 145extern pte_t invalid_pte_table[PTRS_PER_PTE];
129extern pte_t empty_bad_page_table[PTRS_PER_PTE]; 146extern pte_t empty_bad_page_table[PTRS_PER_PTE];
147
148
149#ifndef __PAGETABLE_PMD_FOLDED
150/*
151 * For 3-level pagetables we defines these ourselves, for 2-level the
152 * definitions are supplied by <asm-generic/pgtable-nopmd.h>.
153 */
154typedef struct { unsigned long pmd; } pmd_t;
155#define pmd_val(x) ((x).pmd)
156#define __pmd(x) ((pmd_t) { (x) } )
157
158
130extern pmd_t invalid_pmd_table[PTRS_PER_PMD]; 159extern pmd_t invalid_pmd_table[PTRS_PER_PMD];
131extern pmd_t empty_bad_pmd_table[PTRS_PER_PMD]; 160extern pmd_t empty_bad_pmd_table[PTRS_PER_PMD];
161#endif
132 162
133/* 163/*
134 * Empty pgd/pmd entries point to the invalid_pte_table. 164 * Empty pgd/pmd entries point to the invalid_pte_table.
@@ -149,6 +179,7 @@ static inline void pmd_clear(pmd_t *pmdp)
149{ 179{
150 pmd_val(*pmdp) = ((unsigned long) invalid_pte_table); 180 pmd_val(*pmdp) = ((unsigned long) invalid_pte_table);
151} 181}
182#ifndef __PAGETABLE_PMD_FOLDED
152 183
153/* 184/*
154 * Empty pud entries point to the invalid_pmd_table. 185 * Empty pud entries point to the invalid_pmd_table.
@@ -172,6 +203,7 @@ static inline void pud_clear(pud_t *pudp)
172{ 203{
173 pud_val(*pudp) = ((unsigned long) invalid_pmd_table); 204 pud_val(*pudp) = ((unsigned long) invalid_pmd_table);
174} 205}
206#endif
175 207
176#define pte_page(x) pfn_to_page(pte_pfn(x)) 208#define pte_page(x) pfn_to_page(pte_pfn(x))
177 209
@@ -179,8 +211,8 @@ static inline void pud_clear(pud_t *pudp)
179#define pte_pfn(x) ((unsigned long)((x).pte >> (PAGE_SHIFT + 2))) 211#define pte_pfn(x) ((unsigned long)((x).pte >> (PAGE_SHIFT + 2)))
180#define pfn_pte(pfn, prot) __pte(((pfn) << (PAGE_SHIFT + 2)) | pgprot_val(prot)) 212#define pfn_pte(pfn, prot) __pte(((pfn) << (PAGE_SHIFT + 2)) | pgprot_val(prot))
181#else 213#else
182#define pte_pfn(x) ((unsigned long)((x).pte >> PAGE_SHIFT)) 214#define pte_pfn(x) ((unsigned long)((x).pte >> _PFN_SHIFT))
183#define pfn_pte(pfn, prot) __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot)) 215#define pfn_pte(pfn, prot) __pte(((pfn) << _PFN_SHIFT) | pgprot_val(prot))
184#endif 216#endif
185 217
186#define __pgd_offset(address) pgd_index(address) 218#define __pgd_offset(address) pgd_index(address)
@@ -196,6 +228,7 @@ static inline void pud_clear(pud_t *pudp)
196/* to find an entry in a page-table-directory */ 228/* to find an entry in a page-table-directory */
197#define pgd_offset(mm, addr) ((mm)->pgd + pgd_index(addr)) 229#define pgd_offset(mm, addr) ((mm)->pgd + pgd_index(addr))
198 230
231#ifndef __PAGETABLE_PMD_FOLDED
199static inline unsigned long pud_page_vaddr(pud_t pud) 232static inline unsigned long pud_page_vaddr(pud_t pud)
200{ 233{
201 return pud_val(pud); 234 return pud_val(pud);
@@ -208,6 +241,7 @@ static inline pmd_t *pmd_offset(pud_t * pud, unsigned long address)
208{ 241{
209 return (pmd_t *) pud_page_vaddr(*pud) + pmd_index(address); 242 return (pmd_t *) pud_page_vaddr(*pud) + pmd_index(address);
210} 243}
244#endif
211 245
212/* Find an entry in the third-level page table.. */ 246/* Find an entry in the third-level page table.. */
213#define __pte_offset(address) \ 247#define __pte_offset(address) \
diff --git a/arch/mips/include/asm/pgtable-bits.h b/arch/mips/include/asm/pgtable-bits.h
index 1073e6df8621..e9fe7e97ce4c 100644
--- a/arch/mips/include/asm/pgtable-bits.h
+++ b/arch/mips/include/asm/pgtable-bits.h
@@ -50,7 +50,7 @@
50#define _CACHE_SHIFT 3 50#define _CACHE_SHIFT 3
51#define _CACHE_MASK (7<<3) 51#define _CACHE_MASK (7<<3)
52 52
53#else 53#elif defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
54 54
55#define _PAGE_PRESENT (1<<0) /* implemented in software */ 55#define _PAGE_PRESENT (1<<0) /* implemented in software */
56#define _PAGE_READ (1<<1) /* implemented in software */ 56#define _PAGE_READ (1<<1) /* implemented in software */
@@ -59,8 +59,6 @@
59#define _PAGE_MODIFIED (1<<4) /* implemented in software */ 59#define _PAGE_MODIFIED (1<<4) /* implemented in software */
60#define _PAGE_FILE (1<<4) /* set:pagecache unset:swap */ 60#define _PAGE_FILE (1<<4) /* set:pagecache unset:swap */
61 61
62#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
63
64#define _PAGE_GLOBAL (1<<8) 62#define _PAGE_GLOBAL (1<<8)
65#define _PAGE_VALID (1<<9) 63#define _PAGE_VALID (1<<9)
66#define _PAGE_SILENT_READ (1<<9) /* synonym */ 64#define _PAGE_SILENT_READ (1<<9) /* synonym */
@@ -69,21 +67,113 @@
69#define _CACHE_UNCACHED (1<<11) 67#define _CACHE_UNCACHED (1<<11)
70#define _CACHE_MASK (1<<11) 68#define _CACHE_MASK (1<<11)
71 69
70#else /* 'Normal' r4K case */
71/*
72 * When using the RI/XI bit support, we have 13 bits of flags below
73 * the physical address. The RI/XI bits are placed such that a SRL 5
74 * can strip off the software bits, then a ROTR 2 can move the RI/XI
75 * into bits [63:62]. This also limits physical address to 56 bits,
76 * which is more than we need right now.
77 */
78
79/* implemented in software */
80#define _PAGE_PRESENT_SHIFT (0)
81#define _PAGE_PRESENT (1 << _PAGE_PRESENT_SHIFT)
82/* implemented in software, should be unused if kernel_uses_smartmips_rixi. */
83#define _PAGE_READ_SHIFT (kernel_uses_smartmips_rixi ? _PAGE_PRESENT_SHIFT : _PAGE_PRESENT_SHIFT + 1)
84#define _PAGE_READ ({if (kernel_uses_smartmips_rixi) BUG(); 1 << _PAGE_READ_SHIFT; })
85/* implemented in software */
86#define _PAGE_WRITE_SHIFT (_PAGE_READ_SHIFT + 1)
87#define _PAGE_WRITE (1 << _PAGE_WRITE_SHIFT)
88/* implemented in software */
89#define _PAGE_ACCESSED_SHIFT (_PAGE_WRITE_SHIFT + 1)
90#define _PAGE_ACCESSED (1 << _PAGE_ACCESSED_SHIFT)
91/* implemented in software */
92#define _PAGE_MODIFIED_SHIFT (_PAGE_ACCESSED_SHIFT + 1)
93#define _PAGE_MODIFIED (1 << _PAGE_MODIFIED_SHIFT)
94/* set:pagecache unset:swap */
95#define _PAGE_FILE (_PAGE_MODIFIED)
96
97#ifdef CONFIG_HUGETLB_PAGE
98/* huge tlb page */
99#define _PAGE_HUGE_SHIFT (_PAGE_MODIFIED_SHIFT + 1)
100#define _PAGE_HUGE (1 << _PAGE_HUGE_SHIFT)
72#else 101#else
102#define _PAGE_HUGE_SHIFT (_PAGE_MODIFIED_SHIFT)
103#define _PAGE_HUGE ({BUG(); 1; }) /* Dummy value */
104#endif
73 105
74#define _PAGE_R4KBUG (1<<5) /* workaround for r4k bug */ 106/* Page cannot be executed */
75#define _PAGE_HUGE (1<<5) /* huge tlb page */ 107#define _PAGE_NO_EXEC_SHIFT (kernel_uses_smartmips_rixi ? _PAGE_HUGE_SHIFT + 1 : _PAGE_HUGE_SHIFT)
76#define _PAGE_GLOBAL (1<<6) 108#define _PAGE_NO_EXEC ({if (!kernel_uses_smartmips_rixi) BUG(); 1 << _PAGE_NO_EXEC_SHIFT; })
77#define _PAGE_VALID (1<<7) 109
78#define _PAGE_SILENT_READ (1<<7) /* synonym */ 110/* Page cannot be read */
79#define _PAGE_DIRTY (1<<8) /* The MIPS dirty bit */ 111#define _PAGE_NO_READ_SHIFT (kernel_uses_smartmips_rixi ? _PAGE_NO_EXEC_SHIFT + 1 : _PAGE_NO_EXEC_SHIFT)
80#define _PAGE_SILENT_WRITE (1<<8) 112#define _PAGE_NO_READ ({if (!kernel_uses_smartmips_rixi) BUG(); 1 << _PAGE_NO_READ_SHIFT; })
81#define _CACHE_SHIFT 9 113
82#define _CACHE_MASK (7<<9) 114#define _PAGE_GLOBAL_SHIFT (_PAGE_NO_READ_SHIFT + 1)
115#define _PAGE_GLOBAL (1 << _PAGE_GLOBAL_SHIFT)
116
117#define _PAGE_VALID_SHIFT (_PAGE_GLOBAL_SHIFT + 1)
118#define _PAGE_VALID (1 << _PAGE_VALID_SHIFT)
119/* synonym */
120#define _PAGE_SILENT_READ (_PAGE_VALID)
121
122/* The MIPS dirty bit */
123#define _PAGE_DIRTY_SHIFT (_PAGE_VALID_SHIFT + 1)
124#define _PAGE_DIRTY (1 << _PAGE_DIRTY_SHIFT)
125#define _PAGE_SILENT_WRITE (_PAGE_DIRTY)
126
127#define _CACHE_SHIFT (_PAGE_DIRTY_SHIFT + 1)
128#define _CACHE_MASK (7 << _CACHE_SHIFT)
129
130#define _PFN_SHIFT (PAGE_SHIFT - 12 + _CACHE_SHIFT + 3)
83 131
84#endif
85#endif /* defined(CONFIG_64BIT_PHYS_ADDR && defined(CONFIG_CPU_MIPS32) */ 132#endif /* defined(CONFIG_64BIT_PHYS_ADDR && defined(CONFIG_CPU_MIPS32) */
86 133
134#ifndef _PFN_SHIFT
135#define _PFN_SHIFT PAGE_SHIFT
136#endif
137#define _PFN_MASK (~((1 << (_PFN_SHIFT)) - 1))
138
139#ifndef _PAGE_NO_READ
140#define _PAGE_NO_READ ({BUG(); 0; })
141#define _PAGE_NO_READ_SHIFT ({BUG(); 0; })
142#endif
143#ifndef _PAGE_NO_EXEC
144#define _PAGE_NO_EXEC ({BUG(); 0; })
145#endif
146#ifndef _PAGE_GLOBAL_SHIFT
147#define _PAGE_GLOBAL_SHIFT ilog2(_PAGE_GLOBAL)
148#endif
149
150
151#ifndef __ASSEMBLY__
152/*
153 * pte_to_entrylo converts a page table entry (PTE) into a Mips
154 * entrylo0/1 value.
155 */
156static inline uint64_t pte_to_entrylo(unsigned long pte_val)
157{
158 if (kernel_uses_smartmips_rixi) {
159 int sa;
160#ifdef CONFIG_32BIT
161 sa = 31 - _PAGE_NO_READ_SHIFT;
162#else
163 sa = 63 - _PAGE_NO_READ_SHIFT;
164#endif
165 /*
166 * C has no way to express that this is a DSRL
167 * _PAGE_NO_EXEC_SHIFT followed by a ROTR 2. Luckily
168 * in the fast path this is done in assembly
169 */
170 return (pte_val >> _PAGE_GLOBAL_SHIFT) |
171 ((pte_val & (_PAGE_NO_EXEC | _PAGE_NO_READ)) << sa);
172 }
173
174 return pte_val >> _PAGE_GLOBAL_SHIFT;
175}
176#endif
87 177
88/* 178/*
89 * Cache attributes 179 * Cache attributes
@@ -130,9 +220,9 @@
130 220
131#endif 221#endif
132 222
133#define __READABLE (_PAGE_READ | _PAGE_SILENT_READ | _PAGE_ACCESSED) 223#define __READABLE (_PAGE_SILENT_READ | _PAGE_ACCESSED | (kernel_uses_smartmips_rixi ? 0 : _PAGE_READ))
134#define __WRITEABLE (_PAGE_WRITE | _PAGE_SILENT_WRITE | _PAGE_MODIFIED) 224#define __WRITEABLE (_PAGE_WRITE | _PAGE_SILENT_WRITE | _PAGE_MODIFIED)
135 225
136#define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_MODIFIED | _CACHE_MASK) 226#define _PAGE_CHG_MASK (_PFN_MASK | _PAGE_ACCESSED | _PAGE_MODIFIED | _CACHE_MASK)
137 227
138#endif /* _ASM_PGTABLE_BITS_H */ 228#endif /* _ASM_PGTABLE_BITS_H */
diff --git a/arch/mips/include/asm/pgtable.h b/arch/mips/include/asm/pgtable.h
index 1854336e56a2..7e40f3778179 100644
--- a/arch/mips/include/asm/pgtable.h
+++ b/arch/mips/include/asm/pgtable.h
@@ -22,23 +22,24 @@ struct mm_struct;
22struct vm_area_struct; 22struct vm_area_struct;
23 23
24#define PAGE_NONE __pgprot(_PAGE_PRESENT | _CACHE_CACHABLE_NONCOHERENT) 24#define PAGE_NONE __pgprot(_PAGE_PRESENT | _CACHE_CACHABLE_NONCOHERENT)
25#define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ 25#define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_WRITE | (kernel_uses_smartmips_rixi ? 0 : _PAGE_READ) | \
26 _page_cachable_default) 26 _page_cachable_default)
27#define PAGE_COPY __pgprot(_PAGE_PRESENT | _PAGE_READ | \ 27#define PAGE_COPY __pgprot(_PAGE_PRESENT | (kernel_uses_smartmips_rixi ? 0 : _PAGE_READ) | \
28 _page_cachable_default) 28 (kernel_uses_smartmips_rixi ? _PAGE_NO_EXEC : 0) | _page_cachable_default)
29#define PAGE_READONLY __pgprot(_PAGE_PRESENT | _PAGE_READ | \ 29#define PAGE_READONLY __pgprot(_PAGE_PRESENT | (kernel_uses_smartmips_rixi ? 0 : _PAGE_READ) | \
30 _page_cachable_default) 30 _page_cachable_default)
31#define PAGE_KERNEL __pgprot(_PAGE_PRESENT | __READABLE | __WRITEABLE | \ 31#define PAGE_KERNEL __pgprot(_PAGE_PRESENT | __READABLE | __WRITEABLE | \
32 _PAGE_GLOBAL | _page_cachable_default) 32 _PAGE_GLOBAL | _page_cachable_default)
33#define PAGE_USERIO __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ 33#define PAGE_USERIO __pgprot(_PAGE_PRESENT | (kernel_uses_smartmips_rixi ? 0 : _PAGE_READ) | _PAGE_WRITE | \
34 _page_cachable_default) 34 _page_cachable_default)
35#define PAGE_KERNEL_UNCACHED __pgprot(_PAGE_PRESENT | __READABLE | \ 35#define PAGE_KERNEL_UNCACHED __pgprot(_PAGE_PRESENT | __READABLE | \
36 __WRITEABLE | _PAGE_GLOBAL | _CACHE_UNCACHED) 36 __WRITEABLE | _PAGE_GLOBAL | _CACHE_UNCACHED)
37 37
38/* 38/*
39 * MIPS can't do page protection for execute, and considers that the same like 39 * If _PAGE_NO_EXEC is not defined, we can't do page protection for
40 * read. Also, write permissions imply read permissions. This is the closest 40 * execute, and consider it to be the same as read. Also, write
41 * we can get by reasonable means.. 41 * permissions imply read permissions. This is the closest we can get
42 * by reasonable means..
42 */ 43 */
43 44
44/* 45/*
@@ -177,7 +178,7 @@ static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *pt
177 */ 178 */
178#define set_pmd(pmdptr, pmdval) do { *(pmdptr) = (pmdval); } while(0) 179#define set_pmd(pmdptr, pmdval) do { *(pmdptr) = (pmdval); } while(0)
179 180
180#ifdef CONFIG_64BIT 181#ifndef __PAGETABLE_PMD_FOLDED
181/* 182/*
182 * (puds are folded into pgds so this doesn't get actually called, 183 * (puds are folded into pgds so this doesn't get actually called,
183 * but the define is needed for a generic inline function.) 184 * but the define is needed for a generic inline function.)
@@ -298,8 +299,13 @@ static inline pte_t pte_mkdirty(pte_t pte)
298static inline pte_t pte_mkyoung(pte_t pte) 299static inline pte_t pte_mkyoung(pte_t pte)
299{ 300{
300 pte_val(pte) |= _PAGE_ACCESSED; 301 pte_val(pte) |= _PAGE_ACCESSED;
301 if (pte_val(pte) & _PAGE_READ) 302 if (kernel_uses_smartmips_rixi) {
302 pte_val(pte) |= _PAGE_SILENT_READ; 303 if (!(pte_val(pte) & _PAGE_NO_READ))
304 pte_val(pte) |= _PAGE_SILENT_READ;
305 } else {
306 if (pte_val(pte) & _PAGE_READ)
307 pte_val(pte) |= _PAGE_SILENT_READ;
308 }
303 return pte; 309 return pte;
304} 310}
305 311
@@ -362,8 +368,9 @@ extern void __update_cache(struct vm_area_struct *vma, unsigned long address,
362 pte_t pte); 368 pte_t pte);
363 369
364static inline void update_mmu_cache(struct vm_area_struct *vma, 370static inline void update_mmu_cache(struct vm_area_struct *vma,
365 unsigned long address, pte_t pte) 371 unsigned long address, pte_t *ptep)
366{ 372{
373 pte_t pte = *ptep;
367 __update_tlb(vma, address, pte); 374 __update_tlb(vma, address, pte);
368 __update_cache(vma, address, pte); 375 __update_cache(vma, address, pte);
369} 376}
diff --git a/arch/mips/include/asm/pmc-sierra/msp71xx/msp_prom.h b/arch/mips/include/asm/pmc-sierra/msp71xx/msp_prom.h
index 14ca7dc382a8..54ef1a96d7ce 100644
--- a/arch/mips/include/asm/pmc-sierra/msp71xx/msp_prom.h
+++ b/arch/mips/include/asm/pmc-sierra/msp71xx/msp_prom.h
@@ -118,7 +118,6 @@
118#define ZSP_DUET 'D' /* one DUET zsp engine */ 118#define ZSP_DUET 'D' /* one DUET zsp engine */
119#define ZSP_TRIAD 'T' /* two TRIAD zsp engines */ 119#define ZSP_TRIAD 'T' /* two TRIAD zsp engines */
120 120
121extern char *prom_getcmdline(void);
122extern char *prom_getenv(char *name); 121extern char *prom_getenv(char *name);
123extern void prom_init_cmdline(void); 122extern void prom_init_cmdline(void);
124extern void prom_meminit(void); 123extern void prom_meminit(void);
diff --git a/arch/mips/include/asm/serial.h b/arch/mips/include/asm/serial.h
index c07ebd8eb9e7..a0cb0caff152 100644
--- a/arch/mips/include/asm/serial.h
+++ b/arch/mips/include/asm/serial.h
@@ -1,22 +1 @@
1/* #include <asm-generic/serial.h>
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1999 by Ralf Baechle
7 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
8 */
9#ifndef _ASM_SERIAL_H
10#define _ASM_SERIAL_H
11
12
13/*
14 * This assumes you have a 1.8432 MHz clock for your UART.
15 *
16 * It'd be nice if someone built a serial card with a 24.576 MHz
17 * clock, since the 16550A is capable of handling a top speed of 1.5
18 * megabits/second; but this requires the faster clock.
19 */
20#define BASE_BAUD (1843200 / 16)
21
22#endif /* _ASM_SERIAL_H */
diff --git a/arch/mips/include/asm/sgialib.h b/arch/mips/include/asm/sgialib.h
index 63741ca1e422..2a2f1bddc276 100644
--- a/arch/mips/include/asm/sgialib.h
+++ b/arch/mips/include/asm/sgialib.h
@@ -33,14 +33,6 @@ extern int prom_flags;
33extern void prom_putchar(char c); 33extern void prom_putchar(char c);
34extern char prom_getchar(void); 34extern char prom_getchar(void);
35 35
36/* Memory descriptor management. */
37#define PROM_MAX_PMEMBLOCKS 32
38struct prom_pmemblock {
39 LONG base; /* Within KSEG0 or XKPHYS. */
40 ULONG size; /* In bytes. */
41 ULONG type; /* free or prom memory */
42};
43
44/* Get next memory descriptor after CURR, returns first descriptor 36/* Get next memory descriptor after CURR, returns first descriptor
45 * in chain is CURR is NULL. 37 * in chain is CURR is NULL.
46 */ 38 */
@@ -51,7 +43,6 @@ extern struct linux_mdesc *prom_getmdesc(struct linux_mdesc *curr);
51 * array. 43 * array.
52 */ 44 */
53extern void prom_meminit(void); 45extern void prom_meminit(void);
54extern void prom_fixup_mem_map(unsigned long start_mem, unsigned long end_mem);
55 46
56/* PROM device tree library routines. */ 47/* PROM device tree library routines. */
57#define PROM_NULL_COMPONENT ((pcomponent *) 0) 48#define PROM_NULL_COMPONENT ((pcomponent *) 0)
@@ -62,20 +53,6 @@ extern pcomponent *ArcGetPeer(pcomponent *this);
62/* Get child component of THIS. */ 53/* Get child component of THIS. */
63extern pcomponent *ArcGetChild(pcomponent *this); 54extern pcomponent *ArcGetChild(pcomponent *this);
64 55
65/* Get parent component of CHILD. */
66extern pcomponent *prom_getparent(pcomponent *child);
67
68/* Copy component opaque data of component THIS into BUFFER
69 * if component THIS has opaque data. Returns success or
70 * failure status.
71 */
72extern long prom_getcdata(void *buffer, pcomponent *this);
73
74/* Other misc. component routines. */
75extern pcomponent *prom_childadd(pcomponent *this, pcomponent *tmp, void *data);
76extern long prom_delcomponent(pcomponent *this);
77extern pcomponent *prom_componentbypath(char *path);
78
79/* This is called at prom_init time to identify the 56/* This is called at prom_init time to identify the
80 * ARC architecture we are running on 57 * ARC architecture we are running on
81 */ 58 */
@@ -88,35 +65,13 @@ extern LONG ArcSetEnvironmentVariable(PCHAR name, PCHAR value);
88/* ARCS command line parsing. */ 65/* ARCS command line parsing. */
89extern void prom_init_cmdline(void); 66extern void prom_init_cmdline(void);
90 67
91/* Acquiring info about the current time, etc. */
92extern struct linux_tinfo *prom_gettinfo(void);
93extern unsigned long prom_getrtime(void);
94
95/* File operations. */ 68/* File operations. */
96extern long prom_getvdirent(unsigned long fd, struct linux_vdirent *ent, unsigned long num, unsigned long *cnt);
97extern long prom_open(char *name, enum linux_omode md, unsigned long *fd);
98extern long prom_close(unsigned long fd);
99extern LONG ArcRead(ULONG fd, PVOID buf, ULONG num, PULONG cnt); 69extern LONG ArcRead(ULONG fd, PVOID buf, ULONG num, PULONG cnt);
100extern long prom_getrstatus(unsigned long fd);
101extern LONG ArcWrite(ULONG fd, PVOID buf, ULONG num, PULONG cnt); 70extern LONG ArcWrite(ULONG fd, PVOID buf, ULONG num, PULONG cnt);
102extern long prom_seek(unsigned long fd, struct linux_bigint *off, enum linux_seekmode sm);
103extern long prom_mount(char *name, enum linux_mountops op);
104extern long prom_getfinfo(unsigned long fd, struct linux_finfo *buf);
105extern long prom_setfinfo(unsigned long fd, unsigned long flags, unsigned long msk);
106
107/* Running stand-along programs. */
108extern long prom_load(char *name, unsigned long end, unsigned long *pc, unsigned long *eaddr);
109extern long prom_invoke(unsigned long pc, unsigned long sp, long argc, char **argv, char **envp);
110extern long prom_exec(char *name, long argc, char **argv, char **envp);
111 71
112/* Misc. routines. */ 72/* Misc. routines. */
113extern VOID prom_halt(VOID) __attribute__((noreturn));
114extern VOID prom_powerdown(VOID) __attribute__((noreturn));
115extern VOID prom_restart(VOID) __attribute__((noreturn));
116extern VOID ArcReboot(VOID) __attribute__((noreturn)); 73extern VOID ArcReboot(VOID) __attribute__((noreturn));
117extern VOID ArcEnterInteractiveMode(VOID) __attribute__((noreturn)); 74extern VOID ArcEnterInteractiveMode(VOID) __attribute__((noreturn));
118extern long prom_cfgsave(VOID);
119extern struct linux_sysid *prom_getsysid(VOID);
120extern VOID ArcFlushAllCaches(VOID); 75extern VOID ArcFlushAllCaches(VOID);
121extern DISPLAY_STATUS *ArcGetDisplayStatus(ULONG FileID); 76extern DISPLAY_STATUS *ArcGetDisplayStatus(ULONG FileID);
122 77
diff --git a/arch/mips/include/asm/sibyte/bigsur.h b/arch/mips/include/asm/sibyte/bigsur.h
index ebefe797fc1d..2d1a26d3436a 100644
--- a/arch/mips/include/asm/sibyte/bigsur.h
+++ b/arch/mips/include/asm/sibyte/bigsur.h
@@ -46,4 +46,3 @@
46#endif 46#endif
47 47
48#endif /* __ASM_SIBYTE_BIGSUR_H */ 48#endif /* __ASM_SIBYTE_BIGSUR_H */
49
diff --git a/arch/mips/include/asm/sibyte/sb1250_ldt.h b/arch/mips/include/asm/sibyte/sb1250_ldt.h
index 081e8b1c4ad0..1e76cf137995 100644
--- a/arch/mips/include/asm/sibyte/sb1250_ldt.h
+++ b/arch/mips/include/asm/sibyte/sb1250_ldt.h
@@ -420,4 +420,3 @@
420#endif /* 1250 PASS2 || 112x PASS1 */ 420#endif /* 1250 PASS2 || 112x PASS1 */
421 421
422#endif 422#endif
423
diff --git a/arch/mips/include/asm/sn/klkernvars.h b/arch/mips/include/asm/sn/klkernvars.h
index 5de4c5e8ab30..6af25ba41ade 100644
--- a/arch/mips/include/asm/sn/klkernvars.h
+++ b/arch/mips/include/asm/sn/klkernvars.h
@@ -26,4 +26,3 @@ typedef struct kern_vars_s {
26#endif /* !__ASSEMBLY__ */ 26#endif /* !__ASSEMBLY__ */
27 27
28#endif /* __ASM_SN_KLKERNVARS_H */ 28#endif /* __ASM_SN_KLKERNVARS_H */
29
diff --git a/arch/mips/include/asm/sparsemem.h b/arch/mips/include/asm/sparsemem.h
index 795ac6c23203..7165333ad043 100644
--- a/arch/mips/include/asm/sparsemem.h
+++ b/arch/mips/include/asm/sparsemem.h
@@ -11,4 +11,3 @@
11 11
12#endif /* CONFIG_SPARSEMEM */ 12#endif /* CONFIG_SPARSEMEM */
13#endif /* _MIPS_SPARSEMEM_H */ 13#endif /* _MIPS_SPARSEMEM_H */
14
diff --git a/arch/mips/include/asm/spinlock.h b/arch/mips/include/asm/spinlock.h
index 21ef9efbde43..396e402fbe2c 100644
--- a/arch/mips/include/asm/spinlock.h
+++ b/arch/mips/include/asm/spinlock.h
@@ -36,9 +36,9 @@
36 36
37static inline int arch_spin_is_locked(arch_spinlock_t *lock) 37static inline int arch_spin_is_locked(arch_spinlock_t *lock)
38{ 38{
39 unsigned int counters = ACCESS_ONCE(lock->lock); 39 u32 counters = ACCESS_ONCE(lock->lock);
40 40
41 return ((counters >> 14) ^ counters) & 0x1fff; 41 return ((counters >> 16) ^ counters) & 0xffff;
42} 42}
43 43
44#define arch_spin_lock_flags(lock, flags) arch_spin_lock(lock) 44#define arch_spin_lock_flags(lock, flags) arch_spin_lock(lock)
@@ -47,9 +47,9 @@ static inline int arch_spin_is_locked(arch_spinlock_t *lock)
47 47
48static inline int arch_spin_is_contended(arch_spinlock_t *lock) 48static inline int arch_spin_is_contended(arch_spinlock_t *lock)
49{ 49{
50 unsigned int counters = ACCESS_ONCE(lock->lock); 50 u32 counters = ACCESS_ONCE(lock->lock);
51 51
52 return (((counters >> 14) - counters) & 0x1fff) > 1; 52 return (((counters >> 16) - counters) & 0xffff) > 1;
53} 53}
54#define arch_spin_is_contended arch_spin_is_contended 54#define arch_spin_is_contended arch_spin_is_contended
55 55
@@ -57,6 +57,7 @@ static inline void arch_spin_lock(arch_spinlock_t *lock)
57{ 57{
58 int my_ticket; 58 int my_ticket;
59 int tmp; 59 int tmp;
60 int inc = 0x10000;
60 61
61 if (R10000_LLSC_WAR) { 62 if (R10000_LLSC_WAR) {
62 __asm__ __volatile__ ( 63 __asm__ __volatile__ (
@@ -64,25 +65,24 @@ static inline void arch_spin_lock(arch_spinlock_t *lock)
64 " .set noreorder \n" 65 " .set noreorder \n"
65 " \n" 66 " \n"
66 "1: ll %[ticket], %[ticket_ptr] \n" 67 "1: ll %[ticket], %[ticket_ptr] \n"
67 " addiu %[my_ticket], %[ticket], 0x4000 \n" 68 " addu %[my_ticket], %[ticket], %[inc] \n"
68 " sc %[my_ticket], %[ticket_ptr] \n" 69 " sc %[my_ticket], %[ticket_ptr] \n"
69 " beqzl %[my_ticket], 1b \n" 70 " beqzl %[my_ticket], 1b \n"
70 " nop \n" 71 " nop \n"
71 " srl %[my_ticket], %[ticket], 14 \n" 72 " srl %[my_ticket], %[ticket], 16 \n"
72 " andi %[my_ticket], %[my_ticket], 0x1fff \n" 73 " andi %[ticket], %[ticket], 0xffff \n"
73 " andi %[ticket], %[ticket], 0x1fff \n" 74 " andi %[my_ticket], %[my_ticket], 0xffff \n"
74 " bne %[ticket], %[my_ticket], 4f \n" 75 " bne %[ticket], %[my_ticket], 4f \n"
75 " subu %[ticket], %[my_ticket], %[ticket] \n" 76 " subu %[ticket], %[my_ticket], %[ticket] \n"
76 "2: \n" 77 "2: \n"
77 " .subsection 2 \n" 78 " .subsection 2 \n"
78 "4: andi %[ticket], %[ticket], 0x1fff \n" 79 "4: andi %[ticket], %[ticket], 0xffff \n"
79 " sll %[ticket], 5 \n" 80 " sll %[ticket], 5 \n"
80 " \n" 81 " \n"
81 "6: bnez %[ticket], 6b \n" 82 "6: bnez %[ticket], 6b \n"
82 " subu %[ticket], 1 \n" 83 " subu %[ticket], 1 \n"
83 " \n" 84 " \n"
84 " lw %[ticket], %[ticket_ptr] \n" 85 " lhu %[ticket], %[serving_now_ptr] \n"
85 " andi %[ticket], %[ticket], 0x1fff \n"
86 " beq %[ticket], %[my_ticket], 2b \n" 86 " beq %[ticket], %[my_ticket], 2b \n"
87 " subu %[ticket], %[my_ticket], %[ticket] \n" 87 " subu %[ticket], %[my_ticket], %[ticket] \n"
88 " b 4b \n" 88 " b 4b \n"
@@ -90,36 +90,33 @@ static inline void arch_spin_lock(arch_spinlock_t *lock)
90 " .previous \n" 90 " .previous \n"
91 " .set pop \n" 91 " .set pop \n"
92 : [ticket_ptr] "+m" (lock->lock), 92 : [ticket_ptr] "+m" (lock->lock),
93 [serving_now_ptr] "+m" (lock->h.serving_now),
93 [ticket] "=&r" (tmp), 94 [ticket] "=&r" (tmp),
94 [my_ticket] "=&r" (my_ticket)); 95 [my_ticket] "=&r" (my_ticket)
96 : [inc] "r" (inc));
95 } else { 97 } else {
96 __asm__ __volatile__ ( 98 __asm__ __volatile__ (
97 " .set push # arch_spin_lock \n" 99 " .set push # arch_spin_lock \n"
98 " .set noreorder \n" 100 " .set noreorder \n"
99 " \n" 101 " \n"
100 " ll %[ticket], %[ticket_ptr] \n" 102 "1: ll %[ticket], %[ticket_ptr] \n"
101 "1: addiu %[my_ticket], %[ticket], 0x4000 \n" 103 " addu %[my_ticket], %[ticket], %[inc] \n"
102 " sc %[my_ticket], %[ticket_ptr] \n" 104 " sc %[my_ticket], %[ticket_ptr] \n"
103 " beqz %[my_ticket], 3f \n" 105 " beqz %[my_ticket], 1b \n"
104 " nop \n" 106 " srl %[my_ticket], %[ticket], 16 \n"
105 " srl %[my_ticket], %[ticket], 14 \n" 107 " andi %[ticket], %[ticket], 0xffff \n"
106 " andi %[my_ticket], %[my_ticket], 0x1fff \n" 108 " andi %[my_ticket], %[my_ticket], 0xffff \n"
107 " andi %[ticket], %[ticket], 0x1fff \n"
108 " bne %[ticket], %[my_ticket], 4f \n" 109 " bne %[ticket], %[my_ticket], 4f \n"
109 " subu %[ticket], %[my_ticket], %[ticket] \n" 110 " subu %[ticket], %[my_ticket], %[ticket] \n"
110 "2: \n" 111 "2: \n"
111 " .subsection 2 \n" 112 " .subsection 2 \n"
112 "3: b 1b \n"
113 " ll %[ticket], %[ticket_ptr] \n"
114 " \n"
115 "4: andi %[ticket], %[ticket], 0x1fff \n" 113 "4: andi %[ticket], %[ticket], 0x1fff \n"
116 " sll %[ticket], 5 \n" 114 " sll %[ticket], 5 \n"
117 " \n" 115 " \n"
118 "6: bnez %[ticket], 6b \n" 116 "6: bnez %[ticket], 6b \n"
119 " subu %[ticket], 1 \n" 117 " subu %[ticket], 1 \n"
120 " \n" 118 " \n"
121 " lw %[ticket], %[ticket_ptr] \n" 119 " lhu %[ticket], %[serving_now_ptr] \n"
122 " andi %[ticket], %[ticket], 0x1fff \n"
123 " beq %[ticket], %[my_ticket], 2b \n" 120 " beq %[ticket], %[my_ticket], 2b \n"
124 " subu %[ticket], %[my_ticket], %[ticket] \n" 121 " subu %[ticket], %[my_ticket], %[ticket] \n"
125 " b 4b \n" 122 " b 4b \n"
@@ -127,8 +124,10 @@ static inline void arch_spin_lock(arch_spinlock_t *lock)
127 " .previous \n" 124 " .previous \n"
128 " .set pop \n" 125 " .set pop \n"
129 : [ticket_ptr] "+m" (lock->lock), 126 : [ticket_ptr] "+m" (lock->lock),
127 [serving_now_ptr] "+m" (lock->h.serving_now),
130 [ticket] "=&r" (tmp), 128 [ticket] "=&r" (tmp),
131 [my_ticket] "=&r" (my_ticket)); 129 [my_ticket] "=&r" (my_ticket)
130 : [inc] "r" (inc));
132 } 131 }
133 132
134 smp_llsc_mb(); 133 smp_llsc_mb();
@@ -136,47 +135,16 @@ static inline void arch_spin_lock(arch_spinlock_t *lock)
136 135
137static inline void arch_spin_unlock(arch_spinlock_t *lock) 136static inline void arch_spin_unlock(arch_spinlock_t *lock)
138{ 137{
139 int tmp; 138 unsigned int serving_now = lock->h.serving_now + 1;
140 139 wmb();
141 smp_llsc_mb(); 140 lock->h.serving_now = (u16)serving_now;
142 141 nudge_writes();
143 if (R10000_LLSC_WAR) {
144 __asm__ __volatile__ (
145 " # arch_spin_unlock \n"
146 "1: ll %[ticket], %[ticket_ptr] \n"
147 " addiu %[ticket], %[ticket], 1 \n"
148 " ori %[ticket], %[ticket], 0x2000 \n"
149 " xori %[ticket], %[ticket], 0x2000 \n"
150 " sc %[ticket], %[ticket_ptr] \n"
151 " beqzl %[ticket], 1b \n"
152 : [ticket_ptr] "+m" (lock->lock),
153 [ticket] "=&r" (tmp));
154 } else {
155 __asm__ __volatile__ (
156 " .set push # arch_spin_unlock \n"
157 " .set noreorder \n"
158 " \n"
159 " ll %[ticket], %[ticket_ptr] \n"
160 "1: addiu %[ticket], %[ticket], 1 \n"
161 " ori %[ticket], %[ticket], 0x2000 \n"
162 " xori %[ticket], %[ticket], 0x2000 \n"
163 " sc %[ticket], %[ticket_ptr] \n"
164 " beqz %[ticket], 2f \n"
165 " nop \n"
166 " \n"
167 " .subsection 2 \n"
168 "2: b 1b \n"
169 " ll %[ticket], %[ticket_ptr] \n"
170 " .previous \n"
171 " .set pop \n"
172 : [ticket_ptr] "+m" (lock->lock),
173 [ticket] "=&r" (tmp));
174 }
175} 142}
176 143
177static inline unsigned int arch_spin_trylock(arch_spinlock_t *lock) 144static inline unsigned int arch_spin_trylock(arch_spinlock_t *lock)
178{ 145{
179 int tmp, tmp2, tmp3; 146 int tmp, tmp2, tmp3;
147 int inc = 0x10000;
180 148
181 if (R10000_LLSC_WAR) { 149 if (R10000_LLSC_WAR) {
182 __asm__ __volatile__ ( 150 __asm__ __volatile__ (
@@ -184,11 +152,11 @@ static inline unsigned int arch_spin_trylock(arch_spinlock_t *lock)
184 " .set noreorder \n" 152 " .set noreorder \n"
185 " \n" 153 " \n"
186 "1: ll %[ticket], %[ticket_ptr] \n" 154 "1: ll %[ticket], %[ticket_ptr] \n"
187 " srl %[my_ticket], %[ticket], 14 \n" 155 " srl %[my_ticket], %[ticket], 16 \n"
188 " andi %[my_ticket], %[my_ticket], 0x1fff \n" 156 " andi %[my_ticket], %[my_ticket], 0xffff \n"
189 " andi %[now_serving], %[ticket], 0x1fff \n" 157 " andi %[now_serving], %[ticket], 0xffff \n"
190 " bne %[my_ticket], %[now_serving], 3f \n" 158 " bne %[my_ticket], %[now_serving], 3f \n"
191 " addiu %[ticket], %[ticket], 0x4000 \n" 159 " addu %[ticket], %[ticket], %[inc] \n"
192 " sc %[ticket], %[ticket_ptr] \n" 160 " sc %[ticket], %[ticket_ptr] \n"
193 " beqzl %[ticket], 1b \n" 161 " beqzl %[ticket], 1b \n"
194 " li %[ticket], 1 \n" 162 " li %[ticket], 1 \n"
@@ -201,33 +169,33 @@ static inline unsigned int arch_spin_trylock(arch_spinlock_t *lock)
201 : [ticket_ptr] "+m" (lock->lock), 169 : [ticket_ptr] "+m" (lock->lock),
202 [ticket] "=&r" (tmp), 170 [ticket] "=&r" (tmp),
203 [my_ticket] "=&r" (tmp2), 171 [my_ticket] "=&r" (tmp2),
204 [now_serving] "=&r" (tmp3)); 172 [now_serving] "=&r" (tmp3)
173 : [inc] "r" (inc));
205 } else { 174 } else {
206 __asm__ __volatile__ ( 175 __asm__ __volatile__ (
207 " .set push # arch_spin_trylock \n" 176 " .set push # arch_spin_trylock \n"
208 " .set noreorder \n" 177 " .set noreorder \n"
209 " \n" 178 " \n"
210 " ll %[ticket], %[ticket_ptr] \n" 179 "1: ll %[ticket], %[ticket_ptr] \n"
211 "1: srl %[my_ticket], %[ticket], 14 \n" 180 " srl %[my_ticket], %[ticket], 16 \n"
212 " andi %[my_ticket], %[my_ticket], 0x1fff \n" 181 " andi %[my_ticket], %[my_ticket], 0xffff \n"
213 " andi %[now_serving], %[ticket], 0x1fff \n" 182 " andi %[now_serving], %[ticket], 0xffff \n"
214 " bne %[my_ticket], %[now_serving], 3f \n" 183 " bne %[my_ticket], %[now_serving], 3f \n"
215 " addiu %[ticket], %[ticket], 0x4000 \n" 184 " addu %[ticket], %[ticket], %[inc] \n"
216 " sc %[ticket], %[ticket_ptr] \n" 185 " sc %[ticket], %[ticket_ptr] \n"
217 " beqz %[ticket], 4f \n" 186 " beqz %[ticket], 1b \n"
218 " li %[ticket], 1 \n" 187 " li %[ticket], 1 \n"
219 "2: \n" 188 "2: \n"
220 " .subsection 2 \n" 189 " .subsection 2 \n"
221 "3: b 2b \n" 190 "3: b 2b \n"
222 " li %[ticket], 0 \n" 191 " li %[ticket], 0 \n"
223 "4: b 1b \n"
224 " ll %[ticket], %[ticket_ptr] \n"
225 " .previous \n" 192 " .previous \n"
226 " .set pop \n" 193 " .set pop \n"
227 : [ticket_ptr] "+m" (lock->lock), 194 : [ticket_ptr] "+m" (lock->lock),
228 [ticket] "=&r" (tmp), 195 [ticket] "=&r" (tmp),
229 [my_ticket] "=&r" (tmp2), 196 [my_ticket] "=&r" (tmp2),
230 [now_serving] "=&r" (tmp3)); 197 [now_serving] "=&r" (tmp3)
198 : [inc] "r" (inc));
231 } 199 }
232 200
233 smp_llsc_mb(); 201 smp_llsc_mb();
@@ -305,7 +273,7 @@ static inline void arch_read_unlock(arch_rwlock_t *rw)
305{ 273{
306 unsigned int tmp; 274 unsigned int tmp;
307 275
308 smp_llsc_mb(); 276 smp_mb__before_llsc();
309 277
310 if (R10000_LLSC_WAR) { 278 if (R10000_LLSC_WAR) {
311 __asm__ __volatile__( 279 __asm__ __volatile__(
diff --git a/arch/mips/include/asm/spinlock_types.h b/arch/mips/include/asm/spinlock_types.h
index ee197c2f9c98..c52f36013a9d 100644
--- a/arch/mips/include/asm/spinlock_types.h
+++ b/arch/mips/include/asm/spinlock_types.h
@@ -5,16 +5,28 @@
5# error "please don't include this file directly" 5# error "please don't include this file directly"
6#endif 6#endif
7 7
8typedef struct { 8#include <linux/types.h>
9
10#include <asm/byteorder.h>
11
12typedef union {
9 /* 13 /*
10 * bits 0..13: serving_now 14 * bits 0..15 : serving_now
11 * bits 14 : junk data 15 * bits 16..31 : ticket
12 * bits 15..28: ticket
13 */ 16 */
14 unsigned int lock; 17 u32 lock;
18 struct {
19#ifdef __BIG_ENDIAN
20 u16 ticket;
21 u16 serving_now;
22#else
23 u16 serving_now;
24 u16 ticket;
25#endif
26 } h;
15} arch_spinlock_t; 27} arch_spinlock_t;
16 28
17#define __ARCH_SPIN_LOCK_UNLOCKED { 0 } 29#define __ARCH_SPIN_LOCK_UNLOCKED { .lock = 0 }
18 30
19typedef struct { 31typedef struct {
20 volatile unsigned int lock; 32 volatile unsigned int lock;
diff --git a/arch/mips/include/asm/system.h b/arch/mips/include/asm/system.h
index 83b5509e09e8..bb937ccfba1e 100644
--- a/arch/mips/include/asm/system.h
+++ b/arch/mips/include/asm/system.h
@@ -95,6 +95,8 @@ static inline unsigned long __xchg_u32(volatile int * m, unsigned int val)
95{ 95{
96 __u32 retval; 96 __u32 retval;
97 97
98 smp_mb__before_llsc();
99
98 if (kernel_uses_llsc && R10000_LLSC_WAR) { 100 if (kernel_uses_llsc && R10000_LLSC_WAR) {
99 unsigned long dummy; 101 unsigned long dummy;
100 102
@@ -147,6 +149,8 @@ static inline __u64 __xchg_u64(volatile __u64 * m, __u64 val)
147{ 149{
148 __u64 retval; 150 __u64 retval;
149 151
152 smp_mb__before_llsc();
153
150 if (kernel_uses_llsc && R10000_LLSC_WAR) { 154 if (kernel_uses_llsc && R10000_LLSC_WAR) {
151 unsigned long dummy; 155 unsigned long dummy;
152 156
diff --git a/arch/mips/include/asm/txx9/generic.h b/arch/mips/include/asm/txx9/generic.h
index 827dc22be2ea..64887d3c7ec3 100644
--- a/arch/mips/include/asm/txx9/generic.h
+++ b/arch/mips/include/asm/txx9/generic.h
@@ -42,7 +42,6 @@ struct txx9_board_vec {
42}; 42};
43extern struct txx9_board_vec *txx9_board_vec; 43extern struct txx9_board_vec *txx9_board_vec;
44extern int (*txx9_irq_dispatch)(int pending); 44extern int (*txx9_irq_dispatch)(int pending);
45char *prom_getcmdline(void);
46const char *prom_getenv(const char *name); 45const char *prom_getenv(const char *name);
47void txx9_wdt_init(unsigned long base); 46void txx9_wdt_init(unsigned long base);
48void txx9_wdt_now(unsigned long base); 47void txx9_wdt_now(unsigned long base);
diff --git a/arch/mips/include/asm/uasm.h b/arch/mips/include/asm/uasm.h
new file mode 100644
index 000000000000..b99bd07e199b
--- /dev/null
+++ b/arch/mips/include/asm/uasm.h
@@ -0,0 +1,195 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer
7 * Copyright (C) 2005 Maciej W. Rozycki
8 * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org)
9 */
10
11#include <linux/types.h>
12
13#define Ip_u1u2u3(op) \
14void __cpuinit \
15uasm_i##op(u32 **buf, unsigned int a, unsigned int b, unsigned int c)
16
17#define Ip_u2u1u3(op) \
18void __cpuinit \
19uasm_i##op(u32 **buf, unsigned int a, unsigned int b, unsigned int c)
20
21#define Ip_u3u1u2(op) \
22void __cpuinit \
23uasm_i##op(u32 **buf, unsigned int a, unsigned int b, unsigned int c)
24
25#define Ip_u1u2s3(op) \
26void __cpuinit \
27uasm_i##op(u32 **buf, unsigned int a, unsigned int b, signed int c)
28
29#define Ip_u2s3u1(op) \
30void __cpuinit \
31uasm_i##op(u32 **buf, unsigned int a, signed int b, unsigned int c)
32
33#define Ip_u2u1s3(op) \
34void __cpuinit \
35uasm_i##op(u32 **buf, unsigned int a, unsigned int b, signed int c)
36
37#define Ip_u2u1msbu3(op) \
38void __cpuinit \
39uasm_i##op(u32 **buf, unsigned int a, unsigned int b, unsigned int c, \
40 unsigned int d)
41
42#define Ip_u1u2(op) \
43void __cpuinit uasm_i##op(u32 **buf, unsigned int a, unsigned int b)
44
45#define Ip_u1s2(op) \
46void __cpuinit uasm_i##op(u32 **buf, unsigned int a, signed int b)
47
48#define Ip_u1(op) void __cpuinit uasm_i##op(u32 **buf, unsigned int a)
49
50#define Ip_0(op) void __cpuinit uasm_i##op(u32 **buf)
51
52Ip_u2u1s3(_addiu);
53Ip_u3u1u2(_addu);
54Ip_u2u1u3(_andi);
55Ip_u3u1u2(_and);
56Ip_u1u2s3(_beq);
57Ip_u1u2s3(_beql);
58Ip_u1s2(_bgez);
59Ip_u1s2(_bgezl);
60Ip_u1s2(_bltz);
61Ip_u1s2(_bltzl);
62Ip_u1u2s3(_bne);
63Ip_u2s3u1(_cache);
64Ip_u1u2u3(_dmfc0);
65Ip_u1u2u3(_dmtc0);
66Ip_u2u1s3(_daddiu);
67Ip_u3u1u2(_daddu);
68Ip_u2u1u3(_dsll);
69Ip_u2u1u3(_dsll32);
70Ip_u2u1u3(_dsra);
71Ip_u2u1u3(_dsrl);
72Ip_u2u1u3(_dsrl32);
73Ip_u2u1u3(_drotr);
74Ip_u3u1u2(_dsubu);
75Ip_0(_eret);
76Ip_u1(_j);
77Ip_u1(_jal);
78Ip_u1(_jr);
79Ip_u2s3u1(_ld);
80Ip_u2s3u1(_ll);
81Ip_u2s3u1(_lld);
82Ip_u1s2(_lui);
83Ip_u2s3u1(_lw);
84Ip_u1u2u3(_mfc0);
85Ip_u1u2u3(_mtc0);
86Ip_u2u1u3(_ori);
87Ip_u2s3u1(_pref);
88Ip_0(_rfe);
89Ip_u2s3u1(_sc);
90Ip_u2s3u1(_scd);
91Ip_u2s3u1(_sd);
92Ip_u2u1u3(_sll);
93Ip_u2u1u3(_sra);
94Ip_u2u1u3(_srl);
95Ip_u2u1u3(_rotr);
96Ip_u3u1u2(_subu);
97Ip_u2s3u1(_sw);
98Ip_0(_tlbp);
99Ip_0(_tlbr);
100Ip_0(_tlbwi);
101Ip_0(_tlbwr);
102Ip_u3u1u2(_xor);
103Ip_u2u1u3(_xori);
104Ip_u2u1msbu3(_dins);
105
106/* Handle labels. */
107struct uasm_label {
108 u32 *addr;
109 int lab;
110};
111
112void __cpuinit uasm_build_label(struct uasm_label **lab, u32 *addr, int lid);
113#ifdef CONFIG_64BIT
114int uasm_in_compat_space_p(long addr);
115#endif
116int uasm_rel_hi(long val);
117int uasm_rel_lo(long val);
118void UASM_i_LA_mostly(u32 **buf, unsigned int rs, long addr);
119void UASM_i_LA(u32 **buf, unsigned int rs, long addr);
120
121#define UASM_L_LA(lb) \
122static inline void __cpuinit uasm_l##lb(struct uasm_label **lab, u32 *addr) \
123{ \
124 uasm_build_label(lab, addr, label##lb); \
125}
126
127/* convenience macros for instructions */
128#ifdef CONFIG_64BIT
129# define UASM_i_LW(buf, rs, rt, off) uasm_i_ld(buf, rs, rt, off)
130# define UASM_i_SW(buf, rs, rt, off) uasm_i_sd(buf, rs, rt, off)
131# define UASM_i_SLL(buf, rs, rt, sh) uasm_i_dsll(buf, rs, rt, sh)
132# define UASM_i_SRA(buf, rs, rt, sh) uasm_i_dsra(buf, rs, rt, sh)
133# define UASM_i_SRL(buf, rs, rt, sh) uasm_i_dsrl(buf, rs, rt, sh)
134# define UASM_i_ROTR(buf, rs, rt, sh) uasm_i_drotr(buf, rs, rt, sh)
135# define UASM_i_MFC0(buf, rt, rd...) uasm_i_dmfc0(buf, rt, rd)
136# define UASM_i_MTC0(buf, rt, rd...) uasm_i_dmtc0(buf, rt, rd)
137# define UASM_i_ADDIU(buf, rs, rt, val) uasm_i_daddiu(buf, rs, rt, val)
138# define UASM_i_ADDU(buf, rs, rt, rd) uasm_i_daddu(buf, rs, rt, rd)
139# define UASM_i_SUBU(buf, rs, rt, rd) uasm_i_dsubu(buf, rs, rt, rd)
140# define UASM_i_LL(buf, rs, rt, off) uasm_i_lld(buf, rs, rt, off)
141# define UASM_i_SC(buf, rs, rt, off) uasm_i_scd(buf, rs, rt, off)
142#else
143# define UASM_i_LW(buf, rs, rt, off) uasm_i_lw(buf, rs, rt, off)
144# define UASM_i_SW(buf, rs, rt, off) uasm_i_sw(buf, rs, rt, off)
145# define UASM_i_SLL(buf, rs, rt, sh) uasm_i_sll(buf, rs, rt, sh)
146# define UASM_i_SRA(buf, rs, rt, sh) uasm_i_sra(buf, rs, rt, sh)
147# define UASM_i_SRL(buf, rs, rt, sh) uasm_i_srl(buf, rs, rt, sh)
148# define UASM_i_ROTR(buf, rs, rt, sh) uasm_i_rotr(buf, rs, rt, sh)
149# define UASM_i_MFC0(buf, rt, rd...) uasm_i_mfc0(buf, rt, rd)
150# define UASM_i_MTC0(buf, rt, rd...) uasm_i_mtc0(buf, rt, rd)
151# define UASM_i_ADDIU(buf, rs, rt, val) uasm_i_addiu(buf, rs, rt, val)
152# define UASM_i_ADDU(buf, rs, rt, rd) uasm_i_addu(buf, rs, rt, rd)
153# define UASM_i_SUBU(buf, rs, rt, rd) uasm_i_subu(buf, rs, rt, rd)
154# define UASM_i_LL(buf, rs, rt, off) uasm_i_ll(buf, rs, rt, off)
155# define UASM_i_SC(buf, rs, rt, off) uasm_i_sc(buf, rs, rt, off)
156#endif
157
158#define uasm_i_b(buf, off) uasm_i_beq(buf, 0, 0, off)
159#define uasm_i_beqz(buf, rs, off) uasm_i_beq(buf, rs, 0, off)
160#define uasm_i_beqzl(buf, rs, off) uasm_i_beql(buf, rs, 0, off)
161#define uasm_i_bnez(buf, rs, off) uasm_i_bne(buf, rs, 0, off)
162#define uasm_i_bnezl(buf, rs, off) uasm_i_bnel(buf, rs, 0, off)
163#define uasm_i_move(buf, a, b) UASM_i_ADDU(buf, a, 0, b)
164#define uasm_i_nop(buf) uasm_i_sll(buf, 0, 0, 0)
165#define uasm_i_ssnop(buf) uasm_i_sll(buf, 0, 0, 1)
166#define uasm_i_ehb(buf) uasm_i_sll(buf, 0, 0, 3)
167
168/* Handle relocations. */
169struct uasm_reloc {
170 u32 *addr;
171 unsigned int type;
172 int lab;
173};
174
175/* This is zero so we can use zeroed label arrays. */
176#define UASM_LABEL_INVALID 0
177
178void uasm_r_mips_pc16(struct uasm_reloc **rel, u32 *addr, int lid);
179void uasm_resolve_relocs(struct uasm_reloc *rel, struct uasm_label *lab);
180void uasm_move_relocs(struct uasm_reloc *rel, u32 *first, u32 *end, long off);
181void uasm_move_labels(struct uasm_label *lab, u32 *first, u32 *end, long off);
182void uasm_copy_handler(struct uasm_reloc *rel, struct uasm_label *lab,
183 u32 *first, u32 *end, u32 *target);
184int uasm_insn_has_bdelay(struct uasm_reloc *rel, u32 *addr);
185
186/* Convenience functions for labeled branches. */
187void uasm_il_bltz(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid);
188void uasm_il_b(u32 **p, struct uasm_reloc **r, int lid);
189void uasm_il_beqz(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid);
190void uasm_il_beqzl(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid);
191void uasm_il_bne(u32 **p, struct uasm_reloc **r, unsigned int reg1,
192 unsigned int reg2, int lid);
193void uasm_il_bnez(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid);
194void uasm_il_bgezl(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid);
195void uasm_il_bgez(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid);
diff --git a/arch/mips/include/asm/ucontext.h b/arch/mips/include/asm/ucontext.h
index 8a4b20e88b81..9bc07b9f30fb 100644
--- a/arch/mips/include/asm/ucontext.h
+++ b/arch/mips/include/asm/ucontext.h
@@ -1,21 +1 @@
1/* #include <asm-generic/ucontext.h>
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Low level exception handling
7 *
8 * Copyright (C) 1998, 1999 by Ralf Baechle
9 */
10#ifndef _ASM_UCONTEXT_H
11#define _ASM_UCONTEXT_H
12
13struct ucontext {
14 unsigned long uc_flags;
15 struct ucontext *uc_link;
16 stack_t uc_stack;
17 struct sigcontext uc_mcontext;
18 sigset_t uc_sigmask; /* mask last for extensibility */
19};
20
21#endif /* _ASM_UCONTEXT_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-10 16:17:51 -0500