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-rw-r--r--arch/mips/include/asm/amon.h15
-rw-r--r--arch/mips/include/asm/asmmacro-32.h42
-rw-r--r--arch/mips/include/asm/asmmacro-64.h96
-rw-r--r--arch/mips/include/asm/asmmacro.h107
-rw-r--r--arch/mips/include/asm/bmips.h29
-rw-r--r--arch/mips/include/asm/cpu-features.h7
-rw-r--r--arch/mips/include/asm/cpu-info.h3
-rw-r--r--arch/mips/include/asm/cpu-type.h15
-rw-r--r--arch/mips/include/asm/cpu.h12
-rw-r--r--arch/mips/include/asm/dma-coherence.h9
-rw-r--r--arch/mips/include/asm/elf.h31
-rw-r--r--arch/mips/include/asm/fpu.h104
-rw-r--r--arch/mips/include/asm/highmem.h1
-rw-r--r--arch/mips/include/asm/kvm_host.h7
-rw-r--r--arch/mips/include/asm/mach-ath79/ar71xx_regs.h1
-rw-r--r--arch/mips/include/asm/mach-bcm47xx/bcm47xx.h2
-rw-r--r--arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h1
-rw-r--r--arch/mips/include/asm/mach-bcm47xx/cpu-feature-overrides.h82
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h18
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_hsspi.h8
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h120
-rw-r--r--arch/mips/include/asm/mach-generic/dma-coherence.h4
-rw-r--r--arch/mips/include/asm/mach-generic/floppy.h1
-rw-r--r--arch/mips/include/asm/mach-generic/ide.h6
-rw-r--r--arch/mips/include/asm/mach-jazz/floppy.h1
-rw-r--r--arch/mips/include/asm/mach-jz4740/platform.h1
-rw-r--r--arch/mips/include/asm/mach-netlogic/irq.h3
-rw-r--r--arch/mips/include/asm/mach-netlogic/multi-node.h33
-rw-r--r--arch/mips/include/asm/mach-netlogic/topology.h20
-rw-r--r--arch/mips/include/asm/mips-boards/piix4.h7
-rw-r--r--arch/mips/include/asm/mipsregs.h85
-rw-r--r--arch/mips/include/asm/netlogic/common.h24
-rw-r--r--arch/mips/include/asm/netlogic/mips-extns.h7
-rw-r--r--arch/mips/include/asm/netlogic/xlp-hal/bridge.h69
-rw-r--r--arch/mips/include/asm/netlogic/xlp-hal/iomap.h48
-rw-r--r--arch/mips/include/asm/netlogic/xlp-hal/pcibus.h41
-rw-r--r--arch/mips/include/asm/netlogic/xlp-hal/pic.h77
-rw-r--r--arch/mips/include/asm/netlogic/xlp-hal/sys.h18
-rw-r--r--arch/mips/include/asm/netlogic/xlp-hal/uart.h3
-rw-r--r--arch/mips/include/asm/netlogic/xlp-hal/xlp.h38
-rw-r--r--arch/mips/include/asm/netlogic/xlr/xlr.h5
-rw-r--r--arch/mips/include/asm/octeon/cvmx-helper-board.h9
-rw-r--r--arch/mips/include/asm/page.h25
-rw-r--r--arch/mips/include/asm/rtlx.h49
-rw-r--r--arch/mips/include/asm/switch_to.h16
-rw-r--r--arch/mips/include/asm/syscall.h2
-rw-r--r--arch/mips/include/asm/thread_info.h4
-rw-r--r--arch/mips/include/asm/tlb.h4
-rw-r--r--arch/mips/include/asm/vpe.h131
-rw-r--r--arch/mips/include/uapi/asm/inst.h7
50 files changed, 979 insertions, 469 deletions
diff --git a/arch/mips/include/asm/amon.h b/arch/mips/include/asm/amon.h
index c3dc1a68dd8d..3cc03c64a9c7 100644
--- a/arch/mips/include/asm/amon.h
+++ b/arch/mips/include/asm/amon.h
@@ -1,7 +1,12 @@
1/* 1/*
2 * Amon support 2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2013 Imagination Technologies Ltd.
7 *
8 * Arbitrary Monitor Support (AMON)
3 */ 9 */
4 10int amon_cpu_avail(int cpu);
5int amon_cpu_avail(int); 11int amon_cpu_start(int cpu, unsigned long pc, unsigned long sp,
6void amon_cpu_start(int, unsigned long, unsigned long, 12 unsigned long gp, unsigned long a0);
7 unsigned long, unsigned long);
diff --git a/arch/mips/include/asm/asmmacro-32.h b/arch/mips/include/asm/asmmacro-32.h
index 2413afe21b33..70e1f176f123 100644
--- a/arch/mips/include/asm/asmmacro-32.h
+++ b/arch/mips/include/asm/asmmacro-32.h
@@ -12,27 +12,6 @@
12#include <asm/fpregdef.h> 12#include <asm/fpregdef.h>
13#include <asm/mipsregs.h> 13#include <asm/mipsregs.h>
14 14
15 .macro fpu_save_double thread status tmp1=t0
16 cfc1 \tmp1, fcr31
17 sdc1 $f0, THREAD_FPR0(\thread)
18 sdc1 $f2, THREAD_FPR2(\thread)
19 sdc1 $f4, THREAD_FPR4(\thread)
20 sdc1 $f6, THREAD_FPR6(\thread)
21 sdc1 $f8, THREAD_FPR8(\thread)
22 sdc1 $f10, THREAD_FPR10(\thread)
23 sdc1 $f12, THREAD_FPR12(\thread)
24 sdc1 $f14, THREAD_FPR14(\thread)
25 sdc1 $f16, THREAD_FPR16(\thread)
26 sdc1 $f18, THREAD_FPR18(\thread)
27 sdc1 $f20, THREAD_FPR20(\thread)
28 sdc1 $f22, THREAD_FPR22(\thread)
29 sdc1 $f24, THREAD_FPR24(\thread)
30 sdc1 $f26, THREAD_FPR26(\thread)
31 sdc1 $f28, THREAD_FPR28(\thread)
32 sdc1 $f30, THREAD_FPR30(\thread)
33 sw \tmp1, THREAD_FCR31(\thread)
34 .endm
35
36 .macro fpu_save_single thread tmp=t0 15 .macro fpu_save_single thread tmp=t0
37 cfc1 \tmp, fcr31 16 cfc1 \tmp, fcr31
38 swc1 $f0, THREAD_FPR0(\thread) 17 swc1 $f0, THREAD_FPR0(\thread)
@@ -70,27 +49,6 @@
70 sw \tmp, THREAD_FCR31(\thread) 49 sw \tmp, THREAD_FCR31(\thread)
71 .endm 50 .endm
72 51
73 .macro fpu_restore_double thread status tmp=t0
74 lw \tmp, THREAD_FCR31(\thread)
75 ldc1 $f0, THREAD_FPR0(\thread)
76 ldc1 $f2, THREAD_FPR2(\thread)
77 ldc1 $f4, THREAD_FPR4(\thread)
78 ldc1 $f6, THREAD_FPR6(\thread)
79 ldc1 $f8, THREAD_FPR8(\thread)
80 ldc1 $f10, THREAD_FPR10(\thread)
81 ldc1 $f12, THREAD_FPR12(\thread)
82 ldc1 $f14, THREAD_FPR14(\thread)
83 ldc1 $f16, THREAD_FPR16(\thread)
84 ldc1 $f18, THREAD_FPR18(\thread)
85 ldc1 $f20, THREAD_FPR20(\thread)
86 ldc1 $f22, THREAD_FPR22(\thread)
87 ldc1 $f24, THREAD_FPR24(\thread)
88 ldc1 $f26, THREAD_FPR26(\thread)
89 ldc1 $f28, THREAD_FPR28(\thread)
90 ldc1 $f30, THREAD_FPR30(\thread)
91 ctc1 \tmp, fcr31
92 .endm
93
94 .macro fpu_restore_single thread tmp=t0 52 .macro fpu_restore_single thread tmp=t0
95 lw \tmp, THREAD_FCR31(\thread) 53 lw \tmp, THREAD_FCR31(\thread)
96 lwc1 $f0, THREAD_FPR0(\thread) 54 lwc1 $f0, THREAD_FPR0(\thread)
diff --git a/arch/mips/include/asm/asmmacro-64.h b/arch/mips/include/asm/asmmacro-64.h
index 08a527dfe4a3..38ea609465b1 100644
--- a/arch/mips/include/asm/asmmacro-64.h
+++ b/arch/mips/include/asm/asmmacro-64.h
@@ -13,102 +13,6 @@
13#include <asm/fpregdef.h> 13#include <asm/fpregdef.h>
14#include <asm/mipsregs.h> 14#include <asm/mipsregs.h>
15 15
16 .macro fpu_save_16even thread tmp=t0
17 cfc1 \tmp, fcr31
18 sdc1 $f0, THREAD_FPR0(\thread)
19 sdc1 $f2, THREAD_FPR2(\thread)
20 sdc1 $f4, THREAD_FPR4(\thread)
21 sdc1 $f6, THREAD_FPR6(\thread)
22 sdc1 $f8, THREAD_FPR8(\thread)
23 sdc1 $f10, THREAD_FPR10(\thread)
24 sdc1 $f12, THREAD_FPR12(\thread)
25 sdc1 $f14, THREAD_FPR14(\thread)
26 sdc1 $f16, THREAD_FPR16(\thread)
27 sdc1 $f18, THREAD_FPR18(\thread)
28 sdc1 $f20, THREAD_FPR20(\thread)
29 sdc1 $f22, THREAD_FPR22(\thread)
30 sdc1 $f24, THREAD_FPR24(\thread)
31 sdc1 $f26, THREAD_FPR26(\thread)
32 sdc1 $f28, THREAD_FPR28(\thread)
33 sdc1 $f30, THREAD_FPR30(\thread)
34 sw \tmp, THREAD_FCR31(\thread)
35 .endm
36
37 .macro fpu_save_16odd thread
38 sdc1 $f1, THREAD_FPR1(\thread)
39 sdc1 $f3, THREAD_FPR3(\thread)
40 sdc1 $f5, THREAD_FPR5(\thread)
41 sdc1 $f7, THREAD_FPR7(\thread)
42 sdc1 $f9, THREAD_FPR9(\thread)
43 sdc1 $f11, THREAD_FPR11(\thread)
44 sdc1 $f13, THREAD_FPR13(\thread)
45 sdc1 $f15, THREAD_FPR15(\thread)
46 sdc1 $f17, THREAD_FPR17(\thread)
47 sdc1 $f19, THREAD_FPR19(\thread)
48 sdc1 $f21, THREAD_FPR21(\thread)
49 sdc1 $f23, THREAD_FPR23(\thread)
50 sdc1 $f25, THREAD_FPR25(\thread)
51 sdc1 $f27, THREAD_FPR27(\thread)
52 sdc1 $f29, THREAD_FPR29(\thread)
53 sdc1 $f31, THREAD_FPR31(\thread)
54 .endm
55
56 .macro fpu_save_double thread status tmp
57 sll \tmp, \status, 5
58 bgez \tmp, 2f
59 fpu_save_16odd \thread
602:
61 fpu_save_16even \thread \tmp
62 .endm
63
64 .macro fpu_restore_16even thread tmp=t0
65 lw \tmp, THREAD_FCR31(\thread)
66 ldc1 $f0, THREAD_FPR0(\thread)
67 ldc1 $f2, THREAD_FPR2(\thread)
68 ldc1 $f4, THREAD_FPR4(\thread)
69 ldc1 $f6, THREAD_FPR6(\thread)
70 ldc1 $f8, THREAD_FPR8(\thread)
71 ldc1 $f10, THREAD_FPR10(\thread)
72 ldc1 $f12, THREAD_FPR12(\thread)
73 ldc1 $f14, THREAD_FPR14(\thread)
74 ldc1 $f16, THREAD_FPR16(\thread)
75 ldc1 $f18, THREAD_FPR18(\thread)
76 ldc1 $f20, THREAD_FPR20(\thread)
77 ldc1 $f22, THREAD_FPR22(\thread)
78 ldc1 $f24, THREAD_FPR24(\thread)
79 ldc1 $f26, THREAD_FPR26(\thread)
80 ldc1 $f28, THREAD_FPR28(\thread)
81 ldc1 $f30, THREAD_FPR30(\thread)
82 ctc1 \tmp, fcr31
83 .endm
84
85 .macro fpu_restore_16odd thread
86 ldc1 $f1, THREAD_FPR1(\thread)
87 ldc1 $f3, THREAD_FPR3(\thread)
88 ldc1 $f5, THREAD_FPR5(\thread)
89 ldc1 $f7, THREAD_FPR7(\thread)
90 ldc1 $f9, THREAD_FPR9(\thread)
91 ldc1 $f11, THREAD_FPR11(\thread)
92 ldc1 $f13, THREAD_FPR13(\thread)
93 ldc1 $f15, THREAD_FPR15(\thread)
94 ldc1 $f17, THREAD_FPR17(\thread)
95 ldc1 $f19, THREAD_FPR19(\thread)
96 ldc1 $f21, THREAD_FPR21(\thread)
97 ldc1 $f23, THREAD_FPR23(\thread)
98 ldc1 $f25, THREAD_FPR25(\thread)
99 ldc1 $f27, THREAD_FPR27(\thread)
100 ldc1 $f29, THREAD_FPR29(\thread)
101 ldc1 $f31, THREAD_FPR31(\thread)
102 .endm
103
104 .macro fpu_restore_double thread status tmp
105 sll \tmp, \status, 5
106 bgez \tmp, 1f # 16 register mode?
107
108 fpu_restore_16odd \thread
1091: fpu_restore_16even \thread \tmp
110 .endm
111
112 .macro cpu_save_nonscratch thread 16 .macro cpu_save_nonscratch thread
113 LONG_S s0, THREAD_REG16(\thread) 17 LONG_S s0, THREAD_REG16(\thread)
114 LONG_S s1, THREAD_REG17(\thread) 18 LONG_S s1, THREAD_REG17(\thread)
diff --git a/arch/mips/include/asm/asmmacro.h b/arch/mips/include/asm/asmmacro.h
index 6c8342ae74db..3220c93ea981 100644
--- a/arch/mips/include/asm/asmmacro.h
+++ b/arch/mips/include/asm/asmmacro.h
@@ -62,6 +62,113 @@
62 .endm 62 .endm
63#endif /* CONFIG_MIPS_MT_SMTC */ 63#endif /* CONFIG_MIPS_MT_SMTC */
64 64
65 .macro fpu_save_16even thread tmp=t0
66 cfc1 \tmp, fcr31
67 sdc1 $f0, THREAD_FPR0(\thread)
68 sdc1 $f2, THREAD_FPR2(\thread)
69 sdc1 $f4, THREAD_FPR4(\thread)
70 sdc1 $f6, THREAD_FPR6(\thread)
71 sdc1 $f8, THREAD_FPR8(\thread)
72 sdc1 $f10, THREAD_FPR10(\thread)
73 sdc1 $f12, THREAD_FPR12(\thread)
74 sdc1 $f14, THREAD_FPR14(\thread)
75 sdc1 $f16, THREAD_FPR16(\thread)
76 sdc1 $f18, THREAD_FPR18(\thread)
77 sdc1 $f20, THREAD_FPR20(\thread)
78 sdc1 $f22, THREAD_FPR22(\thread)
79 sdc1 $f24, THREAD_FPR24(\thread)
80 sdc1 $f26, THREAD_FPR26(\thread)
81 sdc1 $f28, THREAD_FPR28(\thread)
82 sdc1 $f30, THREAD_FPR30(\thread)
83 sw \tmp, THREAD_FCR31(\thread)
84 .endm
85
86 .macro fpu_save_16odd thread
87 .set push
88 .set mips64r2
89 sdc1 $f1, THREAD_FPR1(\thread)
90 sdc1 $f3, THREAD_FPR3(\thread)
91 sdc1 $f5, THREAD_FPR5(\thread)
92 sdc1 $f7, THREAD_FPR7(\thread)
93 sdc1 $f9, THREAD_FPR9(\thread)
94 sdc1 $f11, THREAD_FPR11(\thread)
95 sdc1 $f13, THREAD_FPR13(\thread)
96 sdc1 $f15, THREAD_FPR15(\thread)
97 sdc1 $f17, THREAD_FPR17(\thread)
98 sdc1 $f19, THREAD_FPR19(\thread)
99 sdc1 $f21, THREAD_FPR21(\thread)
100 sdc1 $f23, THREAD_FPR23(\thread)
101 sdc1 $f25, THREAD_FPR25(\thread)
102 sdc1 $f27, THREAD_FPR27(\thread)
103 sdc1 $f29, THREAD_FPR29(\thread)
104 sdc1 $f31, THREAD_FPR31(\thread)
105 .set pop
106 .endm
107
108 .macro fpu_save_double thread status tmp
109#if defined(CONFIG_MIPS64) || defined(CONFIG_CPU_MIPS32_R2)
110 sll \tmp, \status, 5
111 bgez \tmp, 10f
112 fpu_save_16odd \thread
11310:
114#endif
115 fpu_save_16even \thread \tmp
116 .endm
117
118 .macro fpu_restore_16even thread tmp=t0
119 lw \tmp, THREAD_FCR31(\thread)
120 ldc1 $f0, THREAD_FPR0(\thread)
121 ldc1 $f2, THREAD_FPR2(\thread)
122 ldc1 $f4, THREAD_FPR4(\thread)
123 ldc1 $f6, THREAD_FPR6(\thread)
124 ldc1 $f8, THREAD_FPR8(\thread)
125 ldc1 $f10, THREAD_FPR10(\thread)
126 ldc1 $f12, THREAD_FPR12(\thread)
127 ldc1 $f14, THREAD_FPR14(\thread)
128 ldc1 $f16, THREAD_FPR16(\thread)
129 ldc1 $f18, THREAD_FPR18(\thread)
130 ldc1 $f20, THREAD_FPR20(\thread)
131 ldc1 $f22, THREAD_FPR22(\thread)
132 ldc1 $f24, THREAD_FPR24(\thread)
133 ldc1 $f26, THREAD_FPR26(\thread)
134 ldc1 $f28, THREAD_FPR28(\thread)
135 ldc1 $f30, THREAD_FPR30(\thread)
136 ctc1 \tmp, fcr31
137 .endm
138
139 .macro fpu_restore_16odd thread
140 .set push
141 .set mips64r2
142 ldc1 $f1, THREAD_FPR1(\thread)
143 ldc1 $f3, THREAD_FPR3(\thread)
144 ldc1 $f5, THREAD_FPR5(\thread)
145 ldc1 $f7, THREAD_FPR7(\thread)
146 ldc1 $f9, THREAD_FPR9(\thread)
147 ldc1 $f11, THREAD_FPR11(\thread)
148 ldc1 $f13, THREAD_FPR13(\thread)
149 ldc1 $f15, THREAD_FPR15(\thread)
150 ldc1 $f17, THREAD_FPR17(\thread)
151 ldc1 $f19, THREAD_FPR19(\thread)
152 ldc1 $f21, THREAD_FPR21(\thread)
153 ldc1 $f23, THREAD_FPR23(\thread)
154 ldc1 $f25, THREAD_FPR25(\thread)
155 ldc1 $f27, THREAD_FPR27(\thread)
156 ldc1 $f29, THREAD_FPR29(\thread)
157 ldc1 $f31, THREAD_FPR31(\thread)
158 .set pop
159 .endm
160
161 .macro fpu_restore_double thread status tmp
162#if defined(CONFIG_MIPS64) || defined(CONFIG_CPU_MIPS32_R2)
163 sll \tmp, \status, 5
164 bgez \tmp, 10f # 16 register mode?
165
166 fpu_restore_16odd \thread
16710:
168#endif
169 fpu_restore_16even \thread \tmp
170 .endm
171
65/* 172/*
66 * Temporary until all gas have MT ASE support 173 * Temporary until all gas have MT ASE support
67 */ 174 */
diff --git a/arch/mips/include/asm/bmips.h b/arch/mips/include/asm/bmips.h
index 27bd060d716e..cbaccebf5065 100644
--- a/arch/mips/include/asm/bmips.h
+++ b/arch/mips/include/asm/bmips.h
@@ -46,8 +46,35 @@
46 46
47#include <linux/cpumask.h> 47#include <linux/cpumask.h>
48#include <asm/r4kcache.h> 48#include <asm/r4kcache.h>
49#include <asm/smp-ops.h>
50
51extern struct plat_smp_ops bmips43xx_smp_ops;
52extern struct plat_smp_ops bmips5000_smp_ops;
53
54static inline int register_bmips_smp_ops(void)
55{
56#if IS_ENABLED(CONFIG_CPU_BMIPS) && IS_ENABLED(CONFIG_SMP)
57 switch (current_cpu_type()) {
58 case CPU_BMIPS32:
59 case CPU_BMIPS3300:
60 return register_up_smp_ops();
61 case CPU_BMIPS4350:
62 case CPU_BMIPS4380:
63 register_smp_ops(&bmips43xx_smp_ops);
64 break;
65 case CPU_BMIPS5000:
66 register_smp_ops(&bmips5000_smp_ops);
67 break;
68 default:
69 return -ENODEV;
70 }
71
72 return 0;
73#else
74 return -ENODEV;
75#endif
76}
49 77
50extern struct plat_smp_ops bmips_smp_ops;
51extern char bmips_reset_nmi_vec; 78extern char bmips_reset_nmi_vec;
52extern char bmips_reset_nmi_vec_end; 79extern char bmips_reset_nmi_vec_end;
53extern char bmips_smp_movevec; 80extern char bmips_smp_movevec;
diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
index d445d060e346..6e70b03b6aab 100644
--- a/arch/mips/include/asm/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
@@ -20,6 +20,13 @@
20#ifndef cpu_has_tlb 20#ifndef cpu_has_tlb
21#define cpu_has_tlb (cpu_data[0].options & MIPS_CPU_TLB) 21#define cpu_has_tlb (cpu_data[0].options & MIPS_CPU_TLB)
22#endif 22#endif
23#ifndef cpu_has_tlbinv
24#define cpu_has_tlbinv (cpu_data[0].options & MIPS_CPU_TLBINV)
25#endif
26#ifndef cpu_has_segments
27#define cpu_has_segments (cpu_data[0].options & MIPS_CPU_SEGMENTS)
28#endif
29
23 30
24/* 31/*
25 * For the moment we don't consider R6000 and R8000 so we can assume that 32 * For the moment we don't consider R6000 and R8000 so we can assume that
diff --git a/arch/mips/include/asm/cpu-info.h b/arch/mips/include/asm/cpu-info.h
index 21c8e29c8f91..8f7adf0ac1e3 100644
--- a/arch/mips/include/asm/cpu-info.h
+++ b/arch/mips/include/asm/cpu-info.h
@@ -52,6 +52,9 @@ struct cpuinfo_mips {
52 unsigned int cputype; 52 unsigned int cputype;
53 int isa_level; 53 int isa_level;
54 int tlbsize; 54 int tlbsize;
55 int tlbsizevtlb;
56 int tlbsizeftlbsets;
57 int tlbsizeftlbways;
55 struct cache_desc icache; /* Primary I-cache */ 58 struct cache_desc icache; /* Primary I-cache */
56 struct cache_desc dcache; /* Primary D or combined I/D cache */ 59 struct cache_desc dcache; /* Primary D or combined I/D cache */
57 struct cache_desc scache; /* Secondary cache */ 60 struct cache_desc scache; /* Secondary cache */
diff --git a/arch/mips/include/asm/cpu-type.h b/arch/mips/include/asm/cpu-type.h
index 4a402cc60c03..02f591bd95ca 100644
--- a/arch/mips/include/asm/cpu-type.h
+++ b/arch/mips/include/asm/cpu-type.h
@@ -27,10 +27,7 @@ static inline int __pure __get_cpu_type(const int cpu_type)
27#ifdef CONFIG_SYS_HAS_CPU_MIPS32_R1 27#ifdef CONFIG_SYS_HAS_CPU_MIPS32_R1
28 case CPU_4KC: 28 case CPU_4KC:
29 case CPU_ALCHEMY: 29 case CPU_ALCHEMY:
30 case CPU_BMIPS3300:
31 case CPU_BMIPS4350:
32 case CPU_PR4450: 30 case CPU_PR4450:
33 case CPU_BMIPS32:
34 case CPU_JZRISC: 31 case CPU_JZRISC:
35#endif 32#endif
36 33
@@ -47,6 +44,8 @@ static inline int __pure __get_cpu_type(const int cpu_type)
47 case CPU_74K: 44 case CPU_74K:
48 case CPU_M14KC: 45 case CPU_M14KC:
49 case CPU_M14KEC: 46 case CPU_M14KEC:
47 case CPU_INTERAPTIV:
48 case CPU_PROAPTIV:
50#endif 49#endif
51 50
52#ifdef CONFIG_SYS_HAS_CPU_MIPS64_R1 51#ifdef CONFIG_SYS_HAS_CPU_MIPS64_R1
@@ -163,6 +162,16 @@ static inline int __pure __get_cpu_type(const int cpu_type)
163 case CPU_CAVIUM_OCTEON2: 162 case CPU_CAVIUM_OCTEON2:
164#endif 163#endif
165 164
165#if defined(CONFIG_SYS_HAS_CPU_BMIPS32_3300) || \
166 defined (CONFIG_SYS_HAS_CPU_MIPS32_R1)
167 case CPU_BMIPS32:
168 case CPU_BMIPS3300:
169#endif
170
171#ifdef CONFIG_SYS_HAS_CPU_BMIPS4350
172 case CPU_BMIPS4350:
173#endif
174
166#ifdef CONFIG_SYS_HAS_CPU_BMIPS4380 175#ifdef CONFIG_SYS_HAS_CPU_BMIPS4380
167 case CPU_BMIPS4380: 176 case CPU_BMIPS4380:
168#endif 177#endif
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index d2035e16502a..76411df3d971 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -111,6 +111,10 @@
111#define PRID_IMP_1074K 0x9a00 111#define PRID_IMP_1074K 0x9a00
112#define PRID_IMP_M14KC 0x9c00 112#define PRID_IMP_M14KC 0x9c00
113#define PRID_IMP_M14KEC 0x9e00 113#define PRID_IMP_M14KEC 0x9e00
114#define PRID_IMP_INTERAPTIV_UP 0xa000
115#define PRID_IMP_INTERAPTIV_MP 0xa100
116#define PRID_IMP_PROAPTIV_UP 0xa200
117#define PRID_IMP_PROAPTIV_MP 0xa300
114 118
115/* 119/*
116 * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE 120 * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE
@@ -194,6 +198,7 @@
194#define PRID_IMP_NETLOGIC_XLP8XX 0x1000 198#define PRID_IMP_NETLOGIC_XLP8XX 0x1000
195#define PRID_IMP_NETLOGIC_XLP3XX 0x1100 199#define PRID_IMP_NETLOGIC_XLP3XX 0x1100
196#define PRID_IMP_NETLOGIC_XLP2XX 0x1200 200#define PRID_IMP_NETLOGIC_XLP2XX 0x1200
201#define PRID_IMP_NETLOGIC_XLP9XX 0x1500
197 202
198/* 203/*
199 * Particular Revision values for bits 7:0 of the PRId register. 204 * Particular Revision values for bits 7:0 of the PRId register.
@@ -249,6 +254,8 @@
249 254
250#define FPIR_IMP_NONE 0x0000 255#define FPIR_IMP_NONE 0x0000
251 256
257#if !defined(__ASSEMBLY__)
258
252enum cpu_type_enum { 259enum cpu_type_enum {
253 CPU_UNKNOWN, 260 CPU_UNKNOWN,
254 261
@@ -289,7 +296,7 @@ enum cpu_type_enum {
289 CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K, 296 CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K,
290 CPU_ALCHEMY, CPU_PR4450, CPU_BMIPS32, CPU_BMIPS3300, CPU_BMIPS4350, 297 CPU_ALCHEMY, CPU_PR4450, CPU_BMIPS32, CPU_BMIPS3300, CPU_BMIPS4350,
291 CPU_BMIPS4380, CPU_BMIPS5000, CPU_JZRISC, CPU_LOONGSON1, CPU_M14KC, 298 CPU_BMIPS4380, CPU_BMIPS5000, CPU_JZRISC, CPU_LOONGSON1, CPU_M14KC,
292 CPU_M14KEC, 299 CPU_M14KEC, CPU_INTERAPTIV, CPU_PROAPTIV,
293 300
294 /* 301 /*
295 * MIPS64 class processors 302 * MIPS64 class processors
@@ -301,6 +308,7 @@ enum cpu_type_enum {
301 CPU_LAST 308 CPU_LAST
302}; 309};
303 310
311#endif /* !__ASSEMBLY */
304 312
305/* 313/*
306 * ISA Level encodings 314 * ISA Level encodings
@@ -348,6 +356,8 @@ enum cpu_type_enum {
348#define MIPS_CPU_PCI 0x00400000 /* CPU has Perf Ctr Int indicator */ 356#define MIPS_CPU_PCI 0x00400000 /* CPU has Perf Ctr Int indicator */
349#define MIPS_CPU_RIXI 0x00800000 /* CPU has TLB Read/eXec Inhibit */ 357#define MIPS_CPU_RIXI 0x00800000 /* CPU has TLB Read/eXec Inhibit */
350#define MIPS_CPU_MICROMIPS 0x01000000 /* CPU has microMIPS capability */ 358#define MIPS_CPU_MICROMIPS 0x01000000 /* CPU has microMIPS capability */
359#define MIPS_CPU_TLBINV 0x02000000 /* CPU supports TLBINV/F */
360#define MIPS_CPU_SEGMENTS 0x04000000 /* CPU supports Segmentation Control registers */
351 361
352/* 362/*
353 * CPU ASE encodings 363 * CPU ASE encodings
diff --git a/arch/mips/include/asm/dma-coherence.h b/arch/mips/include/asm/dma-coherence.h
index 242cbb3ca582..bc5e85d579e6 100644
--- a/arch/mips/include/asm/dma-coherence.h
+++ b/arch/mips/include/asm/dma-coherence.h
@@ -9,7 +9,16 @@
9#ifndef __ASM_DMA_COHERENCE_H 9#ifndef __ASM_DMA_COHERENCE_H
10#define __ASM_DMA_COHERENCE_H 10#define __ASM_DMA_COHERENCE_H
11 11
12#ifdef CONFIG_DMA_MAYBE_COHERENT
12extern int coherentio; 13extern int coherentio;
13extern int hw_coherentio; 14extern int hw_coherentio;
15#else
16#ifdef CONFIG_DMA_COHERENT
17#define coherentio 1
18#else
19#define coherentio 0
20#endif
21#define hw_coherentio 0
22#endif /* CONFIG_DMA_MAYBE_COHERENT */
14 23
15#endif 24#endif
diff --git a/arch/mips/include/asm/elf.h b/arch/mips/include/asm/elf.h
index a66359ef4ece..d4144056e928 100644
--- a/arch/mips/include/asm/elf.h
+++ b/arch/mips/include/asm/elf.h
@@ -36,6 +36,7 @@
36#define EF_MIPS_ABI2 0x00000020 36#define EF_MIPS_ABI2 0x00000020
37#define EF_MIPS_OPTIONS_FIRST 0x00000080 37#define EF_MIPS_OPTIONS_FIRST 0x00000080
38#define EF_MIPS_32BITMODE 0x00000100 38#define EF_MIPS_32BITMODE 0x00000100
39#define EF_MIPS_FP64 0x00000200
39#define EF_MIPS_ABI 0x0000f000 40#define EF_MIPS_ABI 0x0000f000
40#define EF_MIPS_ARCH 0xf0000000 41#define EF_MIPS_ARCH 0xf0000000
41 42
@@ -176,6 +177,18 @@ typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];
176#ifdef CONFIG_32BIT 177#ifdef CONFIG_32BIT
177 178
178/* 179/*
180 * In order to be sure that we don't attempt to execute an O32 binary which
181 * requires 64 bit FP (FR=1) on a system which does not support it we refuse
182 * to execute any binary which has bits specified by the following macro set
183 * in its ELF header flags.
184 */
185#ifdef CONFIG_MIPS_O32_FP64_SUPPORT
186# define __MIPS_O32_FP64_MUST_BE_ZERO 0
187#else
188# define __MIPS_O32_FP64_MUST_BE_ZERO EF_MIPS_FP64
189#endif
190
191/*
179 * This is used to ensure we don't load something for the wrong architecture. 192 * This is used to ensure we don't load something for the wrong architecture.
180 */ 193 */
181#define elf_check_arch(hdr) \ 194#define elf_check_arch(hdr) \
@@ -192,6 +205,8 @@ typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];
192 if (((__h->e_flags & EF_MIPS_ABI) != 0) && \ 205 if (((__h->e_flags & EF_MIPS_ABI) != 0) && \
193 ((__h->e_flags & EF_MIPS_ABI) != EF_MIPS_ABI_O32)) \ 206 ((__h->e_flags & EF_MIPS_ABI) != EF_MIPS_ABI_O32)) \
194 __res = 0; \ 207 __res = 0; \
208 if (__h->e_flags & __MIPS_O32_FP64_MUST_BE_ZERO) \
209 __res = 0; \
195 \ 210 \
196 __res; \ 211 __res; \
197}) 212})
@@ -249,6 +264,11 @@ extern struct mips_abi mips_abi_n32;
249 264
250#define SET_PERSONALITY(ex) \ 265#define SET_PERSONALITY(ex) \
251do { \ 266do { \
267 if ((ex).e_flags & EF_MIPS_FP64) \
268 clear_thread_flag(TIF_32BIT_FPREGS); \
269 else \
270 set_thread_flag(TIF_32BIT_FPREGS); \
271 \
252 if (personality(current->personality) != PER_LINUX) \ 272 if (personality(current->personality) != PER_LINUX) \
253 set_personality(PER_LINUX); \ 273 set_personality(PER_LINUX); \
254 \ 274 \
@@ -271,14 +291,18 @@ do { \
271#endif 291#endif
272 292
273#ifdef CONFIG_MIPS32_O32 293#ifdef CONFIG_MIPS32_O32
274#define __SET_PERSONALITY32_O32() \ 294#define __SET_PERSONALITY32_O32(ex) \
275 do { \ 295 do { \
276 set_thread_flag(TIF_32BIT_REGS); \ 296 set_thread_flag(TIF_32BIT_REGS); \
277 set_thread_flag(TIF_32BIT_ADDR); \ 297 set_thread_flag(TIF_32BIT_ADDR); \
298 \
299 if (!((ex).e_flags & EF_MIPS_FP64)) \
300 set_thread_flag(TIF_32BIT_FPREGS); \
301 \
278 current->thread.abi = &mips_abi_32; \ 302 current->thread.abi = &mips_abi_32; \
279 } while (0) 303 } while (0)
280#else 304#else
281#define __SET_PERSONALITY32_O32() \ 305#define __SET_PERSONALITY32_O32(ex) \
282 do { } while (0) 306 do { } while (0)
283#endif 307#endif
284 308
@@ -289,7 +313,7 @@ do { \
289 ((ex).e_flags & EF_MIPS_ABI) == 0) \ 313 ((ex).e_flags & EF_MIPS_ABI) == 0) \
290 __SET_PERSONALITY32_N32(); \ 314 __SET_PERSONALITY32_N32(); \
291 else \ 315 else \
292 __SET_PERSONALITY32_O32(); \ 316 __SET_PERSONALITY32_O32(ex); \
293} while (0) 317} while (0)
294#else 318#else
295#define __SET_PERSONALITY32(ex) do { } while (0) 319#define __SET_PERSONALITY32(ex) do { } while (0)
@@ -300,6 +324,7 @@ do { \
300 unsigned int p; \ 324 unsigned int p; \
301 \ 325 \
302 clear_thread_flag(TIF_32BIT_REGS); \ 326 clear_thread_flag(TIF_32BIT_REGS); \
327 clear_thread_flag(TIF_32BIT_FPREGS); \
303 clear_thread_flag(TIF_32BIT_ADDR); \ 328 clear_thread_flag(TIF_32BIT_ADDR); \
304 \ 329 \
305 if ((ex).e_ident[EI_CLASS] == ELFCLASS32) \ 330 if ((ex).e_ident[EI_CLASS] == ELFCLASS32) \
diff --git a/arch/mips/include/asm/fpu.h b/arch/mips/include/asm/fpu.h
index d088e5db4903..cfe092fc720d 100644
--- a/arch/mips/include/asm/fpu.h
+++ b/arch/mips/include/asm/fpu.h
@@ -33,11 +33,48 @@ extern void _init_fpu(void);
33extern void _save_fp(struct task_struct *); 33extern void _save_fp(struct task_struct *);
34extern void _restore_fp(struct task_struct *); 34extern void _restore_fp(struct task_struct *);
35 35
36#define __enable_fpu() \ 36/*
37do { \ 37 * This enum specifies a mode in which we want the FPU to operate, for cores
38 set_c0_status(ST0_CU1); \ 38 * which implement the Status.FR bit. Note that FPU_32BIT & FPU_64BIT
39 enable_fpu_hazard(); \ 39 * purposefully have the values 0 & 1 respectively, so that an integer value
40} while (0) 40 * of Status.FR can be trivially casted to the corresponding enum fpu_mode.
41 */
42enum fpu_mode {
43 FPU_32BIT = 0, /* FR = 0 */
44 FPU_64BIT, /* FR = 1 */
45 FPU_AS_IS,
46};
47
48static inline int __enable_fpu(enum fpu_mode mode)
49{
50 int fr;
51
52 switch (mode) {
53 case FPU_AS_IS:
54 /* just enable the FPU in its current mode */
55 set_c0_status(ST0_CU1);
56 enable_fpu_hazard();
57 return 0;
58
59 case FPU_64BIT:
60#if !(defined(CONFIG_CPU_MIPS32_R2) || defined(CONFIG_MIPS64))
61 /* we only have a 32-bit FPU */
62 return SIGFPE;
63#endif
64 /* fall through */
65 case FPU_32BIT:
66 /* set CU1 & change FR appropriately */
67 fr = (int)mode;
68 change_c0_status(ST0_CU1 | ST0_FR, ST0_CU1 | (fr ? ST0_FR : 0));
69 enable_fpu_hazard();
70
71 /* check FR has the desired value */
72 return (!!(read_c0_status() & ST0_FR) == !!fr) ? 0 : SIGFPE;
73
74 default:
75 BUG();
76 }
77}
41 78
42#define __disable_fpu() \ 79#define __disable_fpu() \
43do { \ 80do { \
@@ -45,19 +82,6 @@ do { \
45 disable_fpu_hazard(); \ 82 disable_fpu_hazard(); \
46} while (0) 83} while (0)
47 84
48#define enable_fpu() \
49do { \
50 if (cpu_has_fpu) \
51 __enable_fpu(); \
52} while (0)
53
54#define disable_fpu() \
55do { \
56 if (cpu_has_fpu) \
57 __disable_fpu(); \
58} while (0)
59
60
61#define clear_fpu_owner() clear_thread_flag(TIF_USEDFPU) 85#define clear_fpu_owner() clear_thread_flag(TIF_USEDFPU)
62 86
63static inline int __is_fpu_owner(void) 87static inline int __is_fpu_owner(void)
@@ -70,27 +94,46 @@ static inline int is_fpu_owner(void)
70 return cpu_has_fpu && __is_fpu_owner(); 94 return cpu_has_fpu && __is_fpu_owner();
71} 95}
72 96
73static inline void __own_fpu(void) 97static inline int __own_fpu(void)
74{ 98{
75 __enable_fpu(); 99 enum fpu_mode mode;
100 int ret;
101
102 mode = !test_thread_flag(TIF_32BIT_FPREGS);
103 ret = __enable_fpu(mode);
104 if (ret)
105 return ret;
106
76 KSTK_STATUS(current) |= ST0_CU1; 107 KSTK_STATUS(current) |= ST0_CU1;
108 if (mode == FPU_64BIT)
109 KSTK_STATUS(current) |= ST0_FR;
110 else /* mode == FPU_32BIT */
111 KSTK_STATUS(current) &= ~ST0_FR;
112
77 set_thread_flag(TIF_USEDFPU); 113 set_thread_flag(TIF_USEDFPU);
114 return 0;
78} 115}
79 116
80static inline void own_fpu_inatomic(int restore) 117static inline int own_fpu_inatomic(int restore)
81{ 118{
119 int ret = 0;
120
82 if (cpu_has_fpu && !__is_fpu_owner()) { 121 if (cpu_has_fpu && !__is_fpu_owner()) {
83 __own_fpu(); 122 ret = __own_fpu();
84 if (restore) 123 if (restore && !ret)
85 _restore_fp(current); 124 _restore_fp(current);
86 } 125 }
126 return ret;
87} 127}
88 128
89static inline void own_fpu(int restore) 129static inline int own_fpu(int restore)
90{ 130{
131 int ret;
132
91 preempt_disable(); 133 preempt_disable();
92 own_fpu_inatomic(restore); 134 ret = own_fpu_inatomic(restore);
93 preempt_enable(); 135 preempt_enable();
136 return ret;
94} 137}
95 138
96static inline void lose_fpu(int save) 139static inline void lose_fpu(int save)
@@ -106,16 +149,21 @@ static inline void lose_fpu(int save)
106 preempt_enable(); 149 preempt_enable();
107} 150}
108 151
109static inline void init_fpu(void) 152static inline int init_fpu(void)
110{ 153{
154 int ret = 0;
155
111 preempt_disable(); 156 preempt_disable();
112 if (cpu_has_fpu) { 157 if (cpu_has_fpu) {
113 __own_fpu(); 158 ret = __own_fpu();
114 _init_fpu(); 159 if (!ret)
160 _init_fpu();
115 } else { 161 } else {
116 fpu_emulator_init_fpu(); 162 fpu_emulator_init_fpu();
117 } 163 }
164
118 preempt_enable(); 165 preempt_enable();
166 return ret;
119} 167}
120 168
121static inline void save_fp(struct task_struct *tsk) 169static inline void save_fp(struct task_struct *tsk)
diff --git a/arch/mips/include/asm/highmem.h b/arch/mips/include/asm/highmem.h
index b0dd0c84df70..572e63ec2a38 100644
--- a/arch/mips/include/asm/highmem.h
+++ b/arch/mips/include/asm/highmem.h
@@ -19,7 +19,6 @@
19 19
20#ifdef __KERNEL__ 20#ifdef __KERNEL__
21 21
22#include <linux/init.h>
23#include <linux/interrupt.h> 22#include <linux/interrupt.h>
24#include <linux/uaccess.h> 23#include <linux/uaccess.h>
25#include <asm/kmap_types.h> 24#include <asm/kmap_types.h>
diff --git a/arch/mips/include/asm/kvm_host.h b/arch/mips/include/asm/kvm_host.h
index 32966969f2f9..a995fce87791 100644
--- a/arch/mips/include/asm/kvm_host.h
+++ b/arch/mips/include/asm/kvm_host.h
@@ -391,9 +391,6 @@ struct kvm_vcpu_arch {
391 uint32_t guest_kernel_asid[NR_CPUS]; 391 uint32_t guest_kernel_asid[NR_CPUS];
392 struct mm_struct guest_kernel_mm, guest_user_mm; 392 struct mm_struct guest_kernel_mm, guest_user_mm;
393 393
394 struct kvm_mips_tlb shadow_tlb[NR_CPUS][KVM_MIPS_GUEST_TLB_SIZE];
395
396
397 struct hrtimer comparecount_timer; 394 struct hrtimer comparecount_timer;
398 395
399 int last_sched_cpu; 396 int last_sched_cpu;
@@ -529,7 +526,6 @@ extern enum emulation_result kvm_mips_handle_tlbmod(unsigned long cause,
529 526
530extern void kvm_mips_dump_host_tlbs(void); 527extern void kvm_mips_dump_host_tlbs(void);
531extern void kvm_mips_dump_guest_tlbs(struct kvm_vcpu *vcpu); 528extern void kvm_mips_dump_guest_tlbs(struct kvm_vcpu *vcpu);
532extern void kvm_mips_dump_shadow_tlbs(struct kvm_vcpu *vcpu);
533extern void kvm_mips_flush_host_tlb(int skip_kseg0); 529extern void kvm_mips_flush_host_tlb(int skip_kseg0);
534extern int kvm_mips_host_tlb_inv(struct kvm_vcpu *vcpu, unsigned long entryhi); 530extern int kvm_mips_host_tlb_inv(struct kvm_vcpu *vcpu, unsigned long entryhi);
535extern int kvm_mips_host_tlb_inv_index(struct kvm_vcpu *vcpu, int index); 531extern int kvm_mips_host_tlb_inv_index(struct kvm_vcpu *vcpu, int index);
@@ -541,10 +537,7 @@ extern unsigned long kvm_mips_translate_guest_kseg0_to_hpa(struct kvm_vcpu *vcpu
541 unsigned long gva); 537 unsigned long gva);
542extern void kvm_get_new_mmu_context(struct mm_struct *mm, unsigned long cpu, 538extern void kvm_get_new_mmu_context(struct mm_struct *mm, unsigned long cpu,
543 struct kvm_vcpu *vcpu); 539 struct kvm_vcpu *vcpu);
544extern void kvm_shadow_tlb_put(struct kvm_vcpu *vcpu);
545extern void kvm_shadow_tlb_load(struct kvm_vcpu *vcpu);
546extern void kvm_local_flush_tlb_all(void); 540extern void kvm_local_flush_tlb_all(void);
547extern void kvm_mips_init_shadow_tlb(struct kvm_vcpu *vcpu);
548extern void kvm_mips_alloc_new_mmu_context(struct kvm_vcpu *vcpu); 541extern void kvm_mips_alloc_new_mmu_context(struct kvm_vcpu *vcpu);
549extern void kvm_mips_vcpu_load(struct kvm_vcpu *vcpu, int cpu); 542extern void kvm_mips_vcpu_load(struct kvm_vcpu *vcpu, int cpu);
550extern void kvm_mips_vcpu_put(struct kvm_vcpu *vcpu); 543extern void kvm_mips_vcpu_put(struct kvm_vcpu *vcpu);
diff --git a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
index b86a1253a5bf..cd41e93bc1d8 100644
--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
@@ -16,7 +16,6 @@
16#define __ASM_MACH_AR71XX_REGS_H 16#define __ASM_MACH_AR71XX_REGS_H
17 17
18#include <linux/types.h> 18#include <linux/types.h>
19#include <linux/init.h>
20#include <linux/io.h> 19#include <linux/io.h>
21#include <linux/bitops.h> 20#include <linux/bitops.h>
22 21
diff --git a/arch/mips/include/asm/mach-bcm47xx/bcm47xx.h b/arch/mips/include/asm/mach-bcm47xx/bcm47xx.h
index cc7563ba1cbf..7527c1d33d02 100644
--- a/arch/mips/include/asm/mach-bcm47xx/bcm47xx.h
+++ b/arch/mips/include/asm/mach-bcm47xx/bcm47xx.h
@@ -56,4 +56,6 @@ void bcm47xx_fill_bcma_boardinfo(struct bcma_boardinfo *boardinfo,
56 const char *prefix); 56 const char *prefix);
57#endif 57#endif
58 58
59void bcm47xx_set_system_type(u16 chip_id);
60
59#endif /* __ASM_BCM47XX_H */ 61#endif /* __ASM_BCM47XX_H */
diff --git a/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h b/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h
index 00867dd05a69..40005fb39618 100644
--- a/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h
+++ b/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h
@@ -66,6 +66,7 @@ enum bcm47xx_board {
66 BCM47XX_BOARD_LINKSYS_WRT310NV1, 66 BCM47XX_BOARD_LINKSYS_WRT310NV1,
67 BCM47XX_BOARD_LINKSYS_WRT310NV2, 67 BCM47XX_BOARD_LINKSYS_WRT310NV2,
68 BCM47XX_BOARD_LINKSYS_WRT54G3GV2, 68 BCM47XX_BOARD_LINKSYS_WRT54G3GV2,
69 BCM47XX_BOARD_LINKSYS_WRT54GSV1,
69 BCM47XX_BOARD_LINKSYS_WRT610NV1, 70 BCM47XX_BOARD_LINKSYS_WRT610NV1,
70 BCM47XX_BOARD_LINKSYS_WRT610NV2, 71 BCM47XX_BOARD_LINKSYS_WRT610NV2,
71 BCM47XX_BOARD_LINKSYS_WRTSL54GS, 72 BCM47XX_BOARD_LINKSYS_WRTSL54GS,
diff --git a/arch/mips/include/asm/mach-bcm47xx/cpu-feature-overrides.h b/arch/mips/include/asm/mach-bcm47xx/cpu-feature-overrides.h
new file mode 100644
index 000000000000..b7992cd4aaf9
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm47xx/cpu-feature-overrides.h
@@ -0,0 +1,82 @@
1#ifndef __ASM_MACH_BCM47XX_CPU_FEATURE_OVERRIDES_H
2#define __ASM_MACH_BCM47XX_CPU_FEATURE_OVERRIDES_H
3
4#define cpu_has_tlb 1
5#define cpu_has_4kex 1
6#define cpu_has_3k_cache 0
7#define cpu_has_4k_cache 1
8#define cpu_has_tx39_cache 0
9#define cpu_has_fpu 0
10#define cpu_has_32fpr 0
11#define cpu_has_counter 1
12#if defined(CONFIG_BCM47XX_BCMA) && !defined(CONFIG_BCM47XX_SSB)
13#define cpu_has_watch 1
14#elif defined(CONFIG_BCM47XX_SSB) && !defined(CONFIG_BCM47XX_BCMA)
15#define cpu_has_watch 0
16#endif
17#define cpu_has_divec 1
18#define cpu_has_vce 0
19#define cpu_has_cache_cdex_p 0
20#define cpu_has_cache_cdex_s 0
21#define cpu_has_prefetch 1
22#define cpu_has_mcheck 1
23#define cpu_has_ejtag 1
24#define cpu_has_llsc 1
25
26/* cpu_has_mips16 */
27#define cpu_has_mdmx 0
28#define cpu_has_mips3d 0
29#define cpu_has_rixi 0
30#define cpu_has_mmips 0
31#define cpu_has_smartmips 0
32#define cpu_has_vtag_icache 0
33/* cpu_has_dc_aliases */
34#define cpu_has_ic_fills_f_dc 0
35#define cpu_has_pindexed_dcache 0
36#define cpu_icache_snoops_remote_store 0
37
38#define cpu_has_mips_2 1
39#define cpu_has_mips_3 0
40#define cpu_has_mips32r1 1
41#if defined(CONFIG_BCM47XX_BCMA) && !defined(CONFIG_BCM47XX_SSB)
42#define cpu_has_mips32r2 1
43#elif defined(CONFIG_BCM47XX_SSB) && !defined(CONFIG_BCM47XX_BCMA)
44#define cpu_has_mips32r2 0
45#endif
46#define cpu_has_mips64r1 0
47#define cpu_has_mips64r2 0
48
49#if defined(CONFIG_BCM47XX_BCMA) && !defined(CONFIG_BCM47XX_SSB)
50#define cpu_has_dsp 1
51#define cpu_has_dsp2 1
52#elif defined(CONFIG_BCM47XX_SSB) && !defined(CONFIG_BCM47XX_BCMA)
53#define cpu_has_dsp 0
54#define cpu_has_dsp2 0
55#endif
56#define cpu_has_mipsmt 0
57/* cpu_has_userlocal */
58
59#define cpu_has_nofpuex 0
60#define cpu_has_64bits 0
61#define cpu_has_64bit_zero_reg 0
62#if defined(CONFIG_BCM47XX_BCMA) && !defined(CONFIG_BCM47XX_SSB)
63#define cpu_has_vint 1
64#elif defined(CONFIG_BCM47XX_SSB) && !defined(CONFIG_BCM47XX_BCMA)
65#define cpu_has_vint 0
66#endif
67#define cpu_has_veic 0
68#define cpu_has_inclusive_pcaches 0
69
70#if defined(CONFIG_BCM47XX_BCMA) && !defined(CONFIG_BCM47XX_SSB)
71#define cpu_dcache_line_size() 32
72#define cpu_icache_line_size() 32
73#define cpu_has_perf_cntr_intr_bit 1
74#elif defined(CONFIG_BCM47XX_SSB) && !defined(CONFIG_BCM47XX_BCMA)
75#define cpu_dcache_line_size() 16
76#define cpu_icache_line_size() 16
77#define cpu_has_perf_cntr_intr_bit 0
78#endif
79#define cpu_scache_line_size() 0
80#define cpu_has_vz 0
81
82#endif /* __ASM_MACH_BCM47XX_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
index 19f9134bfe2f..3112f08f0c72 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
@@ -145,6 +145,7 @@ enum bcm63xx_regs_set {
145 RSET_UART1, 145 RSET_UART1,
146 RSET_GPIO, 146 RSET_GPIO,
147 RSET_SPI, 147 RSET_SPI,
148 RSET_HSSPI,
148 RSET_UDC0, 149 RSET_UDC0,
149 RSET_OHCI0, 150 RSET_OHCI0,
150 RSET_OHCI_PRIV, 151 RSET_OHCI_PRIV,
@@ -193,6 +194,7 @@ enum bcm63xx_regs_set {
193#define RSET_ENETDMAS_SIZE(chans) (16 * (chans)) 194#define RSET_ENETDMAS_SIZE(chans) (16 * (chans))
194#define RSET_ENETSW_SIZE 65536 195#define RSET_ENETSW_SIZE 65536
195#define RSET_UART_SIZE 24 196#define RSET_UART_SIZE 24
197#define RSET_HSSPI_SIZE 1536
196#define RSET_UDC_SIZE 256 198#define RSET_UDC_SIZE 256
197#define RSET_OHCI_SIZE 256 199#define RSET_OHCI_SIZE 256
198#define RSET_EHCI_SIZE 256 200#define RSET_EHCI_SIZE 256
@@ -265,6 +267,7 @@ enum bcm63xx_regs_set {
265#define BCM_6328_UART1_BASE (0xb0000120) 267#define BCM_6328_UART1_BASE (0xb0000120)
266#define BCM_6328_GPIO_BASE (0xb0000080) 268#define BCM_6328_GPIO_BASE (0xb0000080)
267#define BCM_6328_SPI_BASE (0xdeadbeef) 269#define BCM_6328_SPI_BASE (0xdeadbeef)
270#define BCM_6328_HSSPI_BASE (0xb0001000)
268#define BCM_6328_UDC0_BASE (0xdeadbeef) 271#define BCM_6328_UDC0_BASE (0xdeadbeef)
269#define BCM_6328_USBDMA_BASE (0xb000c000) 272#define BCM_6328_USBDMA_BASE (0xb000c000)
270#define BCM_6328_OHCI0_BASE (0xb0002600) 273#define BCM_6328_OHCI0_BASE (0xb0002600)
@@ -313,6 +316,7 @@ enum bcm63xx_regs_set {
313#define BCM_6338_UART1_BASE (0xdeadbeef) 316#define BCM_6338_UART1_BASE (0xdeadbeef)
314#define BCM_6338_GPIO_BASE (0xfffe0400) 317#define BCM_6338_GPIO_BASE (0xfffe0400)
315#define BCM_6338_SPI_BASE (0xfffe0c00) 318#define BCM_6338_SPI_BASE (0xfffe0c00)
319#define BCM_6338_HSSPI_BASE (0xdeadbeef)
316#define BCM_6338_UDC0_BASE (0xdeadbeef) 320#define BCM_6338_UDC0_BASE (0xdeadbeef)
317#define BCM_6338_USBDMA_BASE (0xfffe2400) 321#define BCM_6338_USBDMA_BASE (0xfffe2400)
318#define BCM_6338_OHCI0_BASE (0xdeadbeef) 322#define BCM_6338_OHCI0_BASE (0xdeadbeef)
@@ -360,6 +364,7 @@ enum bcm63xx_regs_set {
360#define BCM_6345_UART1_BASE (0xdeadbeef) 364#define BCM_6345_UART1_BASE (0xdeadbeef)
361#define BCM_6345_GPIO_BASE (0xfffe0400) 365#define BCM_6345_GPIO_BASE (0xfffe0400)
362#define BCM_6345_SPI_BASE (0xdeadbeef) 366#define BCM_6345_SPI_BASE (0xdeadbeef)
367#define BCM_6345_HSSPI_BASE (0xdeadbeef)
363#define BCM_6345_UDC0_BASE (0xdeadbeef) 368#define BCM_6345_UDC0_BASE (0xdeadbeef)
364#define BCM_6345_USBDMA_BASE (0xfffe2800) 369#define BCM_6345_USBDMA_BASE (0xfffe2800)
365#define BCM_6345_ENET0_BASE (0xfffe1800) 370#define BCM_6345_ENET0_BASE (0xfffe1800)
@@ -406,6 +411,7 @@ enum bcm63xx_regs_set {
406#define BCM_6348_UART1_BASE (0xdeadbeef) 411#define BCM_6348_UART1_BASE (0xdeadbeef)
407#define BCM_6348_GPIO_BASE (0xfffe0400) 412#define BCM_6348_GPIO_BASE (0xfffe0400)
408#define BCM_6348_SPI_BASE (0xfffe0c00) 413#define BCM_6348_SPI_BASE (0xfffe0c00)
414#define BCM_6348_HSSPI_BASE (0xdeadbeef)
409#define BCM_6348_UDC0_BASE (0xfffe1000) 415#define BCM_6348_UDC0_BASE (0xfffe1000)
410#define BCM_6348_USBDMA_BASE (0xdeadbeef) 416#define BCM_6348_USBDMA_BASE (0xdeadbeef)
411#define BCM_6348_OHCI0_BASE (0xfffe1b00) 417#define BCM_6348_OHCI0_BASE (0xfffe1b00)
@@ -451,6 +457,7 @@ enum bcm63xx_regs_set {
451#define BCM_6358_UART1_BASE (0xfffe0120) 457#define BCM_6358_UART1_BASE (0xfffe0120)
452#define BCM_6358_GPIO_BASE (0xfffe0080) 458#define BCM_6358_GPIO_BASE (0xfffe0080)
453#define BCM_6358_SPI_BASE (0xfffe0800) 459#define BCM_6358_SPI_BASE (0xfffe0800)
460#define BCM_6358_HSSPI_BASE (0xdeadbeef)
454#define BCM_6358_UDC0_BASE (0xfffe0800) 461#define BCM_6358_UDC0_BASE (0xfffe0800)
455#define BCM_6358_USBDMA_BASE (0xdeadbeef) 462#define BCM_6358_USBDMA_BASE (0xdeadbeef)
456#define BCM_6358_OHCI0_BASE (0xfffe1400) 463#define BCM_6358_OHCI0_BASE (0xfffe1400)
@@ -553,6 +560,7 @@ enum bcm63xx_regs_set {
553#define BCM_6368_UART1_BASE (0xb0000120) 560#define BCM_6368_UART1_BASE (0xb0000120)
554#define BCM_6368_GPIO_BASE (0xb0000080) 561#define BCM_6368_GPIO_BASE (0xb0000080)
555#define BCM_6368_SPI_BASE (0xb0000800) 562#define BCM_6368_SPI_BASE (0xb0000800)
563#define BCM_6368_HSSPI_BASE (0xdeadbeef)
556#define BCM_6368_UDC0_BASE (0xdeadbeef) 564#define BCM_6368_UDC0_BASE (0xdeadbeef)
557#define BCM_6368_USBDMA_BASE (0xb0004800) 565#define BCM_6368_USBDMA_BASE (0xb0004800)
558#define BCM_6368_OHCI0_BASE (0xb0001600) 566#define BCM_6368_OHCI0_BASE (0xb0001600)
@@ -604,6 +612,7 @@ extern const unsigned long *bcm63xx_regs_base;
604 __GEN_RSET_BASE(__cpu, UART1) \ 612 __GEN_RSET_BASE(__cpu, UART1) \
605 __GEN_RSET_BASE(__cpu, GPIO) \ 613 __GEN_RSET_BASE(__cpu, GPIO) \
606 __GEN_RSET_BASE(__cpu, SPI) \ 614 __GEN_RSET_BASE(__cpu, SPI) \
615 __GEN_RSET_BASE(__cpu, HSSPI) \
607 __GEN_RSET_BASE(__cpu, UDC0) \ 616 __GEN_RSET_BASE(__cpu, UDC0) \
608 __GEN_RSET_BASE(__cpu, OHCI0) \ 617 __GEN_RSET_BASE(__cpu, OHCI0) \
609 __GEN_RSET_BASE(__cpu, OHCI_PRIV) \ 618 __GEN_RSET_BASE(__cpu, OHCI_PRIV) \
@@ -647,6 +656,7 @@ extern const unsigned long *bcm63xx_regs_base;
647 [RSET_UART1] = BCM_## __cpu ##_UART1_BASE, \ 656 [RSET_UART1] = BCM_## __cpu ##_UART1_BASE, \
648 [RSET_GPIO] = BCM_## __cpu ##_GPIO_BASE, \ 657 [RSET_GPIO] = BCM_## __cpu ##_GPIO_BASE, \
649 [RSET_SPI] = BCM_## __cpu ##_SPI_BASE, \ 658 [RSET_SPI] = BCM_## __cpu ##_SPI_BASE, \
659 [RSET_HSSPI] = BCM_## __cpu ##_HSSPI_BASE, \
650 [RSET_UDC0] = BCM_## __cpu ##_UDC0_BASE, \ 660 [RSET_UDC0] = BCM_## __cpu ##_UDC0_BASE, \
651 [RSET_OHCI0] = BCM_## __cpu ##_OHCI0_BASE, \ 661 [RSET_OHCI0] = BCM_## __cpu ##_OHCI0_BASE, \
652 [RSET_OHCI_PRIV] = BCM_## __cpu ##_OHCI_PRIV_BASE, \ 662 [RSET_OHCI_PRIV] = BCM_## __cpu ##_OHCI_PRIV_BASE, \
@@ -727,6 +737,7 @@ enum bcm63xx_irq {
727 IRQ_ENET0, 737 IRQ_ENET0,
728 IRQ_ENET1, 738 IRQ_ENET1,
729 IRQ_ENET_PHY, 739 IRQ_ENET_PHY,
740 IRQ_HSSPI,
730 IRQ_OHCI0, 741 IRQ_OHCI0,
731 IRQ_EHCI0, 742 IRQ_EHCI0,
732 IRQ_USBD, 743 IRQ_USBD,
@@ -815,6 +826,7 @@ enum bcm63xx_irq {
815#define BCM_6328_ENET0_IRQ 0 826#define BCM_6328_ENET0_IRQ 0
816#define BCM_6328_ENET1_IRQ 0 827#define BCM_6328_ENET1_IRQ 0
817#define BCM_6328_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12) 828#define BCM_6328_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12)
829#define BCM_6328_HSSPI_IRQ (IRQ_INTERNAL_BASE + 29)
818#define BCM_6328_OHCI0_IRQ (BCM_6328_HIGH_IRQ_BASE + 9) 830#define BCM_6328_OHCI0_IRQ (BCM_6328_HIGH_IRQ_BASE + 9)
819#define BCM_6328_EHCI0_IRQ (BCM_6328_HIGH_IRQ_BASE + 10) 831#define BCM_6328_EHCI0_IRQ (BCM_6328_HIGH_IRQ_BASE + 10)
820#define BCM_6328_USBD_IRQ (IRQ_INTERNAL_BASE + 4) 832#define BCM_6328_USBD_IRQ (IRQ_INTERNAL_BASE + 4)
@@ -860,6 +872,7 @@ enum bcm63xx_irq {
860#define BCM_6338_ENET0_IRQ (IRQ_INTERNAL_BASE + 8) 872#define BCM_6338_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
861#define BCM_6338_ENET1_IRQ 0 873#define BCM_6338_ENET1_IRQ 0
862#define BCM_6338_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9) 874#define BCM_6338_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
875#define BCM_6338_HSSPI_IRQ 0
863#define BCM_6338_OHCI0_IRQ 0 876#define BCM_6338_OHCI0_IRQ 0
864#define BCM_6338_EHCI0_IRQ 0 877#define BCM_6338_EHCI0_IRQ 0
865#define BCM_6338_USBD_IRQ 0 878#define BCM_6338_USBD_IRQ 0
@@ -898,6 +911,7 @@ enum bcm63xx_irq {
898#define BCM_6345_ENET0_IRQ (IRQ_INTERNAL_BASE + 8) 911#define BCM_6345_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
899#define BCM_6345_ENET1_IRQ 0 912#define BCM_6345_ENET1_IRQ 0
900#define BCM_6345_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12) 913#define BCM_6345_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12)
914#define BCM_6345_HSSPI_IRQ 0
901#define BCM_6345_OHCI0_IRQ 0 915#define BCM_6345_OHCI0_IRQ 0
902#define BCM_6345_EHCI0_IRQ 0 916#define BCM_6345_EHCI0_IRQ 0
903#define BCM_6345_USBD_IRQ 0 917#define BCM_6345_USBD_IRQ 0
@@ -936,6 +950,7 @@ enum bcm63xx_irq {
936#define BCM_6348_ENET0_IRQ (IRQ_INTERNAL_BASE + 8) 950#define BCM_6348_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
937#define BCM_6348_ENET1_IRQ (IRQ_INTERNAL_BASE + 7) 951#define BCM_6348_ENET1_IRQ (IRQ_INTERNAL_BASE + 7)
938#define BCM_6348_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9) 952#define BCM_6348_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
953#define BCM_6348_HSSPI_IRQ 0
939#define BCM_6348_OHCI0_IRQ (IRQ_INTERNAL_BASE + 12) 954#define BCM_6348_OHCI0_IRQ (IRQ_INTERNAL_BASE + 12)
940#define BCM_6348_EHCI0_IRQ 0 955#define BCM_6348_EHCI0_IRQ 0
941#define BCM_6348_USBD_IRQ 0 956#define BCM_6348_USBD_IRQ 0
@@ -974,6 +989,7 @@ enum bcm63xx_irq {
974#define BCM_6358_ENET0_IRQ (IRQ_INTERNAL_BASE + 8) 989#define BCM_6358_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
975#define BCM_6358_ENET1_IRQ (IRQ_INTERNAL_BASE + 6) 990#define BCM_6358_ENET1_IRQ (IRQ_INTERNAL_BASE + 6)
976#define BCM_6358_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9) 991#define BCM_6358_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
992#define BCM_6358_HSSPI_IRQ 0
977#define BCM_6358_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5) 993#define BCM_6358_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5)
978#define BCM_6358_EHCI0_IRQ (IRQ_INTERNAL_BASE + 10) 994#define BCM_6358_EHCI0_IRQ (IRQ_INTERNAL_BASE + 10)
979#define BCM_6358_USBD_IRQ 0 995#define BCM_6358_USBD_IRQ 0
@@ -1086,6 +1102,7 @@ enum bcm63xx_irq {
1086#define BCM_6368_ENET0_IRQ 0 1102#define BCM_6368_ENET0_IRQ 0
1087#define BCM_6368_ENET1_IRQ 0 1103#define BCM_6368_ENET1_IRQ 0
1088#define BCM_6368_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 15) 1104#define BCM_6368_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 15)
1105#define BCM_6368_HSSPI_IRQ 0
1089#define BCM_6368_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5) 1106#define BCM_6368_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5)
1090#define BCM_6368_EHCI0_IRQ (IRQ_INTERNAL_BASE + 7) 1107#define BCM_6368_EHCI0_IRQ (IRQ_INTERNAL_BASE + 7)
1091#define BCM_6368_USBD_IRQ (IRQ_INTERNAL_BASE + 8) 1108#define BCM_6368_USBD_IRQ (IRQ_INTERNAL_BASE + 8)
@@ -1133,6 +1150,7 @@ extern const int *bcm63xx_irqs;
1133 [IRQ_ENET0] = BCM_## __cpu ##_ENET0_IRQ, \ 1150 [IRQ_ENET0] = BCM_## __cpu ##_ENET0_IRQ, \
1134 [IRQ_ENET1] = BCM_## __cpu ##_ENET1_IRQ, \ 1151 [IRQ_ENET1] = BCM_## __cpu ##_ENET1_IRQ, \
1135 [IRQ_ENET_PHY] = BCM_## __cpu ##_ENET_PHY_IRQ, \ 1152 [IRQ_ENET_PHY] = BCM_## __cpu ##_ENET_PHY_IRQ, \
1153 [IRQ_HSSPI] = BCM_## __cpu ##_HSSPI_IRQ, \
1136 [IRQ_OHCI0] = BCM_## __cpu ##_OHCI0_IRQ, \ 1154 [IRQ_OHCI0] = BCM_## __cpu ##_OHCI0_IRQ, \
1137 [IRQ_EHCI0] = BCM_## __cpu ##_EHCI0_IRQ, \ 1155 [IRQ_EHCI0] = BCM_## __cpu ##_EHCI0_IRQ, \
1138 [IRQ_USBD] = BCM_## __cpu ##_USBD_IRQ, \ 1156 [IRQ_USBD] = BCM_## __cpu ##_USBD_IRQ, \
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_hsspi.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_hsspi.h
new file mode 100644
index 000000000000..1b1acafb3d79
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_hsspi.h
@@ -0,0 +1,8 @@
1#ifndef BCM63XX_DEV_HSSPI_H
2#define BCM63XX_DEV_HSSPI_H
3
4#include <linux/types.h>
5
6int bcm63xx_hsspi_register(void);
7
8#endif /* BCM63XX_DEV_HSSPI_H */
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
index 9875db31d883..ab427f8814e6 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
@@ -463,126 +463,6 @@
463#define WDT_SOFTRESET_REG 0xc 463#define WDT_SOFTRESET_REG 0xc
464 464
465/************************************************************************* 465/*************************************************************************
466 * _REG relative to RSET_UARTx
467 *************************************************************************/
468
469/* UART Control Register */
470#define UART_CTL_REG 0x0
471#define UART_CTL_RXTMOUTCNT_SHIFT 0
472#define UART_CTL_RXTMOUTCNT_MASK (0x1f << UART_CTL_RXTMOUTCNT_SHIFT)
473#define UART_CTL_RSTTXDN_SHIFT 5
474#define UART_CTL_RSTTXDN_MASK (1 << UART_CTL_RSTTXDN_SHIFT)
475#define UART_CTL_RSTRXFIFO_SHIFT 6
476#define UART_CTL_RSTRXFIFO_MASK (1 << UART_CTL_RSTRXFIFO_SHIFT)
477#define UART_CTL_RSTTXFIFO_SHIFT 7
478#define UART_CTL_RSTTXFIFO_MASK (1 << UART_CTL_RSTTXFIFO_SHIFT)
479#define UART_CTL_STOPBITS_SHIFT 8
480#define UART_CTL_STOPBITS_MASK (0xf << UART_CTL_STOPBITS_SHIFT)
481#define UART_CTL_STOPBITS_1 (0x7 << UART_CTL_STOPBITS_SHIFT)
482#define UART_CTL_STOPBITS_2 (0xf << UART_CTL_STOPBITS_SHIFT)
483#define UART_CTL_BITSPERSYM_SHIFT 12
484#define UART_CTL_BITSPERSYM_MASK (0x3 << UART_CTL_BITSPERSYM_SHIFT)
485#define UART_CTL_XMITBRK_SHIFT 14
486#define UART_CTL_XMITBRK_MASK (1 << UART_CTL_XMITBRK_SHIFT)
487#define UART_CTL_RSVD_SHIFT 15
488#define UART_CTL_RSVD_MASK (1 << UART_CTL_RSVD_SHIFT)
489#define UART_CTL_RXPAREVEN_SHIFT 16
490#define UART_CTL_RXPAREVEN_MASK (1 << UART_CTL_RXPAREVEN_SHIFT)
491#define UART_CTL_RXPAREN_SHIFT 17
492#define UART_CTL_RXPAREN_MASK (1 << UART_CTL_RXPAREN_SHIFT)
493#define UART_CTL_TXPAREVEN_SHIFT 18
494#define UART_CTL_TXPAREVEN_MASK (1 << UART_CTL_TXPAREVEN_SHIFT)
495#define UART_CTL_TXPAREN_SHIFT 18
496#define UART_CTL_TXPAREN_MASK (1 << UART_CTL_TXPAREN_SHIFT)
497#define UART_CTL_LOOPBACK_SHIFT 20
498#define UART_CTL_LOOPBACK_MASK (1 << UART_CTL_LOOPBACK_SHIFT)
499#define UART_CTL_RXEN_SHIFT 21
500#define UART_CTL_RXEN_MASK (1 << UART_CTL_RXEN_SHIFT)
501#define UART_CTL_TXEN_SHIFT 22
502#define UART_CTL_TXEN_MASK (1 << UART_CTL_TXEN_SHIFT)
503#define UART_CTL_BRGEN_SHIFT 23
504#define UART_CTL_BRGEN_MASK (1 << UART_CTL_BRGEN_SHIFT)
505
506/* UART Baudword register */
507#define UART_BAUD_REG 0x4
508
509/* UART Misc Control register */
510#define UART_MCTL_REG 0x8
511#define UART_MCTL_DTR_SHIFT 0
512#define UART_MCTL_DTR_MASK (1 << UART_MCTL_DTR_SHIFT)
513#define UART_MCTL_RTS_SHIFT 1
514#define UART_MCTL_RTS_MASK (1 << UART_MCTL_RTS_SHIFT)
515#define UART_MCTL_RXFIFOTHRESH_SHIFT 8
516#define UART_MCTL_RXFIFOTHRESH_MASK (0xf << UART_MCTL_RXFIFOTHRESH_SHIFT)
517#define UART_MCTL_TXFIFOTHRESH_SHIFT 12
518#define UART_MCTL_TXFIFOTHRESH_MASK (0xf << UART_MCTL_TXFIFOTHRESH_SHIFT)
519#define UART_MCTL_RXFIFOFILL_SHIFT 16
520#define UART_MCTL_RXFIFOFILL_MASK (0x1f << UART_MCTL_RXFIFOFILL_SHIFT)
521#define UART_MCTL_TXFIFOFILL_SHIFT 24
522#define UART_MCTL_TXFIFOFILL_MASK (0x1f << UART_MCTL_TXFIFOFILL_SHIFT)
523
524/* UART External Input Configuration register */
525#define UART_EXTINP_REG 0xc
526#define UART_EXTINP_RI_SHIFT 0
527#define UART_EXTINP_RI_MASK (1 << UART_EXTINP_RI_SHIFT)
528#define UART_EXTINP_CTS_SHIFT 1
529#define UART_EXTINP_CTS_MASK (1 << UART_EXTINP_CTS_SHIFT)
530#define UART_EXTINP_DCD_SHIFT 2
531#define UART_EXTINP_DCD_MASK (1 << UART_EXTINP_DCD_SHIFT)
532#define UART_EXTINP_DSR_SHIFT 3
533#define UART_EXTINP_DSR_MASK (1 << UART_EXTINP_DSR_SHIFT)
534#define UART_EXTINP_IRSTAT(x) (1 << (x + 4))
535#define UART_EXTINP_IRMASK(x) (1 << (x + 8))
536#define UART_EXTINP_IR_RI 0
537#define UART_EXTINP_IR_CTS 1
538#define UART_EXTINP_IR_DCD 2
539#define UART_EXTINP_IR_DSR 3
540#define UART_EXTINP_RI_NOSENSE_SHIFT 16
541#define UART_EXTINP_RI_NOSENSE_MASK (1 << UART_EXTINP_RI_NOSENSE_SHIFT)
542#define UART_EXTINP_CTS_NOSENSE_SHIFT 17
543#define UART_EXTINP_CTS_NOSENSE_MASK (1 << UART_EXTINP_CTS_NOSENSE_SHIFT)
544#define UART_EXTINP_DCD_NOSENSE_SHIFT 18
545#define UART_EXTINP_DCD_NOSENSE_MASK (1 << UART_EXTINP_DCD_NOSENSE_SHIFT)
546#define UART_EXTINP_DSR_NOSENSE_SHIFT 19
547#define UART_EXTINP_DSR_NOSENSE_MASK (1 << UART_EXTINP_DSR_NOSENSE_SHIFT)
548
549/* UART Interrupt register */
550#define UART_IR_REG 0x10
551#define UART_IR_MASK(x) (1 << (x + 16))
552#define UART_IR_STAT(x) (1 << (x))
553#define UART_IR_EXTIP 0
554#define UART_IR_TXUNDER 1
555#define UART_IR_TXOVER 2
556#define UART_IR_TXTRESH 3
557#define UART_IR_TXRDLATCH 4
558#define UART_IR_TXEMPTY 5
559#define UART_IR_RXUNDER 6
560#define UART_IR_RXOVER 7
561#define UART_IR_RXTIMEOUT 8
562#define UART_IR_RXFULL 9
563#define UART_IR_RXTHRESH 10
564#define UART_IR_RXNOTEMPTY 11
565#define UART_IR_RXFRAMEERR 12
566#define UART_IR_RXPARERR 13
567#define UART_IR_RXBRK 14
568#define UART_IR_TXDONE 15
569
570/* UART Fifo register */
571#define UART_FIFO_REG 0x14
572#define UART_FIFO_VALID_SHIFT 0
573#define UART_FIFO_VALID_MASK 0xff
574#define UART_FIFO_FRAMEERR_SHIFT 8
575#define UART_FIFO_FRAMEERR_MASK (1 << UART_FIFO_FRAMEERR_SHIFT)
576#define UART_FIFO_PARERR_SHIFT 9
577#define UART_FIFO_PARERR_MASK (1 << UART_FIFO_PARERR_SHIFT)
578#define UART_FIFO_BRKDET_SHIFT 10
579#define UART_FIFO_BRKDET_MASK (1 << UART_FIFO_BRKDET_SHIFT)
580#define UART_FIFO_ANYERR_MASK (UART_FIFO_FRAMEERR_MASK | \
581 UART_FIFO_PARERR_MASK | \
582 UART_FIFO_BRKDET_MASK)
583
584
585/*************************************************************************
586 * _REG relative to RSET_GPIO 466 * _REG relative to RSET_GPIO
587 *************************************************************************/ 467 *************************************************************************/
588 468
diff --git a/arch/mips/include/asm/mach-generic/dma-coherence.h b/arch/mips/include/asm/mach-generic/dma-coherence.h
index a9e8f6b62b0b..7629c35986f7 100644
--- a/arch/mips/include/asm/mach-generic/dma-coherence.h
+++ b/arch/mips/include/asm/mach-generic/dma-coherence.h
@@ -49,11 +49,7 @@ static inline int plat_dma_supported(struct device *dev, u64 mask)
49 49
50static inline int plat_device_is_coherent(struct device *dev) 50static inline int plat_device_is_coherent(struct device *dev)
51{ 51{
52#ifdef CONFIG_DMA_COHERENT
53 return 1;
54#else
55 return coherentio; 52 return coherentio;
56#endif
57} 53}
58 54
59#ifdef CONFIG_SWIOTLB 55#ifdef CONFIG_SWIOTLB
diff --git a/arch/mips/include/asm/mach-generic/floppy.h b/arch/mips/include/asm/mach-generic/floppy.h
index 5b5cd689a2f7..e2561d99a3fe 100644
--- a/arch/mips/include/asm/mach-generic/floppy.h
+++ b/arch/mips/include/asm/mach-generic/floppy.h
@@ -9,7 +9,6 @@
9#define __ASM_MACH_GENERIC_FLOPPY_H 9#define __ASM_MACH_GENERIC_FLOPPY_H
10 10
11#include <linux/delay.h> 11#include <linux/delay.h>
12#include <linux/init.h>
13#include <linux/ioport.h> 12#include <linux/ioport.h>
14#include <linux/sched.h> 13#include <linux/sched.h>
15#include <linux/linkage.h> 14#include <linux/linkage.h>
diff --git a/arch/mips/include/asm/mach-generic/ide.h b/arch/mips/include/asm/mach-generic/ide.h
index affa66f5c2da..4ae5fbcb15a5 100644
--- a/arch/mips/include/asm/mach-generic/ide.h
+++ b/arch/mips/include/asm/mach-generic/ide.h
@@ -23,7 +23,7 @@
23static inline void __ide_flush_prologue(void) 23static inline void __ide_flush_prologue(void)
24{ 24{
25#ifdef CONFIG_SMP 25#ifdef CONFIG_SMP
26 if (cpu_has_dc_aliases) 26 if (cpu_has_dc_aliases || !cpu_has_ic_fills_f_dc)
27 preempt_disable(); 27 preempt_disable();
28#endif 28#endif
29} 29}
@@ -31,14 +31,14 @@ static inline void __ide_flush_prologue(void)
31static inline void __ide_flush_epilogue(void) 31static inline void __ide_flush_epilogue(void)
32{ 32{
33#ifdef CONFIG_SMP 33#ifdef CONFIG_SMP
34 if (cpu_has_dc_aliases) 34 if (cpu_has_dc_aliases || !cpu_has_ic_fills_f_dc)
35 preempt_enable(); 35 preempt_enable();
36#endif 36#endif
37} 37}
38 38
39static inline void __ide_flush_dcache_range(unsigned long addr, unsigned long size) 39static inline void __ide_flush_dcache_range(unsigned long addr, unsigned long size)
40{ 40{
41 if (cpu_has_dc_aliases) { 41 if (cpu_has_dc_aliases || !cpu_has_ic_fills_f_dc) {
42 unsigned long end = addr + size; 42 unsigned long end = addr + size;
43 43
44 while (addr < end) { 44 while (addr < end) {
diff --git a/arch/mips/include/asm/mach-jazz/floppy.h b/arch/mips/include/asm/mach-jazz/floppy.h
index 62aa1e287fba..4b86c88a03b7 100644
--- a/arch/mips/include/asm/mach-jazz/floppy.h
+++ b/arch/mips/include/asm/mach-jazz/floppy.h
@@ -9,7 +9,6 @@
9#define __ASM_MACH_JAZZ_FLOPPY_H 9#define __ASM_MACH_JAZZ_FLOPPY_H
10 10
11#include <linux/delay.h> 11#include <linux/delay.h>
12#include <linux/init.h>
13#include <linux/linkage.h> 12#include <linux/linkage.h>
14#include <linux/types.h> 13#include <linux/types.h>
15#include <linux/mm.h> 14#include <linux/mm.h>
diff --git a/arch/mips/include/asm/mach-jz4740/platform.h b/arch/mips/include/asm/mach-jz4740/platform.h
index 05988c2d6565..069b43a9da6f 100644
--- a/arch/mips/include/asm/mach-jz4740/platform.h
+++ b/arch/mips/include/asm/mach-jz4740/platform.h
@@ -21,6 +21,7 @@
21 21
22extern struct platform_device jz4740_usb_ohci_device; 22extern struct platform_device jz4740_usb_ohci_device;
23extern struct platform_device jz4740_udc_device; 23extern struct platform_device jz4740_udc_device;
24extern struct platform_device jz4740_udc_xceiv_device;
24extern struct platform_device jz4740_mmc_device; 25extern struct platform_device jz4740_mmc_device;
25extern struct platform_device jz4740_rtc_device; 26extern struct platform_device jz4740_rtc_device;
26extern struct platform_device jz4740_i2c_device; 27extern struct platform_device jz4740_i2c_device;
diff --git a/arch/mips/include/asm/mach-netlogic/irq.h b/arch/mips/include/asm/mach-netlogic/irq.h
index 868ed8a2ed5c..c0dbd530cca6 100644
--- a/arch/mips/include/asm/mach-netlogic/irq.h
+++ b/arch/mips/include/asm/mach-netlogic/irq.h
@@ -9,7 +9,8 @@
9#define __ASM_NETLOGIC_IRQ_H 9#define __ASM_NETLOGIC_IRQ_H
10 10
11#include <asm/mach-netlogic/multi-node.h> 11#include <asm/mach-netlogic/multi-node.h>
12#define NR_IRQS (64 * NLM_NR_NODES) 12#define NLM_IRQS_PER_NODE 1024
13#define NR_IRQS (NLM_IRQS_PER_NODE * NLM_NR_NODES)
13 14
14#define MIPS_CPU_IRQ_BASE 0 15#define MIPS_CPU_IRQ_BASE 0
15 16
diff --git a/arch/mips/include/asm/mach-netlogic/multi-node.h b/arch/mips/include/asm/mach-netlogic/multi-node.h
index d62fc773f4d7..9ed8dacdc37c 100644
--- a/arch/mips/include/asm/mach-netlogic/multi-node.h
+++ b/arch/mips/include/asm/mach-netlogic/multi-node.h
@@ -47,8 +47,37 @@
47#endif 47#endif
48#endif 48#endif
49 49
50#define NLM_CORES_PER_NODE 8
51#define NLM_THREADS_PER_CORE 4 50#define NLM_THREADS_PER_CORE 4
52#define NLM_CPUS_PER_NODE (NLM_CORES_PER_NODE * NLM_THREADS_PER_CORE) 51#ifdef CONFIG_CPU_XLR
52#define nlm_cores_per_node() 8
53#else
54extern unsigned int xlp_cores_per_node;
55#define nlm_cores_per_node() xlp_cores_per_node
56#endif
57
58#define nlm_threads_per_node() (nlm_cores_per_node() * NLM_THREADS_PER_CORE)
59#define nlm_cpuid_to_node(c) ((c) / nlm_threads_per_node())
60
61struct nlm_soc_info {
62 unsigned long coremask; /* cores enabled on the soc */
63 unsigned long ebase; /* not used now */
64 uint64_t irqmask; /* EIMR for the node */
65 uint64_t sysbase; /* only for XLP - sys block base */
66 uint64_t picbase; /* PIC block base */
67 spinlock_t piclock; /* lock for PIC access */
68 cpumask_t cpumask; /* logical cpu mask for node */
69 unsigned int socbus;
70};
71
72extern struct nlm_soc_info nlm_nodes[NLM_NR_NODES];
73#define nlm_get_node(i) (&nlm_nodes[i])
74#define nlm_node_present(n) ((n) >= 0 && (n) < NLM_NR_NODES && \
75 nlm_get_node(n)->coremask != 0)
76#ifdef CONFIG_CPU_XLR
77#define nlm_current_node() (&nlm_nodes[0])
78#else
79#define nlm_current_node() (&nlm_nodes[nlm_nodeid()])
80#endif
81void nlm_node_init(int node);
53 82
54#endif 83#endif
diff --git a/arch/mips/include/asm/mach-netlogic/topology.h b/arch/mips/include/asm/mach-netlogic/topology.h
new file mode 100644
index 000000000000..0da99fa11c38
--- /dev/null
+++ b/arch/mips/include/asm/mach-netlogic/topology.h
@@ -0,0 +1,20 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2013 Broadcom Corporation
7 */
8#ifndef _ASM_MACH_NETLOGIC_TOPOLOGY_H
9#define _ASM_MACH_NETLOGIC_TOPOLOGY_H
10
11#include <asm/mach-netlogic/multi-node.h>
12
13#define topology_physical_package_id(cpu) cpu_to_node(cpu)
14#define topology_core_id(cpu) (cpu_logical_map(cpu) / NLM_THREADS_PER_CORE)
15#define topology_thread_cpumask(cpu) (&cpu_sibling_map[cpu])
16#define topology_core_cpumask(cpu) cpumask_of_node(cpu_to_node(cpu))
17
18#include <asm-generic/topology.h>
19
20#endif /* _ASM_MACH_NETLOGIC_TOPOLOGY_H */
diff --git a/arch/mips/include/asm/mips-boards/piix4.h b/arch/mips/include/asm/mips-boards/piix4.h
index e33227998713..836e2ede24de 100644
--- a/arch/mips/include/asm/mips-boards/piix4.h
+++ b/arch/mips/include/asm/mips-boards/piix4.h
@@ -26,6 +26,10 @@
26#define PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_DISABLE (1 << 7) 26#define PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_DISABLE (1 << 7)
27#define PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_MASK 0xf 27#define PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_MASK 0xf
28#define PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_MAX 16 28#define PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_MAX 16
29/* SERIRQ Control */
30#define PIIX4_FUNC0_SERIRQC 0x64
31#define PIIX4_FUNC0_SERIRQC_EN (1 << 7)
32#define PIIX4_FUNC0_SERIRQC_CONT (1 << 6)
29/* Top Of Memory */ 33/* Top Of Memory */
30#define PIIX4_FUNC0_TOM 0x69 34#define PIIX4_FUNC0_TOM 0x69
31#define PIIX4_FUNC0_TOM_TOP_OF_MEMORY_MASK 0xf0 35#define PIIX4_FUNC0_TOM_TOP_OF_MEMORY_MASK 0xf0
@@ -34,6 +38,9 @@
34#define PIIX4_FUNC0_DLC_USBPR_EN (1 << 2) 38#define PIIX4_FUNC0_DLC_USBPR_EN (1 << 2)
35#define PIIX4_FUNC0_DLC_PASSIVE_RELEASE_EN (1 << 1) 39#define PIIX4_FUNC0_DLC_PASSIVE_RELEASE_EN (1 << 1)
36#define PIIX4_FUNC0_DLC_DELAYED_TRANSACTION_EN (1 << 0) 40#define PIIX4_FUNC0_DLC_DELAYED_TRANSACTION_EN (1 << 0)
41/* General Configuration */
42#define PIIX4_FUNC0_GENCFG 0xb0
43#define PIIX4_FUNC0_GENCFG_SERIRQ (1 << 16)
37 44
38/* IDE Timing */ 45/* IDE Timing */
39#define PIIX4_FUNC1_IDETIM_PRIMARY_LO 0x40 46#define PIIX4_FUNC1_IDETIM_PRIMARY_LO 0x40
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index e0331414c7d6..bbc3dd4294bc 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -14,6 +14,7 @@
14#define _ASM_MIPSREGS_H 14#define _ASM_MIPSREGS_H
15 15
16#include <linux/linkage.h> 16#include <linux/linkage.h>
17#include <linux/types.h>
17#include <asm/hazards.h> 18#include <asm/hazards.h>
18#include <asm/war.h> 19#include <asm/war.h>
19 20
@@ -573,7 +574,9 @@
573#define MIPS_CONF1_IA (_ULCAST_(7) << 16) 574#define MIPS_CONF1_IA (_ULCAST_(7) << 16)
574#define MIPS_CONF1_IL (_ULCAST_(7) << 19) 575#define MIPS_CONF1_IL (_ULCAST_(7) << 19)
575#define MIPS_CONF1_IS (_ULCAST_(7) << 22) 576#define MIPS_CONF1_IS (_ULCAST_(7) << 22)
576#define MIPS_CONF1_TLBS (_ULCAST_(63)<< 25) 577#define MIPS_CONF1_TLBS_SHIFT (25)
578#define MIPS_CONF1_TLBS_SIZE (6)
579#define MIPS_CONF1_TLBS (_ULCAST_(63) << MIPS_CONF1_TLBS_SHIFT)
577 580
578#define MIPS_CONF2_SA (_ULCAST_(15)<< 0) 581#define MIPS_CONF2_SA (_ULCAST_(15)<< 0)
579#define MIPS_CONF2_SL (_ULCAST_(15)<< 4) 582#define MIPS_CONF2_SL (_ULCAST_(15)<< 4)
@@ -587,21 +590,53 @@
587#define MIPS_CONF3_TL (_ULCAST_(1) << 0) 590#define MIPS_CONF3_TL (_ULCAST_(1) << 0)
588#define MIPS_CONF3_SM (_ULCAST_(1) << 1) 591#define MIPS_CONF3_SM (_ULCAST_(1) << 1)
589#define MIPS_CONF3_MT (_ULCAST_(1) << 2) 592#define MIPS_CONF3_MT (_ULCAST_(1) << 2)
593#define MIPS_CONF3_CDMM (_ULCAST_(1) << 3)
590#define MIPS_CONF3_SP (_ULCAST_(1) << 4) 594#define MIPS_CONF3_SP (_ULCAST_(1) << 4)
591#define MIPS_CONF3_VINT (_ULCAST_(1) << 5) 595#define MIPS_CONF3_VINT (_ULCAST_(1) << 5)
592#define MIPS_CONF3_VEIC (_ULCAST_(1) << 6) 596#define MIPS_CONF3_VEIC (_ULCAST_(1) << 6)
593#define MIPS_CONF3_LPA (_ULCAST_(1) << 7) 597#define MIPS_CONF3_LPA (_ULCAST_(1) << 7)
598#define MIPS_CONF3_ITL (_ULCAST_(1) << 8)
599#define MIPS_CONF3_CTXTC (_ULCAST_(1) << 9)
594#define MIPS_CONF3_DSP (_ULCAST_(1) << 10) 600#define MIPS_CONF3_DSP (_ULCAST_(1) << 10)
595#define MIPS_CONF3_DSP2P (_ULCAST_(1) << 11) 601#define MIPS_CONF3_DSP2P (_ULCAST_(1) << 11)
596#define MIPS_CONF3_RXI (_ULCAST_(1) << 12) 602#define MIPS_CONF3_RXI (_ULCAST_(1) << 12)
597#define MIPS_CONF3_ULRI (_ULCAST_(1) << 13) 603#define MIPS_CONF3_ULRI (_ULCAST_(1) << 13)
598#define MIPS_CONF3_ISA (_ULCAST_(3) << 14) 604#define MIPS_CONF3_ISA (_ULCAST_(3) << 14)
599#define MIPS_CONF3_ISA_OE (_ULCAST_(1) << 16) 605#define MIPS_CONF3_ISA_OE (_ULCAST_(1) << 16)
606#define MIPS_CONF3_MCU (_ULCAST_(1) << 17)
607#define MIPS_CONF3_MMAR (_ULCAST_(7) << 18)
608#define MIPS_CONF3_IPLW (_ULCAST_(3) << 21)
600#define MIPS_CONF3_VZ (_ULCAST_(1) << 23) 609#define MIPS_CONF3_VZ (_ULCAST_(1) << 23)
601 610#define MIPS_CONF3_PW (_ULCAST_(1) << 24)
611#define MIPS_CONF3_SC (_ULCAST_(1) << 25)
612#define MIPS_CONF3_BI (_ULCAST_(1) << 26)
613#define MIPS_CONF3_BP (_ULCAST_(1) << 27)
614#define MIPS_CONF3_MSA (_ULCAST_(1) << 28)
615#define MIPS_CONF3_CMGCR (_ULCAST_(1) << 29)
616#define MIPS_CONF3_BPG (_ULCAST_(1) << 30)
617
618#define MIPS_CONF4_MMUSIZEEXT_SHIFT (0)
602#define MIPS_CONF4_MMUSIZEEXT (_ULCAST_(255) << 0) 619#define MIPS_CONF4_MMUSIZEEXT (_ULCAST_(255) << 0)
620#define MIPS_CONF4_FTLBSETS_SHIFT (0)
621#define MIPS_CONF4_FTLBSETS_SHIFT (0)
622#define MIPS_CONF4_FTLBSETS (_ULCAST_(15) << MIPS_CONF4_FTLBSETS_SHIFT)
623#define MIPS_CONF4_FTLBWAYS_SHIFT (4)
624#define MIPS_CONF4_FTLBWAYS (_ULCAST_(15) << MIPS_CONF4_FTLBWAYS_SHIFT)
625#define MIPS_CONF4_FTLBPAGESIZE_SHIFT (8)
626/* bits 10:8 in FTLB-only configurations */
627#define MIPS_CONF4_FTLBPAGESIZE (_ULCAST_(7) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
628/* bits 12:8 in VTLB-FTLB only configurations */
629#define MIPS_CONF4_VFTLBPAGESIZE (_ULCAST_(31) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
603#define MIPS_CONF4_MMUEXTDEF (_ULCAST_(3) << 14) 630#define MIPS_CONF4_MMUEXTDEF (_ULCAST_(3) << 14)
604#define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14) 631#define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14)
632#define MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT (_ULCAST_(2) << 14)
633#define MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT (_ULCAST_(3) << 14)
634#define MIPS_CONF4_KSCREXIST (_ULCAST_(255) << 16)
635#define MIPS_CONF4_VTLBSIZEEXT_SHIFT (24)
636#define MIPS_CONF4_VTLBSIZEEXT (_ULCAST_(15) << MIPS_CONF4_VTLBSIZEEXT_SHIFT)
637#define MIPS_CONF4_AE (_ULCAST_(1) << 28)
638#define MIPS_CONF4_IE (_ULCAST_(3) << 29)
639#define MIPS_CONF4_TLBINV (_ULCAST_(2) << 29)
605 640
606#define MIPS_CONF5_NF (_ULCAST_(1) << 0) 641#define MIPS_CONF5_NF (_ULCAST_(1) << 0)
607#define MIPS_CONF5_UFR (_ULCAST_(1) << 2) 642#define MIPS_CONF5_UFR (_ULCAST_(1) << 2)
@@ -611,11 +646,15 @@
611#define MIPS_CONF5_K (_ULCAST_(1) << 30) 646#define MIPS_CONF5_K (_ULCAST_(1) << 30)
612 647
613#define MIPS_CONF6_SYND (_ULCAST_(1) << 13) 648#define MIPS_CONF6_SYND (_ULCAST_(1) << 13)
649/* proAptiv FTLB on/off bit */
650#define MIPS_CONF6_FTLBEN (_ULCAST_(1) << 15)
614 651
615#define MIPS_CONF7_WII (_ULCAST_(1) << 31) 652#define MIPS_CONF7_WII (_ULCAST_(1) << 31)
616 653
617#define MIPS_CONF7_RPS (_ULCAST_(1) << 2) 654#define MIPS_CONF7_RPS (_ULCAST_(1) << 2)
618 655
656/* EntryHI bit definition */
657#define MIPS_ENTRYHI_EHINV (_ULCAST_(1) << 10)
619 658
620/* 659/*
621 * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register. 660 * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
@@ -628,6 +667,26 @@
628#define MIPS_FPIR_L (_ULCAST_(1) << 21) 667#define MIPS_FPIR_L (_ULCAST_(1) << 21)
629#define MIPS_FPIR_F64 (_ULCAST_(1) << 22) 668#define MIPS_FPIR_F64 (_ULCAST_(1) << 22)
630 669
670/*
671 * Bits in the MIPS32 Memory Segmentation registers.
672 */
673#define MIPS_SEGCFG_PA_SHIFT 9
674#define MIPS_SEGCFG_PA (_ULCAST_(127) << MIPS_SEGCFG_PA_SHIFT)
675#define MIPS_SEGCFG_AM_SHIFT 4
676#define MIPS_SEGCFG_AM (_ULCAST_(7) << MIPS_SEGCFG_AM_SHIFT)
677#define MIPS_SEGCFG_EU_SHIFT 3
678#define MIPS_SEGCFG_EU (_ULCAST_(1) << MIPS_SEGCFG_EU_SHIFT)
679#define MIPS_SEGCFG_C_SHIFT 0
680#define MIPS_SEGCFG_C (_ULCAST_(7) << MIPS_SEGCFG_C_SHIFT)
681
682#define MIPS_SEGCFG_UUSK _ULCAST_(7)
683#define MIPS_SEGCFG_USK _ULCAST_(5)
684#define MIPS_SEGCFG_MUSUK _ULCAST_(4)
685#define MIPS_SEGCFG_MUSK _ULCAST_(3)
686#define MIPS_SEGCFG_MSK _ULCAST_(2)
687#define MIPS_SEGCFG_MK _ULCAST_(1)
688#define MIPS_SEGCFG_UK _ULCAST_(0)
689
631#ifndef __ASSEMBLY__ 690#ifndef __ASSEMBLY__
632 691
633/* 692/*
@@ -649,6 +708,19 @@ static inline int mm_insn_16bit(u16 insn)
649} 708}
650 709
651/* 710/*
711 * TLB Invalidate Flush
712 */
713static inline void tlbinvf(void)
714{
715 __asm__ __volatile__(
716 ".set push\n\t"
717 ".set noreorder\n\t"
718 ".word 0x42000004\n\t" /* tlbinvf */
719 ".set pop");
720}
721
722
723/*
652 * Functions to access the R10000 performance counters. These are basically 724 * Functions to access the R10000 performance counters. These are basically
653 * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit 725 * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit
654 * performance counter number encoded into bits 1 ... 5 of the instruction. 726 * performance counter number encoded into bits 1 ... 5 of the instruction.
@@ -1102,6 +1174,15 @@ do { \
1102#define read_c0_ebase() __read_32bit_c0_register($15, 1) 1174#define read_c0_ebase() __read_32bit_c0_register($15, 1)
1103#define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val) 1175#define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val)
1104 1176
1177/* MIPSR3 */
1178#define read_c0_segctl0() __read_32bit_c0_register($5, 2)
1179#define write_c0_segctl0(val) __write_32bit_c0_register($5, 2, val)
1180
1181#define read_c0_segctl1() __read_32bit_c0_register($5, 3)
1182#define write_c0_segctl1(val) __write_32bit_c0_register($5, 3, val)
1183
1184#define read_c0_segctl2() __read_32bit_c0_register($5, 4)
1185#define write_c0_segctl2(val) __write_32bit_c0_register($5, 4, val)
1105 1186
1106/* Cavium OCTEON (cnMIPS) */ 1187/* Cavium OCTEON (cnMIPS) */
1107#define read_c0_cvmcount() __read_ulong_c0_register($9, 6) 1188#define read_c0_cvmcount() __read_ulong_c0_register($9, 6)
diff --git a/arch/mips/include/asm/netlogic/common.h b/arch/mips/include/asm/netlogic/common.h
index bb68c3398c80..c281f03eb312 100644
--- a/arch/mips/include/asm/netlogic/common.h
+++ b/arch/mips/include/asm/netlogic/common.h
@@ -84,7 +84,6 @@ nlm_set_nmi_handler(void *handler)
84 */ 84 */
85void nlm_init_boot_cpu(void); 85void nlm_init_boot_cpu(void);
86unsigned int nlm_get_cpu_frequency(void); 86unsigned int nlm_get_cpu_frequency(void);
87void nlm_node_init(int node);
88extern struct plat_smp_ops nlm_smp_ops; 87extern struct plat_smp_ops nlm_smp_ops;
89extern char nlm_reset_entry[], nlm_reset_entry_end[]; 88extern char nlm_reset_entry[], nlm_reset_entry_end[];
90 89
@@ -94,26 +93,16 @@ extern struct dma_map_ops nlm_swiotlb_dma_ops;
94extern unsigned int nlm_threads_per_core; 93extern unsigned int nlm_threads_per_core;
95extern cpumask_t nlm_cpumask; 94extern cpumask_t nlm_cpumask;
96 95
97struct nlm_soc_info {
98 unsigned long coremask; /* cores enabled on the soc */
99 unsigned long ebase;
100 uint64_t irqmask;
101 uint64_t sysbase; /* only for XLP */
102 uint64_t picbase;
103 spinlock_t piclock;
104};
105
106#define nlm_get_node(i) (&nlm_nodes[i])
107#ifdef CONFIG_CPU_XLR
108#define nlm_current_node() (&nlm_nodes[0])
109#else
110#define nlm_current_node() (&nlm_nodes[nlm_nodeid()])
111#endif
112
113struct irq_data; 96struct irq_data;
114uint64_t nlm_pci_irqmask(int node); 97uint64_t nlm_pci_irqmask(int node);
98void nlm_setup_pic_irq(int node, int picirq, int irq, int irt);
115void nlm_set_pic_extra_ack(int node, int irq, void (*xack)(struct irq_data *)); 99void nlm_set_pic_extra_ack(int node, int irq, void (*xack)(struct irq_data *));
116 100
101#ifdef CONFIG_PCI_MSI
102void nlm_dispatch_msi(int node, int lirq);
103void nlm_dispatch_msix(int node, int msixirq);
104#endif
105
117/* 106/*
118 * The NR_IRQs is divided between nodes, each of them has a separate irq space 107 * The NR_IRQs is divided between nodes, each of them has a separate irq space
119 */ 108 */
@@ -122,7 +111,6 @@ static inline int nlm_irq_to_xirq(int node, int irq)
122 return node * NR_IRQS / NLM_NR_NODES + irq; 111 return node * NR_IRQS / NLM_NR_NODES + irq;
123} 112}
124 113
125extern struct nlm_soc_info nlm_nodes[NLM_NR_NODES];
126extern int nlm_cpu_ready[]; 114extern int nlm_cpu_ready[];
127#endif 115#endif
128#endif /* _NETLOGIC_COMMON_H_ */ 116#endif /* _NETLOGIC_COMMON_H_ */
diff --git a/arch/mips/include/asm/netlogic/mips-extns.h b/arch/mips/include/asm/netlogic/mips-extns.h
index f299d31d7c1a..de9aada6f4c1 100644
--- a/arch/mips/include/asm/netlogic/mips-extns.h
+++ b/arch/mips/include/asm/netlogic/mips-extns.h
@@ -146,7 +146,12 @@ static inline int hard_smp_processor_id(void)
146 146
147static inline int nlm_nodeid(void) 147static inline int nlm_nodeid(void)
148{ 148{
149 return (__read_32bit_c0_register($15, 1) >> 5) & 0x3; 149 uint32_t prid = read_c0_prid();
150
151 if ((prid & 0xff00) == PRID_IMP_NETLOGIC_XLP9XX)
152 return (__read_32bit_c0_register($15, 1) >> 7) & 0x7;
153 else
154 return (__read_32bit_c0_register($15, 1) >> 5) & 0x3;
150} 155}
151 156
152static inline unsigned int nlm_core_id(void) 157static inline unsigned int nlm_core_id(void)
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/bridge.h b/arch/mips/include/asm/netlogic/xlp-hal/bridge.h
index 4e8eacb9588a..3067f983495d 100644
--- a/arch/mips/include/asm/netlogic/xlp-hal/bridge.h
+++ b/arch/mips/include/asm/netlogic/xlp-hal/bridge.h
@@ -69,44 +69,9 @@
69#define BRIDGE_FLASH_LIMIT3 0x13 69#define BRIDGE_FLASH_LIMIT3 0x13
70 70
71#define BRIDGE_DRAM_BAR(i) (0x14 + (i)) 71#define BRIDGE_DRAM_BAR(i) (0x14 + (i))
72#define BRIDGE_DRAM_BAR0 0x14
73#define BRIDGE_DRAM_BAR1 0x15
74#define BRIDGE_DRAM_BAR2 0x16
75#define BRIDGE_DRAM_BAR3 0x17
76#define BRIDGE_DRAM_BAR4 0x18
77#define BRIDGE_DRAM_BAR5 0x19
78#define BRIDGE_DRAM_BAR6 0x1a
79#define BRIDGE_DRAM_BAR7 0x1b
80
81#define BRIDGE_DRAM_LIMIT(i) (0x1c + (i)) 72#define BRIDGE_DRAM_LIMIT(i) (0x1c + (i))
82#define BRIDGE_DRAM_LIMIT0 0x1c
83#define BRIDGE_DRAM_LIMIT1 0x1d
84#define BRIDGE_DRAM_LIMIT2 0x1e
85#define BRIDGE_DRAM_LIMIT3 0x1f
86#define BRIDGE_DRAM_LIMIT4 0x20
87#define BRIDGE_DRAM_LIMIT5 0x21
88#define BRIDGE_DRAM_LIMIT6 0x22
89#define BRIDGE_DRAM_LIMIT7 0x23
90
91#define BRIDGE_DRAM_NODE_TRANSLN(i) (0x24 + (i)) 73#define BRIDGE_DRAM_NODE_TRANSLN(i) (0x24 + (i))
92#define BRIDGE_DRAM_NODE_TRANSLN0 0x24
93#define BRIDGE_DRAM_NODE_TRANSLN1 0x25
94#define BRIDGE_DRAM_NODE_TRANSLN2 0x26
95#define BRIDGE_DRAM_NODE_TRANSLN3 0x27
96#define BRIDGE_DRAM_NODE_TRANSLN4 0x28
97#define BRIDGE_DRAM_NODE_TRANSLN5 0x29
98#define BRIDGE_DRAM_NODE_TRANSLN6 0x2a
99#define BRIDGE_DRAM_NODE_TRANSLN7 0x2b
100
101#define BRIDGE_DRAM_CHNL_TRANSLN(i) (0x2c + (i)) 74#define BRIDGE_DRAM_CHNL_TRANSLN(i) (0x2c + (i))
102#define BRIDGE_DRAM_CHNL_TRANSLN0 0x2c
103#define BRIDGE_DRAM_CHNL_TRANSLN1 0x2d
104#define BRIDGE_DRAM_CHNL_TRANSLN2 0x2e
105#define BRIDGE_DRAM_CHNL_TRANSLN3 0x2f
106#define BRIDGE_DRAM_CHNL_TRANSLN4 0x30
107#define BRIDGE_DRAM_CHNL_TRANSLN5 0x31
108#define BRIDGE_DRAM_CHNL_TRANSLN6 0x32
109#define BRIDGE_DRAM_CHNL_TRANSLN7 0x33
110 75
111#define BRIDGE_PCIEMEM_BASE0 0x34 76#define BRIDGE_PCIEMEM_BASE0 0x34
112#define BRIDGE_PCIEMEM_BASE1 0x35 77#define BRIDGE_PCIEMEM_BASE1 0x35
@@ -178,12 +143,42 @@
178#define BRIDGE_GIO_WEIGHT 0x2cb 143#define BRIDGE_GIO_WEIGHT 0x2cb
179#define BRIDGE_FLASH_WEIGHT 0x2cc 144#define BRIDGE_FLASH_WEIGHT 0x2cc
180 145
146/* FIXME verify */
147#define BRIDGE_9XX_FLASH_BAR(i) (0x11 + (i))
148#define BRIDGE_9XX_FLASH_BAR_LIMIT(i) (0x15 + (i))
149
150#define BRIDGE_9XX_DRAM_BAR(i) (0x19 + (i))
151#define BRIDGE_9XX_DRAM_LIMIT(i) (0x29 + (i))
152#define BRIDGE_9XX_DRAM_NODE_TRANSLN(i) (0x39 + (i))
153#define BRIDGE_9XX_DRAM_CHNL_TRANSLN(i) (0x49 + (i))
154
155#define BRIDGE_9XX_ADDRESS_ERROR0 0x9d
156#define BRIDGE_9XX_ADDRESS_ERROR1 0x9e
157#define BRIDGE_9XX_ADDRESS_ERROR2 0x9f
158
159#define BRIDGE_9XX_PCIEMEM_BASE0 0x59
160#define BRIDGE_9XX_PCIEMEM_BASE1 0x5a
161#define BRIDGE_9XX_PCIEMEM_BASE2 0x5b
162#define BRIDGE_9XX_PCIEMEM_BASE3 0x5c
163#define BRIDGE_9XX_PCIEMEM_LIMIT0 0x5d
164#define BRIDGE_9XX_PCIEMEM_LIMIT1 0x5e
165#define BRIDGE_9XX_PCIEMEM_LIMIT2 0x5f
166#define BRIDGE_9XX_PCIEMEM_LIMIT3 0x60
167#define BRIDGE_9XX_PCIEIO_BASE0 0x61
168#define BRIDGE_9XX_PCIEIO_BASE1 0x62
169#define BRIDGE_9XX_PCIEIO_BASE2 0x63
170#define BRIDGE_9XX_PCIEIO_BASE3 0x64
171#define BRIDGE_9XX_PCIEIO_LIMIT0 0x65
172#define BRIDGE_9XX_PCIEIO_LIMIT1 0x66
173#define BRIDGE_9XX_PCIEIO_LIMIT2 0x67
174#define BRIDGE_9XX_PCIEIO_LIMIT3 0x68
175
181#ifndef __ASSEMBLY__ 176#ifndef __ASSEMBLY__
182 177
183#define nlm_read_bridge_reg(b, r) nlm_read_reg(b, r) 178#define nlm_read_bridge_reg(b, r) nlm_read_reg(b, r)
184#define nlm_write_bridge_reg(b, r, v) nlm_write_reg(b, r, v) 179#define nlm_write_bridge_reg(b, r, v) nlm_write_reg(b, r, v)
185#define nlm_get_bridge_pcibase(node) \ 180#define nlm_get_bridge_pcibase(node) nlm_pcicfg_base(cpu_is_xlp9xx() ? \
186 nlm_pcicfg_base(XLP_IO_BRIDGE_OFFSET(node)) 181 XLP9XX_IO_BRIDGE_OFFSET(node) : XLP_IO_BRIDGE_OFFSET(node))
187#define nlm_get_bridge_regbase(node) \ 182#define nlm_get_bridge_regbase(node) \
188 (nlm_get_bridge_pcibase(node) + XLP_IO_PCI_HDRSZ) 183 (nlm_get_bridge_pcibase(node) + XLP_IO_PCI_HDRSZ)
189 184
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/iomap.h b/arch/mips/include/asm/netlogic/xlp-hal/iomap.h
index 55eee77adaca..1f23dfaa7167 100644
--- a/arch/mips/include/asm/netlogic/xlp-hal/iomap.h
+++ b/arch/mips/include/asm/netlogic/xlp-hal/iomap.h
@@ -48,8 +48,10 @@
48#define XLP_IO_SIZE (64 << 20) /* ECFG space size */ 48#define XLP_IO_SIZE (64 << 20) /* ECFG space size */
49#define XLP_IO_PCI_HDRSZ 0x100 49#define XLP_IO_PCI_HDRSZ 0x100
50#define XLP_IO_DEV(node, dev) ((dev) + (node) * 8) 50#define XLP_IO_DEV(node, dev) ((dev) + (node) * 8)
51#define XLP_HDR_OFFSET(node, bus, dev, fn) (((bus) << 20) | \ 51#define XLP_IO_PCI_OFFSET(b, d, f) (((b) << 20) | ((d) << 15) | ((f) << 12))
52 ((XLP_IO_DEV(node, dev)) << 15) | ((fn) << 12)) 52
53#define XLP_HDR_OFFSET(node, bus, dev, fn) \
54 XLP_IO_PCI_OFFSET(bus, XLP_IO_DEV(node, dev), fn)
53 55
54#define XLP_IO_BRIDGE_OFFSET(node) XLP_HDR_OFFSET(node, 0, 0, 0) 56#define XLP_IO_BRIDGE_OFFSET(node) XLP_HDR_OFFSET(node, 0, 0, 0)
55/* coherent inter chip */ 57/* coherent inter chip */
@@ -109,6 +111,36 @@
109#define XLP_IO_MMC_OFFSET(node, slot) \ 111#define XLP_IO_MMC_OFFSET(node, slot) \
110 ((XLP_IO_SD_OFFSET(node))+(slot*0x100)+XLP_IO_PCI_HDRSZ) 112 ((XLP_IO_SD_OFFSET(node))+(slot*0x100)+XLP_IO_PCI_HDRSZ)
111 113
114/* Things have changed drastically in XLP 9XX */
115#define XLP9XX_HDR_OFFSET(n, d, f) \
116 XLP_IO_PCI_OFFSET(xlp9xx_get_socbus(n), d, f)
117
118#define XLP9XX_IO_BRIDGE_OFFSET(node) XLP_IO_PCI_OFFSET(0, 0, node)
119#define XLP9XX_IO_PIC_OFFSET(node) XLP9XX_HDR_OFFSET(node, 2, 0)
120#define XLP9XX_IO_UART_OFFSET(node) XLP9XX_HDR_OFFSET(node, 2, 2)
121#define XLP9XX_IO_SYS_OFFSET(node) XLP9XX_HDR_OFFSET(node, 6, 0)
122#define XLP9XX_IO_FUSE_OFFSET(node) XLP9XX_HDR_OFFSET(node, 6, 1)
123#define XLP9XX_IO_JTAG_OFFSET(node) XLP9XX_HDR_OFFSET(node, 6, 4)
124
125#define XLP9XX_IO_PCIE_OFFSET(node, i) XLP9XX_HDR_OFFSET(node, 1, i)
126#define XLP9XX_IO_PCIE0_OFFSET(node) XLP9XX_HDR_OFFSET(node, 1, 0)
127#define XLP9XX_IO_PCIE2_OFFSET(node) XLP9XX_HDR_OFFSET(node, 1, 2)
128#define XLP9XX_IO_PCIE3_OFFSET(node) XLP9XX_HDR_OFFSET(node, 1, 3)
129
130/* XLP9xx USB block */
131#define XLP9XX_IO_USB_OFFSET(node, i) XLP9XX_HDR_OFFSET(node, 4, i)
132#define XLP9XX_IO_USB_XHCI0_OFFSET(node) XLP9XX_HDR_OFFSET(node, 4, 1)
133#define XLP9XX_IO_USB_XHCI1_OFFSET(node) XLP9XX_HDR_OFFSET(node, 4, 2)
134
135/* XLP9XX on-chip SATA controller */
136#define XLP9XX_IO_SATA_OFFSET(node) XLP9XX_HDR_OFFSET(node, 3, 2)
137
138#define XLP9XX_IO_NOR_OFFSET(node) XLP9XX_HDR_OFFSET(node, 7, 0)
139#define XLP9XX_IO_NAND_OFFSET(node) XLP9XX_HDR_OFFSET(node, 7, 1)
140#define XLP9XX_IO_SPI_OFFSET(node) XLP9XX_HDR_OFFSET(node, 7, 2)
141/* SD flash */
142#define XLP9XX_IO_MMCSD_OFFSET(node) XLP9XX_HDR_OFFSET(node, 7, 3)
143
112/* PCI config header register id's */ 144/* PCI config header register id's */
113#define XLP_PCI_CFGREG0 0x00 145#define XLP_PCI_CFGREG0 0x00
114#define XLP_PCI_CFGREG1 0x01 146#define XLP_PCI_CFGREG1 0x01
@@ -156,11 +188,23 @@
156#define PCI_DEVICE_ID_NLM_MMC 0x1018 188#define PCI_DEVICE_ID_NLM_MMC 0x1018
157#define PCI_DEVICE_ID_NLM_XHCI 0x101d 189#define PCI_DEVICE_ID_NLM_XHCI 0x101d
158 190
191#define PCI_DEVICE_ID_XLP9XX_SATA 0x901A
192#define PCI_DEVICE_ID_XLP9XX_XHCI 0x901D
193
159#ifndef __ASSEMBLY__ 194#ifndef __ASSEMBLY__
160 195
161#define nlm_read_pci_reg(b, r) nlm_read_reg(b, r) 196#define nlm_read_pci_reg(b, r) nlm_read_reg(b, r)
162#define nlm_write_pci_reg(b, r, v) nlm_write_reg(b, r, v) 197#define nlm_write_pci_reg(b, r, v) nlm_write_reg(b, r, v)
163 198
199static inline int xlp9xx_get_socbus(int node)
200{
201 uint64_t socbridge;
202
203 if (node == 0)
204 return 1;
205 socbridge = nlm_pcicfg_base(XLP9XX_IO_BRIDGE_OFFSET(node));
206 return (nlm_read_pci_reg(socbridge, 0x6) >> 8) & 0xff;
207}
164#endif /* !__ASSEMBLY */ 208#endif /* !__ASSEMBLY */
165 209
166#endif /* __NLM_HAL_IOMAP_H__ */ 210#endif /* __NLM_HAL_IOMAP_H__ */
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/pcibus.h b/arch/mips/include/asm/netlogic/xlp-hal/pcibus.h
index b559cb9f56ea..d4deb87ad069 100644
--- a/arch/mips/include/asm/netlogic/xlp-hal/pcibus.h
+++ b/arch/mips/include/asm/netlogic/xlp-hal/pcibus.h
@@ -52,25 +52,48 @@
52#define PCIE_BYTE_SWAP_MEM_LIM 0x248 52#define PCIE_BYTE_SWAP_MEM_LIM 0x248
53#define PCIE_BYTE_SWAP_IO_BASE 0x249 53#define PCIE_BYTE_SWAP_IO_BASE 0x249
54#define PCIE_BYTE_SWAP_IO_LIM 0x24A 54#define PCIE_BYTE_SWAP_IO_LIM 0x24A
55
56#define PCIE_BRIDGE_MSIX_ADDR_BASE 0x24F
57#define PCIE_BRIDGE_MSIX_ADDR_LIMIT 0x250
55#define PCIE_MSI_STATUS 0x25A 58#define PCIE_MSI_STATUS 0x25A
56#define PCIE_MSI_EN 0x25B 59#define PCIE_MSI_EN 0x25B
60#define PCIE_MSIX_STATUS 0x25D
61#define PCIE_INT_STATUS0 0x25F
62#define PCIE_INT_STATUS1 0x260
57#define PCIE_INT_EN0 0x261 63#define PCIE_INT_EN0 0x261
64#define PCIE_INT_EN1 0x262
58 65
59/* PCIE_MSI_EN */ 66/* XLP9XX has basic changes */
60#define PCIE_MSI_VECTOR_INT_EN 0xFFFFFFFF 67#define PCIE_9XX_BYTE_SWAP_MEM_BASE 0x25c
68#define PCIE_9XX_BYTE_SWAP_MEM_LIM 0x25d
69#define PCIE_9XX_BYTE_SWAP_IO_BASE 0x25e
70#define PCIE_9XX_BYTE_SWAP_IO_LIM 0x25f
61 71
62/* PCIE_INT_EN0 */ 72/* other */
63#define PCIE_MSI_INT_EN (1 << 9) 73#define PCIE_NLINKS 4
64 74
75/* MSI addresses */
76#define MSI_ADDR_BASE 0xfffee00000ULL
77#define MSI_ADDR_SZ 0x10000
78#define MSI_LINK_ADDR(n, l) (MSI_ADDR_BASE + \
79 (PCIE_NLINKS * (n) + (l)) * MSI_ADDR_SZ)
80#define MSIX_ADDR_BASE 0xfffef00000ULL
81#define MSIX_LINK_ADDR(n, l) (MSIX_ADDR_BASE + \
82 (PCIE_NLINKS * (n) + (l)) * MSI_ADDR_SZ)
65#ifndef __ASSEMBLY__ 83#ifndef __ASSEMBLY__
66 84
67#define nlm_read_pcie_reg(b, r) nlm_read_reg(b, r) 85#define nlm_read_pcie_reg(b, r) nlm_read_reg(b, r)
68#define nlm_write_pcie_reg(b, r, v) nlm_write_reg(b, r, v) 86#define nlm_write_pcie_reg(b, r, v) nlm_write_reg(b, r, v)
69#define nlm_get_pcie_base(node, inst) \ 87#define nlm_get_pcie_base(node, inst) nlm_pcicfg_base(cpu_is_xlp9xx() ? \
70 nlm_pcicfg_base(XLP_IO_PCIE_OFFSET(node, inst)) 88 XLP9XX_IO_PCIE_OFFSET(node, inst) : XLP_IO_PCIE_OFFSET(node, inst))
71#define nlm_get_pcie_regbase(node, inst) \ 89
72 (nlm_get_pcie_base(node, inst) + XLP_IO_PCI_HDRSZ) 90#ifdef CONFIG_PCI_MSI
91void xlp_init_node_msi_irqs(int node, int link);
92#else
93static inline void xlp_init_node_msi_irqs(int node, int link) {}
94#endif
95
96struct pci_dev *xlp_get_pcie_link(const struct pci_dev *dev);
73 97
74int xlp_pcie_link_irt(int link);
75#endif 98#endif
76#endif /* __NLM_HAL_PCIBUS_H__ */ 99#endif /* __NLM_HAL_PCIBUS_H__ */
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/pic.h b/arch/mips/include/asm/netlogic/xlp-hal/pic.h
index 105389b79f09..f10bf3bba58f 100644
--- a/arch/mips/include/asm/netlogic/xlp-hal/pic.h
+++ b/arch/mips/include/asm/netlogic/xlp-hal/pic.h
@@ -150,12 +150,19 @@
150#define PIC_IRT0 0x74 150#define PIC_IRT0 0x74
151#define PIC_IRT(i) (PIC_IRT0 + ((i) * 2)) 151#define PIC_IRT(i) (PIC_IRT0 + ((i) * 2))
152 152
153#define TIMER_CYCLES_MAXVAL 0xffffffffffffffffULL 153#define PIC_9XX_PENDING_0 0x6
154#define PIC_9XX_PENDING_1 0x8
155#define PIC_9XX_PENDING_2 0xa
156#define PIC_9XX_PENDING_3 0xc
157
158#define PIC_9XX_IRT0 0x1c0
159#define PIC_9XX_IRT(i) (PIC_9XX_IRT0 + ((i) * 2))
154 160
155/* 161/*
156 * IRT Map 162 * IRT Map
157 */ 163 */
158#define PIC_NUM_IRTS 160 164#define PIC_NUM_IRTS 160
165#define PIC_9XX_NUM_IRTS 256
159 166
160#define PIC_IRT_WD_0_INDEX 0 167#define PIC_IRT_WD_0_INDEX 0
161#define PIC_IRT_WD_1_INDEX 1 168#define PIC_IRT_WD_1_INDEX 1
@@ -193,14 +200,9 @@
193#define PIC_IRT_PCIE_LINK_INDEX(num) ((num) + PIC_IRT_PCIE_LINK_0_INDEX) 200#define PIC_IRT_PCIE_LINK_INDEX(num) ((num) + PIC_IRT_PCIE_LINK_0_INDEX)
194 201
195#define PIC_CLOCK_TIMER 7 202#define PIC_CLOCK_TIMER 7
196#define PIC_IRQ_BASE 8
197 203
198#if !defined(LOCORE) && !defined(__ASSEMBLY__) 204#if !defined(LOCORE) && !defined(__ASSEMBLY__)
199 205
200#define PIC_IRT_FIRST_IRQ (PIC_IRQ_BASE)
201#define PIC_IRT_LAST_IRQ 63
202#define PIC_IRQ_IS_IRT(irq) ((irq) >= PIC_IRT_FIRST_IRQ)
203
204/* 206/*
205 * Misc 207 * Misc
206 */ 208 */
@@ -210,30 +212,26 @@
210 212
211#define nlm_read_pic_reg(b, r) nlm_read_reg64(b, r) 213#define nlm_read_pic_reg(b, r) nlm_read_reg64(b, r)
212#define nlm_write_pic_reg(b, r, v) nlm_write_reg64(b, r, v) 214#define nlm_write_pic_reg(b, r, v) nlm_write_reg64(b, r, v)
213#define nlm_get_pic_pcibase(node) nlm_pcicfg_base(XLP_IO_PIC_OFFSET(node)) 215#define nlm_get_pic_pcibase(node) nlm_pcicfg_base(cpu_is_xlp9xx() ? \
216 XLP9XX_IO_PIC_OFFSET(node) : XLP_IO_PIC_OFFSET(node))
214#define nlm_get_pic_regbase(node) (nlm_get_pic_pcibase(node) + XLP_IO_PCI_HDRSZ) 217#define nlm_get_pic_regbase(node) (nlm_get_pic_pcibase(node) + XLP_IO_PCI_HDRSZ)
215 218
216/* We use PIC on node 0 as a timer */ 219/* We use PIC on node 0 as a timer */
217#define pic_timer_freq() nlm_get_pic_frequency(0) 220#define pic_timer_freq() nlm_get_pic_frequency(0)
218 221
219/* IRT and h/w interrupt routines */ 222/* IRT and h/w interrupt routines */
220static inline int
221nlm_pic_read_irt(uint64_t base, int irt_index)
222{
223 return nlm_read_pic_reg(base, PIC_IRT(irt_index));
224}
225
226static inline void 223static inline void
227nlm_set_irt_to_cpu(uint64_t base, int irt, int cpu) 224nlm_9xx_pic_write_irt(uint64_t base, int irt_num, int en, int nmi,
225 int sch, int vec, int dt, int db, int cpu)
228{ 226{
229 uint64_t val; 227 uint64_t val;
230 228
231 val = nlm_read_pic_reg(base, PIC_IRT(irt)); 229 val = (((uint64_t)en & 0x1) << 22) | ((nmi & 0x1) << 23) |
232 /* clear cpuset and mask */ 230 ((0 /*mc*/) << 20) | ((vec & 0x3f) << 24) |
233 val &= ~((0x7ull << 16) | 0xffff); 231 ((dt & 0x1) << 21) | (0 /*ptr*/ << 16) |
234 /* set DB, cpuset and cpumask */ 232 (cpu & 0x3ff);
235 val |= (1 << 19) | ((cpu >> 4) << 16) | (1 << (cpu & 0xf)); 233
236 nlm_write_pic_reg(base, PIC_IRT(irt), val); 234 nlm_write_pic_reg(base, PIC_9XX_IRT(irt_num), val);
237} 235}
238 236
239static inline void 237static inline void
@@ -254,9 +252,13 @@ static inline void
254nlm_pic_write_irt_direct(uint64_t base, int irt_num, int en, int nmi, 252nlm_pic_write_irt_direct(uint64_t base, int irt_num, int en, int nmi,
255 int sch, int vec, int cpu) 253 int sch, int vec, int cpu)
256{ 254{
257 nlm_pic_write_irt(base, irt_num, en, nmi, sch, vec, 1, 255 if (cpu_is_xlp9xx())
258 (cpu >> 4), /* thread group */ 256 nlm_9xx_pic_write_irt(base, irt_num, en, nmi, sch, vec,
259 1 << (cpu & 0xf)); /* thread mask */ 257 1, 0, cpu);
258 else
259 nlm_pic_write_irt(base, irt_num, en, nmi, sch, vec, 1,
260 (cpu >> 4), /* thread group */
261 1 << (cpu & 0xf)); /* thread mask */
260} 262}
261 263
262static inline uint64_t 264static inline uint64_t
@@ -298,8 +300,13 @@ nlm_pic_enable_irt(uint64_t base, int irt)
298{ 300{
299 uint64_t reg; 301 uint64_t reg;
300 302
301 reg = nlm_read_pic_reg(base, PIC_IRT(irt)); 303 if (cpu_is_xlp9xx()) {
302 nlm_write_pic_reg(base, PIC_IRT(irt), reg | (1u << 31)); 304 reg = nlm_read_pic_reg(base, PIC_9XX_IRT(irt));
305 nlm_write_pic_reg(base, PIC_9XX_IRT(irt), reg | (1 << 22));
306 } else {
307 reg = nlm_read_pic_reg(base, PIC_IRT(irt));
308 nlm_write_pic_reg(base, PIC_IRT(irt), reg | (1u << 31));
309 }
303} 310}
304 311
305static inline void 312static inline void
@@ -307,8 +314,15 @@ nlm_pic_disable_irt(uint64_t base, int irt)
307{ 314{
308 uint64_t reg; 315 uint64_t reg;
309 316
310 reg = nlm_read_pic_reg(base, PIC_IRT(irt)); 317 if (cpu_is_xlp9xx()) {
311 nlm_write_pic_reg(base, PIC_IRT(irt), reg & ~((uint64_t)1 << 31)); 318 reg = nlm_read_pic_reg(base, PIC_9XX_IRT(irt));
319 reg &= ~((uint64_t)1 << 22);
320 nlm_write_pic_reg(base, PIC_9XX_IRT(irt), reg);
321 } else {
322 reg = nlm_read_pic_reg(base, PIC_IRT(irt));
323 reg &= ~((uint64_t)1 << 31);
324 nlm_write_pic_reg(base, PIC_IRT(irt), reg);
325 }
312} 326}
313 327
314static inline void 328static inline void
@@ -316,8 +330,13 @@ nlm_pic_send_ipi(uint64_t base, int hwt, int irq, int nmi)
316{ 330{
317 uint64_t ipi; 331 uint64_t ipi;
318 332
319 ipi = ((uint64_t)nmi << 31) | (irq << 20); 333 if (cpu_is_xlp9xx())
320 ipi |= ((hwt >> 4) << 16) | (1 << (hwt & 0xf)); /* cpuset and mask */ 334 ipi = (nmi << 23) | (irq << 24) |
335 (0/*mcm*/ << 20) | (0/*ptr*/ << 16) | hwt;
336 else
337 ipi = ((uint64_t)nmi << 31) | (irq << 20) |
338 ((hwt >> 4) << 16) | (1 << (hwt & 0xf));
339
321 nlm_write_pic_reg(base, PIC_IPI_CTL, ipi); 340 nlm_write_pic_reg(base, PIC_IPI_CTL, ipi);
322} 341}
323 342
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/sys.h b/arch/mips/include/asm/netlogic/xlp-hal/sys.h
index fcf2833c16ca..d9b107ffca93 100644
--- a/arch/mips/include/asm/netlogic/xlp-hal/sys.h
+++ b/arch/mips/include/asm/netlogic/xlp-hal/sys.h
@@ -147,13 +147,29 @@
147#define SYS_SYS_PLL_MEM_REQ 0x2a3 147#define SYS_SYS_PLL_MEM_REQ 0x2a3
148#define SYS_PLL_MEM_STAT 0x2a4 148#define SYS_PLL_MEM_STAT 0x2a4
149 149
150/* Registers changed on 9XX */
151#define SYS_9XX_POWER_ON_RESET_CFG 0x00
152#define SYS_9XX_CHIP_RESET 0x01
153#define SYS_9XX_CPU_RESET 0x02
154#define SYS_9XX_CPU_NONCOHERENT_MODE 0x03
155
156/* XLP 9XX fuse block registers */
157#define FUSE_9XX_DEVCFG6 0xc6
158
150#ifndef __ASSEMBLY__ 159#ifndef __ASSEMBLY__
151 160
152#define nlm_read_sys_reg(b, r) nlm_read_reg(b, r) 161#define nlm_read_sys_reg(b, r) nlm_read_reg(b, r)
153#define nlm_write_sys_reg(b, r, v) nlm_write_reg(b, r, v) 162#define nlm_write_sys_reg(b, r, v) nlm_write_reg(b, r, v)
154#define nlm_get_sys_pcibase(node) nlm_pcicfg_base(XLP_IO_SYS_OFFSET(node)) 163#define nlm_get_sys_pcibase(node) nlm_pcicfg_base(cpu_is_xlp9xx() ? \
164 XLP9XX_IO_SYS_OFFSET(node) : XLP_IO_SYS_OFFSET(node))
155#define nlm_get_sys_regbase(node) (nlm_get_sys_pcibase(node) + XLP_IO_PCI_HDRSZ) 165#define nlm_get_sys_regbase(node) (nlm_get_sys_pcibase(node) + XLP_IO_PCI_HDRSZ)
156 166
167/* XLP9XX fuse block */
168#define nlm_get_fuse_pcibase(node) \
169 nlm_pcicfg_base(XLP9XX_IO_FUSE_OFFSET(node))
170#define nlm_get_fuse_regbase(node) \
171 (nlm_get_fuse_pcibase(node) + XLP_IO_PCI_HDRSZ)
172
157unsigned int nlm_get_pic_frequency(int node); 173unsigned int nlm_get_pic_frequency(int node);
158#endif 174#endif
159#endif 175#endif
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/uart.h b/arch/mips/include/asm/netlogic/xlp-hal/uart.h
index 86d16e1e6072..a6c54424dd95 100644
--- a/arch/mips/include/asm/netlogic/xlp-hal/uart.h
+++ b/arch/mips/include/asm/netlogic/xlp-hal/uart.h
@@ -94,7 +94,8 @@
94#define nlm_read_uart_reg(b, r) nlm_read_reg(b, r) 94#define nlm_read_uart_reg(b, r) nlm_read_reg(b, r)
95#define nlm_write_uart_reg(b, r, v) nlm_write_reg(b, r, v) 95#define nlm_write_uart_reg(b, r, v) nlm_write_reg(b, r, v)
96#define nlm_get_uart_pcibase(node, inst) \ 96#define nlm_get_uart_pcibase(node, inst) \
97 nlm_pcicfg_base(XLP_IO_UART_OFFSET(node, inst)) 97 nlm_pcicfg_base(cpu_is_xlp9xx() ? XLP9XX_IO_UART_OFFSET(node) : \
98 XLP_IO_UART_OFFSET(node, inst))
98#define nlm_get_uart_regbase(node, inst) \ 99#define nlm_get_uart_regbase(node, inst) \
99 (nlm_get_uart_pcibase(node, inst) + XLP_IO_PCI_HDRSZ) 100 (nlm_get_uart_pcibase(node, inst) + XLP_IO_PCI_HDRSZ)
100 101
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/xlp.h b/arch/mips/include/asm/netlogic/xlp-hal/xlp.h
index 470f2095b346..2b0c9599ebe5 100644
--- a/arch/mips/include/asm/netlogic/xlp-hal/xlp.h
+++ b/arch/mips/include/asm/netlogic/xlp-hal/xlp.h
@@ -37,10 +37,9 @@
37 37
38#define PIC_UART_0_IRQ 17 38#define PIC_UART_0_IRQ 17
39#define PIC_UART_1_IRQ 18 39#define PIC_UART_1_IRQ 18
40#define PIC_PCIE_LINK_0_IRQ 19 40
41#define PIC_PCIE_LINK_1_IRQ 20 41#define PIC_PCIE_LINK_LEGACY_IRQ_BASE 19
42#define PIC_PCIE_LINK_2_IRQ 21 42#define PIC_PCIE_LINK_LEGACY_IRQ(i) (19 + (i))
43#define PIC_PCIE_LINK_3_IRQ 22
44 43
45#define PIC_EHCI_0_IRQ 23 44#define PIC_EHCI_0_IRQ 23
46#define PIC_EHCI_1_IRQ 24 45#define PIC_EHCI_1_IRQ 24
@@ -51,6 +50,8 @@
51#define PIC_2XX_XHCI_0_IRQ 23 50#define PIC_2XX_XHCI_0_IRQ 23
52#define PIC_2XX_XHCI_1_IRQ 24 51#define PIC_2XX_XHCI_1_IRQ 24
53#define PIC_2XX_XHCI_2_IRQ 25 52#define PIC_2XX_XHCI_2_IRQ 25
53#define PIC_9XX_XHCI_0_IRQ 23
54#define PIC_9XX_XHCI_1_IRQ 24
54 55
55#define PIC_MMC_IRQ 29 56#define PIC_MMC_IRQ 29
56#define PIC_I2C_0_IRQ 30 57#define PIC_I2C_0_IRQ 30
@@ -58,6 +59,23 @@
58#define PIC_I2C_2_IRQ 32 59#define PIC_I2C_2_IRQ 32
59#define PIC_I2C_3_IRQ 33 60#define PIC_I2C_3_IRQ 33
60 61
62#define PIC_PCIE_LINK_MSI_IRQ_BASE 44 /* 44 - 47 MSI IRQ */
63#define PIC_PCIE_LINK_MSI_IRQ(i) (44 + (i))
64
65/* MSI-X with second link-level dispatch */
66#define PIC_PCIE_MSIX_IRQ_BASE 48 /* 48 - 51 MSI-X IRQ */
67#define PIC_PCIE_MSIX_IRQ(i) (48 + (i))
68
69#define NLM_MSIX_VEC_BASE 96 /* 96 - 127 - MSIX mapped */
70#define NLM_MSI_VEC_BASE 128 /* 128 -255 - MSI mapped */
71
72#define NLM_PIC_INDIRECT_VEC_BASE 512
73#define NLM_GPIO_VEC_BASE 768
74
75#define PIC_IRQ_BASE 8
76#define PIC_IRT_FIRST_IRQ PIC_IRQ_BASE
77#define PIC_IRT_LAST_IRQ 63
78
61#ifndef __ASSEMBLY__ 79#ifndef __ASSEMBLY__
62 80
63/* SMP support functions */ 81/* SMP support functions */
@@ -68,6 +86,9 @@ void xlp_mmu_init(void);
68void nlm_hal_init(void); 86void nlm_hal_init(void);
69int xlp_get_dram_map(int n, uint64_t *dram_map); 87int xlp_get_dram_map(int n, uint64_t *dram_map);
70 88
89struct pci_dev;
90int xlp_socdev_to_node(const struct pci_dev *dev);
91
71/* Device tree related */ 92/* Device tree related */
72void xlp_early_init_devtree(void); 93void xlp_early_init_devtree(void);
73void *xlp_dt_init(void *fdtp); 94void *xlp_dt_init(void *fdtp);
@@ -76,8 +97,15 @@ static inline int cpu_is_xlpii(void)
76{ 97{
77 int chip = read_c0_prid() & 0xff00; 98 int chip = read_c0_prid() & 0xff00;
78 99
79 return chip == PRID_IMP_NETLOGIC_XLP2XX; 100 return chip == PRID_IMP_NETLOGIC_XLP2XX ||
101 chip == PRID_IMP_NETLOGIC_XLP9XX;
80} 102}
81 103
104static inline int cpu_is_xlp9xx(void)
105{
106 int chip = read_c0_prid() & 0xff00;
107
108 return chip == PRID_IMP_NETLOGIC_XLP9XX;
109}
82#endif /* !__ASSEMBLY__ */ 110#endif /* !__ASSEMBLY__ */
83#endif /* _ASM_NLM_XLP_H */ 111#endif /* _ASM_NLM_XLP_H */
diff --git a/arch/mips/include/asm/netlogic/xlr/xlr.h b/arch/mips/include/asm/netlogic/xlr/xlr.h
index c1667e0c272a..ceb991ca8436 100644
--- a/arch/mips/include/asm/netlogic/xlr/xlr.h
+++ b/arch/mips/include/asm/netlogic/xlr/xlr.h
@@ -35,11 +35,6 @@
35#ifndef _ASM_NLM_XLR_H 35#ifndef _ASM_NLM_XLR_H
36#define _ASM_NLM_XLR_H 36#define _ASM_NLM_XLR_H
37 37
38/* Platform UART functions */
39struct uart_port;
40unsigned int nlm_xlr_uart_in(struct uart_port *, int);
41void nlm_xlr_uart_out(struct uart_port *, int, int);
42
43/* SMP helpers */ 38/* SMP helpers */
44void xlr_wakeup_secondary_cpus(void); 39void xlr_wakeup_secondary_cpus(void);
45 40
diff --git a/arch/mips/include/asm/octeon/cvmx-helper-board.h b/arch/mips/include/asm/octeon/cvmx-helper-board.h
index 41785dd0ddd0..893320375aef 100644
--- a/arch/mips/include/asm/octeon/cvmx-helper-board.h
+++ b/arch/mips/include/asm/octeon/cvmx-helper-board.h
@@ -36,6 +36,13 @@
36 36
37#include <asm/octeon/cvmx-helper.h> 37#include <asm/octeon/cvmx-helper.h>
38 38
39enum cvmx_helper_board_usb_clock_types {
40 USB_CLOCK_TYPE_REF_12,
41 USB_CLOCK_TYPE_REF_24,
42 USB_CLOCK_TYPE_REF_48,
43 USB_CLOCK_TYPE_CRYSTAL_12,
44};
45
39typedef enum { 46typedef enum {
40 set_phy_link_flags_autoneg = 0x1, 47 set_phy_link_flags_autoneg = 0x1,
41 set_phy_link_flags_flow_control_dont_touch = 0x0 << 1, 48 set_phy_link_flags_flow_control_dont_touch = 0x0 << 1,
@@ -154,4 +161,6 @@ extern int __cvmx_helper_board_interface_probe(int interface,
154 */ 161 */
155extern int __cvmx_helper_board_hardware_enable(int interface); 162extern int __cvmx_helper_board_hardware_enable(int interface);
156 163
164enum cvmx_helper_board_usb_clock_types __cvmx_helper_board_usb_get_clock_type(void);
165
157#endif /* __CVMX_HELPER_BOARD_H__ */ 166#endif /* __CVMX_HELPER_BOARD_H__ */
diff --git a/arch/mips/include/asm/page.h b/arch/mips/include/asm/page.h
index f6be4741f7e8..5e08bcc74897 100644
--- a/arch/mips/include/asm/page.h
+++ b/arch/mips/include/asm/page.h
@@ -11,6 +11,8 @@
11 11
12#include <spaces.h> 12#include <spaces.h>
13#include <linux/const.h> 13#include <linux/const.h>
14#include <linux/kernel.h>
15#include <asm/mipsregs.h>
14 16
15/* 17/*
16 * PAGE_SHIFT determines the page size 18 * PAGE_SHIFT determines the page size
@@ -33,6 +35,29 @@
33#define PAGE_SIZE (_AC(1,UL) << PAGE_SHIFT) 35#define PAGE_SIZE (_AC(1,UL) << PAGE_SHIFT)
34#define PAGE_MASK (~((1 << PAGE_SHIFT) - 1)) 36#define PAGE_MASK (~((1 << PAGE_SHIFT) - 1))
35 37
38/*
39 * This is used for calculating the real page sizes
40 * for FTLB or VTLB + FTLB confugrations.
41 */
42static inline unsigned int page_size_ftlb(unsigned int mmuextdef)
43{
44 switch (mmuextdef) {
45 case MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT:
46 if (PAGE_SIZE == (1 << 30))
47 return 5;
48 if (PAGE_SIZE == (1llu << 32))
49 return 6;
50 if (PAGE_SIZE > (256 << 10))
51 return 7; /* reserved */
52 /* fall through */
53 case MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT:
54 return (PAGE_SHIFT - 10) / 2;
55 default:
56 panic("Invalid FTLB configuration with Conf4_mmuextdef=%d value\n",
57 mmuextdef >> 14);
58 }
59}
60
36#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 61#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
37#define HPAGE_SHIFT (PAGE_SHIFT + PAGE_SHIFT - 3) 62#define HPAGE_SHIFT (PAGE_SHIFT + PAGE_SHIFT - 3)
38#define HPAGE_SIZE (_AC(1,UL) << HPAGE_SHIFT) 63#define HPAGE_SIZE (_AC(1,UL) << HPAGE_SHIFT)
diff --git a/arch/mips/include/asm/rtlx.h b/arch/mips/include/asm/rtlx.h
index 90985b61dbd9..c1020654876e 100644
--- a/arch/mips/include/asm/rtlx.h
+++ b/arch/mips/include/asm/rtlx.h
@@ -1,13 +1,18 @@
1/* 1/*
2 * Copyright (C) 2004, 2005 MIPS Technologies, Inc. All rights reserved. 2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
3 * 5 *
6 * Copyright (C) 2004, 2005 MIPS Technologies, Inc. All rights reserved.
7 * Copyright (C) 2013 Imagination Technologies Ltd.
4 */ 8 */
5
6#ifndef __ASM_RTLX_H_ 9#ifndef __ASM_RTLX_H_
7#define __ASM_RTLX_H_ 10#define __ASM_RTLX_H_
8 11
9#include <irq.h> 12#include <irq.h>
10 13
14#define RTLX_MODULE_NAME "rtlx"
15
11#define LX_NODE_BASE 10 16#define LX_NODE_BASE 10
12 17
13#define MIPS_CPU_RTLX_IRQ 0 18#define MIPS_CPU_RTLX_IRQ 0
@@ -15,18 +20,31 @@
15#define RTLX_VERSION 2 20#define RTLX_VERSION 2
16#define RTLX_xID 0x12345600 21#define RTLX_xID 0x12345600
17#define RTLX_ID (RTLX_xID | RTLX_VERSION) 22#define RTLX_ID (RTLX_xID | RTLX_VERSION)
23#define RTLX_BUFFER_SIZE 2048
18#define RTLX_CHANNELS 8 24#define RTLX_CHANNELS 8
19 25
20#define RTLX_CHANNEL_STDIO 0 26#define RTLX_CHANNEL_STDIO 0
21#define RTLX_CHANNEL_DBG 1 27#define RTLX_CHANNEL_DBG 1
22#define RTLX_CHANNEL_SYSIO 2 28#define RTLX_CHANNEL_SYSIO 2
23 29
24extern int rtlx_open(int index, int can_sleep); 30void rtlx_starting(int vpe);
25extern int rtlx_release(int index); 31void rtlx_stopping(int vpe);
26extern ssize_t rtlx_read(int index, void __user *buff, size_t count); 32
27extern ssize_t rtlx_write(int index, const void __user *buffer, size_t count); 33int rtlx_open(int index, int can_sleep);
28extern unsigned int rtlx_read_poll(int index, int can_sleep); 34int rtlx_release(int index);
29extern unsigned int rtlx_write_poll(int index); 35ssize_t rtlx_read(int index, void __user *buff, size_t count);
36ssize_t rtlx_write(int index, const void __user *buffer, size_t count);
37unsigned int rtlx_read_poll(int index, int can_sleep);
38unsigned int rtlx_write_poll(int index);
39
40int __init rtlx_module_init(void);
41void __exit rtlx_module_exit(void);
42
43void _interrupt_sp(void);
44
45extern struct vpe_notifications rtlx_notify;
46extern const struct file_operations rtlx_fops;
47extern void (*aprp_hook)(void);
30 48
31enum rtlx_state { 49enum rtlx_state {
32 RTLX_STATE_UNUSED = 0, 50 RTLX_STATE_UNUSED = 0,
@@ -35,10 +53,15 @@ enum rtlx_state {
35 RTLX_STATE_OPENED 53 RTLX_STATE_OPENED
36}; 54};
37 55
38#define RTLX_BUFFER_SIZE 2048 56extern struct chan_waitqueues {
57 wait_queue_head_t rt_queue;
58 wait_queue_head_t lx_queue;
59 atomic_t in_open;
60 struct mutex mutex;
61} channel_wqs[RTLX_CHANNELS];
39 62
40/* each channel supports read and write. 63/* each channel supports read and write.
41 linux (vpe0) reads lx_buffer and writes rt_buffer 64 linux (vpe0) reads lx_buffer and writes rt_buffer
42 SP (vpe1) reads rt_buffer and writes lx_buffer 65 SP (vpe1) reads rt_buffer and writes lx_buffer
43*/ 66*/
44struct rtlx_channel { 67struct rtlx_channel {
@@ -55,11 +78,11 @@ struct rtlx_channel {
55 char *lx_buffer; 78 char *lx_buffer;
56}; 79};
57 80
58struct rtlx_info { 81extern struct rtlx_info {
59 unsigned long id; 82 unsigned long id;
60 enum rtlx_state state; 83 enum rtlx_state state;
84 int ap_int_pending; /* Status of 0 or 1 for CONFIG_MIPS_CMP only */
61 85
62 struct rtlx_channel channel[RTLX_CHANNELS]; 86 struct rtlx_channel channel[RTLX_CHANNELS];
63}; 87} *rtlx;
64
65#endif /* __ASM_RTLX_H_ */ 88#endif /* __ASM_RTLX_H_ */
diff --git a/arch/mips/include/asm/switch_to.h b/arch/mips/include/asm/switch_to.h
index eb0af15ac656..278d45a09728 100644
--- a/arch/mips/include/asm/switch_to.h
+++ b/arch/mips/include/asm/switch_to.h
@@ -19,11 +19,19 @@
19 19
20struct task_struct; 20struct task_struct;
21 21
22/* 22/**
23 * switch_to(n) should switch tasks to task nr n, first 23 * resume - resume execution of a task
24 * checking that n isn't the current task, in which case it does nothing. 24 * @prev: The task previously executed.
25 * @next: The task to begin executing.
26 * @next_ti: task_thread_info(next).
27 * @usedfpu: Non-zero if prev's FP context should be saved.
28 *
29 * This function is used whilst scheduling to save the context of prev & load
30 * the context of next. Returns prev.
25 */ 31 */
26extern asmlinkage void *resume(void *last, void *next, void *next_ti, u32 __usedfpu); 32extern asmlinkage struct task_struct *resume(struct task_struct *prev,
33 struct task_struct *next, struct thread_info *next_ti,
34 u32 usedfpu);
27 35
28extern unsigned int ll_bit; 36extern unsigned int ll_bit;
29extern struct task_struct *ll_task; 37extern struct task_struct *ll_task;
diff --git a/arch/mips/include/asm/syscall.h b/arch/mips/include/asm/syscall.h
index 81c89132c59d..33e8dbfc1b63 100644
--- a/arch/mips/include/asm/syscall.h
+++ b/arch/mips/include/asm/syscall.h
@@ -29,7 +29,7 @@ static inline long syscall_get_nr(struct task_struct *task,
29static inline unsigned long mips_get_syscall_arg(unsigned long *arg, 29static inline unsigned long mips_get_syscall_arg(unsigned long *arg,
30 struct task_struct *task, struct pt_regs *regs, unsigned int n) 30 struct task_struct *task, struct pt_regs *regs, unsigned int n)
31{ 31{
32 unsigned long usp = regs->regs[29]; 32 unsigned long usp __maybe_unused = regs->regs[29];
33 33
34 switch (n) { 34 switch (n) {
35 case 0: case 1: case 2: case 3: 35 case 0: case 1: case 2: case 3:
diff --git a/arch/mips/include/asm/thread_info.h b/arch/mips/include/asm/thread_info.h
index 4f58ef6d0eed..24846f9053fe 100644
--- a/arch/mips/include/asm/thread_info.h
+++ b/arch/mips/include/asm/thread_info.h
@@ -110,11 +110,12 @@ static inline struct thread_info *current_thread_info(void)
110#define TIF_NOHZ 19 /* in adaptive nohz mode */ 110#define TIF_NOHZ 19 /* in adaptive nohz mode */
111#define TIF_FIXADE 20 /* Fix address errors in software */ 111#define TIF_FIXADE 20 /* Fix address errors in software */
112#define TIF_LOGADE 21 /* Log address errors to syslog */ 112#define TIF_LOGADE 21 /* Log address errors to syslog */
113#define TIF_32BIT_REGS 22 /* also implies 16/32 fprs */ 113#define TIF_32BIT_REGS 22 /* 32-bit general purpose registers */
114#define TIF_32BIT_ADDR 23 /* 32-bit address space (o32/n32) */ 114#define TIF_32BIT_ADDR 23 /* 32-bit address space (o32/n32) */
115#define TIF_FPUBOUND 24 /* thread bound to FPU-full CPU set */ 115#define TIF_FPUBOUND 24 /* thread bound to FPU-full CPU set */
116#define TIF_LOAD_WATCH 25 /* If set, load watch registers */ 116#define TIF_LOAD_WATCH 25 /* If set, load watch registers */
117#define TIF_SYSCALL_TRACEPOINT 26 /* syscall tracepoint instrumentation */ 117#define TIF_SYSCALL_TRACEPOINT 26 /* syscall tracepoint instrumentation */
118#define TIF_32BIT_FPREGS 27 /* 32-bit floating point registers */
118#define TIF_SYSCALL_TRACE 31 /* syscall trace active */ 119#define TIF_SYSCALL_TRACE 31 /* syscall trace active */
119 120
120#define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE) 121#define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE)
@@ -131,6 +132,7 @@ static inline struct thread_info *current_thread_info(void)
131#define _TIF_32BIT_ADDR (1<<TIF_32BIT_ADDR) 132#define _TIF_32BIT_ADDR (1<<TIF_32BIT_ADDR)
132#define _TIF_FPUBOUND (1<<TIF_FPUBOUND) 133#define _TIF_FPUBOUND (1<<TIF_FPUBOUND)
133#define _TIF_LOAD_WATCH (1<<TIF_LOAD_WATCH) 134#define _TIF_LOAD_WATCH (1<<TIF_LOAD_WATCH)
135#define _TIF_32BIT_FPREGS (1<<TIF_32BIT_FPREGS)
134#define _TIF_SYSCALL_TRACEPOINT (1<<TIF_SYSCALL_TRACEPOINT) 136#define _TIF_SYSCALL_TRACEPOINT (1<<TIF_SYSCALL_TRACEPOINT)
135 137
136#define _TIF_WORK_SYSCALL_ENTRY (_TIF_NOHZ | _TIF_SYSCALL_TRACE | \ 138#define _TIF_WORK_SYSCALL_ENTRY (_TIF_NOHZ | _TIF_SYSCALL_TRACE | \
diff --git a/arch/mips/include/asm/tlb.h b/arch/mips/include/asm/tlb.h
index c67842bc8ef3..4a2349302b55 100644
--- a/arch/mips/include/asm/tlb.h
+++ b/arch/mips/include/asm/tlb.h
@@ -18,6 +18,10 @@
18 */ 18 */
19#define tlb_flush(tlb) flush_tlb_mm((tlb)->mm) 19#define tlb_flush(tlb) flush_tlb_mm((tlb)->mm)
20 20
21#define UNIQUE_ENTRYHI(idx) \
22 ((CKSEG0 + ((idx) << (PAGE_SHIFT + 1))) | \
23 (cpu_has_tlbinv ? MIPS_ENTRYHI_EHINV : 0))
24
21#include <asm-generic/tlb.h> 25#include <asm-generic/tlb.h>
22 26
23#endif /* __ASM_TLB_H */ 27#endif /* __ASM_TLB_H */
diff --git a/arch/mips/include/asm/vpe.h b/arch/mips/include/asm/vpe.h
index 0880fe8809b1..7849f3978fea 100644
--- a/arch/mips/include/asm/vpe.h
+++ b/arch/mips/include/asm/vpe.h
@@ -1,24 +1,95 @@
1/* 1/*
2 * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved. 2 * This file is subject to the terms and conditions of the GNU General Public
3 * 3 * License. See the file "COPYING" in the main directory of this archive
4 * This program is free software; you can distribute it and/or modify it 4 * for more details.
5 * under the terms of the GNU General Public License (Version 2) as
6 * published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
11 * for more details.
12 *
13 * You should have received a copy of the GNU General Public License along
14 * with this program; if not, write to the Free Software Foundation, Inc.,
15 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
16 * 5 *
6 * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved.
7 * Copyright (C) 2013 Imagination Technologies Ltd.
17 */ 8 */
18
19#ifndef _ASM_VPE_H 9#ifndef _ASM_VPE_H
20#define _ASM_VPE_H 10#define _ASM_VPE_H
21 11
12#include <linux/init.h>
13#include <linux/list.h>
14#include <linux/smp.h>
15#include <linux/spinlock.h>
16
17#define VPE_MODULE_NAME "vpe"
18#define VPE_MODULE_MINOR 1
19
20/* grab the likely amount of memory we will need. */
21#ifdef CONFIG_MIPS_VPE_LOADER_TOM
22#define P_SIZE (2 * 1024 * 1024)
23#else
24/* add an overhead to the max kmalloc size for non-striped symbols/etc */
25#define P_SIZE (256 * 1024)
26#endif
27
28#define MAX_VPES 16
29#define VPE_PATH_MAX 256
30
31static inline int aprp_cpu_index(void)
32{
33#ifdef CONFIG_MIPS_CMP
34 return setup_max_cpus;
35#else
36 extern int tclimit;
37 return tclimit;
38#endif
39}
40
41enum vpe_state {
42 VPE_STATE_UNUSED = 0,
43 VPE_STATE_INUSE,
44 VPE_STATE_RUNNING
45};
46
47enum tc_state {
48 TC_STATE_UNUSED = 0,
49 TC_STATE_INUSE,
50 TC_STATE_RUNNING,
51 TC_STATE_DYNAMIC
52};
53
54struct vpe {
55 enum vpe_state state;
56
57 /* (device) minor associated with this vpe */
58 int minor;
59
60 /* elfloader stuff */
61 void *load_addr;
62 unsigned long len;
63 char *pbuffer;
64 unsigned long plen;
65 char cwd[VPE_PATH_MAX];
66
67 unsigned long __start;
68
69 /* tc's associated with this vpe */
70 struct list_head tc;
71
72 /* The list of vpe's */
73 struct list_head list;
74
75 /* shared symbol address */
76 void *shared_ptr;
77
78 /* the list of who wants to know when something major happens */
79 struct list_head notify;
80
81 unsigned int ntcs;
82};
83
84struct tc {
85 enum tc_state state;
86 int index;
87
88 struct vpe *pvpe; /* parent VPE */
89 struct list_head tc; /* The list of TC's with this VPE */
90 struct list_head list; /* The global list of tc's */
91};
92
22struct vpe_notifications { 93struct vpe_notifications {
23 void (*start)(int vpe); 94 void (*start)(int vpe);
24 void (*stop)(int vpe); 95 void (*stop)(int vpe);
@@ -26,10 +97,34 @@ struct vpe_notifications {
26 struct list_head list; 97 struct list_head list;
27}; 98};
28 99
100struct vpe_control {
101 spinlock_t vpe_list_lock;
102 struct list_head vpe_list; /* Virtual processing elements */
103 spinlock_t tc_list_lock;
104 struct list_head tc_list; /* Thread contexts */
105};
106
107extern unsigned long physical_memsize;
108extern struct vpe_control vpecontrol;
109extern const struct file_operations vpe_fops;
110
111int vpe_notify(int index, struct vpe_notifications *notify);
112
113void *vpe_get_shared(int index);
114char *vpe_getcwd(int index);
115
116struct vpe *get_vpe(int minor);
117struct tc *get_tc(int index);
118struct vpe *alloc_vpe(int minor);
119struct tc *alloc_tc(int index);
120void release_vpe(struct vpe *v);
29 121
30extern int vpe_notify(int index, struct vpe_notifications *notify); 122void *alloc_progmem(unsigned long len);
123void release_progmem(void *ptr);
31 124
32extern void *vpe_get_shared(int index); 125int __weak vpe_run(struct vpe *v);
33extern char *vpe_getcwd(int index); 126void cleanup_tc(struct tc *tc);
34 127
128int __init vpe_module_init(void);
129void __exit vpe_module_exit(void);
35#endif /* _ASM_VPE_H */ 130#endif /* _ASM_VPE_H */
diff --git a/arch/mips/include/uapi/asm/inst.h b/arch/mips/include/uapi/asm/inst.h
index e5a676e3d3c0..b39ba25b41cc 100644
--- a/arch/mips/include/uapi/asm/inst.h
+++ b/arch/mips/include/uapi/asm/inst.h
@@ -98,8 +98,9 @@ enum rt_op {
98 */ 98 */
99enum cop_op { 99enum cop_op {
100 mfc_op = 0x00, dmfc_op = 0x01, 100 mfc_op = 0x00, dmfc_op = 0x01,
101 cfc_op = 0x02, mtc_op = 0x04, 101 cfc_op = 0x02, mfhc_op = 0x03,
102 dmtc_op = 0x05, ctc_op = 0x06, 102 mtc_op = 0x04, dmtc_op = 0x05,
103 ctc_op = 0x06, mthc_op = 0x07,
103 bc_op = 0x08, cop_op = 0x10, 104 bc_op = 0x08, cop_op = 0x10,
104 copm_op = 0x18 105 copm_op = 0x18
105}; 106};
@@ -397,8 +398,10 @@ enum mm_32f_73_minor_op {
397 mm_movt1_op = 0xa5, 398 mm_movt1_op = 0xa5,
398 mm_ftruncw_op = 0xac, 399 mm_ftruncw_op = 0xac,
399 mm_fneg1_op = 0xad, 400 mm_fneg1_op = 0xad,
401 mm_mfhc1_op = 0xc0,
400 mm_froundl_op = 0xcc, 402 mm_froundl_op = 0xcc,
401 mm_fcvtd1_op = 0xcd, 403 mm_fcvtd1_op = 0xcd,
404 mm_mthc1_op = 0xe0,
402 mm_froundw_op = 0xec, 405 mm_froundw_op = 0xec,
403 mm_fcvts1_op = 0xed, 406 mm_fcvts1_op = 0xed,
404}; 407};
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-03 03:27:22 -0500