98 files changed, 1565 insertions, 1022 deletions
diff --git a/arch/mips/include/asm/asm-eva.h b/arch/mips/include/asm/asm-eva.h
index e41c56e375b1..1e38f0e1ea3e 100644
--- a/arch/mips/include/asm/asm-eva.h
+++ b/arch/mips/include/asm/asm-eva.h
@@ -11,6 +11,36 @@
 #define __ASM_ASM_EVA_H
 #ifndef __ASSEMBLY__
+/* Kernel variants */
+#define kernel_cache(op, base)          "cache " op ", " base "\n"
+#define kernel_ll(reg, addr)            "ll " reg ", " addr "\n"
+#define kernel_sc(reg, addr)            "sc " reg ", " addr "\n"
+#define kernel_lw(reg, addr)            "lw " reg ", " addr "\n"
+#define kernel_lwl(reg, addr)           "lwl " reg ", " addr "\n"
+#define kernel_lwr(reg, addr)           "lwr " reg ", " addr "\n"
+#define kernel_lh(reg, addr)            "lh " reg ", " addr "\n"
+#define kernel_lb(reg, addr)            "lb " reg ", " addr "\n"
+#define kernel_lbu(reg, addr)           "lbu " reg ", " addr "\n"
+#define kernel_sw(reg, addr)            "sw " reg ", " addr "\n"
+#define kernel_swl(reg, addr)           "swl " reg ", " addr "\n"
+#define kernel_swr(reg, addr)           "swr " reg ", " addr "\n"
+#define kernel_sh(reg, addr)            "sh " reg ", " addr "\n"
+#define kernel_sb(reg, addr)            "sb " reg ", " addr "\n"
+#ifdef CONFIG_32BIT
+/*
+ * No 'sd' or 'ld' instructions in 32-bit but the code will
+ * do the correct thing
+ */
+#define kernel_sd(reg, addr)            user_sw(reg, addr)
+#define kernel_ld(reg, addr)            user_lw(reg, addr)
+#else
+#define kernel_sd(reg, addr)            "sd " reg", " addr "\n"
+#define kernel_ld(reg, addr)            "ld " reg", " addr "\n"
+#endif /* CONFIG_32BIT */
 #ifdef CONFIG_EVA
 #define __BUILD_EVA_INSN(insn, reg, addr)                               \
@@ -41,37 +71,60 @@
 #else
-#define user_cache(op, base)            "cache " op ", " base "\n"
+#define user_cache(op, base)            kernel_cache(op, base)
-#define user_ll(reg, addr)              "ll " reg ", " addr "\n"
+#define user_ll(reg, addr)              kernel_ll(reg, addr)
-#define user_sc(reg, addr)              "sc " reg ", " addr "\n"
+#define user_sc(reg, addr)              kernel_sc(reg, addr)
-#define user_lw(reg, addr)              "lw " reg ", " addr "\n"
+#define user_lw(reg, addr)              kernel_lw(reg, addr)
-#define user_lwl(reg, addr)             "lwl " reg ", " addr "\n"
+#define user_lwl(reg, addr)             kernel_lwl(reg, addr)
-#define user_lwr(reg, addr)             "lwr " reg ", " addr "\n"
+#define user_lwr(reg, addr)             kernel_lwr(reg, addr)
-#define user_lh(reg, addr)              "lh " reg ", " addr "\n"
+#define user_lh(reg, addr)              kernel_lh(reg, addr)
-#define user_lb(reg, addr)              "lb " reg ", " addr "\n"
+#define user_lb(reg, addr)              kernel_lb(reg, addr)
-#define user_lbu(reg, addr)             "lbu " reg ", " addr "\n"
+#define user_lbu(reg, addr)             kernel_lbu(reg, addr)
-#define user_sw(reg, addr)              "sw " reg ", " addr "\n"
+#define user_sw(reg, addr)              kernel_sw(reg, addr)
-#define user_swl(reg, addr)             "swl " reg ", " addr "\n"
+#define user_swl(reg, addr)             kernel_swl(reg, addr)
-#define user_swr(reg, addr)             "swr " reg ", " addr "\n"
+#define user_swr(reg, addr)             kernel_swr(reg, addr)
-#define user_sh(reg, addr)              "sh " reg ", " addr "\n"
+#define user_sh(reg, addr)              kernel_sh(reg, addr)
-#define user_sb(reg, addr)              "sb " reg ", " addr "\n"
+#define user_sb(reg, addr)              kernel_sb(reg, addr)
 #ifdef CONFIG_32BIT
-/*
+#define user_sd(reg, addr)              kernel_sw(reg, addr)
- * No 'sd' or 'ld' instructions in 32-bit but the code will
+#define user_ld(reg, addr)              kernel_lw(reg, addr)
- * do the correct thing
- */
-#define user_sd(reg, addr)              user_sw(reg, addr)
-#define user_ld(reg, addr)              user_lw(reg, addr)
 #else
-#define user_sd(reg, addr)              "sd " reg", " addr "\n"
+#define user_sd(reg, addr)              kernel_sd(reg, addr)
-#define user_ld(reg, addr)              "ld " reg", " addr "\n"
+#define user_ld(reg, addr)              kernel_ld(reg, addr)
 #endif /* CONFIG_32BIT */
 #endif /* CONFIG_EVA */
 #else /* __ASSEMBLY__ */
+#define kernel_cache(op, base)          cache op, base
+#define kernel_ll(reg, addr)            ll reg, addr
+#define kernel_sc(reg, addr)            sc reg, addr
+#define kernel_lw(reg, addr)            lw reg, addr
+#define kernel_lwl(reg, addr)           lwl reg, addr
+#define kernel_lwr(reg, addr)           lwr reg, addr
+#define kernel_lh(reg, addr)            lh reg, addr
+#define kernel_lb(reg, addr)            lb reg, addr
+#define kernel_lbu(reg, addr)           lbu reg, addr
+#define kernel_sw(reg, addr)            sw reg, addr
+#define kernel_swl(reg, addr)           swl reg, addr
+#define kernel_swr(reg, addr)           swr reg, addr
+#define kernel_sh(reg, addr)            sh reg, addr
+#define kernel_sb(reg, addr)            sb reg, addr
+#ifdef CONFIG_32BIT
+/*
+ * No 'sd' or 'ld' instructions in 32-bit but the code will
+ * do the correct thing
+ */
+#define kernel_sd(reg, addr)            user_sw(reg, addr)
+#define kernel_ld(reg, addr)            user_lw(reg, addr)
+#else
+#define kernel_sd(reg, addr)            sd reg, addr
+#define kernel_ld(reg, addr)            ld reg, addr
+#endif /* CONFIG_32BIT */
 #ifdef CONFIG_EVA
 #define __BUILD_EVA_INSN(insn, reg, addr)                       \
@@ -101,31 +154,27 @@
 #define user_sd(reg, addr)              user_sw(reg, addr)
 #else
-#define user_cache(op, base)            cache op, base
+#define user_cache(op, base)            kernel_cache(op, base)
-#define user_ll(reg, addr)              ll reg, addr
+#define user_ll(reg, addr)              kernel_ll(reg, addr)
-#define user_sc(reg, addr)              sc reg, addr
+#define user_sc(reg, addr)              kernel_sc(reg, addr)
-#define user_lw(reg, addr)              lw reg, addr
+#define user_lw(reg, addr)              kernel_lw(reg, addr)
-#define user_lwl(reg, addr)             lwl reg, addr
+#define user_lwl(reg, addr)             kernel_lwl(reg, addr)
-#define user_lwr(reg, addr)             lwr reg, addr
+#define user_lwr(reg, addr)             kernel_lwr(reg, addr)
-#define user_lh(reg, addr)              lh reg, addr
+#define user_lh(reg, addr)              kernel_lh(reg, addr)
-#define user_lb(reg, addr)              lb reg, addr
+#define user_lb(reg, addr)              kernel_lb(reg, addr)
-#define user_lbu(reg, addr)             lbu reg, addr
+#define user_lbu(reg, addr)             kernel_lbu(reg, addr)
-#define user_sw(reg, addr)              sw reg, addr
+#define user_sw(reg, addr)              kernel_sw(reg, addr)
-#define user_swl(reg, addr)             swl reg, addr
+#define user_swl(reg, addr)             kernel_swl(reg, addr)
-#define user_swr(reg, addr)             swr reg, addr
+#define user_swr(reg, addr)             kernel_swr(reg, addr)
-#define user_sh(reg, addr)              sh reg, addr
+#define user_sh(reg, addr)              kernel_sh(reg, addr)
-#define user_sb(reg, addr)              sb reg, addr
+#define user_sb(reg, addr)              kernel_sb(reg, addr)
 #ifdef CONFIG_32BIT
-/*
+#define user_sd(reg, addr)              kernel_sw(reg, addr)
- * No 'sd' or 'ld' instructions in 32-bit but the code will
+#define user_ld(reg, addr)              kernel_lw(reg, addr)
- * do the correct thing
- */
-#define user_sd(reg, addr)              user_sw(reg, addr)
-#define user_ld(reg, addr)              user_lw(reg, addr)
 #else
-#define user_sd(reg, addr)              sd reg, addr
+#define user_sd(reg, addr)              kernel_sd(reg, addr)
-#define user_ld(reg, addr)              ld reg, addr
+#define user_ld(reg, addr)              kernel_sd(reg, addr)
 #endif /* CONFIG_32BIT */
 #endif /* CONFIG_EVA */
diff --git a/arch/mips/include/asm/asmmacro-32.h b/arch/mips/include/asm/asmmacro-32.h
index 80386470d3a4..0ef39ad0f2d4 100644
--- a/arch/mips/include/asm/asmmacro-32.h
+++ b/arch/mips/include/asm/asmmacro-32.h
@@ -16,38 +16,22 @@
        .set push
        SET_HARDFLOAT
        cfc1    \tmp,  fcr31
-        swc1    $f0,  THREAD_FPR0(\thread)
+        s.d     $f0,  THREAD_FPR0(\thread)
-        swc1    $f1,  THREAD_FPR1(\thread)
+        s.d     $f2,  THREAD_FPR2(\thread)
-        swc1    $f2,  THREAD_FPR2(\thread)
+        s.d     $f4,  THREAD_FPR4(\thread)
-        swc1    $f3,  THREAD_FPR3(\thread)
+        s.d     $f6,  THREAD_FPR6(\thread)
-        swc1    $f4,  THREAD_FPR4(\thread)
+        s.d     $f8,  THREAD_FPR8(\thread)
-        swc1    $f5,  THREAD_FPR5(\thread)
+        s.d     $f10, THREAD_FPR10(\thread)
-        swc1    $f6,  THREAD_FPR6(\thread)
+        s.d     $f12, THREAD_FPR12(\thread)
-        swc1    $f7,  THREAD_FPR7(\thread)
+        s.d     $f14, THREAD_FPR14(\thread)
-        swc1    $f8,  THREAD_FPR8(\thread)
+        s.d     $f16, THREAD_FPR16(\thread)
-        swc1    $f9,  THREAD_FPR9(\thread)
+        s.d     $f18, THREAD_FPR18(\thread)
-        swc1    $f10, THREAD_FPR10(\thread)
+        s.d     $f20, THREAD_FPR20(\thread)
-        swc1    $f11, THREAD_FPR11(\thread)
+        s.d     $f22, THREAD_FPR22(\thread)
-        swc1    $f12, THREAD_FPR12(\thread)
+        s.d     $f24, THREAD_FPR24(\thread)
-        swc1    $f13, THREAD_FPR13(\thread)
+        s.d     $f26, THREAD_FPR26(\thread)
-        swc1    $f14, THREAD_FPR14(\thread)
+        s.d     $f28, THREAD_FPR28(\thread)
-        swc1    $f15, THREAD_FPR15(\thread)
+        s.d     $f30, THREAD_FPR30(\thread)
-        swc1    $f16, THREAD_FPR16(\thread)
-        swc1    $f17, THREAD_FPR17(\thread)
-        swc1    $f18, THREAD_FPR18(\thread)
-        swc1    $f19, THREAD_FPR19(\thread)
-        swc1    $f20, THREAD_FPR20(\thread)
-        swc1    $f21, THREAD_FPR21(\thread)
-        swc1    $f22, THREAD_FPR22(\thread)
-        swc1    $f23, THREAD_FPR23(\thread)
-        swc1    $f24, THREAD_FPR24(\thread)
-        swc1    $f25, THREAD_FPR25(\thread)
-        swc1    $f26, THREAD_FPR26(\thread)
-        swc1    $f27, THREAD_FPR27(\thread)
-        swc1    $f28, THREAD_FPR28(\thread)
-        swc1    $f29, THREAD_FPR29(\thread)
-        swc1    $f30, THREAD_FPR30(\thread)
-        swc1    $f31, THREAD_FPR31(\thread)
        sw      \tmp, THREAD_FCR31(\thread)
        .set pop
        .endm
@@ -56,38 +40,22 @@
        .set push
        SET_HARDFLOAT
        lw      \tmp, THREAD_FCR31(\thread)
-        lwc1    $f0,  THREAD_FPR0(\thread)
+        l.d     $f0,  THREAD_FPR0(\thread)
-        lwc1    $f1,  THREAD_FPR1(\thread)
+        l.d     $f2,  THREAD_FPR2(\thread)
-        lwc1    $f2,  THREAD_FPR2(\thread)
+        l.d     $f4,  THREAD_FPR4(\thread)
-        lwc1    $f3,  THREAD_FPR3(\thread)
+        l.d     $f6,  THREAD_FPR6(\thread)
-        lwc1    $f4,  THREAD_FPR4(\thread)
+        l.d     $f8,  THREAD_FPR8(\thread)
-        lwc1    $f5,  THREAD_FPR5(\thread)
+        l.d     $f10, THREAD_FPR10(\thread)
-        lwc1    $f6,  THREAD_FPR6(\thread)
+        l.d     $f12, THREAD_FPR12(\thread)
-        lwc1    $f7,  THREAD_FPR7(\thread)
+        l.d     $f14, THREAD_FPR14(\thread)
-        lwc1    $f8,  THREAD_FPR8(\thread)
+        l.d     $f16, THREAD_FPR16(\thread)
-        lwc1    $f9,  THREAD_FPR9(\thread)
+        l.d     $f18, THREAD_FPR18(\thread)
-        lwc1    $f10, THREAD_FPR10(\thread)
+        l.d     $f20, THREAD_FPR20(\thread)
-        lwc1    $f11, THREAD_FPR11(\thread)
+        l.d     $f22, THREAD_FPR22(\thread)
-        lwc1    $f12, THREAD_FPR12(\thread)
+        l.d     $f24, THREAD_FPR24(\thread)
-        lwc1    $f13, THREAD_FPR13(\thread)
+        l.d     $f26, THREAD_FPR26(\thread)
-        lwc1    $f14, THREAD_FPR14(\thread)
+        l.d     $f28, THREAD_FPR28(\thread)
-        lwc1    $f15, THREAD_FPR15(\thread)
+        l.d     $f30, THREAD_FPR30(\thread)
-        lwc1    $f16, THREAD_FPR16(\thread)
-        lwc1    $f17, THREAD_FPR17(\thread)
-        lwc1    $f18, THREAD_FPR18(\thread)
-        lwc1    $f19, THREAD_FPR19(\thread)
-        lwc1    $f20, THREAD_FPR20(\thread)
-        lwc1    $f21, THREAD_FPR21(\thread)
-        lwc1    $f22, THREAD_FPR22(\thread)
-        lwc1    $f23, THREAD_FPR23(\thread)
-        lwc1    $f24, THREAD_FPR24(\thread)
-        lwc1    $f25, THREAD_FPR25(\thread)
-        lwc1    $f26, THREAD_FPR26(\thread)
-        lwc1    $f27, THREAD_FPR27(\thread)
-        lwc1    $f28, THREAD_FPR28(\thread)
-        lwc1    $f29, THREAD_FPR29(\thread)
-        lwc1    $f30, THREAD_FPR30(\thread)
-        lwc1    $f31, THREAD_FPR31(\thread)
        ctc1    \tmp, fcr31
        .set pop
        .endm
diff --git a/arch/mips/include/asm/bitops.h b/arch/mips/include/asm/bitops.h
index 9f935f6aa996..0cf29bd5dc5c 100644
--- a/arch/mips/include/asm/bitops.h
+++ b/arch/mips/include/asm/bitops.h
@@ -481,7 +481,7 @@ static inline unsigned long __fls(unsigned long word)
 {
        int num;
-        if (BITS_PER_LONG == 32 &&
+        if (BITS_PER_LONG == 32 && !__builtin_constant_p(word) &&
            __builtin_constant_p(cpu_has_clo_clz) && cpu_has_clo_clz) {
                __asm__(
                "       .set    push                                    \n"
@@ -494,7 +494,7 @@ static inline unsigned long __fls(unsigned long word)
                return 31 - num;
        }
-        if (BITS_PER_LONG == 64 &&
+        if (BITS_PER_LONG == 64 && !__builtin_constant_p(word) &&
            __builtin_constant_p(cpu_has_mips64) && cpu_has_mips64) {
                __asm__(
                "       .set    push                                    \n"
@@ -559,7 +559,8 @@ static inline int fls(int x)
 {
        int r;
-        if (__builtin_constant_p(cpu_has_clo_clz) && cpu_has_clo_clz) {
+        if (!__builtin_constant_p(x) &&
+            __builtin_constant_p(cpu_has_clo_clz) && cpu_has_clo_clz) {
                __asm__(
                "       .set    push                                    \n"
                "       .set    "MIPS_ISA_LEVEL"                        \n"
diff --git a/arch/mips/include/asm/bmips.h b/arch/mips/include/asm/bmips.h
index 30939b02e3ff..6d25ad33ec78 100644
--- a/arch/mips/include/asm/bmips.h
+++ b/arch/mips/include/asm/bmips.h
@@ -122,6 +122,22 @@ static inline void bmips_write_zscm_reg(unsigned int offset, unsigned long data)
        barrier();
 }
+static inline void bmips_post_dma_flush(struct device *dev)
+{
+        void __iomem *cbr = BMIPS_GET_CBR();
+        u32 cfg;
+        if (boot_cpu_type() != CPU_BMIPS3300 &&
+            boot_cpu_type() != CPU_BMIPS4350 &&
+            boot_cpu_type() != CPU_BMIPS4380)
+                return;
+        /* Flush stale data out of the readahead cache */
+        cfg = __raw_readl(cbr + BMIPS_RAC_CONFIG);
+        __raw_writel(cfg | 0x100, cbr + BMIPS_RAC_CONFIG);
+        __raw_readl(cbr + BMIPS_RAC_CONFIG);
+}
 #endif /* !defined(__ASSEMBLY__) */
 #endif /* _ASM_BMIPS_H */
diff --git a/arch/mips/include/asm/cacheflush.h b/arch/mips/include/asm/cacheflush.h
index e08381a37f8b..723229f4cf27 100644
--- a/arch/mips/include/asm/cacheflush.h
+++ b/arch/mips/include/asm/cacheflush.h
@@ -29,6 +29,20 @@
 *  - flush_icache_all() flush the entire instruction cache
 *  - flush_data_cache_page() flushes a page from the data cache
 */
+ /*
+ * This flag is used to indicate that the page pointed to by a pte
+ * is dirty and requires cleaning before returning it to the user.
+ */
+#define PG_dcache_dirty                 PG_arch_1
+#define Page_dcache_dirty(page)         \
+        test_bit(PG_dcache_dirty, &(page)->flags)
+#define SetPageDcacheDirty(page)        \
+        set_bit(PG_dcache_dirty, &(page)->flags)
+#define ClearPageDcacheDirty(page)      \
+        clear_bit(PG_dcache_dirty, &(page)->flags)
 extern void (*flush_cache_all)(void);
 extern void (*__flush_cache_all)(void);
 extern void (*flush_cache_mm)(struct mm_struct *mm);
@@ -37,13 +51,15 @@ extern void (*flush_cache_range)(struct vm_area_struct *vma,
        unsigned long start, unsigned long end);
 extern void (*flush_cache_page)(struct vm_area_struct *vma, unsigned long page, unsigned long pfn);
 extern void __flush_dcache_page(struct page *page);
+extern void __flush_icache_page(struct vm_area_struct *vma, struct page *page);
 #define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
 static inline void flush_dcache_page(struct page *page)
 {
-        if (cpu_has_dc_aliases || !cpu_has_ic_fills_f_dc)
+        if (cpu_has_dc_aliases)
                __flush_dcache_page(page);
+        else if (!cpu_has_ic_fills_f_dc)
+                SetPageDcacheDirty(page);
 }
 #define flush_dcache_mmap_lock(mapping)         do { } while (0)
@@ -61,6 +77,11 @@ static inline void flush_anon_page(struct vm_area_struct *vma,
 static inline void flush_icache_page(struct vm_area_struct *vma,
        struct page *page)
 {
+        if (!cpu_has_ic_fills_f_dc && (vma->vm_flags & VM_EXEC) &&
+            Page_dcache_dirty(page)) {
+                __flush_icache_page(vma, page);
+                ClearPageDcacheDirty(page);
+        }
 }
 extern void (*flush_icache_range)(unsigned long start, unsigned long end);
@@ -95,19 +116,6 @@ extern void (*flush_icache_all)(void);
 extern void (*local_flush_data_cache_page)(void * addr);
 extern void (*flush_data_cache_page)(unsigned long addr);
-/*
- * This flag is used to indicate that the page pointed to by a pte
- * is dirty and requires cleaning before returning it to the user.
- */
-#define PG_dcache_dirty                 PG_arch_1
-#define Page_dcache_dirty(page)         \
-        test_bit(PG_dcache_dirty, &(page)->flags)
-#define SetPageDcacheDirty(page)        \
-        set_bit(PG_dcache_dirty, &(page)->flags)
-#define ClearPageDcacheDirty(page)      \
-        clear_bit(PG_dcache_dirty, &(page)->flags)
 /* Run kernel code uncached, useful for cache probing functions. */
 unsigned long run_uncached(void *func);
diff --git a/arch/mips/include/asm/cdmm.h b/arch/mips/include/asm/cdmm.h
new file mode 100644
index 000000000000..16e22ce9719f
--- /dev/null
+++ b/arch/mips/include/asm/cdmm.h
@@ -0,0 +1,98 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2014 Imagination Technologies Ltd.
+ */
+#ifndef __ASM_CDMM_H
+#define __ASM_CDMM_H
+#include <linux/device.h>
+#include <linux/mod_devicetable.h>
+/**
+ * struct mips_cdmm_device - Represents a single device on a CDMM bus.
+ * @dev:        Driver model device object.
+ * @cpu:        CPU which can access this device.
+ * @res:        MMIO resource.
+ * @type:       Device type identifier.
+ * @rev:        Device revision number.
+ */
+struct mips_cdmm_device {
+        struct device           dev;
+        unsigned int            cpu;
+        struct resource         res;
+        unsigned int            type;
+        unsigned int            rev;
+};
+/**
+ * struct mips_cdmm_driver - Represents a driver for a CDMM device.
+ * @drv:        Driver model driver object.
+ * @probe       Callback for probing newly discovered devices.
+ * @remove:     Callback to remove the device.
+ * @shutdown:   Callback on system shutdown.
+ * @cpu_down:   Callback when the parent CPU is going down.
+ *              Any CPU pinned threads/timers should be disabled.
+ * @cpu_up:     Callback when the parent CPU is coming back up again.
+ *              CPU pinned threads/timers can be restarted.
+ * @id_table:   Table for CDMM IDs to match against.
+ */
+struct mips_cdmm_driver {
+        struct device_driver    drv;
+        int                     (*probe)(struct mips_cdmm_device *);
+        int                     (*remove)(struct mips_cdmm_device *);
+        void                    (*shutdown)(struct mips_cdmm_device *);
+        int                     (*cpu_down)(struct mips_cdmm_device *);
+        int                     (*cpu_up)(struct mips_cdmm_device *);
+        const struct mips_cdmm_device_id *id_table;
+};
+/**
+ * mips_cdmm_phys_base() - Choose a physical base address for CDMM region.
+ *
+ * Picking a suitable physical address at which to map the CDMM region is
+ * platform specific, so this weak function can be defined by platform code to
+ * pick a suitable value if none is configured by the bootloader.
+ *
+ * This address must be 32kB aligned, and the region occupies a maximum of 32kB
+ * of physical address space which must not be used for anything else.
+ *
+ * Returns:     Physical base address for CDMM region, or 0 on failure.
+ */
+phys_addr_t __weak mips_cdmm_phys_base(void);
+extern struct bus_type mips_cdmm_bustype;
+void __iomem *mips_cdmm_early_probe(unsigned int dev_type);
+#define to_mips_cdmm_device(d)  container_of(d, struct mips_cdmm_device, dev)
+#define mips_cdmm_get_drvdata(d)        dev_get_drvdata(&d->dev)
+#define mips_cdmm_set_drvdata(d, p)     dev_set_drvdata(&d->dev, p)
+int mips_cdmm_driver_register(struct mips_cdmm_driver *);
+void mips_cdmm_driver_unregister(struct mips_cdmm_driver *);
+/*
+ * module_mips_cdmm_driver() - Helper macro for drivers that don't do
+ * anything special in module init/exit.  This eliminates a lot of
+ * boilerplate.  Each module may only use this macro once, and
+ * calling it replaces module_init() and module_exit()
+ */
+#define module_mips_cdmm_driver(__mips_cdmm_driver) \
+        module_driver(__mips_cdmm_driver, mips_cdmm_driver_register, \
+                        mips_cdmm_driver_unregister)
+/* drivers/tty/mips_ejtag_fdc.c */
+#ifdef CONFIG_MIPS_EJTAG_FDC_EARLYCON
+int setup_early_fdc_console(void);
+#else
+static inline int setup_early_fdc_console(void)
+{
+        return -ENODEV;
+}
+#endif
+#endif /* __ASM_CDMM_H */
diff --git a/arch/mips/include/asm/cevt-r4k.h b/arch/mips/include/asm/cevt-r4k.h
index 65f9bdd02f1f..f0edf6fcd002 100644
--- a/arch/mips/include/asm/cevt-r4k.h
+++ b/arch/mips/include/asm/cevt-r4k.h
@@ -27,23 +27,4 @@ irqreturn_t c0_compare_interrupt(int, void *);
 extern struct irqaction c0_compare_irqaction;
 extern int cp0_timer_irq_installed;
-/*
- * Possibly handle a performance counter interrupt.
- * Return true if the timer interrupt should not be checked
- */
-static inline int handle_perf_irq(int r2)
-{
-        /*
-         * The performance counter overflow interrupt may be shared with the
-         * timer interrupt (cp0_perfcount_irq < 0). If it is and a
-         * performance counter has overflowed (perf_irq() == IRQ_HANDLED)
-         * and we can't reliably determine if a counter interrupt has also
-         * happened (!r2) then don't check for a timer interrupt.
-         */
-        return (cp0_perfcount_irq < 0) &&
-                perf_irq() == IRQ_HANDLED &&
-                !r2;
-}
 #endif /* __ASM_CEVT_R4K_H */
diff --git a/arch/mips/include/asm/checksum.h b/arch/mips/include/asm/checksum.h
index 5c585c5c1c3e..3ceacde5eb6e 100644
--- a/arch/mips/include/asm/checksum.h
+++ b/arch/mips/include/asm/checksum.h
@@ -218,6 +218,8 @@ static __inline__ __sum16 csum_ipv6_magic(const struct in6_addr *saddr,
                                          __u32 len, unsigned short proto,
                                          __wsum sum)
 {
+        __wsum tmp;
        __asm__(
        "       .set    push            # csum_ipv6_magic\n"
        "       .set    noreorder       \n"
@@ -270,9 +272,9 @@ static __inline__ __sum16 csum_ipv6_magic(const struct in6_addr *saddr,
        "       addu    %0, $1          # Add final carry\n"
        "       .set    pop"
-        : "=r" (sum), "=r" (proto)
+        : "=&r" (sum), "=&r" (tmp)
        : "r" (saddr), "r" (daddr),
-          "0" (htonl(len)), "1" (htonl(proto)), "r" (sum));
+          "0" (htonl(len)), "r" (htonl(proto)), "r" (sum));
        return csum_fold(sum);
 }
diff --git a/arch/mips/include/asm/cmpxchg.h b/arch/mips/include/asm/cmpxchg.h
index d0a2a68ca600..412f945f1f5e 100644
--- a/arch/mips/include/asm/cmpxchg.h
+++ b/arch/mips/include/asm/cmpxchg.h
@@ -229,21 +229,22 @@ extern void __cmpxchg_called_with_bad_pointer(void);
 #define cmpxchg(ptr, old, new)          __cmpxchg(ptr, old, new, smp_mb__before_llsc(), smp_llsc_mb())
 #define cmpxchg_local(ptr, old, new)    __cmpxchg(ptr, old, new, , )
-#define cmpxchg64(ptr, o, n)                                            \
+#ifdef CONFIG_64BIT
+#define cmpxchg64_local(ptr, o, n)                                      \
  ({                                                                    \
        BUILD_BUG_ON(sizeof(*(ptr)) != 8);                              \
-        cmpxchg((ptr), (o), (n));                                       \
+        cmpxchg_local((ptr), (o), (n));                                 \
  })
-#ifdef CONFIG_64BIT
+#define cmpxchg64(ptr, o, n)                                            \
-#define cmpxchg64_local(ptr, o, n)                                      \
  ({                                                                    \
        BUILD_BUG_ON(sizeof(*(ptr)) != 8);                              \
-        cmpxchg_local((ptr), (o), (n));                                 \
+        cmpxchg((ptr), (o), (n));                                       \
  })
 #else
 #include <asm-generic/cmpxchg-local.h>
 #define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
+#define cmpxchg64(ptr, o, n) cmpxchg64_local((ptr), (o), (n))
 #endif
 #endif /* __ASM_CMPXCHG_H */
diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
index 0d8208de9a3f..5aeaf19c26b0 100644
--- a/arch/mips/include/asm/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
@@ -68,6 +68,7 @@
 #ifndef cpu_has_octeon_cache
 #define cpu_has_octeon_cache    0
 #endif
+/* Don't override `cpu_has_fpu' to 1 or the "nofpu" option won't work.  */
 #ifndef cpu_has_fpu
 #define cpu_has_fpu             (current_cpu_data.options & MIPS_CPU_FPU)
 #define raw_cpu_has_fpu         (raw_current_cpu_data.options & MIPS_CPU_FPU)
@@ -139,6 +140,9 @@
 # endif
 #endif
+#ifndef cpu_has_xpa
+#define cpu_has_xpa             (cpu_data[0].options & MIPS_CPU_XPA)
+#endif
 #ifndef cpu_has_vtag_icache
 #define cpu_has_vtag_icache     (cpu_data[0].icache.flags & MIPS_CACHE_VTAG)
 #endif
@@ -220,8 +224,11 @@
 #define cpu_has_mips_4_5_r      (cpu_has_mips_4 | cpu_has_mips_5_r)
 #define cpu_has_mips_5_r        (cpu_has_mips_5 | cpu_has_mips_r)
-#define cpu_has_mips_4_5_r2_r6  (cpu_has_mips_4_5 | cpu_has_mips_r2 | \
+#define cpu_has_mips_3_4_5_64_r2_r6                                     \
-                                 cpu_has_mips_r6)
+                                (cpu_has_mips_3 | cpu_has_mips_4_5_64_r2_r6)
+#define cpu_has_mips_4_5_64_r2_r6                                       \
+                                (cpu_has_mips_4_5 | cpu_has_mips64r1 |  \
+                                 cpu_has_mips_r2 | cpu_has_mips_r6)
 #define cpu_has_mips32  (cpu_has_mips32r1 | cpu_has_mips32r2 | cpu_has_mips32r6)
 #define cpu_has_mips64  (cpu_has_mips64r1 | cpu_has_mips64r2 | cpu_has_mips64r6)
@@ -235,8 +242,39 @@
 /* MIPSR2 and MIPSR6 have a lot of similarities */
 #define cpu_has_mips_r2_r6      (cpu_has_mips_r2 | cpu_has_mips_r6)
+/*
+ * cpu_has_mips_r2_exec_hazard - return if IHB is required on current processor
+ *
+ * Returns non-zero value if the current processor implementation requires
+ * an IHB instruction to deal with an instruction hazard as per MIPS R2
+ * architecture specification, zero otherwise.
+ */
 #ifndef cpu_has_mips_r2_exec_hazard
-#define cpu_has_mips_r2_exec_hazard (cpu_has_mips_r2 | cpu_has_mips_r6)
+#define cpu_has_mips_r2_exec_hazard                                     \
+({                                                                      \
+        int __res;                                                      \
+                                                                        \
+        switch (current_cpu_type()) {                                   \
+        case CPU_M14KC:                                                 \
+        case CPU_74K:                                                   \
+        case CPU_1074K:                                                 \
+        case CPU_PROAPTIV:                                              \
+        case CPU_P5600:                                                 \
+        case CPU_M5150:                                                 \
+        case CPU_QEMU_GENERIC:                                          \
+        case CPU_CAVIUM_OCTEON:                                         \
+        case CPU_CAVIUM_OCTEON_PLUS:                                    \
+        case CPU_CAVIUM_OCTEON2:                                        \
+        case CPU_CAVIUM_OCTEON3:                                        \
+                __res = 0;                                              \
+                break;                                                  \
+                                                                        \
+        default:                                                        \
+                __res = 1;                                              \
+        }                                                               \
+                                                                        \
+        __res;                                                          \
+})
 #endif
 /*
@@ -366,4 +404,8 @@
 # define cpu_has_fre            (cpu_data[0].options & MIPS_CPU_FRE)
 #endif
+#ifndef cpu_has_cdmm
+# define cpu_has_cdmm           (cpu_data[0].options & MIPS_CPU_CDMM)
+#endif
 #endif /* __ASM_CPU_FEATURES_H */
diff --git a/arch/mips/include/asm/cpu-info.h b/arch/mips/include/asm/cpu-info.h
index c3f4f2d2e108..e7dc785a91ca 100644
--- a/arch/mips/include/asm/cpu-info.h
+++ b/arch/mips/include/asm/cpu-info.h
@@ -49,6 +49,8 @@ struct cpuinfo_mips {
        unsigned int            udelay_val;
        unsigned int            processor_id;
        unsigned int            fpu_id;
+        unsigned int            fpu_csr31;
+        unsigned int            fpu_msk31;
        unsigned int            msa_id;
        unsigned int            cputype;
        int                     isa_level;
diff --git a/arch/mips/include/asm/cpu-type.h b/arch/mips/include/asm/cpu-type.h
index 8245875f8b33..33f3cab9e689 100644
--- a/arch/mips/include/asm/cpu-type.h
+++ b/arch/mips/include/asm/cpu-type.h
@@ -157,6 +157,7 @@ static inline int __pure __get_cpu_type(const int cpu_type)
        case CPU_R10000:
        case CPU_R12000:
        case CPU_R14000:
+        case CPU_R16000:
 #endif
 #ifdef CONFIG_SYS_HAS_CPU_RM7000
        case CPU_RM7000:
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index 15687234d70a..e3adca1d0b99 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -67,7 +67,7 @@
 #define PRID_IMP_R4300          0x0b00
 #define PRID_IMP_VR41XX         0x0c00
 #define PRID_IMP_R12000         0x0e00
-#define PRID_IMP_R14000         0x0f00
+#define PRID_IMP_R14000         0x0f00          /* R14K && R16K */
 #define PRID_IMP_R8000          0x1000
 #define PRID_IMP_PR4450         0x1200
 #define PRID_IMP_R4600          0x2000
@@ -284,8 +284,8 @@ enum cpu_type_enum {
        CPU_R4000PC, CPU_R4000SC, CPU_R4000MC, CPU_R4200, CPU_R4300, CPU_R4310,
        CPU_R4400PC, CPU_R4400SC, CPU_R4400MC, CPU_R4600, CPU_R4640, CPU_R4650,
        CPU_R4700, CPU_R5000, CPU_R5500, CPU_NEVADA, CPU_R5432, CPU_R10000,
-        CPU_R12000, CPU_R14000, CPU_VR41XX, CPU_VR4111, CPU_VR4121, CPU_VR4122,
+        CPU_R12000, CPU_R14000, CPU_R16000, CPU_VR41XX, CPU_VR4111, CPU_VR4121,
-        CPU_VR4131, CPU_VR4133, CPU_VR4181, CPU_VR4181A, CPU_RM7000,
+        CPU_VR4122, CPU_VR4131, CPU_VR4133, CPU_VR4181, CPU_VR4181A, CPU_RM7000,
        CPU_SR71000, CPU_TX49XX,
        /*
@@ -377,6 +377,8 @@ enum cpu_type_enum {
 #define MIPS_CPU_MAAR           0x400000000ull /* MAAR(I) registers are present */
 #define MIPS_CPU_FRE            0x800000000ull /* FRE & UFE bits implemented */
 #define MIPS_CPU_RW_LLB         0x1000000000ull /* LLADDR/LLB writes are allowed */
+#define MIPS_CPU_XPA            0x2000000000ull /* CPU supports Extended Physical Addressing */
+#define MIPS_CPU_CDMM           0x4000000000ull /* CPU has Common Device Memory Map */
 /*
 * CPU ASE encodings
diff --git a/arch/mips/include/asm/dma-mapping.h b/arch/mips/include/asm/dma-mapping.h
index 06412aa9e3fb..fd1b4a150759 100644
--- a/arch/mips/include/asm/dma-mapping.h
+++ b/arch/mips/include/asm/dma-mapping.h
@@ -23,7 +23,7 @@ static inline struct dma_map_ops *get_dma_ops(struct device *dev)
 static inline bool dma_capable(struct device *dev, dma_addr_t addr, size_t size)
 {
        if (!dev->dma_mask)
-                return 0;
+                return false;
        return addr + size <= *dev->dma_mask;
 }
diff --git a/arch/mips/include/asm/elf.h b/arch/mips/include/asm/elf.h
index 31d747d46a23..a594d8ed9698 100644
--- a/arch/mips/include/asm/elf.h
+++ b/arch/mips/include/asm/elf.h
@@ -11,6 +11,9 @@
 #include <linux/fs.h>
 #include <uapi/linux/elf.h>
+#include <asm/cpu-info.h>
+#include <asm/current.h>
 /* ELF header e_flags defines. */
 /* MIPS architecture level. */
 #define EF_MIPS_ARCH_1          0x00000000      /* -mips1 code.  */
@@ -294,9 +297,14 @@ do {									\
        if (personality(current->personality) != PER_LINUX)             \
                set_personality(PER_LINUX);                             \
                                                                        \
+        clear_thread_flag(TIF_HYBRID_FPREGS);                           \
+        set_thread_flag(TIF_32BIT_FPREGS);                              \
+                                                                        \
        mips_set_personality_fp(state);                                 \
                                                                        \
        current->thread.abi = &mips_abi;                                \
+                                                                        \
+        current->thread.fpu.fcr31 = current_cpu_data.fpu_csr31;         \
 } while (0)
 #endif /* CONFIG_32BIT */
@@ -319,6 +327,8 @@ do {									\
        do {                                                            \
                set_thread_flag(TIF_32BIT_REGS);                        \
                set_thread_flag(TIF_32BIT_ADDR);                        \
+                clear_thread_flag(TIF_HYBRID_FPREGS);                   \
+                set_thread_flag(TIF_32BIT_FPREGS);                      \
                                                                        \
                mips_set_personality_fp(state);                         \
                                                                        \
@@ -356,6 +366,8 @@ do {									\
        else                                                            \
                current->thread.abi = &mips_abi;                        \
                                                                        \
+        current->thread.fpu.fcr31 = current_cpu_data.fpu_csr31;         \
+                                                                        \
        p = personality(current->personality);                          \
        if (p != PER_LINUX32 && p != PER_LINUX)                         \
                set_personality(PER_LINUX);                             \
diff --git a/arch/mips/include/asm/fpu.h b/arch/mips/include/asm/fpu.h
index b104ad9d655f..084780b355aa 100644
--- a/arch/mips/include/asm/fpu.h
+++ b/arch/mips/include/asm/fpu.h
@@ -30,7 +30,7 @@
 struct sigcontext;
 struct sigcontext32;
-extern void _init_fpu(void);
+extern void _init_fpu(unsigned int);
 extern void _save_fp(struct task_struct *);
 extern void _restore_fp(struct task_struct *);
@@ -188,6 +188,7 @@ static inline void lose_fpu(int save)
 static inline int init_fpu(void)
 {
+        unsigned int fcr31 = current->thread.fpu.fcr31;
        int ret = 0;
        if (cpu_has_fpu) {
@@ -198,7 +199,7 @@ static inline int init_fpu(void)
                        return ret;
                if (!cpu_has_fre) {
-                        _init_fpu();
+                        _init_fpu(fcr31);
                        return 0;
                }
@@ -212,7 +213,7 @@ static inline int init_fpu(void)
                config5 = clear_c0_config5(MIPS_CONF5_FRE);
                enable_fpu_hazard();
-                _init_fpu();
+                _init_fpu(fcr31);
                /* Restore FRE */
                write_c0_config5(config5);
diff --git a/arch/mips/include/asm/fpu_emulator.h b/arch/mips/include/asm/fpu_emulator.h
index 3ee347713307..2f021cdfba4f 100644
--- a/arch/mips/include/asm/fpu_emulator.h
+++ b/arch/mips/include/asm/fpu_emulator.h
@@ -44,6 +44,7 @@ struct mips_fpu_emulator_stats {
        unsigned long ieee754_overflow;
        unsigned long ieee754_zerodiv;
        unsigned long ieee754_invalidop;
+        unsigned long ds_emul;
 };
 DECLARE_PER_CPU(struct mips_fpu_emulator_stats, fpuemustats);
@@ -65,7 +66,8 @@ extern int do_dsemulret(struct pt_regs *xcp);
 extern int fpu_emulator_cop1Handler(struct pt_regs *xcp,
                                    struct mips_fpu_struct *ctx, int has_fpu,
                                    void *__user *fault_addr);
-int process_fpemu_return(int sig, void __user *fault_addr);
+int process_fpemu_return(int sig, void __user *fault_addr,
+                         unsigned long fcr31);
 int mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
                     unsigned long *contpc);
@@ -86,8 +88,6 @@ static inline void fpu_emulator_init_fpu(void)
        struct task_struct *t = current;
        int i;
-        t->thread.fpu.fcr31 = 0;
        for (i = 0; i < 32; i++)
                set_fpr64(&t->thread.fpu.fpr[i], 0, SIGNALLING_NAN);
 }
diff --git a/arch/mips/include/asm/irq.h b/arch/mips/include/asm/irq.h
index 5a4e1bb8fb1b..f0db99f8defe 100644
--- a/arch/mips/include/asm/irq.h
+++ b/arch/mips/include/asm/irq.h
@@ -47,6 +47,9 @@ extern void free_irqno(unsigned int irq);
 extern int cp0_compare_irq;
 extern int cp0_compare_irq_shift;
 extern int cp0_perfcount_irq;
+extern int cp0_fdc_irq;
+extern int __weak get_c0_fdc_int(void);
 void arch_trigger_all_cpu_backtrace(bool);
 #define arch_trigger_all_cpu_backtrace arch_trigger_all_cpu_backtrace
diff --git a/arch/mips/include/asm/mach-ar7/war.h b/arch/mips/include/asm/mach-ar7/war.h
deleted file mode 100644
index 99071e50faab..000000000000
--- a/arch/mips/include/asm/mach-ar7/war.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
- */
-#ifndef __ASM_MIPS_MACH_AR7_WAR_H
-#define __ASM_MIPS_MACH_AR7_WAR_H
-#define R4600_V1_INDEX_ICACHEOP_WAR     0
-#define R4600_V1_HIT_CACHEOP_WAR        0
-#define R4600_V2_HIT_CACHEOP_WAR        0
-#define R5432_CP0_INTERRUPT_WAR         0
-#define BCM1250_M3_WAR                  0
-#define SIBYTE_1956_WAR                 0
-#define MIPS4K_ICACHE_REFILL_WAR        0
-#define MIPS_CACHE_SYNC_WAR             0
-#define TX49XX_ICACHE_INDEX_INV_WAR     0
-#define ICACHE_REFILLS_WORKAROUND_WAR   0
-#define R10000_LLSC_WAR                 0
-#define MIPS34K_MISSED_ITLB_WAR         0
-#endif /* __ASM_MIPS_MACH_AR7_WAR_H */
diff --git a/arch/mips/include/asm/mach-ath25/dma-coherence.h b/arch/mips/include/asm/mach-ath25/dma-coherence.h
index d8009c93a465..d5defdde32db 100644
--- a/arch/mips/include/asm/mach-ath25/dma-coherence.h
+++ b/arch/mips/include/asm/mach-ath25/dma-coherence.h
@@ -59,16 +59,6 @@ static inline int plat_dma_supported(struct device *dev, u64 mask)
        return 1;
 }
-static inline void plat_extra_sync_for_device(struct device *dev)
-{
-}
-static inline int plat_dma_mapping_error(struct device *dev,
-                                         dma_addr_t dma_addr)
-{
-        return 0;
-}
 static inline int plat_device_is_coherent(struct device *dev)
 {
 #ifdef CONFIG_DMA_COHERENT
@@ -79,4 +69,8 @@ static inline int plat_device_is_coherent(struct device *dev)
 #endif
 }
+static inline void plat_post_dma_flush(struct device *dev)
+{
+}
 #endif /* __ASM_MACH_ATH25_DMA_COHERENCE_H */
diff --git a/arch/mips/include/asm/mach-ath25/war.h b/arch/mips/include/asm/mach-ath25/war.h
deleted file mode 100644
index e3a5250ebd67..000000000000
--- a/arch/mips/include/asm/mach-ath25/war.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2008 Felix Fietkau <nbd@openwrt.org>
- */
-#ifndef __ASM_MACH_ATH25_WAR_H
-#define __ASM_MACH_ATH25_WAR_H
-#define R4600_V1_INDEX_ICACHEOP_WAR     0
-#define R4600_V1_HIT_CACHEOP_WAR        0
-#define R4600_V2_HIT_CACHEOP_WAR        0
-#define R5432_CP0_INTERRUPT_WAR         0
-#define BCM1250_M3_WAR                  0
-#define SIBYTE_1956_WAR                 0
-#define MIPS4K_ICACHE_REFILL_WAR        0
-#define MIPS_CACHE_SYNC_WAR             0
-#define TX49XX_ICACHE_INDEX_INV_WAR     0
-#define RM9000_CDEX_SMP_WAR             0
-#define ICACHE_REFILLS_WORKAROUND_WAR   0
-#define R10000_LLSC_WAR                 0
-#define MIPS34K_MISSED_ITLB_WAR         0
-#endif /* __ASM_MACH_ATH25_WAR_H */
diff --git a/arch/mips/include/asm/mach-ath79/war.h b/arch/mips/include/asm/mach-ath79/war.h
deleted file mode 100644
index 0bb30905fd5b..000000000000
--- a/arch/mips/include/asm/mach-ath79/war.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
- */
-#ifndef __ASM_MACH_ATH79_WAR_H
-#define __ASM_MACH_ATH79_WAR_H
-#define R4600_V1_INDEX_ICACHEOP_WAR     0
-#define R4600_V1_HIT_CACHEOP_WAR        0
-#define R4600_V2_HIT_CACHEOP_WAR        0
-#define R5432_CP0_INTERRUPT_WAR         0
-#define BCM1250_M3_WAR                  0
-#define SIBYTE_1956_WAR                 0
-#define MIPS4K_ICACHE_REFILL_WAR        0
-#define MIPS_CACHE_SYNC_WAR             0
-#define TX49XX_ICACHE_INDEX_INV_WAR     0
-#define ICACHE_REFILLS_WORKAROUND_WAR   0
-#define R10000_LLSC_WAR                 0
-#define MIPS34K_MISSED_ITLB_WAR         0
-#endif /* __ASM_MACH_ATH79_WAR_H */
diff --git a/arch/mips/include/asm/mach-au1x00/war.h b/arch/mips/include/asm/mach-au1x00/war.h
deleted file mode 100644
index 72e260d24e59..000000000000
--- a/arch/mips/include/asm/mach-au1x00/war.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
- */
-#ifndef __ASM_MIPS_MACH_AU1X00_WAR_H
-#define __ASM_MIPS_MACH_AU1X00_WAR_H
-#define R4600_V1_INDEX_ICACHEOP_WAR     0
-#define R4600_V1_HIT_CACHEOP_WAR        0
-#define R4600_V2_HIT_CACHEOP_WAR        0
-#define R5432_CP0_INTERRUPT_WAR         0
-#define BCM1250_M3_WAR                  0
-#define SIBYTE_1956_WAR                 0
-#define MIPS4K_ICACHE_REFILL_WAR        0
-#define MIPS_CACHE_SYNC_WAR             0
-#define TX49XX_ICACHE_INDEX_INV_WAR     0
-#define ICACHE_REFILLS_WORKAROUND_WAR   0
-#define R10000_LLSC_WAR                 0
-#define MIPS34K_MISSED_ITLB_WAR         0
-#endif /* __ASM_MIPS_MACH_AU1X00_WAR_H */
diff --git a/arch/mips/include/asm/mach-bcm3384/war.h b/arch/mips/include/asm/mach-bcm3384/war.h
deleted file mode 100644
index 59d7599059b0..000000000000
--- a/arch/mips/include/asm/mach-bcm3384/war.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
- */
-#ifndef __ASM_MIPS_MACH_BCM3384_WAR_H
-#define __ASM_MIPS_MACH_BCM3384_WAR_H
-#define R4600_V1_INDEX_ICACHEOP_WAR     0
-#define R4600_V1_HIT_CACHEOP_WAR        0
-#define R4600_V2_HIT_CACHEOP_WAR        0
-#define R5432_CP0_INTERRUPT_WAR         0
-#define BCM1250_M3_WAR                  0
-#define SIBYTE_1956_WAR                 0
-#define MIPS4K_ICACHE_REFILL_WAR        0
-#define MIPS_CACHE_SYNC_WAR             0
-#define TX49XX_ICACHE_INDEX_INV_WAR     0
-#define ICACHE_REFILLS_WORKAROUND_WAR   0
-#define R10000_LLSC_WAR                 0
-#define MIPS34K_MISSED_ITLB_WAR         0
-#endif /* __ASM_MIPS_MACH_BCM3384_WAR_H */
diff --git a/arch/mips/include/asm/mach-bcm47xx/bcm47xx.h b/arch/mips/include/asm/mach-bcm47xx/bcm47xx.h
index 7527c1d33d02..8ed77f618940 100644
--- a/arch/mips/include/asm/mach-bcm47xx/bcm47xx.h
+++ b/arch/mips/include/asm/mach-bcm47xx/bcm47xx.h
@@ -22,6 +22,7 @@
 #include <linux/ssb/ssb.h>
 #include <linux/bcma/bcma.h>
 #include <linux/bcma/bcma_soc.h>
+#include <linux/bcm47xx_nvram.h>
 enum bcm47xx_bus_type {
 #ifdef CONFIG_BCM47XX_SSB
diff --git a/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h b/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h
index 1f5643b89a91..c41d1dce1062 100644
--- a/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h
+++ b/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h
@@ -67,6 +67,7 @@ enum bcm47xx_board {
        BCM47XX_BOARD_LINKSYS_WRT150NV11,
        BCM47XX_BOARD_LINKSYS_WRT160NV1,
        BCM47XX_BOARD_LINKSYS_WRT160NV3,
+        BCM47XX_BOARD_LINKSYS_WRT300N_V1,
        BCM47XX_BOARD_LINKSYS_WRT300NV11,
        BCM47XX_BOARD_LINKSYS_WRT310NV1,
        BCM47XX_BOARD_LINKSYS_WRT310NV2,
@@ -74,6 +75,7 @@ enum bcm47xx_board {
        BCM47XX_BOARD_LINKSYS_WRT54G_TYPE_0101,
        BCM47XX_BOARD_LINKSYS_WRT54G_TYPE_0467,
        BCM47XX_BOARD_LINKSYS_WRT54G_TYPE_0708,
+        BCM47XX_BOARD_LINKSYS_WRT600N_V11,
        BCM47XX_BOARD_LINKSYS_WRT610NV1,
        BCM47XX_BOARD_LINKSYS_WRT610NV2,
        BCM47XX_BOARD_LINKSYS_WRTSL54GS,
@@ -86,9 +88,11 @@ enum bcm47xx_board {
        BCM47XX_BOARD_NETGEAR_WGR614V8,
        BCM47XX_BOARD_NETGEAR_WGR614V9,
+        BCM47XX_BOARD_NETGEAR_WGR614_V10,
        BCM47XX_BOARD_NETGEAR_WNDR3300,
        BCM47XX_BOARD_NETGEAR_WNDR3400V1,
        BCM47XX_BOARD_NETGEAR_WNDR3400V2,
+        BCM47XX_BOARD_NETGEAR_WNDR3400_V3,
        BCM47XX_BOARD_NETGEAR_WNDR3400VCNA,
        BCM47XX_BOARD_NETGEAR_WNDR3700V3,
        BCM47XX_BOARD_NETGEAR_WNDR4000,
diff --git a/arch/mips/include/asm/mach-bcm47xx/bcm47xx_nvram.h b/arch/mips/include/asm/mach-bcm47xx/bcm47xx_nvram.h
deleted file mode 100644
index ee59ffe99922..000000000000
--- a/arch/mips/include/asm/mach-bcm47xx/bcm47xx_nvram.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- *  Copyright (C) 2005, Broadcom Corporation
- *  Copyright (C) 2006, Felix Fietkau <nbd@openwrt.org>
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- */
-#ifndef __BCM47XX_NVRAM_H
-#define __BCM47XX_NVRAM_H
-#include <linux/types.h>
-#include <linux/kernel.h>
-int bcm47xx_nvram_init_from_mem(u32 base, u32 lim);
-int bcm47xx_nvram_getenv(const char *name, char *val, size_t val_len);
-int bcm47xx_nvram_gpio_pin(const char *name);
-#endif /* __BCM47XX_NVRAM_H */
diff --git a/arch/mips/include/asm/mach-bcm47xx/war.h b/arch/mips/include/asm/mach-bcm47xx/war.h
deleted file mode 100644
index a3d2f448b10e..000000000000
--- a/arch/mips/include/asm/mach-bcm47xx/war.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
- */
-#ifndef __ASM_MIPS_MACH_BCM47XX_WAR_H
-#define __ASM_MIPS_MACH_BCM47XX_WAR_H
-#define R4600_V1_INDEX_ICACHEOP_WAR     0
-#define R4600_V1_HIT_CACHEOP_WAR        0
-#define R4600_V2_HIT_CACHEOP_WAR        0
-#define R5432_CP0_INTERRUPT_WAR         0
-#define BCM1250_M3_WAR                  0
-#define SIBYTE_1956_WAR                 0
-#define MIPS4K_ICACHE_REFILL_WAR        0
-#define MIPS_CACHE_SYNC_WAR             0
-#define TX49XX_ICACHE_INDEX_INV_WAR     0
-#define ICACHE_REFILLS_WORKAROUND_WAR   0
-#define R10000_LLSC_WAR                 0
-#define MIPS34K_MISSED_ITLB_WAR         0
-#endif /* __ASM_MIPS_MACH_BCM47XX_WAR_H */
diff --git a/arch/mips/include/asm/mach-bcm63xx/dma-coherence.h b/arch/mips/include/asm/mach-bcm63xx/dma-coherence.h
new file mode 100644
index 000000000000..11d3b572b1b3
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm63xx/dma-coherence.h
@@ -0,0 +1,10 @@
+#ifndef __ASM_MACH_BCM63XX_DMA_COHERENCE_H
+#define __ASM_MACH_BCM63XX_DMA_COHERENCE_H
+#include <asm/bmips.h>
+#define plat_post_dma_flush     bmips_post_dma_flush
+#include <asm/mach-generic/dma-coherence.h>
+#endif /* __ASM_MACH_BCM63XX_DMA_COHERENCE_H */
diff --git a/arch/mips/include/asm/mach-bcm63xx/war.h b/arch/mips/include/asm/mach-bcm63xx/war.h
deleted file mode 100644
index 05ee8671bef1..000000000000
--- a/arch/mips/include/asm/mach-bcm63xx/war.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
- */
-#ifndef __ASM_MIPS_MACH_BCM63XX_WAR_H
-#define __ASM_MIPS_MACH_BCM63XX_WAR_H
-#define R4600_V1_INDEX_ICACHEOP_WAR     0
-#define R4600_V1_HIT_CACHEOP_WAR        0
-#define R4600_V2_HIT_CACHEOP_WAR        0
-#define R5432_CP0_INTERRUPT_WAR         0
-#define BCM1250_M3_WAR                  0
-#define SIBYTE_1956_WAR                 0
-#define MIPS4K_ICACHE_REFILL_WAR        0
-#define MIPS_CACHE_SYNC_WAR             0
-#define TX49XX_ICACHE_INDEX_INV_WAR     0
-#define ICACHE_REFILLS_WORKAROUND_WAR   0
-#define R10000_LLSC_WAR                 0
-#define MIPS34K_MISSED_ITLB_WAR         0
-#endif /* __ASM_MIPS_MACH_BCM63XX_WAR_H */
diff --git a/arch/mips/include/asm/mach-bcm3384/dma-coherence.h b/arch/mips/include/asm/mach-bmips/dma-coherence.h
index a3be8e50e1f0..d29781f02285 100644
--- a/arch/mips/include/asm/mach-bcm3384/dma-coherence.h
+++ b/arch/mips/include/asm/mach-bmips/dma-coherence.h
@@ -12,8 +12,12 @@
 * GNU General Public License for more details.
 */
-#ifndef __ASM_MACH_BCM3384_DMA_COHERENCE_H
+#ifndef __ASM_MACH_BMIPS_DMA_COHERENCE_H
-#define __ASM_MACH_BCM3384_DMA_COHERENCE_H
+#define __ASM_MACH_BMIPS_DMA_COHERENCE_H
+#include <asm/bmips.h>
+#include <asm/cpu-type.h>
+#include <asm/cpu.h>
 struct device;
@@ -45,4 +49,6 @@ static inline int plat_device_is_coherent(struct device *dev)
        return 0;
 }
-#endif /* __ASM_MACH_BCM3384_DMA_COHERENCE_H */
+#define plat_post_dma_flush     bmips_post_dma_flush
+#endif /* __ASM_MACH_BMIPS_DMA_COHERENCE_H */
diff --git a/arch/mips/include/asm/mach-bmips/spaces.h b/arch/mips/include/asm/mach-bmips/spaces.h
new file mode 100644
index 000000000000..1b05bddc8ec5
--- /dev/null
+++ b/arch/mips/include/asm/mach-bmips/spaces.h
@@ -0,0 +1,18 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1994 - 1999, 2000, 03, 04 Ralf Baechle
+ * Copyright (C) 2000, 2002  Maciej W. Rozycki
+ * Copyright (C) 1990, 1999, 2000 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_BMIPS_SPACES_H
+#define _ASM_BMIPS_SPACES_H
+/* Avoid collisions with system base register (SBR) region on BMIPS3300 */
+#define FIXADDR_TOP             ((unsigned long)(long)(int)0xff000000)
+#include <asm/mach-generic/spaces.h>
+#endif /* __ASM_BMIPS_SPACES_H */
diff --git a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
index fa1f3cfbae8d..d68e685cde60 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
@@ -50,7 +50,6 @@
 #define cpu_has_mips32r2        0
 #define cpu_has_mips64r1        0
 #define cpu_has_mips64r2        1
-#define cpu_has_mips_r2_exec_hazard 0
 #define cpu_has_dsp             0
 #define cpu_has_dsp2            0
 #define cpu_has_mipsmt          0
diff --git a/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h b/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h
index f9f448650505..460042ee5d6f 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h
@@ -57,6 +57,10 @@ static inline int plat_device_is_coherent(struct device *dev)
        return 1;
 }
+static inline void plat_post_dma_flush(struct device *dev)
+{
+}
 dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr);
 phys_addr_t dma_to_phys(struct device *dev, dma_addr_t daddr);
diff --git a/arch/mips/include/asm/mach-cavium-octeon/mangle-port.h b/arch/mips/include/asm/mach-cavium-octeon/mangle-port.h
new file mode 100644
index 000000000000..374eefafb320
--- /dev/null
+++ b/arch/mips/include/asm/mach-cavium-octeon/mangle-port.h
@@ -0,0 +1,74 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2003, 2004 Ralf Baechle
+ */
+#ifndef __ASM_MACH_GENERIC_MANGLE_PORT_H
+#define __ASM_MACH_GENERIC_MANGLE_PORT_H
+#include <asm/byteorder.h>
+#ifdef __BIG_ENDIAN
+# define __swizzle_addr_b(port) (port)
+# define __swizzle_addr_w(port) (port)
+# define __swizzle_addr_l(port) (port)
+# define __swizzle_addr_q(port) (port)
+#else /* __LITTLE_ENDIAN */
+static inline bool __should_swizzle_addr(unsigned long p)
+{
+        /* boot bus? */
+        return ((p >> 40) & 0xff) == 0;
+}
+# define __swizzle_addr_b(port) \
+        (__should_swizzle_addr(port) ? (port) ^ 7 : (port))
+# define __swizzle_addr_w(port) \
+        (__should_swizzle_addr(port) ? (port) ^ 6 : (port))
+# define __swizzle_addr_l(port) \
+        (__should_swizzle_addr(port) ? (port) ^ 4 : (port))
+# define __swizzle_addr_q(port) (port)
+#endif /* __BIG_ENDIAN */
+/*
+ * Sane hardware offers swapping of PCI/ISA I/O space accesses in hardware;
+ * less sane hardware forces software to fiddle with this...
+ *
+ * Regardless, if the host bus endianness mismatches that of PCI/ISA, then
+ * you can't have the numerical value of data and byte addresses within
+ * multibyte quantities both preserved at the same time.  Hence two
+ * variations of functions: non-prefixed ones that preserve the value
+ * and prefixed ones that preserve byte addresses.  The latters are
+ * typically used for moving raw data between a peripheral and memory (cf.
+ * string I/O functions), hence the "__mem_" prefix.
+ */
+#if defined(CONFIG_SWAP_IO_SPACE)
+# define ioswabb(a, x)          (x)
+# define __mem_ioswabb(a, x)    (x)
+# define ioswabw(a, x)          le16_to_cpu(x)
+# define __mem_ioswabw(a, x)    (x)
+# define ioswabl(a, x)          le32_to_cpu(x)
+# define __mem_ioswabl(a, x)    (x)
+# define ioswabq(a, x)          le64_to_cpu(x)
+# define __mem_ioswabq(a, x)    (x)
+#else
+# define ioswabb(a, x)          (x)
+# define __mem_ioswabb(a, x)    (x)
+# define ioswabw(a, x)          (x)
+# define __mem_ioswabw(a, x)    cpu_to_le16(x)
+# define ioswabl(a, x)          (x)
+# define __mem_ioswabl(a, x)    cpu_to_le32(x)
+# define ioswabq(a, x)          (x)
+# define __mem_ioswabq(a, x)    cpu_to_le32(x)
+#endif
+#endif /* __ASM_MACH_GENERIC_MANGLE_PORT_H */
diff --git a/arch/mips/include/asm/mach-cobalt/cpu-feature-overrides.h b/arch/mips/include/asm/mach-cobalt/cpu-feature-overrides.h
index 71d4bface1dc..30c5cd9fd973 100644
--- a/arch/mips/include/asm/mach-cobalt/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-cobalt/cpu-feature-overrides.h
@@ -14,7 +14,6 @@
 #define cpu_has_3k_cache        0
 #define cpu_has_4k_cache        1
 #define cpu_has_tx39_cache      0
-#define cpu_has_fpu             1
 #define cpu_has_32fpr           1
 #define cpu_has_counter         1
 #define cpu_has_watch           0
diff --git a/arch/mips/include/asm/mach-cobalt/war.h b/arch/mips/include/asm/mach-cobalt/war.h
deleted file mode 100644
index 34ae4046541e..000000000000
--- a/arch/mips/include/asm/mach-cobalt/war.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
- */
-#ifndef __ASM_MIPS_MACH_COBALT_WAR_H
-#define __ASM_MIPS_MACH_COBALT_WAR_H
-#define R4600_V1_INDEX_ICACHEOP_WAR     0
-#define R4600_V1_HIT_CACHEOP_WAR        0
-#define R4600_V2_HIT_CACHEOP_WAR        0
-#define R5432_CP0_INTERRUPT_WAR         0
-#define BCM1250_M3_WAR                  0
-#define SIBYTE_1956_WAR                 0
-#define MIPS4K_ICACHE_REFILL_WAR        0
-#define MIPS_CACHE_SYNC_WAR             0
-#define TX49XX_ICACHE_INDEX_INV_WAR     0
-#define ICACHE_REFILLS_WORKAROUND_WAR   0
-#define R10000_LLSC_WAR                 0
-#define MIPS34K_MISSED_ITLB_WAR         0
-#endif /* __ASM_MIPS_MACH_COBALT_WAR_H */
diff --git a/arch/mips/include/asm/mach-dec/cpu-feature-overrides.h b/arch/mips/include/asm/mach-dec/cpu-feature-overrides.h
index acce27fd2bb8..bdf045fb00c8 100644
--- a/arch/mips/include/asm/mach-dec/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-dec/cpu-feature-overrides.h
@@ -15,7 +15,6 @@
 /* Generic ones first.  */
 #define cpu_has_tlb                     1
 #define cpu_has_tx39_cache              0
-#define cpu_has_fpu                     1
 #define cpu_has_divec                   0
 #define cpu_has_prefetch                0
 #define cpu_has_mcheck                  0
diff --git a/arch/mips/include/asm/mach-dec/war.h b/arch/mips/include/asm/mach-dec/war.h
deleted file mode 100644
index d29996feb3e7..000000000000
--- a/arch/mips/include/asm/mach-dec/war.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
- */
-#ifndef __ASM_MIPS_MACH_DEC_WAR_H
-#define __ASM_MIPS_MACH_DEC_WAR_H
-#define R4600_V1_INDEX_ICACHEOP_WAR     0
-#define R4600_V1_HIT_CACHEOP_WAR        0
-#define R4600_V2_HIT_CACHEOP_WAR        0
-#define R5432_CP0_INTERRUPT_WAR         0
-#define BCM1250_M3_WAR                  0
-#define SIBYTE_1956_WAR                 0
-#define MIPS4K_ICACHE_REFILL_WAR        0
-#define MIPS_CACHE_SYNC_WAR             0
-#define TX49XX_ICACHE_INDEX_INV_WAR     0
-#define ICACHE_REFILLS_WORKAROUND_WAR   0
-#define R10000_LLSC_WAR                 0
-#define MIPS34K_MISSED_ITLB_WAR         0
-#endif /* __ASM_MIPS_MACH_DEC_WAR_H */
diff --git a/arch/mips/include/asm/mach-emma2rh/war.h b/arch/mips/include/asm/mach-emma2rh/war.h
deleted file mode 100644
index 79ae82da3ec7..000000000000
--- a/arch/mips/include/asm/mach-emma2rh/war.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
- */
-#ifndef __ASM_MIPS_MACH_EMMA2RH_WAR_H
-#define __ASM_MIPS_MACH_EMMA2RH_WAR_H
-#define R4600_V1_INDEX_ICACHEOP_WAR     0
-#define R4600_V1_HIT_CACHEOP_WAR        0
-#define R4600_V2_HIT_CACHEOP_WAR        0
-#define R5432_CP0_INTERRUPT_WAR         0
-#define BCM1250_M3_WAR                  0
-#define SIBYTE_1956_WAR                 0
-#define MIPS4K_ICACHE_REFILL_WAR        0
-#define MIPS_CACHE_SYNC_WAR             0
-#define TX49XX_ICACHE_INDEX_INV_WAR     0
-#define ICACHE_REFILLS_WORKAROUND_WAR   0
-#define R10000_LLSC_WAR                 0
-#define MIPS34K_MISSED_ITLB_WAR         0
-#endif /* __ASM_MIPS_MACH_EMMA2RH_WAR_H */
diff --git a/arch/mips/include/asm/mach-generic/dma-coherence.h b/arch/mips/include/asm/mach-generic/dma-coherence.h
index 7629c35986f7..0f8a354fd468 100644
--- a/arch/mips/include/asm/mach-generic/dma-coherence.h
+++ b/arch/mips/include/asm/mach-generic/dma-coherence.h
@@ -52,6 +52,12 @@ static inline int plat_device_is_coherent(struct device *dev)
        return coherentio;
 }
+#ifndef plat_post_dma_flush
+static inline void plat_post_dma_flush(struct device *dev)
+{
+}
+#endif
 #ifdef CONFIG_SWIOTLB
 static inline dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr)
 {
diff --git a/arch/mips/include/asm/mach-ralink/war.h b/arch/mips/include/asm/mach-generic/war.h
index c074b5dc1f82..a1bc2e71f983 100644
--- a/arch/mips/include/asm/mach-ralink/war.h
+++ b/arch/mips/include/asm/mach-generic/war.h
@@ -5,8 +5,8 @@
 *
 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
 */
-#ifndef __ASM_MACH_RALINK_WAR_H
+#ifndef __ASM_MACH_GENERIC_WAR_H
-#define __ASM_MACH_RALINK_WAR_H
+#define __ASM_MACH_GENERIC_WAR_H
 #define R4600_V1_INDEX_ICACHEOP_WAR     0
 #define R4600_V1_HIT_CACHEOP_WAR        0
@@ -21,4 +21,4 @@
 #define R10000_LLSC_WAR                 0
 #define MIPS34K_MISSED_ITLB_WAR         0
-#endif /* __ASM_MACH_RALINK_WAR_H */
+#endif /* __ASM_MACH_GENERIC_WAR_H */
diff --git a/arch/mips/include/asm/mach-ip22/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ip22/cpu-feature-overrides.h
index 1dfe47453ea4..9b19b72dba56 100644
--- a/arch/mips/include/asm/mach-ip22/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-ip22/cpu-feature-overrides.h
@@ -16,7 +16,6 @@
 #define cpu_has_tlb             1
 #define cpu_has_4kex            1
 #define cpu_has_4k_cache        1
-#define cpu_has_fpu             1
 #define cpu_has_32fpr           1
 #define cpu_has_counter         1
 #define cpu_has_mips16          0
diff --git a/arch/mips/include/asm/mach-ip27/dma-coherence.h b/arch/mips/include/asm/mach-ip27/dma-coherence.h
index 4ffddfdb5062..1daa64412569 100644
--- a/arch/mips/include/asm/mach-ip27/dma-coherence.h
+++ b/arch/mips/include/asm/mach-ip27/dma-coherence.h
@@ -58,6 +58,10 @@ static inline int plat_dma_supported(struct device *dev, u64 mask)
        return 1;
 }
+static inline void plat_post_dma_flush(struct device *dev)
+{
+}
 static inline int plat_device_is_coherent(struct device *dev)
 {
        return 1;               /* IP27 non-cohernet mode is unsupported */
diff --git a/arch/mips/include/asm/mach-ip32/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ip32/cpu-feature-overrides.h
index 2e1ec6cfedd5..241409b78ff1 100644
--- a/arch/mips/include/asm/mach-ip32/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-ip32/cpu-feature-overrides.h
@@ -26,7 +26,6 @@
 /* Settings which are common for all ip32 CPUs */
 #define cpu_has_tlb             1
 #define cpu_has_4kex            1
-#define cpu_has_fpu             1
 #define cpu_has_32fpr           1
 #define cpu_has_counter         1
 #define cpu_has_mips16          0
diff --git a/arch/mips/include/asm/mach-ip32/dma-coherence.h b/arch/mips/include/asm/mach-ip32/dma-coherence.h
index 104cfbc3ed63..0a0b0e2ced60 100644
--- a/arch/mips/include/asm/mach-ip32/dma-coherence.h
+++ b/arch/mips/include/asm/mach-ip32/dma-coherence.h
@@ -80,6 +80,10 @@ static inline int plat_dma_supported(struct device *dev, u64 mask)
        return 1;
 }
+static inline void plat_post_dma_flush(struct device *dev)
+{
+}
 static inline int plat_device_is_coherent(struct device *dev)
 {
        return 0;               /* IP32 is non-cohernet */
diff --git a/arch/mips/include/asm/mach-jazz/dma-coherence.h b/arch/mips/include/asm/mach-jazz/dma-coherence.h
index 949003ef97b3..dc347c25c343 100644
--- a/arch/mips/include/asm/mach-jazz/dma-coherence.h
+++ b/arch/mips/include/asm/mach-jazz/dma-coherence.h
@@ -48,6 +48,10 @@ static inline int plat_dma_supported(struct device *dev, u64 mask)
        return 1;
 }
+static inline void plat_post_dma_flush(struct device *dev)
+{
+}
 static inline int plat_device_is_coherent(struct device *dev)
 {
        return 0;
diff --git a/arch/mips/include/asm/mach-jazz/war.h b/arch/mips/include/asm/mach-jazz/war.h
deleted file mode 100644
index 5b18b9a3d0ec..000000000000
--- a/arch/mips/include/asm/mach-jazz/war.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
- */
-#ifndef __ASM_MIPS_MACH_JAZZ_WAR_H
-#define __ASM_MIPS_MACH_JAZZ_WAR_H
-#define R4600_V1_INDEX_ICACHEOP_WAR     0
-#define R4600_V1_HIT_CACHEOP_WAR        0
-#define R4600_V2_HIT_CACHEOP_WAR        0
-#define R5432_CP0_INTERRUPT_WAR         0
-#define BCM1250_M3_WAR                  0
-#define SIBYTE_1956_WAR                 0
-#define MIPS4K_ICACHE_REFILL_WAR        0
-#define MIPS_CACHE_SYNC_WAR             0
-#define TX49XX_ICACHE_INDEX_INV_WAR     0
-#define ICACHE_REFILLS_WORKAROUND_WAR   0
-#define R10000_LLSC_WAR                 0
-#define MIPS34K_MISSED_ITLB_WAR         0
-#endif /* __ASM_MIPS_MACH_JAZZ_WAR_H */
diff --git a/arch/mips/include/asm/mach-jz4740/war.h b/arch/mips/include/asm/mach-jz4740/war.h
deleted file mode 100644
index 9b511d323838..000000000000
--- a/arch/mips/include/asm/mach-jz4740/war.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
- */
-#ifndef __ASM_MIPS_MACH_JZ4740_WAR_H
-#define __ASM_MIPS_MACH_JZ4740_WAR_H
-#define R4600_V1_INDEX_ICACHEOP_WAR     0
-#define R4600_V1_HIT_CACHEOP_WAR        0
-#define R4600_V2_HIT_CACHEOP_WAR        0
-#define R5432_CP0_INTERRUPT_WAR         0
-#define BCM1250_M3_WAR                  0
-#define SIBYTE_1956_WAR                 0
-#define MIPS4K_ICACHE_REFILL_WAR        0
-#define MIPS_CACHE_SYNC_WAR             0
-#define TX49XX_ICACHE_INDEX_INV_WAR     0
-#define ICACHE_REFILLS_WORKAROUND_WAR   0
-#define R10000_LLSC_WAR                 0
-#define MIPS34K_MISSED_ITLB_WAR         0
-#endif /* __ASM_MIPS_MACH_JZ4740_WAR_H */
diff --git a/arch/mips/include/asm/mach-lantiq/war.h b/arch/mips/include/asm/mach-lantiq/war.h
deleted file mode 100644
index 358ca979c1bd..000000000000
--- a/arch/mips/include/asm/mach-lantiq/war.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- */
-#ifndef __ASM_MIPS_MACH_LANTIQ_WAR_H
-#define __ASM_MIPS_MACH_LANTIQ_WAR_H
-#define R4600_V1_INDEX_ICACHEOP_WAR     0
-#define R4600_V1_HIT_CACHEOP_WAR        0
-#define R4600_V2_HIT_CACHEOP_WAR        0
-#define R5432_CP0_INTERRUPT_WAR         0
-#define BCM1250_M3_WAR                  0
-#define SIBYTE_1956_WAR                 0
-#define MIPS4K_ICACHE_REFILL_WAR        0
-#define MIPS_CACHE_SYNC_WAR             0
-#define TX49XX_ICACHE_INDEX_INV_WAR     0
-#define ICACHE_REFILLS_WORKAROUND_WAR   0
-#define R10000_LLSC_WAR                 0
-#define MIPS34K_MISSED_ITLB_WAR         0
-#endif
diff --git a/arch/mips/include/asm/mach-lasat/war.h b/arch/mips/include/asm/mach-lasat/war.h
deleted file mode 100644
index 741ae724adc6..000000000000
--- a/arch/mips/include/asm/mach-lasat/war.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
- */
-#ifndef __ASM_MIPS_MACH_LASAT_WAR_H
-#define __ASM_MIPS_MACH_LASAT_WAR_H
-#define R4600_V1_INDEX_ICACHEOP_WAR     0
-#define R4600_V1_HIT_CACHEOP_WAR        0
-#define R4600_V2_HIT_CACHEOP_WAR        0
-#define R5432_CP0_INTERRUPT_WAR         0
-#define BCM1250_M3_WAR                  0
-#define SIBYTE_1956_WAR                 0
-#define MIPS4K_ICACHE_REFILL_WAR        0
-#define MIPS_CACHE_SYNC_WAR             0
-#define TX49XX_ICACHE_INDEX_INV_WAR     0
-#define ICACHE_REFILLS_WORKAROUND_WAR   0
-#define R10000_LLSC_WAR                 0
-#define MIPS34K_MISSED_ITLB_WAR         0
-#endif /* __ASM_MIPS_MACH_LASAT_WAR_H */
diff --git a/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h b/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h
index 6d69332f21ec..acc376897e46 100644
--- a/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h
@@ -34,7 +34,6 @@
 #define cpu_has_dsp             0
 #define cpu_has_dsp2            0
 #define cpu_has_ejtag           0
-#define cpu_has_fpu             1
 #define cpu_has_ic_fills_f_dc   0
 #define cpu_has_inclusive_pcaches       1
 #define cpu_has_llsc            1
diff --git a/arch/mips/include/asm/mach-loongson/dma-coherence.h b/arch/mips/include/asm/mach-loongson/dma-coherence.h
index a90534161bd2..4bf4e19f72e8 100644
--- a/arch/mips/include/asm/mach-loongson/dma-coherence.h
+++ b/arch/mips/include/asm/mach-loongson/dma-coherence.h
@@ -78,4 +78,8 @@ static inline int plat_device_is_coherent(struct device *dev)
 #endif /* CONFIG_DMA_NONCOHERENT */
 }
+static inline void plat_post_dma_flush(struct device *dev)
+{
+}
 #endif /* __ASM_MACH_LOONGSON_DMA_COHERENCE_H */
diff --git a/arch/mips/include/asm/mach-loongson/loongson.h b/arch/mips/include/asm/mach-loongson/loongson.h
index 5459ac09679f..9783103fd6f6 100644
--- a/arch/mips/include/asm/mach-loongson/loongson.h
+++ b/arch/mips/include/asm/mach-loongson/loongson.h
@@ -255,6 +255,10 @@ static inline void do_perfcnt_IRQ(void)
 extern u64 loongson_chipcfg[MAX_PACKAGES];
 #define LOONGSON_CHIPCFG(id) (*(volatile u32 *)(loongson_chipcfg[id]))
+/* Chip Temperature registor of each physical cpu package, PRid >= Loongson-3A */
+extern u64 loongson_chiptemp[MAX_PACKAGES];
+#define LOONGSON_CHIPTEMP(id) (*(volatile u32 *)(loongson_chiptemp[id]))
 /* Freq Control register of each physical cpu package, PRid >= Loongson-3B */
 extern u64 loongson_freqctrl[MAX_PACKAGES];
 #define LOONGSON_FREQCTRL(id) (*(volatile u32 *)(loongson_freqctrl[id]))
diff --git a/arch/mips/include/asm/mach-loongson/war.h b/arch/mips/include/asm/mach-loongson/war.h
deleted file mode 100644
index f2570df66bb5..000000000000
--- a/arch/mips/include/asm/mach-loongson/war.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
- */
-#ifndef __ASM_MACH_LOONGSON_WAR_H
-#define __ASM_MACH_LOONGSON_WAR_H
-#define R4600_V1_INDEX_ICACHEOP_WAR     0
-#define R4600_V1_HIT_CACHEOP_WAR        0
-#define R4600_V2_HIT_CACHEOP_WAR        0
-#define R5432_CP0_INTERRUPT_WAR         0
-#define BCM1250_M3_WAR                  0
-#define SIBYTE_1956_WAR                 0
-#define MIPS4K_ICACHE_REFILL_WAR        0
-#define MIPS_CACHE_SYNC_WAR             0
-#define TX49XX_ICACHE_INDEX_INV_WAR     0
-#define ICACHE_REFILLS_WORKAROUND_WAR   0
-#define R10000_LLSC_WAR                 0
-#define MIPS34K_MISSED_ITLB_WAR         0
-#endif /* __ASM_MACH_LEMOTE_WAR_H */
diff --git a/arch/mips/include/asm/mach-loongson1/war.h b/arch/mips/include/asm/mach-loongson1/war.h
deleted file mode 100644
index 8fb50d008131..000000000000
--- a/arch/mips/include/asm/mach-loongson1/war.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
- */
-#ifndef __ASM_MACH_LOONGSON1_WAR_H
-#define __ASM_MACH_LOONGSON1_WAR_H
-#define R4600_V1_INDEX_ICACHEOP_WAR     0
-#define R4600_V1_HIT_CACHEOP_WAR        0
-#define R4600_V2_HIT_CACHEOP_WAR        0
-#define R5432_CP0_INTERRUPT_WAR         0
-#define BCM1250_M3_WAR                  0
-#define SIBYTE_1956_WAR                 0
-#define MIPS4K_ICACHE_REFILL_WAR        0
-#define MIPS_CACHE_SYNC_WAR             0
-#define TX49XX_ICACHE_INDEX_INV_WAR     0
-#define ICACHE_REFILLS_WORKAROUND_WAR   0
-#define R10000_LLSC_WAR                 0
-#define MIPS34K_MISSED_ITLB_WAR         0
-#endif /* __ASM_MACH_LOONGSON1_WAR_H */
diff --git a/arch/mips/include/asm/mach-netlogic/multi-node.h b/arch/mips/include/asm/mach-netlogic/multi-node.h
index 9ed8dacdc37c..8bdf47e29145 100644
--- a/arch/mips/include/asm/mach-netlogic/multi-node.h
+++ b/arch/mips/include/asm/mach-netlogic/multi-node.h
@@ -48,15 +48,6 @@
 #endif
 #define NLM_THREADS_PER_CORE    4
-#ifdef CONFIG_CPU_XLR
-#define nlm_cores_per_node()    8
-#else
-extern unsigned int xlp_cores_per_node;
-#define nlm_cores_per_node()    xlp_cores_per_node
-#endif
-#define nlm_threads_per_node()  (nlm_cores_per_node() * NLM_THREADS_PER_CORE)
-#define nlm_cpuid_to_node(c)    ((c) / nlm_threads_per_node())
 struct nlm_soc_info {
        unsigned long   coremask;       /* cores enabled on the soc */
diff --git a/arch/mips/include/asm/mach-netlogic/topology.h b/arch/mips/include/asm/mach-netlogic/topology.h
deleted file mode 100644
index 0eb43c832b25..000000000000
--- a/arch/mips/include/asm/mach-netlogic/topology.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2013 Broadcom Corporation
- */
-#ifndef _ASM_MACH_NETLOGIC_TOPOLOGY_H
-#define _ASM_MACH_NETLOGIC_TOPOLOGY_H
-#include <asm/mach-netlogic/multi-node.h>
-#include <asm-generic/topology.h>
-#endif /* _ASM_MACH_NETLOGIC_TOPOLOGY_H */
diff --git a/arch/mips/include/asm/mach-netlogic/war.h b/arch/mips/include/asm/mach-netlogic/war.h
deleted file mode 100644
index 2c7216840e18..000000000000
--- a/arch/mips/include/asm/mach-netlogic/war.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2011 Netlogic Microsystems.
- * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
- */
-#ifndef __ASM_MIPS_MACH_NLM_WAR_H
-#define __ASM_MIPS_MACH_NLM_WAR_H
-#define R4600_V1_INDEX_ICACHEOP_WAR     0
-#define R4600_V1_HIT_CACHEOP_WAR        0
-#define R4600_V2_HIT_CACHEOP_WAR        0
-#define R5432_CP0_INTERRUPT_WAR         0
-#define BCM1250_M3_WAR                  0
-#define SIBYTE_1956_WAR                 0
-#define MIPS4K_ICACHE_REFILL_WAR        0
-#define MIPS_CACHE_SYNC_WAR             0
-#define TX49XX_ICACHE_INDEX_INV_WAR     0
-#define ICACHE_REFILLS_WORKAROUND_WAR   0
-#define R10000_LLSC_WAR                 0
-#define MIPS34K_MISSED_ITLB_WAR         0
-#endif /* __ASM_MIPS_MACH_NLM_WAR_H */
diff --git a/arch/mips/include/asm/mach-paravirt/war.h b/arch/mips/include/asm/mach-paravirt/war.h
deleted file mode 100644
index 36d3afb98451..000000000000
--- a/arch/mips/include/asm/mach-paravirt/war.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
- * Copyright (C) 2013 Cavium Networks <support@caviumnetworks.com>
- */
-#ifndef __ASM_MIPS_MACH_PARAVIRT_WAR_H
-#define __ASM_MIPS_MACH_PARAVIRT_WAR_H
-#define R4600_V1_INDEX_ICACHEOP_WAR     0
-#define R4600_V1_HIT_CACHEOP_WAR        0
-#define R4600_V2_HIT_CACHEOP_WAR        0
-#define R5432_CP0_INTERRUPT_WAR         0
-#define BCM1250_M3_WAR                  0
-#define SIBYTE_1956_WAR                 0
-#define MIPS4K_ICACHE_REFILL_WAR        0
-#define MIPS_CACHE_SYNC_WAR             0
-#define TX49XX_ICACHE_INDEX_INV_WAR     0
-#define ICACHE_REFILLS_WORKAROUND_WAR   0
-#define R10000_LLSC_WAR                 0
-#define MIPS34K_MISSED_ITLB_WAR         0
-#endif /* __ASM_MIPS_MACH_PARAVIRT_WAR_H */
diff --git a/arch/mips/include/asm/mach-pistachio/gpio.h b/arch/mips/include/asm/mach-pistachio/gpio.h
new file mode 100644
index 000000000000..6c1649c27b8d
--- /dev/null
+++ b/arch/mips/include/asm/mach-pistachio/gpio.h
@@ -0,0 +1,21 @@
+/*
+ * Pistachio IRQ setup
+ *
+ * Copyright (C) 2014 Google, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ */
+#ifndef __ASM_MACH_PISTACHIO_GPIO_H
+#define __ASM_MACH_PISTACHIO_GPIO_H
+#include <asm-generic/gpio.h>
+#define gpio_get_value  __gpio_get_value
+#define gpio_set_value  __gpio_set_value
+#define gpio_cansleep   __gpio_cansleep
+#define gpio_to_irq     __gpio_to_irq
+#endif /* __ASM_MACH_PISTACHIO_GPIO_H */
diff --git a/arch/mips/include/asm/mach-pistachio/irq.h b/arch/mips/include/asm/mach-pistachio/irq.h
new file mode 100644
index 000000000000..b94a09a54221
--- /dev/null
+++ b/arch/mips/include/asm/mach-pistachio/irq.h
@@ -0,0 +1,18 @@
+/*
+ * Pistachio IRQ setup
+ *
+ * Copyright (C) 2014 Google, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ */
+#ifndef __ASM_MACH_PISTACHIO_IRQ_H
+#define __ASM_MACH_PISTACHIO_IRQ_H
+#define NR_IRQS 256
+#include_next <irq.h>
+#endif /* __ASM_MACH_PISTACHIO_IRQ_H */
diff --git a/arch/mips/include/asm/mach-pnx833x/war.h b/arch/mips/include/asm/mach-pnx833x/war.h
deleted file mode 100644
index e410df4e1b3a..000000000000
--- a/arch/mips/include/asm/mach-pnx833x/war.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
- */
-#ifndef __ASM_MIPS_MACH_PNX833X_WAR_H
-#define __ASM_MIPS_MACH_PNX833X_WAR_H
-#define R4600_V1_INDEX_ICACHEOP_WAR     0
-#define R4600_V1_HIT_CACHEOP_WAR        0
-#define R4600_V2_HIT_CACHEOP_WAR        0
-#define R5432_CP0_INTERRUPT_WAR         0
-#define BCM1250_M3_WAR                  0
-#define SIBYTE_1956_WAR                 0
-#define MIPS4K_ICACHE_REFILL_WAR        0
-#define MIPS_CACHE_SYNC_WAR             0
-#define TX49XX_ICACHE_INDEX_INV_WAR     0
-#define ICACHE_REFILLS_WORKAROUND_WAR   0
-#define R10000_LLSC_WAR                 0
-#define MIPS34K_MISSED_ITLB_WAR         0
-#endif /* __ASM_MIPS_MACH_PNX833X_WAR_H */
diff --git a/arch/mips/include/asm/mach-rm/cpu-feature-overrides.h b/arch/mips/include/asm/mach-rm/cpu-feature-overrides.h
index f095c529c48c..98cf40417c5d 100644
--- a/arch/mips/include/asm/mach-rm/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-rm/cpu-feature-overrides.h
@@ -15,7 +15,6 @@
 #define cpu_has_tlb             1
 #define cpu_has_4kex            1
 #define cpu_has_4k_cache        1
-#define cpu_has_fpu             1
 #define cpu_has_32fpr           1
 #define cpu_has_counter         1
 #define cpu_has_watch           0
diff --git a/arch/mips/include/asm/mach-tx39xx/war.h b/arch/mips/include/asm/mach-tx39xx/war.h
deleted file mode 100644
index 6a52e6534776..000000000000
--- a/arch/mips/include/asm/mach-tx39xx/war.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
- */
-#ifndef __ASM_MIPS_MACH_TX39XX_WAR_H
-#define __ASM_MIPS_MACH_TX39XX_WAR_H
-#define R4600_V1_INDEX_ICACHEOP_WAR     0
-#define R4600_V1_HIT_CACHEOP_WAR        0
-#define R4600_V2_HIT_CACHEOP_WAR        0
-#define R5432_CP0_INTERRUPT_WAR         0
-#define BCM1250_M3_WAR                  0
-#define SIBYTE_1956_WAR                 0
-#define MIPS4K_ICACHE_REFILL_WAR        0
-#define MIPS_CACHE_SYNC_WAR             0
-#define TX49XX_ICACHE_INDEX_INV_WAR     0
-#define ICACHE_REFILLS_WORKAROUND_WAR   0
-#define R10000_LLSC_WAR                 0
-#define MIPS34K_MISSED_ITLB_WAR         0
-#endif /* __ASM_MIPS_MACH_TX39XX_WAR_H */
diff --git a/arch/mips/include/asm/mach-vr41xx/war.h b/arch/mips/include/asm/mach-vr41xx/war.h
deleted file mode 100644
index ffe31e736009..000000000000
--- a/arch/mips/include/asm/mach-vr41xx/war.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
- */
-#ifndef __ASM_MIPS_MACH_VR41XX_WAR_H
-#define __ASM_MIPS_MACH_VR41XX_WAR_H
-#define R4600_V1_INDEX_ICACHEOP_WAR     0
-#define R4600_V1_HIT_CACHEOP_WAR        0
-#define R4600_V2_HIT_CACHEOP_WAR        0
-#define R5432_CP0_INTERRUPT_WAR         0
-#define BCM1250_M3_WAR                  0
-#define SIBYTE_1956_WAR                 0
-#define MIPS4K_ICACHE_REFILL_WAR        0
-#define MIPS_CACHE_SYNC_WAR             0
-#define TX49XX_ICACHE_INDEX_INV_WAR     0
-#define ICACHE_REFILLS_WORKAROUND_WAR   0
-#define R10000_LLSC_WAR                 0
-#define MIPS34K_MISSED_ITLB_WAR         0
-#endif /* __ASM_MIPS_MACH_VR41XX_WAR_H */
diff --git a/arch/mips/include/asm/mips-boards/sead3-addr.h b/arch/mips/include/asm/mips-boards/sead3-addr.h
new file mode 100644
index 000000000000..c0db57802f7c
--- /dev/null
+++ b/arch/mips/include/asm/mips-boards/sead3-addr.h
@@ -0,0 +1,83 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2015 Imagination Technologies, Inc.
+ *   written by Ralf Baechle <ralf@linux-mips.org>
+ */
+#ifndef __ASM_MIPS_BOARDS_SEAD3_ADDR_H
+#define __ASM_MIPS_BOARDS_SEAD3_ADDR_H
+/*
+ * Target #0 Register Decode
+ */
+#define SEAD3_SD_SPDCNF                         0xbb000040
+#define SEAD3_SD_SPADDR                         0xbb000048
+#define SEAD3_SD_DATA                           0xbb000050
+/*
+ * Target #1 Register Decode
+ */
+#define SEAD3_CFG                               0xbb100110
+#define SEAD3_GIC_BASE_ADDRESS                  0xbb1c0000
+#define SEAD3_SHARED_SECTION                    0xbb1c0000
+#define SEAD3_VPE_LOCAL_SECTION                 0xbb1c8000
+#define SEAD3_VPE_OTHER_SECTION                 0xbb1cc000
+#define SEAD3_USER_MODE_VISIBLE_SECTION         0xbb1d0000
+/*
+ * Target #3 Register Decode
+ */
+#define SEAD3_USB_HS_BASE                       0xbb200000
+#define SEAD3_USB_HS_IDENTIFICATION_REGS        0xbb200000
+#define SEAD3_USB_HS_CAPABILITY_REGS            0xbb200100
+#define SEAD3_USB_HS_OPERATIONAL_REGS           0xbb200140
+#define SEAD3_RESERVED                          0xbe800000
+/*
+ * Target #3 Register Decode
+ */
+#define SEAD3_SRAM                              0xbe000000
+#define SEAD3_OPTIONAL_SRAM                     0xbe400000
+#define SEAD3_FPGA                              0xbf000000
+#define SEAD3_PI_PIC32_USB_STATUS               0xbf000060
+#define   SEAD3_PI_PIC32_USB_STATUS_IO_RDY      (1 << 0)
+#define   SEAD3_PI_PIC32_USB_STATUS_SPL_INT     (1 << 1)
+#define   SEAD3_PI_PIC32_USB_STATUS_GPIOA_INT   (1 << 2)
+#define   SEAD3_PI_PIC32_USB_STATUS_GPIOB_INT   (1 << 3)
+#define SEAD3_PI_SOFT_ENDIAN                    0xbf000070
+#define SEAD3_CPLD_P_SWITCH                     0xbf000200
+#define SEAD3_CPLD_F_SWITCH                     0xbf000208
+#define SEAD3_CPLD_P_LED                        0xbf000210
+#define SEAD3_CPLD_F_LED                        0xbf000218
+#define SEAD3_NEWSC_LIVE                        0xbf000220
+#define SEAD3_NEWSC_REG                         0xbf000228
+#define SEAD3_NEWSC_CTRL                        0xbf000230
+#define SEAD3_LCD_CONTROL                       0xbf000400
+#define SEAD3_LCD_DATA                          0xbf000408
+#define SEAD3_CPLD_LCD_STATUS                   0xbf000410
+#define SEAD3_CPLD_LCD_DATA                     0xbf000418
+#define SEAD3_CPLD_PI_DEVRST                    0xbf000480
+#define SEAD3_CPLD_PI_DEVRST_IC32_RST           (1 << 0)
+#define SEAD3_RESERVED_0                        0xbf000500
+#define SEAD3_PIC32_REGISTERS                   0xbf000600
+#define SEAD3_RESERVED_1                        0xbf000700
+#define SEAD3_UART_CH_0                         0xbf000800
+#define SEAD3_UART_CH_1                         0xbf000900
+#define SEAD3_RESERVED_2                        0xbf000a00
+#define SEAD3_ETHERNET                          0xbf010000
+#define SEAD3_RESERVED_3                        0xbf020000
+#define SEAD3_USER_EXPANSION                    0xbf400000
+#define SEAD3_RESERVED_4                        0xbf800000
+#define SEAD3_BOOT_FLASH_EXTENSION              0xbfa00000
+#define SEAD3_BOOT_FLASH                        0xbfc00000
+#define SEAD3_REVISION_REGISTER                 0xbfc00010
+#endif /* __ASM_MIPS_BOARDS_SEAD3_ADDR_H  */
diff --git a/arch/mips/include/asm/mips-r2-to-r6-emul.h b/arch/mips/include/asm/mips-r2-to-r6-emul.h
index 60570f2c3ba2..4b89f28047f7 100644
--- a/arch/mips/include/asm/mips-r2-to-r6-emul.h
+++ b/arch/mips/include/asm/mips-r2-to-r6-emul.h
@@ -84,11 +84,16 @@ extern void do_trap_or_bp(struct pt_regs *regs, unsigned int code,
 #ifndef CONFIG_MIPSR2_TO_R6_EMULATOR
 static int mipsr2_emulation;
-static __maybe_unused int mipsr2_decoder(struct pt_regs *regs, u32 inst) { return 0; };
+static inline int mipsr2_decoder(struct pt_regs *regs, u32 inst,
+                                 unsigned long *fcr31)
+{
+        return 0;
+};
 #else
 /* MIPS R2 Emulator ON/OFF */
 extern int mipsr2_emulation;
-extern int mipsr2_decoder(struct pt_regs *regs, u32 inst);
+extern int mipsr2_decoder(struct pt_regs *regs, u32 inst,
+                          unsigned long *fcr31);
 #endif /* CONFIG_MIPSR2_TO_R6_EMULATOR */
 #define NO_R6EMU        (cpu_has_mips_r6 && !mipsr2_emulation)
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index fef004434096..764e2756b54d 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -111,70 +111,6 @@
 */
 #define CP0_TX39_CACHE  $7
-/*
- * Coprocessor 1 (FPU) register names
- */
-#define CP1_REVISION   $0
-#define CP1_STATUS     $31
-/*
- * FPU Status Register Values
- */
-/*
- * Status Register Values
- */
-#define FPU_CSR_FLUSH   0x01000000      /* flush denormalised results to 0 */
-#define FPU_CSR_COND    0x00800000      /* $fcc0 */
-#define FPU_CSR_COND0   0x00800000      /* $fcc0 */
-#define FPU_CSR_COND1   0x02000000      /* $fcc1 */
-#define FPU_CSR_COND2   0x04000000      /* $fcc2 */
-#define FPU_CSR_COND3   0x08000000      /* $fcc3 */
-#define FPU_CSR_COND4   0x10000000      /* $fcc4 */
-#define FPU_CSR_COND5   0x20000000      /* $fcc5 */
-#define FPU_CSR_COND6   0x40000000      /* $fcc6 */
-#define FPU_CSR_COND7   0x80000000      /* $fcc7 */
-/*
- * Bits 18 - 20 of the FPU Status Register will be read as 0,
- * and should be written as zero.
- */
-#define FPU_CSR_RSVD    0x001c0000
-/*
- * X the exception cause indicator
- * E the exception enable
- * S the sticky/flag bit
-*/
-#define FPU_CSR_ALL_X   0x0003f000
-#define FPU_CSR_UNI_X   0x00020000
-#define FPU_CSR_INV_X   0x00010000
-#define FPU_CSR_DIV_X   0x00008000
-#define FPU_CSR_OVF_X   0x00004000
-#define FPU_CSR_UDF_X   0x00002000
-#define FPU_CSR_INE_X   0x00001000
-#define FPU_CSR_ALL_E   0x00000f80
-#define FPU_CSR_INV_E   0x00000800
-#define FPU_CSR_DIV_E   0x00000400
-#define FPU_CSR_OVF_E   0x00000200
-#define FPU_CSR_UDF_E   0x00000100
-#define FPU_CSR_INE_E   0x00000080
-#define FPU_CSR_ALL_S   0x0000007c
-#define FPU_CSR_INV_S   0x00000040
-#define FPU_CSR_DIV_S   0x00000020
-#define FPU_CSR_OVF_S   0x00000010
-#define FPU_CSR_UDF_S   0x00000008
-#define FPU_CSR_INE_S   0x00000004
-/* Bits 0 and 1 of FPU Status Register specify the rounding mode */
-#define FPU_CSR_RM      0x00000003
-#define FPU_CSR_RN      0x0     /* nearest */
-#define FPU_CSR_RZ      0x1     /* towards zero */
-#define FPU_CSR_RU      0x2     /* towards +Infinity */
-#define FPU_CSR_RD      0x3     /* towards -Infinity */
 /*
 * Values for PageMask register
@@ -341,39 +277,6 @@
 #define ST0_MX                  0x01000000
 /*
- * Bitfields in the TX39 family CP0 Configuration Register 3
- */
-#define TX39_CONF_ICS_SHIFT     19
-#define TX39_CONF_ICS_MASK      0x00380000
-#define TX39_CONF_ICS_1KB       0x00000000
-#define TX39_CONF_ICS_2KB       0x00080000
-#define TX39_CONF_ICS_4KB       0x00100000
-#define TX39_CONF_ICS_8KB       0x00180000
-#define TX39_CONF_ICS_16KB      0x00200000
-#define TX39_CONF_DCS_SHIFT     16
-#define TX39_CONF_DCS_MASK      0x00070000
-#define TX39_CONF_DCS_1KB       0x00000000
-#define TX39_CONF_DCS_2KB       0x00010000
-#define TX39_CONF_DCS_4KB       0x00020000
-#define TX39_CONF_DCS_8KB       0x00030000
-#define TX39_CONF_DCS_16KB      0x00040000
-#define TX39_CONF_CWFON         0x00004000
-#define TX39_CONF_WBON          0x00002000
-#define TX39_CONF_RF_SHIFT      10
-#define TX39_CONF_RF_MASK       0x00000c00
-#define TX39_CONF_DOZE          0x00000200
-#define TX39_CONF_HALT          0x00000100
-#define TX39_CONF_LOCK          0x00000080
-#define TX39_CONF_ICE           0x00000020
-#define TX39_CONF_DCE           0x00000010
-#define TX39_CONF_IRSIZE_SHIFT  2
-#define TX39_CONF_IRSIZE_MASK   0x0000000c
-#define TX39_CONF_DRSIZE_SHIFT  0
-#define TX39_CONF_DRSIZE_MASK   0x00000003
-/*
 * Status register bits available in all MIPS CPUs.
 */
 #define ST0_IM                  0x0000ff00
@@ -425,9 +328,9 @@
 /*
 * Bitfields and bit numbers in the coprocessor 0 IntCtl register. (MIPSR2)
- *
- * Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
 */
+#define INTCTLB_IPFDC           23
+#define INTCTLF_IPFDC           (_ULCAST_(7) << INTCTLB_IPFDC)
 #define INTCTLB_IPPCI           26
 #define INTCTLF_IPPCI           (_ULCAST_(7) << INTCTLB_IPPCI)
 #define INTCTLB_IPTI            29
@@ -438,10 +341,10 @@
 *
 * Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
 */
-#define  CAUSEB_EXCCODE         2
+#define CAUSEB_EXCCODE          2
-#define  CAUSEF_EXCCODE         (_ULCAST_(31)  <<  2)
+#define CAUSEF_EXCCODE          (_ULCAST_(31)  <<  2)
-#define  CAUSEB_IP              8
+#define CAUSEB_IP               8
-#define  CAUSEF_IP              (_ULCAST_(255) <<  8)
+#define CAUSEF_IP               (_ULCAST_(255) <<  8)
 #define  CAUSEB_IP0             8
 #define  CAUSEF_IP0             (_ULCAST_(1)   <<  8)
 #define  CAUSEB_IP1             9
@@ -458,16 +361,18 @@
 #define  CAUSEF_IP6             (_ULCAST_(1)   << 14)
 #define  CAUSEB_IP7             15
 #define  CAUSEF_IP7             (_ULCAST_(1)   << 15)
-#define  CAUSEB_IV              23
+#define CAUSEB_FDCI             21
-#define  CAUSEF_IV              (_ULCAST_(1)   << 23)
+#define CAUSEF_FDCI             (_ULCAST_(1)   << 21)
-#define  CAUSEB_PCI             26
+#define CAUSEB_IV               23
-#define  CAUSEF_PCI             (_ULCAST_(1)   << 26)
+#define CAUSEF_IV               (_ULCAST_(1)   << 23)
-#define  CAUSEB_CE              28
+#define CAUSEB_PCI              26
-#define  CAUSEF_CE              (_ULCAST_(3)   << 28)
+#define CAUSEF_PCI              (_ULCAST_(1)   << 26)
-#define  CAUSEB_TI              30
+#define CAUSEB_CE               28
-#define  CAUSEF_TI              (_ULCAST_(1)   << 30)
+#define CAUSEF_CE               (_ULCAST_(3)   << 28)
-#define  CAUSEB_BD              31
+#define CAUSEB_TI               30
-#define  CAUSEF_BD              (_ULCAST_(1)   << 31)
+#define CAUSEF_TI               (_ULCAST_(1)   << 30)
+#define CAUSEB_BD               31
+#define CAUSEF_BD               (_ULCAST_(1)   << 31)
 /*
 * Bits in the coprocessor 0 config register.
@@ -689,18 +594,6 @@
 #define MIPS_CMGCRF_BASE        (~_ULCAST_((1 << MIPS_CMGCRB_BASE) - 1))
 /*
- * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
- */
-#define MIPS_FPIR_S             (_ULCAST_(1) << 16)
-#define MIPS_FPIR_D             (_ULCAST_(1) << 17)
-#define MIPS_FPIR_PS            (_ULCAST_(1) << 18)
-#define MIPS_FPIR_3D            (_ULCAST_(1) << 19)
-#define MIPS_FPIR_W             (_ULCAST_(1) << 20)
-#define MIPS_FPIR_L             (_ULCAST_(1) << 21)
-#define MIPS_FPIR_F64           (_ULCAST_(1) << 22)
-#define MIPS_FPIR_FREP          (_ULCAST_(1) << 29)
-/*
 * Bits in the MIPS32 Memory Segmentation registers.
 */
 #define MIPS_SEGCFG_PA_SHIFT    9
@@ -751,6 +644,172 @@
 #define MIPS_PWCTL_PSN_SHIFT    0
 #define MIPS_PWCTL_PSN_MASK     0x0000003f
+/* CDMMBase register bit definitions */
+#define MIPS_CDMMBASE_SIZE_SHIFT 0
+#define MIPS_CDMMBASE_SIZE      (_ULCAST_(511) << MIPS_CDMMBASE_SIZE_SHIFT)
+#define MIPS_CDMMBASE_CI        (_ULCAST_(1) << 9)
+#define MIPS_CDMMBASE_EN        (_ULCAST_(1) << 10)
+#define MIPS_CDMMBASE_ADDR_SHIFT 11
+#define MIPS_CDMMBASE_ADDR_START 15
+/*
+ * Bitfields in the TX39 family CP0 Configuration Register 3
+ */
+#define TX39_CONF_ICS_SHIFT     19
+#define TX39_CONF_ICS_MASK      0x00380000
+#define TX39_CONF_ICS_1KB       0x00000000
+#define TX39_CONF_ICS_2KB       0x00080000
+#define TX39_CONF_ICS_4KB       0x00100000
+#define TX39_CONF_ICS_8KB       0x00180000
+#define TX39_CONF_ICS_16KB      0x00200000
+#define TX39_CONF_DCS_SHIFT     16
+#define TX39_CONF_DCS_MASK      0x00070000
+#define TX39_CONF_DCS_1KB       0x00000000
+#define TX39_CONF_DCS_2KB       0x00010000
+#define TX39_CONF_DCS_4KB       0x00020000
+#define TX39_CONF_DCS_8KB       0x00030000
+#define TX39_CONF_DCS_16KB      0x00040000
+#define TX39_CONF_CWFON         0x00004000
+#define TX39_CONF_WBON          0x00002000
+#define TX39_CONF_RF_SHIFT      10
+#define TX39_CONF_RF_MASK       0x00000c00
+#define TX39_CONF_DOZE          0x00000200
+#define TX39_CONF_HALT          0x00000100
+#define TX39_CONF_LOCK          0x00000080
+#define TX39_CONF_ICE           0x00000020
+#define TX39_CONF_DCE           0x00000010
+#define TX39_CONF_IRSIZE_SHIFT  2
+#define TX39_CONF_IRSIZE_MASK   0x0000000c
+#define TX39_CONF_DRSIZE_SHIFT  0
+#define TX39_CONF_DRSIZE_MASK   0x00000003
+/*
+ * Coprocessor 1 (FPU) register names
+ */
+#define CP1_REVISION    $0
+#define CP1_UFR         $1
+#define CP1_UNFR        $4
+#define CP1_FCCR        $25
+#define CP1_FEXR        $26
+#define CP1_FENR        $28
+#define CP1_STATUS      $31
+/*
+ * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
+ */
+#define MIPS_FPIR_S             (_ULCAST_(1) << 16)
+#define MIPS_FPIR_D             (_ULCAST_(1) << 17)
+#define MIPS_FPIR_PS            (_ULCAST_(1) << 18)
+#define MIPS_FPIR_3D            (_ULCAST_(1) << 19)
+#define MIPS_FPIR_W             (_ULCAST_(1) << 20)
+#define MIPS_FPIR_L             (_ULCAST_(1) << 21)
+#define MIPS_FPIR_F64           (_ULCAST_(1) << 22)
+#define MIPS_FPIR_HAS2008       (_ULCAST_(1) << 23)
+#define MIPS_FPIR_UFRP          (_ULCAST_(1) << 28)
+#define MIPS_FPIR_FREP          (_ULCAST_(1) << 29)
+/*
+ * Bits in the MIPS32/64 coprocessor 1 (FPU) condition codes register.
+ */
+#define MIPS_FCCR_CONDX_S       0
+#define MIPS_FCCR_CONDX         (_ULCAST_(255) << MIPS_FCCR_CONDX_S)
+#define MIPS_FCCR_COND0_S       0
+#define MIPS_FCCR_COND0         (_ULCAST_(1) << MIPS_FCCR_COND0_S)
+#define MIPS_FCCR_COND1_S       1
+#define MIPS_FCCR_COND1         (_ULCAST_(1) << MIPS_FCCR_COND1_S)
+#define MIPS_FCCR_COND2_S       2
+#define MIPS_FCCR_COND2         (_ULCAST_(1) << MIPS_FCCR_COND2_S)
+#define MIPS_FCCR_COND3_S       3
+#define MIPS_FCCR_COND3         (_ULCAST_(1) << MIPS_FCCR_COND3_S)
+#define MIPS_FCCR_COND4_S       4
+#define MIPS_FCCR_COND4         (_ULCAST_(1) << MIPS_FCCR_COND4_S)
+#define MIPS_FCCR_COND5_S       5
+#define MIPS_FCCR_COND5         (_ULCAST_(1) << MIPS_FCCR_COND5_S)
+#define MIPS_FCCR_COND6_S       6
+#define MIPS_FCCR_COND6         (_ULCAST_(1) << MIPS_FCCR_COND6_S)
+#define MIPS_FCCR_COND7_S       7
+#define MIPS_FCCR_COND7         (_ULCAST_(1) << MIPS_FCCR_COND7_S)
+/*
+ * Bits in the MIPS32/64 coprocessor 1 (FPU) enables register.
+ */
+#define MIPS_FENR_FS_S          2
+#define MIPS_FENR_FS            (_ULCAST_(1) << MIPS_FENR_FS_S)
+/*
+ * FPU Status Register Values
+ */
+#define FPU_CSR_COND_S  23                                      /* $fcc0 */
+#define FPU_CSR_COND    (_ULCAST_(1) << FPU_CSR_COND_S)
+#define FPU_CSR_FS_S    24              /* flush denormalised results to 0 */
+#define FPU_CSR_FS      (_ULCAST_(1) << FPU_CSR_FS_S)
+#define FPU_CSR_CONDX_S 25                                      /* $fcc[7:1] */
+#define FPU_CSR_CONDX   (_ULCAST_(127) << FPU_CSR_CONDX_S)
+#define FPU_CSR_COND1_S 25                                      /* $fcc1 */
+#define FPU_CSR_COND1   (_ULCAST_(1) << FPU_CSR_COND1_S)
+#define FPU_CSR_COND2_S 26                                      /* $fcc2 */
+#define FPU_CSR_COND2   (_ULCAST_(1) << FPU_CSR_COND2_S)
+#define FPU_CSR_COND3_S 27                                      /* $fcc3 */
+#define FPU_CSR_COND3   (_ULCAST_(1) << FPU_CSR_COND3_S)
+#define FPU_CSR_COND4_S 28                                      /* $fcc4 */
+#define FPU_CSR_COND4   (_ULCAST_(1) << FPU_CSR_COND4_S)
+#define FPU_CSR_COND5_S 29                                      /* $fcc5 */
+#define FPU_CSR_COND5   (_ULCAST_(1) << FPU_CSR_COND5_S)
+#define FPU_CSR_COND6_S 30                                      /* $fcc6 */
+#define FPU_CSR_COND6   (_ULCAST_(1) << FPU_CSR_COND6_S)
+#define FPU_CSR_COND7_S 31                                      /* $fcc7 */
+#define FPU_CSR_COND7   (_ULCAST_(1) << FPU_CSR_COND7_S)
+/*
+ * Bits 22:20 of the FPU Status Register will be read as 0,
+ * and should be written as zero.
+ */
+#define FPU_CSR_RSVD    (_ULCAST_(7) << 20)
+#define FPU_CSR_ABS2008 (_ULCAST_(1) << 19)
+#define FPU_CSR_NAN2008 (_ULCAST_(1) << 18)
+/*
+ * X the exception cause indicator
+ * E the exception enable
+ * S the sticky/flag bit
+*/
+#define FPU_CSR_ALL_X   0x0003f000
+#define FPU_CSR_UNI_X   0x00020000
+#define FPU_CSR_INV_X   0x00010000
+#define FPU_CSR_DIV_X   0x00008000
+#define FPU_CSR_OVF_X   0x00004000
+#define FPU_CSR_UDF_X   0x00002000
+#define FPU_CSR_INE_X   0x00001000
+#define FPU_CSR_ALL_E   0x00000f80
+#define FPU_CSR_INV_E   0x00000800
+#define FPU_CSR_DIV_E   0x00000400
+#define FPU_CSR_OVF_E   0x00000200
+#define FPU_CSR_UDF_E   0x00000100
+#define FPU_CSR_INE_E   0x00000080
+#define FPU_CSR_ALL_S   0x0000007c
+#define FPU_CSR_INV_S   0x00000040
+#define FPU_CSR_DIV_S   0x00000020
+#define FPU_CSR_OVF_S   0x00000010
+#define FPU_CSR_UDF_S   0x00000008
+#define FPU_CSR_INE_S   0x00000004
+/* Bits 0 and 1 of FPU Status Register specify the rounding mode */
+#define FPU_CSR_RM      0x00000003
+#define FPU_CSR_RN      0x0     /* nearest */
+#define FPU_CSR_RZ      0x1     /* towards zero */
+#define FPU_CSR_RU      0x2     /* towards +Infinity */
+#define FPU_CSR_RD      0x3     /* towards -Infinity */
 #ifndef __ASSEMBLY__
 /*
@@ -1282,6 +1341,9 @@ do {									\
 #define read_c0_ebase()         __read_32bit_c0_register($15, 1)
 #define write_c0_ebase(val)     __write_32bit_c0_register($15, 1, val)
+#define read_c0_cdmmbase()      __read_ulong_c0_register($15, 2)
+#define write_c0_cdmmbase(val)  __write_ulong_c0_register($15, 2, val)
 /* MIPSR3 */
 #define read_c0_segctl0()       __read_32bit_c0_register($5, 2)
 #define write_c0_segctl0(val)   __write_32bit_c0_register($5, 2, val)
diff --git a/arch/mips/include/asm/netlogic/common.h b/arch/mips/include/asm/netlogic/common.h
index c281f03eb312..2a4c128277e4 100644
--- a/arch/mips/include/asm/netlogic/common.h
+++ b/arch/mips/include/asm/netlogic/common.h
@@ -111,6 +111,25 @@ static inline int nlm_irq_to_xirq(int node, int irq)
        return node * NR_IRQS / NLM_NR_NODES + irq;
 }
-extern int nlm_cpu_ready[];
+#ifdef CONFIG_CPU_XLR
+#define nlm_cores_per_node()    8
+#else
+static inline int nlm_cores_per_node(void)
+{
+        return ((read_c0_prid() & PRID_IMP_MASK)
+                                == PRID_IMP_NETLOGIC_XLP9XX) ? 32 : 8;
+}
 #endif
+static inline int nlm_threads_per_node(void)
+{
+        return nlm_cores_per_node() * NLM_THREADS_PER_CORE;
+}
+static inline int nlm_hwtid_to_node(int hwtid)
+{
+        return hwtid / nlm_threads_per_node();
+}
+extern int nlm_cpu_ready[];
+#endif /* __ASSEMBLY__ */
 #endif /* _NETLOGIC_COMMON_H_ */
diff --git a/arch/mips/include/asm/netlogic/mips-extns.h b/arch/mips/include/asm/netlogic/mips-extns.h
index 06f1f75bfa9b..788baf399e69 100644
--- a/arch/mips/include/asm/netlogic/mips-extns.h
+++ b/arch/mips/include/asm/netlogic/mips-extns.h
@@ -157,7 +157,13 @@ static inline int nlm_nodeid(void)
 static inline unsigned int nlm_core_id(void)
 {
-        return (read_c0_ebase() & 0x1c) >> 2;
+        uint32_t prid = read_c0_prid() & PRID_IMP_MASK;
+        if ((prid == PRID_IMP_NETLOGIC_XLP9XX) ||
+                        (prid == PRID_IMP_NETLOGIC_XLP5XX))
+                return (read_c0_ebase() & 0x7c) >> 2;
+        else
+                return (read_c0_ebase() & 0x1c) >> 2;
 }
 static inline unsigned int nlm_thread_id(void)
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h b/arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h
index 6d2e58a9a542..a06b59292153 100644
--- a/arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h
+++ b/arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h
@@ -46,6 +46,8 @@
 #define CPU_BLOCKID_FPU         9
 #define CPU_BLOCKID_MAP         10
+#define IFU_BRUB_RESERVE        0x007
 #define ICU_DEFEATURE           0x100
 #define LSU_DEFEATURE           0x304
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/sys.h b/arch/mips/include/asm/netlogic/xlp-hal/sys.h
index bc7bddf25be9..6bcf3952e556 100644
--- a/arch/mips/include/asm/netlogic/xlp-hal/sys.h
+++ b/arch/mips/include/asm/netlogic/xlp-hal/sys.h
@@ -177,6 +177,9 @@
 #define SYS_9XX_CLK_DEV_DIV                     0x18d
 #define SYS_9XX_CLK_DEV_CHG                     0x18f
+#define SYS_9XX_CLK_DEV_SEL_REG                 0x1a4
+#define SYS_9XX_CLK_DEV_DIV_REG                 0x1a6
 /* Registers changed on 9XX */
 #define SYS_9XX_POWER_ON_RESET_CFG              0x00
 #define SYS_9XX_CHIP_RESET                      0x01
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/xlp.h b/arch/mips/include/asm/netlogic/xlp-hal/xlp.h
index a862b93223cc..feb6ed807ec6 100644
--- a/arch/mips/include/asm/netlogic/xlp-hal/xlp.h
+++ b/arch/mips/include/asm/netlogic/xlp-hal/xlp.h
@@ -52,6 +52,7 @@
 #define PIC_2XX_XHCI_2_IRQ              25
 #define PIC_9XX_XHCI_0_IRQ              23
 #define PIC_9XX_XHCI_1_IRQ              24
+#define PIC_9XX_XHCI_2_IRQ              25
 #define PIC_MMC_IRQ                     29
 #define PIC_I2C_0_IRQ                   30
@@ -89,7 +90,7 @@ void xlp_wakeup_secondary_cpus(void);
 void xlp_mmu_init(void);
 void nlm_hal_init(void);
-int xlp_get_dram_map(int n, uint64_t *dram_map);
+int nlm_get_dram_map(int node, uint64_t *dram_map, int nentries);
 struct pci_dev;
 int xlp_socdev_to_node(const struct pci_dev *dev);
diff --git a/arch/mips/include/asm/octeon/cvmx-address.h b/arch/mips/include/asm/octeon/cvmx-address.h
index e2d874e681f6..e4444f8c4a61 100644
--- a/arch/mips/include/asm/octeon/cvmx-address.h
+++ b/arch/mips/include/asm/octeon/cvmx-address.h
@@ -104,6 +104,7 @@ typedef enum {
 typedef union {
        uint64_t u64;
+#ifdef __BIG_ENDIAN_BITFIELD
        /* mapped or unmapped virtual address */
        struct {
                uint64_t R:2;
@@ -202,6 +203,72 @@ typedef union {
                uint64_t didspace:24;
                uint64_t unused:40;
        } sfilldidspace;
+#else
+        struct {
+                uint64_t offset:62;
+                uint64_t R:2;
+        } sva;
+        struct {
+                uint64_t offset:31;
+                uint64_t zeroes:33;
+        } suseg;
+        struct {
+                uint64_t offset:29;
+                uint64_t sp:2;
+                uint64_t ones:33;
+        } sxkseg;
+        struct {
+                uint64_t pa:49;
+                uint64_t mbz:10;
+                uint64_t cca:3;
+                uint64_t R:2;
+        } sxkphys;
+        struct {
+                uint64_t offset:36;
+                uint64_t unaddr:4;
+                uint64_t did:8;
+                uint64_t is_io:1;
+                uint64_t mbz:15;
+        } sphys;
+        struct {
+                uint64_t offset:36;
+                uint64_t unaddr:4;
+                uint64_t zeroes:24;
+        } smem;
+        struct {
+                uint64_t offset:36;
+                uint64_t unaddr:4;
+                uint64_t did:8;
+                uint64_t is_io:1;
+                uint64_t mbz:13;
+                uint64_t mem_region:2;
+        } sio;
+        struct {
+                uint64_t addr:13;
+                cvmx_add_win_dec_t csrdec:2;
+                uint64_t ones:49;
+        } sscr;
+        struct {
+                uint64_t addr:7;
+                uint64_t type:3;
+                uint64_t unused2:3;
+                uint64_t csrdec:2;
+                uint64_t ones:49;
+        } sdma;
+        struct {
+                uint64_t unused:40;
+                uint64_t didspace:24;
+        } sfilldidspace;
+#endif
 } cvmx_addr_t;
diff --git a/arch/mips/include/asm/octeon/cvmx-bootinfo.h b/arch/mips/include/asm/octeon/cvmx-bootinfo.h
index 2298199a287e..c373d95b5e2c 100644
--- a/arch/mips/include/asm/octeon/cvmx-bootinfo.h
+++ b/arch/mips/include/asm/octeon/cvmx-bootinfo.h
@@ -53,6 +53,7 @@
 * to 0.
 */
 struct cvmx_bootinfo {
+#ifdef __BIG_ENDIAN_BITFIELD
        uint32_t major_version;
        uint32_t minor_version;
@@ -123,6 +124,60 @@ struct cvmx_bootinfo {
         */
        uint64_t fdt_addr;
 #endif
+#else                           /* __BIG_ENDIAN */
+        /*
+         * Little-Endian: When the CPU mode is switched to
+         * little-endian, the view of the structure has some of the
+         * fields swapped.
+         */
+        uint32_t minor_version;
+        uint32_t major_version;
+        uint64_t stack_top;
+        uint64_t heap_base;
+        uint64_t heap_end;
+        uint64_t desc_vaddr;
+        uint32_t stack_size;
+        uint32_t exception_base_addr;
+        uint32_t core_mask;
+        uint32_t flags;
+        uint32_t phy_mem_desc_addr;
+        uint32_t dram_size;
+        uint32_t eclock_hz;
+        uint32_t debugger_flags_base_addr;
+        uint32_t reserved0;
+        uint32_t dclock_hz;
+        uint8_t reserved3;
+        uint8_t reserved2;
+        uint16_t reserved1;
+        uint8_t board_rev_minor;
+        uint8_t board_rev_major;
+        uint16_t board_type;
+        char board_serial_number[CVMX_BOOTINFO_OCTEON_SERIAL_LEN];
+        uint8_t mac_addr_base[6];
+        uint8_t mac_addr_count;
+        uint8_t pad[5];
+#if (CVMX_BOOTINFO_MIN_VER >= 1)
+        uint64_t compact_flash_common_base_addr;
+        uint64_t compact_flash_attribute_base_addr;
+        uint64_t led_display_base_addr;
+#endif
+#if (CVMX_BOOTINFO_MIN_VER >= 2)
+        uint32_t config_flags;
+        uint32_t dfa_ref_clock_hz;
+#endif
+#if (CVMX_BOOTINFO_MIN_VER >= 3)
+        uint64_t fdt_addr;
+#endif
+#endif
 };
 #define CVMX_BOOTINFO_CFG_FLAG_PCI_HOST                 (1ull << 0)
diff --git a/arch/mips/include/asm/octeon/cvmx-bootmem.h b/arch/mips/include/asm/octeon/cvmx-bootmem.h
index 352f1dc2508b..374562507d0b 100644
--- a/arch/mips/include/asm/octeon/cvmx-bootmem.h
+++ b/arch/mips/include/asm/octeon/cvmx-bootmem.h
@@ -95,6 +95,7 @@ struct cvmx_bootmem_named_block_desc {
 * positions for backwards compatibility.
 */
 struct cvmx_bootmem_desc {
+#if defined(__BIG_ENDIAN_BITFIELD) || defined(CVMX_BUILD_FOR_LINUX_HOST)
        /* spinlock to control access to list */
        uint32_t lock;
        /* flags for indicating various conditions */
@@ -120,7 +121,20 @@ struct cvmx_bootmem_desc {
        uint32_t named_block_name_len;
        /* address of named memory block descriptors */
        uint64_t named_block_array_addr;
+#else                           /* __LITTLE_ENDIAN */
+        uint32_t flags;
+        uint32_t lock;
+        uint64_t head_addr;
+        uint32_t minor_version;
+        uint32_t major_version;
+        uint64_t app_data_addr;
+        uint64_t app_data_size;
+        uint32_t named_block_name_len;
+        uint32_t named_block_num_blocks;
+        uint64_t named_block_array_addr;
+#endif
 };
 /**
diff --git a/arch/mips/include/asm/octeon/cvmx-fau.h b/arch/mips/include/asm/octeon/cvmx-fau.h
index ef98f7fc102f..dafeae300c97 100644
--- a/arch/mips/include/asm/octeon/cvmx-fau.h
+++ b/arch/mips/include/asm/octeon/cvmx-fau.h
@@ -105,6 +105,16 @@ typedef union {
        } s;
 } cvmx_fau_async_tagwait_result_t;
+#ifdef __BIG_ENDIAN_BITFIELD
+#define SWIZZLE_8  0
+#define SWIZZLE_16 0
+#define SWIZZLE_32 0
+#else
+#define SWIZZLE_8  0x7
+#define SWIZZLE_16 0x6
+#define SWIZZLE_32 0x4
+#endif
 /**
 * Builds a store I/O address for writing to the FAU
 *
@@ -175,6 +185,7 @@ static inline int64_t cvmx_fau_fetch_and_add64(cvmx_fau_reg_64_t reg,
 static inline int32_t cvmx_fau_fetch_and_add32(cvmx_fau_reg_32_t reg,
                                               int32_t value)
 {
+        reg ^= SWIZZLE_32;
        return cvmx_read64_int32(__cvmx_fau_atomic_address(0, reg, value));
 }
@@ -189,6 +200,7 @@ static inline int32_t cvmx_fau_fetch_and_add32(cvmx_fau_reg_32_t reg,
 static inline int16_t cvmx_fau_fetch_and_add16(cvmx_fau_reg_16_t reg,
                                               int16_t value)
 {
+        reg ^= SWIZZLE_16;
        return cvmx_read64_int16(__cvmx_fau_atomic_address(0, reg, value));
 }
@@ -201,6 +213,7 @@ static inline int16_t cvmx_fau_fetch_and_add16(cvmx_fau_reg_16_t reg,
 */
 static inline int8_t cvmx_fau_fetch_and_add8(cvmx_fau_reg_8_t reg, int8_t value)
 {
+        reg ^= SWIZZLE_8;
        return cvmx_read64_int8(__cvmx_fau_atomic_address(0, reg, value));
 }
@@ -247,6 +260,7 @@ cvmx_fau_tagwait_fetch_and_add32(cvmx_fau_reg_32_t reg, int32_t value)
                uint64_t i32;
                cvmx_fau_tagwait32_t t;
        } result;
+        reg ^= SWIZZLE_32;
        result.i32 =
            cvmx_read64_int32(__cvmx_fau_atomic_address(1, reg, value));
        return result.t;
@@ -270,6 +284,7 @@ cvmx_fau_tagwait_fetch_and_add16(cvmx_fau_reg_16_t reg, int16_t value)
                uint64_t i16;
                cvmx_fau_tagwait16_t t;
        } result;
+        reg ^= SWIZZLE_16;
        result.i16 =
            cvmx_read64_int16(__cvmx_fau_atomic_address(1, reg, value));
        return result.t;
@@ -292,6 +307,7 @@ cvmx_fau_tagwait_fetch_and_add8(cvmx_fau_reg_8_t reg, int8_t value)
                uint64_t i8;
                cvmx_fau_tagwait8_t t;
        } result;
+        reg ^= SWIZZLE_8;
        result.i8 = cvmx_read64_int8(__cvmx_fau_atomic_address(1, reg, value));
        return result.t;
 }
@@ -521,6 +537,7 @@ static inline void cvmx_fau_atomic_add64(cvmx_fau_reg_64_t reg, int64_t value)
 */
 static inline void cvmx_fau_atomic_add32(cvmx_fau_reg_32_t reg, int32_t value)
 {
+        reg ^= SWIZZLE_32;
        cvmx_write64_int32(__cvmx_fau_store_address(0, reg), value);
 }
@@ -533,6 +550,7 @@ static inline void cvmx_fau_atomic_add32(cvmx_fau_reg_32_t reg, int32_t value)
 */
 static inline void cvmx_fau_atomic_add16(cvmx_fau_reg_16_t reg, int16_t value)
 {
+        reg ^= SWIZZLE_16;
        cvmx_write64_int16(__cvmx_fau_store_address(0, reg), value);
 }
@@ -544,6 +562,7 @@ static inline void cvmx_fau_atomic_add16(cvmx_fau_reg_16_t reg, int16_t value)
 */
 static inline void cvmx_fau_atomic_add8(cvmx_fau_reg_8_t reg, int8_t value)
 {
+        reg ^= SWIZZLE_8;
        cvmx_write64_int8(__cvmx_fau_store_address(0, reg), value);
 }
@@ -568,6 +587,7 @@ static inline void cvmx_fau_atomic_write64(cvmx_fau_reg_64_t reg, int64_t value)
 */
 static inline void cvmx_fau_atomic_write32(cvmx_fau_reg_32_t reg, int32_t value)
 {
+        reg ^= SWIZZLE_32;
        cvmx_write64_int32(__cvmx_fau_store_address(1, reg), value);
 }
@@ -580,6 +600,7 @@ static inline void cvmx_fau_atomic_write32(cvmx_fau_reg_32_t reg, int32_t value)
 */
 static inline void cvmx_fau_atomic_write16(cvmx_fau_reg_16_t reg, int16_t value)
 {
+        reg ^= SWIZZLE_16;
        cvmx_write64_int16(__cvmx_fau_store_address(1, reg), value);
 }
@@ -591,6 +612,7 @@ static inline void cvmx_fau_atomic_write16(cvmx_fau_reg_16_t reg, int16_t value)
 */
 static inline void cvmx_fau_atomic_write8(cvmx_fau_reg_8_t reg, int8_t value)
 {
+        reg ^= SWIZZLE_8;
        cvmx_write64_int8(__cvmx_fau_store_address(1, reg), value);
 }
diff --git a/arch/mips/include/asm/octeon/cvmx-fpa.h b/arch/mips/include/asm/octeon/cvmx-fpa.h
index aa26a2ce5a0e..c00501d0f7ae 100644
--- a/arch/mips/include/asm/octeon/cvmx-fpa.h
+++ b/arch/mips/include/asm/octeon/cvmx-fpa.h
@@ -49,6 +49,7 @@
 typedef union {
        uint64_t u64;
        struct {
+#ifdef __BIG_ENDIAN_BITFIELD
                /*
                 * the (64-bit word) location in scratchpad to write
                 * to (if len != 0)
@@ -63,6 +64,12 @@ typedef union {
                 * the NCB bus.
                 */
                uint64_t addr:40;
+#else
+                uint64_t addr:40;
+                uint64_t did:8;
+                uint64_t len:8;
+                uint64_t scraddr:8;
+#endif
        } s;
 } cvmx_fpa_iobdma_data_t;
diff --git a/arch/mips/include/asm/octeon/cvmx-l2c.h b/arch/mips/include/asm/octeon/cvmx-l2c.h
index 11c0a8fa8eb5..ddb429210a0e 100644
--- a/arch/mips/include/asm/octeon/cvmx-l2c.h
+++ b/arch/mips/include/asm/octeon/cvmx-l2c.h
@@ -53,12 +53,21 @@
 union cvmx_l2c_tag {
        uint64_t u64;
        struct {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved:28;
                uint64_t V:1;           /* Line valid */
                uint64_t D:1;           /* Line dirty */
                uint64_t L:1;           /* Line locked */
                uint64_t U:1;           /* Use, LRU eviction */
                uint64_t addr:32;       /* Phys mem (not all bits valid) */
+#else
+                uint64_t addr:32;       /* Phys mem (not all bits valid) */
+                uint64_t U:1;           /* Use, LRU eviction */
+                uint64_t L:1;           /* Line locked */
+                uint64_t D:1;           /* Line dirty */
+                uint64_t V:1;           /* Line valid */
+                uint64_t reserved:28;
+#endif
        } s;
 };
diff --git a/arch/mips/include/asm/octeon/cvmx-packet.h b/arch/mips/include/asm/octeon/cvmx-packet.h
index 38aefa1bab9d..895e93d682c2 100644
--- a/arch/mips/include/asm/octeon/cvmx-packet.h
+++ b/arch/mips/include/asm/octeon/cvmx-packet.h
@@ -39,6 +39,7 @@ union cvmx_buf_ptr {
        void *ptr;
        uint64_t u64;
        struct {
+#ifdef __BIG_ENDIAN_BITFIELD
                /* if set, invert the "free" pick of the overall
                 * packet. HW always sets this bit to 0 on inbound
                 * packet */
@@ -55,6 +56,13 @@ union cvmx_buf_ptr {
                uint64_t size:16;
                /* Pointer to the first byte of the data, NOT buffer */
                uint64_t addr:40;
+#else
+                uint64_t addr:40;
+                uint64_t size:16;
+                uint64_t pool:3;
+                uint64_t back:4;
+                uint64_t i:1;
+#endif
        } s;
 };
diff --git a/arch/mips/include/asm/octeon/cvmx-pko.h b/arch/mips/include/asm/octeon/cvmx-pko.h
index f7d2a6718849..3da59bb8ce24 100644
--- a/arch/mips/include/asm/octeon/cvmx-pko.h
+++ b/arch/mips/include/asm/octeon/cvmx-pko.h
@@ -127,6 +127,7 @@ typedef struct {
 typedef union {
        uint64_t u64;
        struct {
+#ifdef __BIG_ENDIAN_BITFIELD
                /* Must CVMX_IO_SEG */
                uint64_t mem_space:2;
                /* Must be zero */
@@ -151,6 +152,17 @@ typedef union {
                uint64_t queue:9;
                /* Must be zero */
                uint64_t reserved4:3;
+#else
+                uint64_t reserved4:3;
+                uint64_t queue:9;
+                uint64_t port:9;
+                uint64_t reserved3:15;
+                uint64_t reserved2:4;
+                uint64_t did:8;
+                uint64_t is_io:1;
+                uint64_t reserved:13;
+                uint64_t mem_space:2;
+#endif
        } s;
 } cvmx_pko_doorbell_address_t;
@@ -160,6 +172,7 @@ typedef union {
 typedef union {
        uint64_t u64;
        struct {
+#ifdef __BIG_ENDIAN_BITFIELD
                /*
                 * The size of the reg1 operation - could be 8, 16,
                 * 32, or 64 bits.
@@ -229,6 +242,24 @@ typedef union {
                uint64_t segs:6;
                /* Including L2, but no trailing CRC */
                uint64_t total_bytes:16;
+#else
+                uint64_t total_bytes:16;
+                uint64_t segs:6;
+                uint64_t dontfree:1;
+                uint64_t ignore_i:1;
+                uint64_t ipoffp1:7;
+                uint64_t gather:1;
+                uint64_t rsp:1;
+                uint64_t wqp:1;
+                uint64_t n2:1;
+                uint64_t le:1;
+                uint64_t reg0:11;
+                uint64_t subone0:1;
+                uint64_t reg1:11;
+                uint64_t subone1:1;
+                uint64_t size0:2;
+                uint64_t size1:2;
+#endif
        } s;
 } cvmx_pko_command_word0_t;
diff --git a/arch/mips/include/asm/octeon/cvmx-pow.h b/arch/mips/include/asm/octeon/cvmx-pow.h
index 2188e65afb86..d5565d758ddd 100644
--- a/arch/mips/include/asm/octeon/cvmx-pow.h
+++ b/arch/mips/include/asm/octeon/cvmx-pow.h
@@ -178,6 +178,7 @@ typedef enum {
 typedef union {
        uint64_t u64;
        struct {
+#ifdef __BIG_ENDIAN_BITFIELD
                /*
                 * Don't reschedule this entry. no_sched is used for
                 * CVMX_POW_TAG_OP_SWTAG_DESCH and
@@ -217,6 +218,17 @@ typedef union {
                 * CVMX_POW_TAG_OP_*_NSCHED
                 */
                uint64_t tag:32;
+#else
+                uint64_t tag:32;
+                uint64_t type:3;
+                uint64_t grp:4;
+                uint64_t qos:3;
+                uint64_t unused2:2;
+                cvmx_pow_tag_op_t op:4;
+                uint64_t index:13;
+                uint64_t unused:2;
+                uint64_t no_sched:1;
+#endif
        } s;
 } cvmx_pow_tag_req_t;
@@ -230,6 +242,7 @@ typedef union {
     * Address for new work request loads (did<2:0> == 0)
     */
        struct {
+#ifdef __BIG_ENDIAN_BITFIELD
                /* Mips64 address region. Should be CVMX_IO_SEG */
                uint64_t mem_region:2;
                /* Must be zero */
@@ -247,12 +260,22 @@ typedef union {
                uint64_t wait:1;
                /* Must be zero */
                uint64_t reserved_0_2:3;
+#else
+                uint64_t reserved_0_2:3;
+                uint64_t wait:1;
+                uint64_t reserved_4_39:36;
+                uint64_t did:8;
+                uint64_t is_io:1;
+                uint64_t reserved_49_61:13;
+                uint64_t mem_region:2;
+#endif
        } swork;
    /**
     * Address for loads to get POW internal status
     */
        struct {
+#ifdef __BIG_ENDIAN_BITFIELD
                /* Mips64 address region. Should be CVMX_IO_SEG */
                uint64_t mem_region:2;
                /* Must be zero */
@@ -282,12 +305,25 @@ typedef union {
                uint64_t get_wqp:1;
                /* Must be zero */
                uint64_t reserved_0_2:3;
+#else
+                uint64_t reserved_0_2:3;
+                uint64_t get_wqp:1;
+                uint64_t get_cur:1;
+                uint64_t get_rev:1;
+                uint64_t coreid:4;
+                uint64_t reserved_10_39:30;
+                uint64_t did:8;
+                uint64_t is_io:1;
+                uint64_t reserved_49_61:13;
+                uint64_t mem_region:2;
+#endif
        } sstatus;
    /**
     * Address for memory loads to get POW internal state
     */
        struct {
+#ifdef __BIG_ENDIAN_BITFIELD
                /* Mips64 address region. Should be CVMX_IO_SEG */
                uint64_t mem_region:2;
                /* Must be zero */
@@ -314,12 +350,24 @@ typedef union {
                uint64_t get_wqp:1;
                /* Must be zero */
                uint64_t reserved_0_2:3;
+#else
+                uint64_t reserved_0_2:3;
+                uint64_t get_wqp:1;
+                uint64_t get_des:1;
+                uint64_t index:11;
+                uint64_t reserved_16_39:24;
+                uint64_t did:8;
+                uint64_t is_io:1;
+                uint64_t reserved_49_61:13;
+                uint64_t mem_region:2;
+#endif
        } smemload;
    /**
     * Address for index/pointer loads
     */
        struct {
+#ifdef __BIG_ENDIAN_BITFIELD
                /* Mips64 address region. Should be CVMX_IO_SEG */
                uint64_t mem_region:2;
                /* Must be zero */
@@ -366,6 +414,17 @@ typedef union {
                uint64_t get_rmt:1;
                /* Must be zero */
                uint64_t reserved_0_2:3;
+#else
+                uint64_t reserved_0_2:3;
+                uint64_t get_rmt:1;
+                uint64_t get_des_get_tail:1;
+                uint64_t qosgrp:4;
+                uint64_t reserved_9_39:31;
+                uint64_t did:8;
+                uint64_t is_io:1;
+                uint64_t reserved_49_61:13;
+                uint64_t mem_region:2;
+#endif
        } sindexload;
    /**
@@ -377,6 +436,7 @@ typedef union {
     * available.)
     */
        struct {
+#ifdef __BIG_ENDIAN_BITFIELD
                /* Mips64 address region. Should be CVMX_IO_SEG */
                uint64_t mem_region:2;
                /* Must be zero */
@@ -387,6 +447,13 @@ typedef union {
                uint64_t did:8;
                /* Must be zero */
                uint64_t reserved_0_39:40;
+#else
+                uint64_t reserved_0_39:40;
+                uint64_t did:8;
+                uint64_t is_io:1;
+                uint64_t reserved_49_61:13;
+                uint64_t mem_region:2;
+#endif
        } snull_rd;
 } cvmx_pow_load_addr_t;
@@ -401,6 +468,7 @@ typedef union {
     * Response to new work request loads
     */
        struct {
+#ifdef __BIG_ENDIAN_BITFIELD
                /*
                 * Set when no new work queue entry was returned.  *
                 * If there was de-scheduled work, the HW will
@@ -419,12 +487,18 @@ typedef union {
                uint64_t reserved_40_62:23;
                /* 36 in O1 -- the work queue pointer */
                uint64_t addr:40;
+#else
+                uint64_t addr:40;
+                uint64_t reserved_40_62:23;
+                uint64_t no_work:1;
+#endif
        } s_work;
    /**
     * Result for a POW Status Load (when get_cur==0 and get_wqp==0)
     */
        struct {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_62_63:2;
                /* Set when there is a pending non-NULL SWTAG or
                 * SWTAG_FULL, and the POW entry has not left the list
@@ -476,12 +550,32 @@ typedef union {
                 *    AND pend_desched_switch) are set.
                 */
                uint64_t pend_tag:32;
+#else
+                uint64_t pend_tag:32;
+                uint64_t pend_type:2;
+                uint64_t reserved_34_35:2;
+                uint64_t pend_grp:4;
+                uint64_t pend_index:11;
+                uint64_t reserved_51:1;
+                uint64_t pend_nosched_clr:1;
+                uint64_t pend_null_rd:1;
+                uint64_t pend_new_work_wait:1;
+                uint64_t pend_new_work:1;
+                uint64_t pend_nosched:1;
+                uint64_t pend_desched_switch:1;
+                uint64_t pend_desched:1;
+                uint64_t pend_switch_null:1;
+                uint64_t pend_switch_full:1;
+                uint64_t pend_switch:1;
+                uint64_t reserved_62_63:2;
+#endif
        } s_sstatus0;
    /**
     * Result for a POW Status Load (when get_cur==0 and get_wqp==1)
     */
        struct {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_62_63:2;
                /*
                 * Set when there is a pending non-NULL SWTAG or
@@ -529,6 +623,23 @@ typedef union {
                uint64_t pend_grp:4;
                /* This is the wqp when pend_nosched_clr is set. */
                uint64_t pend_wqp:36;
+#else
+                uint64_t pend_wqp:36;
+                uint64_t pend_grp:4;
+                uint64_t pend_index:11;
+                uint64_t reserved_51:1;
+                uint64_t pend_nosched_clr:1;
+                uint64_t pend_null_rd:1;
+                uint64_t pend_new_work_wait:1;
+                uint64_t pend_new_work:1;
+                uint64_t pend_nosched:1;
+                uint64_t pend_desched_switch:1;
+                uint64_t pend_desched:1;
+                uint64_t pend_switch_null:1;
+                uint64_t pend_switch_full:1;
+                uint64_t pend_switch:1;
+                uint64_t reserved_62_63:2;
+#endif
        } s_sstatus1;
    /**
@@ -536,6 +647,7 @@ typedef union {
     * get_rev==0)
     */
        struct {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_62_63:2;
                /*
                 * Points to the next POW entry in the tag list when
@@ -573,12 +685,23 @@ typedef union {
                 * SWTAG_DESCHED).
                 */
                uint64_t tag:32;
+#else
+                uint64_t tag:32;
+                uint64_t tag_type:2;
+                uint64_t tail:1;
+                uint64_t head:1;
+                uint64_t grp:4;
+                uint64_t index:11;
+                uint64_t link_index:11;
+                uint64_t reserved_62_63:2;
+#endif
        } s_sstatus2;
    /**
     * Result for a POW Status Load (when get_cur==1, get_wqp==0, and get_rev==1)
     */
        struct {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_62_63:2;
                /*
                 * Points to the prior POW entry in the tag list when
@@ -617,6 +740,16 @@ typedef union {
                 * SWTAG_DESCHED).
                 */
                uint64_t tag:32;
+#else
+                uint64_t tag:32;
+                uint64_t tag_type:2;
+                uint64_t tail:1;
+                uint64_t head:1;
+                uint64_t grp:4;
+                uint64_t index:11;
+                uint64_t revlink_index:11;
+                uint64_t reserved_62_63:2;
+#endif
        } s_sstatus3;
    /**
@@ -624,6 +757,7 @@ typedef union {
     * get_rev==0)
     */
        struct {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_62_63:2;
                /*
                 * Points to the next POW entry in the tag list when
@@ -642,6 +776,13 @@ typedef union {
                 * list entered on SWTAG_FULL).
                 */
                uint64_t wqp:36;
+#else
+                uint64_t wqp:36;
+                uint64_t grp:4;
+                uint64_t index:11;
+                uint64_t link_index:11;
+                uint64_t reserved_62_63:2;
+#endif
        } s_sstatus4;
    /**
@@ -649,6 +790,7 @@ typedef union {
     * get_rev==1)
     */
        struct {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_62_63:2;
                /*
                 * Points to the prior POW entry in the tag list when
@@ -669,12 +811,20 @@ typedef union {
                 * list entered on SWTAG_FULL).
                 */
                uint64_t wqp:36;
+#else
+                uint64_t wqp:36;
+                uint64_t grp:4;
+                uint64_t index:11;
+                uint64_t revlink_index:11;
+                uint64_t reserved_62_63:2;
+#endif
        } s_sstatus5;
    /**
     * Result For POW Memory Load (get_des == 0 and get_wqp == 0)
     */
        struct {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_51_63:13;
                /*
                 * The next entry in the input, free, descheduled_head
@@ -695,12 +845,22 @@ typedef union {
                uint64_t tag_type:2;
                /* The tag of the POW entry. */
                uint64_t tag:32;
+#else
+                uint64_t tag:32;
+                uint64_t tag_type:2;
+                uint64_t tail:1;
+                uint64_t reserved_35:1;
+                uint64_t grp:4;
+                uint64_t next_index:11;
+                uint64_t reserved_51_63:13;
+#endif
        } s_smemload0;
    /**
     * Result For POW Memory Load (get_des == 0 and get_wqp == 1)
     */
        struct {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_51_63:13;
                /*
                 * The next entry in the input, free, descheduled_head
@@ -712,12 +872,19 @@ typedef union {
                uint64_t grp:4;
                /* The WQP held in the POW entry. */
                uint64_t wqp:36;
+#else
+                uint64_t wqp:36;
+                uint64_t grp:4;
+                uint64_t next_index:11;
+                uint64_t reserved_51_63:13;
+#endif
        } s_smemload1;
    /**
     * Result For POW Memory Load (get_des == 1)
     */
        struct {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_51_63:13;
                /*
                 * The next entry in the tag list connected to the
@@ -740,12 +907,22 @@ typedef union {
                 * is set.
                 */
                uint64_t pend_tag:32;
+#else
+                uint64_t pend_tag:32;
+                uint64_t pend_type:2;
+                uint64_t pend_switch:1;
+                uint64_t nosched:1;
+                uint64_t grp:4;
+                uint64_t fwd_index:11;
+                uint64_t reserved_51_63:13;
+#endif
        } s_smemload2;
    /**
     * Result For POW Index/Pointer Load (get_rmt == 0/get_des_get_tail == 0)
     */
        struct {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_52_63:12;
                /*
                 * set when there is one or more POW entries on the
@@ -791,12 +968,28 @@ typedef union {
                 * the input Q list selected by qosgrp.
                 */
                uint64_t loc_tail:11;
+#else
+                uint64_t loc_tail:11;
+                uint64_t reserved_11:1;
+                uint64_t loc_head:11;
+                uint64_t reserved_23:1;
+                uint64_t loc_one:1;
+                uint64_t loc_val:1;
+                uint64_t free_tail:11;
+                uint64_t reserved_37:1;
+                uint64_t free_head:11;
+                uint64_t reserved_49:1;
+                uint64_t free_one:1;
+                uint64_t free_val:1;
+                uint64_t reserved_52_63:12;
+#endif
        } sindexload0;
    /**
     * Result For POW Index/Pointer Load (get_rmt == 0/get_des_get_tail == 1)
     */
        struct {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_52_63:12;
                /*
                 * set when there is one or more POW entries on the
@@ -843,12 +1036,28 @@ typedef union {
                 * head on the descheduled list selected by qosgrp.
                 */
                uint64_t des_tail:11;
+#else
+                uint64_t des_tail:11;
+                uint64_t reserved_11:1;
+                uint64_t des_head:11;
+                uint64_t reserved_23:1;
+                uint64_t des_one:1;
+                uint64_t des_val:1;
+                uint64_t nosched_tail:11;
+                uint64_t reserved_37:1;
+                uint64_t nosched_head:11;
+                uint64_t reserved_49:1;
+                uint64_t nosched_one:1;
+                uint64_t nosched_val:1;
+                uint64_t reserved_52_63:12;
+#endif
        } sindexload1;
    /**
     * Result For POW Index/Pointer Load (get_rmt == 1/get_des_get_tail == 0)
     */
        struct {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_39_63:25;
                /*
                 * Set when this DRAM list is the current head
@@ -877,6 +1086,13 @@ typedef union {
                 * qosgrp.
                 */
                uint64_t rmt_head:36;
+#else
+                uint64_t rmt_head:36;
+                uint64_t rmt_one:1;
+                uint64_t rmt_val:1;
+                uint64_t rmt_is_head:1;
+                uint64_t reserved_39_63:25;
+#endif
        } sindexload2;
    /**
@@ -884,6 +1100,7 @@ typedef union {
     * 1/get_des_get_tail == 1)
     */
        struct {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t reserved_39_63:25;
                /*
                 * set when this DRAM list is the current head
@@ -912,12 +1129,20 @@ typedef union {
                 * qosgrp.
                 */
                uint64_t rmt_tail:36;
+#else
+                uint64_t rmt_tail:36;
+                uint64_t rmt_one:1;
+                uint64_t rmt_val:1;
+                uint64_t rmt_is_head:1;
+                uint64_t reserved_39_63:25;
+#endif
        } sindexload3;
    /**
     * Response to NULL_RD request loads
     */
        struct {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t unused:62;
                /* of type cvmx_pow_tag_type_t. state is one of the
                 * following:
@@ -928,6 +1153,10 @@ typedef union {
                 * - CVMX_POW_TAG_TYPE_NULL_NULL
                 */
                uint64_t state:2;
+#else
+                uint64_t state:2;
+                uint64_t unused:62;
+#endif
        } s_null_rd;
 } cvmx_pow_tag_load_resp_t;
@@ -962,6 +1191,7 @@ typedef union {
        uint64_t u64;
        struct {
+#ifdef __BIG_ENDIAN_BITFIELD
                /* Memory region.  Should be CVMX_IO_SEG in most cases */
                uint64_t mem_reg:2;
                uint64_t reserved_49_61:13;     /* Must be zero */
@@ -971,6 +1201,14 @@ typedef union {
                uint64_t reserved_36_39:4;      /* Must be zero */
                /* Address field. addr<2:0> must be zero */
                uint64_t addr:36;
+#else
+                uint64_t addr:36;
+                uint64_t reserved_36_39:4;
+                uint64_t did:8;
+                uint64_t is_io:1;
+                uint64_t reserved_49_61:13;
+                uint64_t mem_reg:2;
+#endif
        } stag;
 } cvmx_pow_tag_store_addr_t;
@@ -981,6 +1219,7 @@ typedef union {
        uint64_t u64;
        struct {
+#ifdef __BIG_ENDIAN_BITFIELD
                /*
                 * the (64-bit word) location in scratchpad to write
                 * to (if len != 0)
@@ -994,6 +1233,14 @@ typedef union {
                /* if set, don't return load response until work is available */
                uint64_t wait:1;
                uint64_t unused2:3;
+#else
+                uint64_t unused2:3;
+                uint64_t wait:1;
+                uint64_t unused:36;
+                uint64_t did:8;
+                uint64_t len:8;
+                uint64_t scraddr:8;
+#endif
        } s;
 } cvmx_pow_iobdma_store_t;
diff --git a/arch/mips/include/asm/octeon/cvmx-wqe.h b/arch/mips/include/asm/octeon/cvmx-wqe.h
index aa0d3d0de75c..2d6d0c7127a7 100644
--- a/arch/mips/include/asm/octeon/cvmx-wqe.h
+++ b/arch/mips/include/asm/octeon/cvmx-wqe.h
@@ -57,6 +57,7 @@ typedef union {
        /* Use this struct if the hardware determines that the packet is IP */
        struct {
+#ifdef __BIG_ENDIAN_BITFIELD
                /* HW sets this to the number of buffers used by this packet */
                uint64_t bufs:8;
                /* HW sets to the number of L2 bytes prior to the IP */
@@ -166,13 +167,45 @@ typedef union {
                 * the slow path */
                /* type is cvmx_pip_err_t */
                uint64_t err_code:8;
+#else
+                uint64_t err_code:8;
+                uint64_t rcv_error:1;
+                uint64_t not_IP:1;
+                uint64_t is_mcast:1;
+                uint64_t is_bcast:1;
+                uint64_t IP_exc:1;
+                uint64_t is_frag:1;
+                uint64_t L4_error:1;
+                uint64_t software:1;
+                uint64_t is_v6:1;
+                uint64_t dec_ipsec:1;
+                uint64_t tcp_or_udp:1;
+                uint64_t dec_ipcomp:1;
+                uint64_t unassigned2:4;
+                uint64_t unassigned2a:4;
+                uint64_t pr:4;
+                uint64_t vlan_id:12;
+                uint64_t vlan_cfi:1;
+                uint64_t unassigned:1;
+                uint64_t vlan_stacked:1;
+                uint64_t vlan_valid:1;
+                uint64_t ip_offset:8;
+                uint64_t bufs:8;
+#endif
        } s;
        /* use this to get at the 16 vlan bits */
        struct {
+#ifdef __BIG_ENDIAN_BITFIELD
                uint64_t unused1:16;
                uint64_t vlan:16;
                uint64_t unused2:32;
+#else
+                uint64_t unused2:32;
+                uint64_t vlan:16;
+                uint64_t unused1:16;
+#endif
        } svlan;
        /*
@@ -180,6 +213,7 @@ typedef union {
         * the packet is ip.
         */
        struct {
+#ifdef __BIG_ENDIAN_BITFIELD
                /*
                 * HW sets this to the number of buffers used by this
                 * packet.
@@ -296,6 +330,27 @@ typedef union {
                 */
                /* type is cvmx_pip_err_t (union, so can't use directly */
                uint64_t err_code:8;
+#else
+                uint64_t err_code:8;
+                uint64_t rcv_error:1;
+                uint64_t not_IP:1;
+                uint64_t is_mcast:1;
+                uint64_t is_bcast:1;
+                uint64_t is_arp:1;
+                uint64_t is_rarp:1;
+                uint64_t unassigned3:1;
+                uint64_t software:1;
+                uint64_t unassigned2:4;
+                uint64_t unassigned2a:8;
+                uint64_t pr:4;
+                uint64_t vlan_id:12;
+                uint64_t vlan_cfi:1;
+                uint64_t unassigned:1;
+                uint64_t vlan_stacked:1;
+                uint64_t vlan_valid:1;
+                uint64_t unused:8;
+                uint64_t bufs:8;
+#endif
        } snoip;
 } cvmx_pip_wqe_word2;
@@ -312,6 +367,7 @@ typedef struct {
     *  HW WRITE: the following 64 bits are filled by HW when a packet arrives
     */
+#ifdef __BIG_ENDIAN_BITFIELD
    /**
     * raw chksum result generated by the HW
     */
@@ -327,12 +383,18 @@ typedef struct {
     * (Only 36 bits used in Octeon 1)
     */
        uint64_t next_ptr:40;
+#else
+        uint64_t next_ptr:40;
+        uint8_t unused;
+        uint16_t hw_chksum;
+#endif
    /*****************************************************************
     * WORD 1
     *  HW WRITE: the following 64 bits are filled by HW when a packet arrives
     */
+#ifdef __BIG_ENDIAN_BITFIELD
    /**
     * HW sets to the total number of bytes in the packet
     */
@@ -359,6 +421,15 @@ typedef struct {
     * the synchronization/ordering tag
     */
        uint64_t tag:32;
+#else
+        uint64_t tag:32;
+        uint64_t tag_type:2;
+        uint64_t zero_2:1;
+        uint64_t grp:4;
+        uint64_t qos:3;
+        uint64_t ipprt:6;
+        uint64_t len:16;
+#endif
    /**
     * WORD 2 HW WRITE: the following 64-bits are filled in by
diff --git a/arch/mips/include/asm/octeon/cvmx.h b/arch/mips/include/asm/octeon/cvmx.h
index 33db1c806b01..774bb45834cb 100644
--- a/arch/mips/include/asm/octeon/cvmx.h
+++ b/arch/mips/include/asm/octeon/cvmx.h
@@ -436,14 +436,6 @@ static inline uint64_t cvmx_get_cycle_global(void)
 /***************************************************************************/
-static inline void cvmx_reset_octeon(void)
-{
-        union cvmx_ciu_soft_rst ciu_soft_rst;
-        ciu_soft_rst.u64 = 0;
-        ciu_soft_rst.s.soft_rst = 1;
-        cvmx_write_csr(CVMX_CIU_SOFT_RST, ciu_soft_rst.u64);
-}
 /* Return the number of cores available in the chip */
 static inline uint32_t cvmx_octeon_num_cores(void)
 {
diff --git a/arch/mips/include/asm/octeon/octeon.h b/arch/mips/include/asm/octeon/octeon.h
index 041596570856..de9f74ee5dd0 100644
--- a/arch/mips/include/asm/octeon/octeon.h
+++ b/arch/mips/include/asm/octeon/octeon.h
@@ -335,4 +335,6 @@ void octeon_irq_set_ip4_handler(octeon_irq_ip4_handler_t);
 extern void octeon_fixup_irqs(void);
+extern struct semaphore octeon_bootbus_sem;
 #endif /* __ASM_OCTEON_OCTEON_H */
diff --git a/arch/mips/include/asm/octeon/pci-octeon.h b/arch/mips/include/asm/octeon/pci-octeon.h
index 64ba56a02843..1884609741a8 100644
--- a/arch/mips/include/asm/octeon/pci-octeon.h
+++ b/arch/mips/include/asm/octeon/pci-octeon.h
@@ -11,9 +11,6 @@
 #include <linux/pci.h>
-/* Some PCI cards require delays when accessing config space. */
-#define PCI_CONFIG_SPACE_DELAY 10000
 /*
 * The physical memory base mapped by BAR1.  256MB at the end of the
 * first 4GB.
diff --git a/arch/mips/include/asm/page.h b/arch/mips/include/asm/page.h
index 154b70a10483..89dd7fed1a57 100644
--- a/arch/mips/include/asm/page.h
+++ b/arch/mips/include/asm/page.h
@@ -105,8 +105,6 @@ static inline void clear_user_page(void *addr, unsigned long vaddr,
                flush_data_cache_page((unsigned long)addr);
 }
-extern void copy_user_page(void *vto, void *vfrom, unsigned long vaddr,
-        struct page *to);
 struct vm_area_struct;
 extern void copy_user_highpage(struct page *to, struct page *from,
        unsigned long vaddr, struct vm_area_struct *vma);
diff --git a/arch/mips/include/asm/pci.h b/arch/mips/include/asm/pci.h
index 193b4c6b7541..d9692993fc83 100644
--- a/arch/mips/include/asm/pci.h
+++ b/arch/mips/include/asm/pci.h
@@ -35,6 +35,8 @@ struct pci_controller {
        struct resource *io_resource;
        unsigned long io_offset;
        unsigned long io_map_base;
+        struct resource *busn_resource;
+        unsigned long busn_offset;
        unsigned int index;
        /* For compatibility with current (as of July 2003) pciutils
diff --git a/arch/mips/include/asm/pci/bridge.h b/arch/mips/include/asm/pci/bridge.h
index af2c8a351ca7..8d7a63b52ac7 100644
--- a/arch/mips/include/asm/pci/bridge.h
+++ b/arch/mips/include/asm/pci/bridge.h
@@ -835,6 +835,7 @@ struct bridge_controller {
        struct pci_controller   pc;
        struct resource         mem;
        struct resource         io;
+        struct resource         busn;
        bridge_t                *base;
        nasid_t                 nasid;
        unsigned int            widget_id;
diff --git a/arch/mips/include/asm/pgtable-32.h b/arch/mips/include/asm/pgtable-32.h
index a6be006b6f75..7d56686c0e62 100644
--- a/arch/mips/include/asm/pgtable-32.h
+++ b/arch/mips/include/asm/pgtable-32.h
@@ -105,13 +105,16 @@ static inline void pmd_clear(pmd_t *pmdp)
 #if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32)
 #define pte_page(x)             pfn_to_page(pte_pfn(x))
-#define pte_pfn(x)              ((unsigned long)((x).pte_high >> 6))
+#define pte_pfn(x)              (((unsigned long)((x).pte_high >> _PFN_SHIFT)) | (unsigned long)((x).pte_low << _PAGE_PRESENT_SHIFT))
 static inline pte_t
 pfn_pte(unsigned long pfn, pgprot_t prot)
 {
        pte_t pte;
-        pte.pte_high = (pfn << 6) | (pgprot_val(prot) & 0x3f);
-        pte.pte_low = pgprot_val(prot);
+        pte.pte_low = (pfn >> _PAGE_PRESENT_SHIFT) |
+                                (pgprot_val(prot) & ~_PFNX_MASK);
+        pte.pte_high = (pfn << _PFN_SHIFT) |
+                                (pgprot_val(prot) & ~_PFN_MASK);
        return pte;
 }
@@ -166,9 +169,9 @@ pfn_pte(unsigned long pfn, pgprot_t prot)
 #if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32)
 /* Swap entries must have VALID and GLOBAL bits cleared. */
-#define __swp_type(x)                   (((x).val >> 2) & 0x1f)
+#define __swp_type(x)                   (((x).val >> 4) & 0x1f)
-#define __swp_offset(x)                  ((x).val >> 7)
+#define __swp_offset(x)                  ((x).val >> 9)
-#define __swp_entry(type,offset)        ((swp_entry_t)  { ((type) << 2) | ((offset) << 7) })
+#define __swp_entry(type,offset)        ((swp_entry_t)  { ((type) << 4) | ((offset) << 9) })
 #define __pte_to_swp_entry(pte)         ((swp_entry_t) { (pte).pte_high })
 #define __swp_entry_to_pte(x)           ((pte_t) { 0, (x).val })
diff --git a/arch/mips/include/asm/pgtable-64.h b/arch/mips/include/asm/pgtable-64.h
index 1659bb91ae21..cf661a2fb141 100644
--- a/arch/mips/include/asm/pgtable-64.h
+++ b/arch/mips/include/asm/pgtable-64.h
@@ -279,14 +279,14 @@ extern void pgd_init(unsigned long page);
 extern void pmd_init(unsigned long page, unsigned long pagetable);
 /*
- * Non-present pages:  high 24 bits are offset, next 8 bits type,
+ * Non-present pages:  high 40 bits are offset, next 8 bits type,
- * low 32 bits zero.
+ * low 16 bits zero.
 */
 static inline pte_t mk_swap_pte(unsigned long type, unsigned long offset)
-{ pte_t pte; pte_val(pte) = (type << 32) | (offset << 40); return pte; }
+{ pte_t pte; pte_val(pte) = (type << 16) | (offset << 24); return pte; }
-#define __swp_type(x)           (((x).val >> 32) & 0xff)
+#define __swp_type(x)           (((x).val >> 16) & 0xff)
-#define __swp_offset(x)         ((x).val >> 40)
+#define __swp_offset(x)         ((x).val >> 24)
 #define __swp_entry(type, offset) ((swp_entry_t) { pte_val(mk_swap_pte((type), (offset))) })
 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
 #define __swp_entry_to_pte(x)   ((pte_t) { (x).val })
diff --git a/arch/mips/include/asm/pgtable-bits.h b/arch/mips/include/asm/pgtable-bits.h
index 91747c282bb3..18ae5ddef118 100644
--- a/arch/mips/include/asm/pgtable-bits.h
+++ b/arch/mips/include/asm/pgtable-bits.h
@@ -37,7 +37,11 @@
 /*
 * The following bits are implemented by the TLB hardware
 */
-#define _PAGE_GLOBAL_SHIFT      0
+#define _PAGE_NO_EXEC_SHIFT     0
+#define _PAGE_NO_EXEC           (1 << _PAGE_NO_EXEC_SHIFT)
+#define _PAGE_NO_READ_SHIFT     (_PAGE_NO_EXEC_SHIFT + 1)
+#define _PAGE_NO_READ           (1 << _PAGE_NO_READ_SHIFT)
+#define _PAGE_GLOBAL_SHIFT      (_PAGE_NO_READ_SHIFT + 1)
 #define _PAGE_GLOBAL            (1 << _PAGE_GLOBAL_SHIFT)
 #define _PAGE_VALID_SHIFT       (_PAGE_GLOBAL_SHIFT + 1)
 #define _PAGE_VALID             (1 << _PAGE_VALID_SHIFT)
@@ -49,7 +53,7 @@
 /*
 * The following bits are implemented in software
 */
-#define _PAGE_PRESENT_SHIFT     (_CACHE_SHIFT + 3)
+#define _PAGE_PRESENT_SHIFT     (24)
 #define _PAGE_PRESENT           (1 << _PAGE_PRESENT_SHIFT)
 #define _PAGE_READ_SHIFT        (_PAGE_PRESENT_SHIFT + 1)
 #define _PAGE_READ              (1 << _PAGE_READ_SHIFT)
@@ -62,6 +66,11 @@
 #define _PFN_SHIFT              (PAGE_SHIFT - 12 + _CACHE_SHIFT + 3)
+/*
+ * Bits for extended EntryLo0/EntryLo1 registers
+ */
+#define _PFNX_MASK              0xffffff
 #elif defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
 /*
@@ -95,11 +104,7 @@
 #else
 /*
- * When using the RI/XI bit support, we have 13 bits of flags below
+ * Below are the "Normal" R4K cases
- * the physical address. The RI/XI bits are placed such that a SRL 5
- * can strip off the software bits, then a ROTR 2 can move the RI/XI
- * into bits [63:62]. This also limits physical address to 56 bits,
- * which is more than we need right now.
 */
 /*
@@ -107,38 +112,59 @@
 */
 #define _PAGE_PRESENT_SHIFT     0
 #define _PAGE_PRESENT           (1 << _PAGE_PRESENT_SHIFT)
-#define _PAGE_READ_SHIFT        (cpu_has_rixi ? _PAGE_PRESENT_SHIFT : _PAGE_PRESENT_SHIFT + 1)
+/* R2 or later cores check for RI/XI support to determine _PAGE_READ */
-#define _PAGE_READ ({BUG_ON(cpu_has_rixi); 1 << _PAGE_READ_SHIFT; })
+#ifdef CONFIG_CPU_MIPSR2
+#define _PAGE_WRITE_SHIFT       (_PAGE_PRESENT_SHIFT + 1)
+#define _PAGE_WRITE             (1 << _PAGE_WRITE_SHIFT)
+#else
+#define _PAGE_READ_SHIFT        (_PAGE_PRESENT_SHIFT + 1)
+#define _PAGE_READ              (1 << _PAGE_READ_SHIFT)
 #define _PAGE_WRITE_SHIFT       (_PAGE_READ_SHIFT + 1)
 #define _PAGE_WRITE             (1 << _PAGE_WRITE_SHIFT)
+#endif
 #define _PAGE_ACCESSED_SHIFT    (_PAGE_WRITE_SHIFT + 1)
 #define _PAGE_ACCESSED          (1 << _PAGE_ACCESSED_SHIFT)
 #define _PAGE_MODIFIED_SHIFT    (_PAGE_ACCESSED_SHIFT + 1)
 #define _PAGE_MODIFIED          (1 << _PAGE_MODIFIED_SHIFT)
-#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
+#if defined(CONFIG_64BIT) && defined(CONFIG_MIPS_HUGE_TLB_SUPPORT)
-/* huge tlb page */
+/* Huge TLB page */
 #define _PAGE_HUGE_SHIFT        (_PAGE_MODIFIED_SHIFT + 1)
 #define _PAGE_HUGE              (1 << _PAGE_HUGE_SHIFT)
 #define _PAGE_SPLITTING_SHIFT   (_PAGE_HUGE_SHIFT + 1)
 #define _PAGE_SPLITTING         (1 << _PAGE_SPLITTING_SHIFT)
+/* Only R2 or newer cores have the XI bit */
+#ifdef CONFIG_CPU_MIPSR2
+#define _PAGE_NO_EXEC_SHIFT     (_PAGE_SPLITTING_SHIFT + 1)
 #else
-#define _PAGE_HUGE_SHIFT        (_PAGE_MODIFIED_SHIFT)
+#define _PAGE_GLOBAL_SHIFT      (_PAGE_SPLITTING_SHIFT + 1)
-#define _PAGE_HUGE              ({BUG(); 1; })  /* Dummy value */
+#define _PAGE_GLOBAL            (1 << _PAGE_GLOBAL_SHIFT)
-#define _PAGE_SPLITTING_SHIFT   (_PAGE_HUGE_SHIFT)
+#endif  /* CONFIG_CPU_MIPSR2 */
-#define _PAGE_SPLITTING         ({BUG(); 1; })  /* Dummy value */
-#endif
-/* Page cannot be executed */
+#endif  /* CONFIG_64BIT && CONFIG_MIPS_HUGE_TLB_SUPPORT */
-#define _PAGE_NO_EXEC_SHIFT     (cpu_has_rixi ? _PAGE_SPLITTING_SHIFT + 1 : _PAGE_SPLITTING_SHIFT)
-#define _PAGE_NO_EXEC           ({BUG_ON(!cpu_has_rixi); 1 << _PAGE_NO_EXEC_SHIFT; })
-/* Page cannot be read */
+#ifdef CONFIG_CPU_MIPSR2
-#define _PAGE_NO_READ_SHIFT     (cpu_has_rixi ? _PAGE_NO_EXEC_SHIFT + 1 : _PAGE_NO_EXEC_SHIFT)
+/* XI - page cannot be executed */
-#define _PAGE_NO_READ           ({BUG_ON(!cpu_has_rixi); 1 << _PAGE_NO_READ_SHIFT; })
+#ifndef _PAGE_NO_EXEC_SHIFT
+#define _PAGE_NO_EXEC_SHIFT     (_PAGE_MODIFIED_SHIFT + 1)
+#endif
+#define _PAGE_NO_EXEC           (cpu_has_rixi ? (1 << _PAGE_NO_EXEC_SHIFT) : 0)
+/* RI - page cannot be read */
+#define _PAGE_READ_SHIFT        (_PAGE_NO_EXEC_SHIFT + 1)
+#define _PAGE_READ              (cpu_has_rixi ? 0 : (1 << _PAGE_READ_SHIFT))
+#define _PAGE_NO_READ_SHIFT     _PAGE_READ_SHIFT
+#define _PAGE_NO_READ           (cpu_has_rixi ? (1 << _PAGE_READ_SHIFT) : 0)
 #define _PAGE_GLOBAL_SHIFT      (_PAGE_NO_READ_SHIFT + 1)
 #define _PAGE_GLOBAL            (1 << _PAGE_GLOBAL_SHIFT)
+#else   /* !CONFIG_CPU_MIPSR2 */
+#define _PAGE_GLOBAL_SHIFT      (_PAGE_MODIFIED_SHIFT + 1)
+#define _PAGE_GLOBAL            (1 << _PAGE_GLOBAL_SHIFT)
+#endif  /* CONFIG_CPU_MIPSR2 */
 #define _PAGE_VALID_SHIFT       (_PAGE_GLOBAL_SHIFT + 1)
 #define _PAGE_VALID             (1 << _PAGE_VALID_SHIFT)
 #define _PAGE_DIRTY_SHIFT       (_PAGE_VALID_SHIFT + 1)
@@ -150,18 +176,26 @@
 #endif /* defined(CONFIG_PHYS_ADDR_T_64BIT && defined(CONFIG_CPU_MIPS32) */
+#ifndef _PAGE_NO_EXEC
+#define _PAGE_NO_EXEC           0
+#endif
+#ifndef _PAGE_NO_READ
+#define _PAGE_NO_READ           0
+#endif
 #define _PAGE_SILENT_READ       _PAGE_VALID
 #define _PAGE_SILENT_WRITE      _PAGE_DIRTY
 #define _PFN_MASK               (~((1 << (_PFN_SHIFT)) - 1))
-#ifndef _PAGE_NO_READ
+/*
-#define _PAGE_NO_READ ({BUG(); 0; })
+ * The final layouts of the PTE bits are:
-#define _PAGE_NO_READ_SHIFT ({BUG(); 0; })
+ *
-#endif
+ *   64-bit, R1 or earlier:     CCC D V G [S H] M A W R P
-#ifndef _PAGE_NO_EXEC
+ *   32-bit, R1 or earler:      CCC D V G M A W R P
-#define _PAGE_NO_EXEC ({BUG(); 0; })
+ *   64-bit, R2 or later:       CCC D V G RI/R XI [S H] M A W P
-#endif
+ *   32-bit, R2 or later:       CCC D V G RI/R XI M A W P
+ */
 #ifndef __ASSEMBLY__
@@ -171,6 +205,7 @@
 */
 static inline uint64_t pte_to_entrylo(unsigned long pte_val)
 {
+#ifdef CONFIG_CPU_MIPSR2
        if (cpu_has_rixi) {
                int sa;
 #ifdef CONFIG_32BIT
@@ -186,6 +221,7 @@ static inline uint64_t pte_to_entrylo(unsigned long pte_val)
                return (pte_val >> _PAGE_GLOBAL_SHIFT) |
                        ((pte_val & (_PAGE_NO_EXEC | _PAGE_NO_READ)) << sa);
        }
+#endif
        return pte_val >> _PAGE_GLOBAL_SHIFT;
 }
@@ -245,7 +281,7 @@ static inline uint64_t pte_to_entrylo(unsigned long pte_val)
 #define _CACHE_UNCACHED_ACCELERATED     (7<<_CACHE_SHIFT)
 #endif
-#define __READABLE      (_PAGE_SILENT_READ | _PAGE_ACCESSED | (cpu_has_rixi ? 0 : _PAGE_READ))
+#define __READABLE      (_PAGE_SILENT_READ | _PAGE_READ | _PAGE_ACCESSED)
 #define __WRITEABLE     (_PAGE_SILENT_WRITE | _PAGE_WRITE | _PAGE_MODIFIED)
 #define _PAGE_CHG_MASK  (_PAGE_ACCESSED | _PAGE_MODIFIED |      \
diff --git a/arch/mips/include/asm/pgtable.h b/arch/mips/include/asm/pgtable.h
index bef782c4a44b..819af9d057a8 100644
--- a/arch/mips/include/asm/pgtable.h
+++ b/arch/mips/include/asm/pgtable.h
@@ -24,17 +24,17 @@ struct mm_struct;
 struct vm_area_struct;
 #define PAGE_NONE       __pgprot(_PAGE_PRESENT | _CACHE_CACHABLE_NONCOHERENT)
-#define PAGE_SHARED     __pgprot(_PAGE_PRESENT | _PAGE_WRITE | (cpu_has_rixi ? 0 : _PAGE_READ) | \
+#define PAGE_SHARED     __pgprot(_PAGE_PRESENT | _PAGE_WRITE | _PAGE_READ | \
                                 _page_cachable_default)
-#define PAGE_COPY       __pgprot(_PAGE_PRESENT | (cpu_has_rixi ? 0 : _PAGE_READ) | \
+#define PAGE_COPY       __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_NO_EXEC | \
-                                 (cpu_has_rixi ?  _PAGE_NO_EXEC : 0) | _page_cachable_default)
+                                 _page_cachable_default)
-#define PAGE_READONLY   __pgprot(_PAGE_PRESENT | (cpu_has_rixi ? 0 : _PAGE_READ) | \
+#define PAGE_READONLY   __pgprot(_PAGE_PRESENT | _PAGE_READ | \
                                 _page_cachable_default)
 #define PAGE_KERNEL     __pgprot(_PAGE_PRESENT | __READABLE | __WRITEABLE | \
                                 _PAGE_GLOBAL | _page_cachable_default)
 #define PAGE_KERNEL_NC  __pgprot(_PAGE_PRESENT | __READABLE | __WRITEABLE | \
                                 _PAGE_GLOBAL | _CACHE_CACHABLE_NONCOHERENT)
-#define PAGE_USERIO     __pgprot(_PAGE_PRESENT | (cpu_has_rixi ? 0 : _PAGE_READ) | _PAGE_WRITE | \
+#define PAGE_USERIO     __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \
                                 _page_cachable_default)
 #define PAGE_KERNEL_UNCACHED __pgprot(_PAGE_PRESENT | __READABLE | \
                        __WRITEABLE | _PAGE_GLOBAL | _CACHE_UNCACHED)
@@ -127,13 +127,9 @@ do {									\
        }                                                               \
 } while(0)
-extern void set_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *ptep,
-        pte_t pteval);
 #if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32)
-#define pte_none(pte)           (!(((pte).pte_low | (pte).pte_high) & ~_PAGE_GLOBAL))
+#define pte_none(pte)           (!(((pte).pte_high) & ~_PAGE_GLOBAL))
 #define pte_present(pte)        ((pte).pte_low & _PAGE_PRESENT)
 static inline void set_pte(pte_t *ptep, pte_t pte)
@@ -142,18 +138,17 @@ static inline void set_pte(pte_t *ptep, pte_t pte)
        smp_wmb();
        ptep->pte_low = pte.pte_low;
-        if (pte.pte_low & _PAGE_GLOBAL) {
+        if (pte.pte_high & _PAGE_GLOBAL) {
                pte_t *buddy = ptep_buddy(ptep);
                /*
                 * Make sure the buddy is global too (if it's !none,
                 * it better already be global)
                 */
-                if (pte_none(*buddy)) {
+                if (pte_none(*buddy))
-                        buddy->pte_low  |= _PAGE_GLOBAL;
                        buddy->pte_high |= _PAGE_GLOBAL;
-                }
        }
 }
+#define set_pte_at(mm, addr, ptep, pteval) set_pte(ptep, pteval)
 static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
 {
@@ -161,8 +156,8 @@ static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *pt
        htw_stop();
        /* Preserve global status for the pair */
-        if (ptep_buddy(ptep)->pte_low & _PAGE_GLOBAL)
+        if (ptep_buddy(ptep)->pte_high & _PAGE_GLOBAL)
-                null.pte_low = null.pte_high = _PAGE_GLOBAL;
+                null.pte_high = _PAGE_GLOBAL;
        set_pte_at(mm, addr, ptep, null);
        htw_start();
@@ -192,6 +187,7 @@ static inline void set_pte(pte_t *ptep, pte_t pteval)
        }
 #endif
 }
+#define set_pte_at(mm, addr, ptep, pteval) set_pte(ptep, pteval)
 static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
 {
@@ -242,21 +238,21 @@ static inline int pte_young(pte_t pte)	{ return pte.pte_low & _PAGE_ACCESSED; }
 static inline pte_t pte_wrprotect(pte_t pte)
 {
-        pte.pte_low  &= ~(_PAGE_WRITE | _PAGE_SILENT_WRITE);
+        pte.pte_low  &= ~_PAGE_WRITE;
        pte.pte_high &= ~_PAGE_SILENT_WRITE;
        return pte;
 }
 static inline pte_t pte_mkclean(pte_t pte)
 {
-        pte.pte_low  &= ~(_PAGE_MODIFIED | _PAGE_SILENT_WRITE);
+        pte.pte_low  &= ~_PAGE_MODIFIED;
        pte.pte_high &= ~_PAGE_SILENT_WRITE;
        return pte;
 }
 static inline pte_t pte_mkold(pte_t pte)
 {
-        pte.pte_low  &= ~(_PAGE_ACCESSED | _PAGE_SILENT_READ);
+        pte.pte_low  &= ~_PAGE_ACCESSED;
        pte.pte_high &= ~_PAGE_SILENT_READ;
        return pte;
 }
@@ -264,30 +260,24 @@ static inline pte_t pte_mkold(pte_t pte)
 static inline pte_t pte_mkwrite(pte_t pte)
 {
        pte.pte_low |= _PAGE_WRITE;
-        if (pte.pte_low & _PAGE_MODIFIED) {
+        if (pte.pte_low & _PAGE_MODIFIED)
-                pte.pte_low  |= _PAGE_SILENT_WRITE;
                pte.pte_high |= _PAGE_SILENT_WRITE;
-        }
        return pte;
 }
 static inline pte_t pte_mkdirty(pte_t pte)
 {
        pte.pte_low |= _PAGE_MODIFIED;
-        if (pte.pte_low & _PAGE_WRITE) {
+        if (pte.pte_low & _PAGE_WRITE)
-                pte.pte_low  |= _PAGE_SILENT_WRITE;
                pte.pte_high |= _PAGE_SILENT_WRITE;
-        }
        return pte;
 }
 static inline pte_t pte_mkyoung(pte_t pte)
 {
        pte.pte_low |= _PAGE_ACCESSED;
-        if (pte.pte_low & _PAGE_READ) {
+        if (pte.pte_low & _PAGE_READ)
-                pte.pte_low  |= _PAGE_SILENT_READ;
                pte.pte_high |= _PAGE_SILENT_READ;
-        }
        return pte;
 }
 #else
@@ -332,13 +322,13 @@ static inline pte_t pte_mkdirty(pte_t pte)
 static inline pte_t pte_mkyoung(pte_t pte)
 {
        pte_val(pte) |= _PAGE_ACCESSED;
-        if (cpu_has_rixi) {
+#ifdef CONFIG_CPU_MIPSR2
-                if (!(pte_val(pte) & _PAGE_NO_READ))
+        if (!(pte_val(pte) & _PAGE_NO_READ))
-                        pte_val(pte) |= _PAGE_SILENT_READ;
+                pte_val(pte) |= _PAGE_SILENT_READ;
-        } else {
+        else
-                if (pte_val(pte) & _PAGE_READ)
+#endif
-                        pte_val(pte) |= _PAGE_SILENT_READ;
+        if (pte_val(pte) & _PAGE_READ)
-        }
+                pte_val(pte) |= _PAGE_SILENT_READ;
        return pte;
 }
@@ -391,10 +381,10 @@ static inline pgprot_t pgprot_writecombine(pgprot_t _prot)
 #if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32)
 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
 {
-        pte.pte_low  &= _PAGE_CHG_MASK;
+        pte.pte_low  &= (_PAGE_MODIFIED | _PAGE_ACCESSED | _PFNX_MASK);
        pte.pte_high &= (_PFN_MASK | _CACHE_MASK);
-        pte.pte_low  |= pgprot_val(newprot);
+        pte.pte_low  |= pgprot_val(newprot) & ~_PFNX_MASK;
-        pte.pte_high |= pgprot_val(newprot) & ~(_PFN_MASK | _CACHE_MASK);
+        pte.pte_high |= pgprot_val(newprot) & ~_PFN_MASK;
        return pte;
 }
 #else
@@ -407,12 +397,15 @@ static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
 extern void __update_tlb(struct vm_area_struct *vma, unsigned long address,
        pte_t pte);
+extern void __update_cache(struct vm_area_struct *vma, unsigned long address,
+        pte_t pte);
 static inline void update_mmu_cache(struct vm_area_struct *vma,
        unsigned long address, pte_t *ptep)
 {
        pte_t pte = *ptep;
        __update_tlb(vma, address, pte);
+        __update_cache(vma, address, pte);
 }
 static inline void update_mmu_cache_pmd(struct vm_area_struct *vma,
@@ -534,13 +527,13 @@ static inline pmd_t pmd_mkyoung(pmd_t pmd)
 {
        pmd_val(pmd) |= _PAGE_ACCESSED;
-        if (cpu_has_rixi) {
+#ifdef CONFIG_CPU_MIPSR2
-                if (!(pmd_val(pmd) & _PAGE_NO_READ))
+        if (!(pmd_val(pmd) & _PAGE_NO_READ))
-                        pmd_val(pmd) |= _PAGE_SILENT_READ;
+                pmd_val(pmd) |= _PAGE_SILENT_READ;
-        } else {
+        else
-                if (pmd_val(pmd) & _PAGE_READ)
+#endif
-                        pmd_val(pmd) |= _PAGE_SILENT_READ;
+        if (pmd_val(pmd) & _PAGE_READ)
-        }
+                pmd_val(pmd) |= _PAGE_SILENT_READ;
        return pmd;
 }
diff --git a/arch/mips/include/asm/r4kcache.h b/arch/mips/include/asm/r4kcache.h
index 1b22d2da88a1..38902bf97adc 100644
--- a/arch/mips/include/asm/r4kcache.h
+++ b/arch/mips/include/asm/r4kcache.h
@@ -12,6 +12,8 @@
 #ifndef _ASM_R4KCACHE_H
 #define _ASM_R4KCACHE_H
+#include <linux/stringify.h>
 #include <asm/asm.h>
 #include <asm/cacheops.h>
 #include <asm/compiler.h>
@@ -344,7 +346,7 @@ static inline void invalidate_tcache_page(unsigned long addr)
        "       cache %1, 0x0a0(%0); cache %1, 0x0b0(%0)\n"     \
        "       cache %1, 0x0c0(%0); cache %1, 0x0d0(%0)\n"     \
        "       cache %1, 0x0e0(%0); cache %1, 0x0f0(%0)\n"     \
-        "       addiu $1, $0, 0x100                     \n"     \
+        "       "__stringify(LONG_ADDIU)" $1, %0, 0x100 \n"     \
        "       cache %1, 0x000($1); cache %1, 0x010($1)\n"     \
        "       cache %1, 0x020($1); cache %1, 0x030($1)\n"     \
        "       cache %1, 0x040($1); cache %1, 0x050($1)\n"     \
@@ -368,17 +370,17 @@ static inline void invalidate_tcache_page(unsigned long addr)
        "       cache %1, 0x040(%0); cache %1, 0x060(%0)\n"     \
        "       cache %1, 0x080(%0); cache %1, 0x0a0(%0)\n"     \
        "       cache %1, 0x0c0(%0); cache %1, 0x0e0(%0)\n"     \
-        "       addiu $1, %0, 0x100\n"                          \
+        "       "__stringify(LONG_ADDIU)" $1, %0, 0x100 \n"     \
        "       cache %1, 0x000($1); cache %1, 0x020($1)\n"     \
        "       cache %1, 0x040($1); cache %1, 0x060($1)\n"     \
        "       cache %1, 0x080($1); cache %1, 0x0a0($1)\n"     \
        "       cache %1, 0x0c0($1); cache %1, 0x0e0($1)\n"     \
-        "       addiu $1, $1, 0x100\n"                          \
+        "       "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n"     \
        "       cache %1, 0x000($1); cache %1, 0x020($1)\n"     \
        "       cache %1, 0x040($1); cache %1, 0x060($1)\n"     \
        "       cache %1, 0x080($1); cache %1, 0x0a0($1)\n"     \
        "       cache %1, 0x0c0($1); cache %1, 0x0e0($1)\n"     \
-        "       addiu $1, $1, 0x100\n"                          \
+        "       "__stringify(LONG_ADDIU)" $1, $1, 0x100\n"      \
        "       cache %1, 0x000($1); cache %1, 0x020($1)\n"     \
        "       cache %1, 0x040($1); cache %1, 0x060($1)\n"     \
        "       cache %1, 0x080($1); cache %1, 0x0a0($1)\n"     \
@@ -396,25 +398,25 @@ static inline void invalidate_tcache_page(unsigned long addr)
        "       .set noat\n"                                    \
        "       cache %1, 0x000(%0); cache %1, 0x040(%0)\n"     \
        "       cache %1, 0x080(%0); cache %1, 0x0c0(%0)\n"     \
-        "       addiu $1, %0, 0x100\n"                          \
+        "       "__stringify(LONG_ADDIU)" $1, %0, 0x100 \n"     \
        "       cache %1, 0x000($1); cache %1, 0x040($1)\n"     \
        "       cache %1, 0x080($1); cache %1, 0x0c0($1)\n"     \
-        "       addiu $1, %0, 0x100\n"                          \
+        "       "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n"     \
        "       cache %1, 0x000($1); cache %1, 0x040($1)\n"     \
        "       cache %1, 0x080($1); cache %1, 0x0c0($1)\n"     \
-        "       addiu $1, %0, 0x100\n"                          \
+        "       "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n"     \
        "       cache %1, 0x000($1); cache %1, 0x040($1)\n"     \
        "       cache %1, 0x080($1); cache %1, 0x0c0($1)\n"     \
-        "       addiu $1, %0, 0x100\n"                          \
+        "       "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n"     \
        "       cache %1, 0x000($1); cache %1, 0x040($1)\n"     \
        "       cache %1, 0x080($1); cache %1, 0x0c0($1)\n"     \
-        "       addiu $1, %0, 0x100\n"                          \
+        "       "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n"     \
        "       cache %1, 0x000($1); cache %1, 0x040($1)\n"     \
        "       cache %1, 0x080($1); cache %1, 0x0c0($1)\n"     \
-        "       addiu $1, %0, 0x100\n"                          \
+        "       "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n"     \
        "       cache %1, 0x000($1); cache %1, 0x040($1)\n"     \
        "       cache %1, 0x080($1); cache %1, 0x0c0($1)\n"     \
-        "       addiu $1, %0, 0x100\n"                          \
+        "       "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n"     \
        "       cache %1, 0x000($1); cache %1, 0x040($1)\n"     \
        "       cache %1, 0x080($1); cache %1, 0x0c0($1)\n"     \
        "       .set pop\n"                                     \
@@ -429,39 +431,38 @@ static inline void invalidate_tcache_page(unsigned long addr)
        "       .set mips64r6\n"                                \
        "       .set noat\n"                                    \
        "       cache %1, 0x000(%0); cache %1, 0x080(%0)\n"     \
-        "       addiu $1, %0, 0x100\n"                          \
+        "       "__stringify(LONG_ADDIU)" $1, %0, 0x100 \n"     \
-        "       cache %1, 0x000(%0); cache %1, 0x080(%0)\n"     \
+        "       cache %1, 0x000($1); cache %1, 0x080($1)\n"     \
-        "       addiu $1, %0, 0x100\n"                          \
+        "       "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n"     \
-        "       cache %1, 0x000(%0); cache %1, 0x080(%0)\n"     \
+        "       cache %1, 0x000($1); cache %1, 0x080($1)\n"     \
-        "       addiu $1, %0, 0x100\n"                          \
+        "       "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n"     \
-        "       cache %1, 0x000(%0); cache %1, 0x080(%0)\n"     \
+        "       cache %1, 0x000($1); cache %1, 0x080($1)\n"     \
-        "       addiu $1, %0, 0x100\n"                          \
+        "       "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n"     \
-        "       cache %1, 0x000(%0); cache %1, 0x080(%0)\n"     \
+        "       cache %1, 0x000($1); cache %1, 0x080($1)\n"     \
-        "       addiu $1, %0, 0x100\n"                          \
+        "       "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n"     \
-        "       cache %1, 0x000(%0); cache %1, 0x080(%0)\n"     \
+        "       cache %1, 0x000($1); cache %1, 0x080($1)\n"     \
-        "       addiu $1, %0, 0x100\n"                          \
+        "       "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n"     \
-        "       cache %1, 0x000(%0); cache %1, 0x080(%0)\n"     \
+        "       cache %1, 0x000($1); cache %1, 0x080($1)\n"     \
-        "       addiu $1, %0, 0x100\n"                          \
+        "       "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n"     \
-        "       cache %1, 0x000(%0); cache %1, 0x080(%0)\n"     \
+        "       cache %1, 0x000($1); cache %1, 0x080($1)\n"     \
-        "       addiu $1, %0, 0x100\n"                          \
+        "       "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n"     \
-        "       cache %1, 0x000(%0); cache %1, 0x080(%0)\n"     \
+        "       cache %1, 0x000($1); cache %1, 0x080($1)\n"     \
-        "       addiu $1, %0, 0x100\n"                          \
+        "       "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n"     \
-        "       cache %1, 0x000(%0); cache %1, 0x080(%0)\n"     \
+        "       cache %1, 0x000($1); cache %1, 0x080($1)\n"     \
-        "       addiu $1, %0, 0x100\n"                          \
+        "       "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n"     \
-        "       cache %1, 0x000(%0); cache %1, 0x080(%0)\n"     \
+        "       cache %1, 0x000($1); cache %1, 0x080($1)\n"     \
-        "       addiu $1, %0, 0x100\n"                          \
+        "       "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n"     \
-        "       cache %1, 0x000(%0); cache %1, 0x080(%0)\n"     \
+        "       cache %1, 0x000($1); cache %1, 0x080($1)\n"     \
-        "       addiu $1, %0, 0x100\n"                          \
+        "       "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n"     \
-        "       cache %1, 0x000(%0); cache %1, 0x080(%0)\n"     \
+        "       cache %1, 0x000($1); cache %1, 0x080($1)\n"     \
-        "       addiu $1, %0, 0x100\n"                          \
+        "       "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n"     \
-        "       cache %1, 0x000(%0); cache %1, 0x080(%0)\n"     \
+        "       cache %1, 0x000($1); cache %1, 0x080($1)\n"     \
-        "       addiu $1, %0, 0x100\n"                          \
+        "       "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n"     \
-        "       cache %1, 0x000(%0); cache %1, 0x080(%0)\n"     \
+        "       cache %1, 0x000($1); cache %1, 0x080($1)\n"     \
-        "       addiu $1, %0, 0x100\n"                          \
+        "       "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n"     \
-        "       cache %1, 0x000(%0); cache %1, 0x080(%0)\n"     \
+        "       cache %1, 0x000($1); cache %1, 0x080($1)\n"     \
-        "       addiu $1, %0, 0x100\n"                          \
+        "       "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n"     \
-        "       cache %1, 0x000(%0); cache %1, 0x080(%0)\n"     \
+        "       cache %1, 0x000($1); cache %1, 0x080($1)\n"     \
-        "       addiu $1, %0, 0x100\n"                          \
        "       .set pop\n"                                     \
                :                                               \
                : "r" (base),                                   \
diff --git a/arch/mips/include/asm/sgi/sgi.h b/arch/mips/include/asm/sgi/sgi.h
index 645cea7c0f8e..b61557151e3f 100644
--- a/arch/mips/include/asm/sgi/sgi.h
+++ b/arch/mips/include/asm/sgi/sgi.h
@@ -22,14 +22,15 @@ enum sgi_mach {
        ip17,   /* R4K UP */
        ip19,   /* R4K MP */
        ip20,   /* R4K UP, Indigo */
-        ip21,   /* TFP MP */
+        ip21,   /* R8k/TFP MP */
-        ip22,   /* R4x00 UP, Indigo2 */
+        ip22,   /* R4x00 UP, Indy, Indigo2 */
        ip25,   /* R10k MP */
-        ip26,   /* TFP UP, Indigo2 */
+        ip26,   /* R8k/TFP UP, Indigo2 */
-        ip27,   /* R10k MP, R12k MP, Origin */
+        ip27,   /* R10k MP, R12k MP, R14k MP, Origin 200/2k, Onyx2 */
-        ip28,   /* R10k UP, Indigo2 */
+        ip28,   /* R10k UP, Indigo2 Impact R10k */
-        ip30,   /* Octane */
+        ip30,   /* R10k MP, R12k MP, R14k MP, Octane */
-        ip32,   /* O2 */
+        ip32,   /* R5k UP, RM5200 UP, RM7k UP, R10k UP, R12k UP, O2 */
+        ip35,   /* R14k MP, R16k MP, Origin 300/3k, Onyx3, Fuel, Tezro */
 };
 extern enum sgi_mach sgimach;
diff --git a/arch/mips/include/asm/spinlock.h b/arch/mips/include/asm/spinlock.h
index b4548690ade9..1fca2e0793dc 100644
--- a/arch/mips/include/asm/spinlock.h
+++ b/arch/mips/include/asm/spinlock.h
@@ -263,7 +263,7 @@ static inline void arch_read_unlock(arch_rwlock_t *rw)
        if (R10000_LLSC_WAR) {
                __asm__ __volatile__(
                "1:     ll      %1, %2          # arch_read_unlock      \n"
-                "       addiu   %1, 1                                   \n"
+                "       addiu   %1, -1                                  \n"
                "       sc      %1, %0                                  \n"
                "       beqzl   %1, 1b                                  \n"
                : "=" GCC_OFF_SMALL_ASM() (rw->lock), "=&r" (tmp)
diff --git a/arch/mips/include/asm/thread_info.h b/arch/mips/include/asm/thread_info.h
index 8408a30c47f3..9c0014e87c17 100644
--- a/arch/mips/include/asm/thread_info.h
+++ b/arch/mips/include/asm/thread_info.h
@@ -53,10 +53,10 @@ struct thread_info {
 #define init_stack              (init_thread_union.stack)
 /* How to get the thread information struct from C.  */
+register struct thread_info *__current_thread_info __asm__("$28");
 static inline struct thread_info *current_thread_info(void)
 {
-        register struct thread_info *__current_thread_info __asm__("$28");
        return __current_thread_info;
 }