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-rw-r--r--arch/mips/include/asm/mach-lantiq/xway/irq.h18
-rw-r--r--arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h66
-rw-r--r--arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h140
3 files changed, 224 insertions, 0 deletions
diff --git a/arch/mips/include/asm/mach-lantiq/xway/irq.h b/arch/mips/include/asm/mach-lantiq/xway/irq.h
new file mode 100644
index 000000000000..a1471d2dd0d2
--- /dev/null
+++ b/arch/mips/include/asm/mach-lantiq/xway/irq.h
@@ -0,0 +1,18 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
5 *
6 * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
7 */
8
9#ifndef __LANTIQ_IRQ_H
10#define __LANTIQ_IRQ_H
11
12#include <lantiq_irq.h>
13
14#define NR_IRQS 256
15
16#include_next <irq.h>
17
18#endif
diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h
new file mode 100644
index 000000000000..b4465a888e20
--- /dev/null
+++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h
@@ -0,0 +1,66 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
5 *
6 * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
7 */
8
9#ifndef _LANTIQ_XWAY_IRQ_H__
10#define _LANTIQ_XWAY_IRQ_H__
11
12#define INT_NUM_IRQ0 8
13#define INT_NUM_IM0_IRL0 (INT_NUM_IRQ0 + 0)
14#define INT_NUM_IM1_IRL0 (INT_NUM_IRQ0 + 32)
15#define INT_NUM_IM2_IRL0 (INT_NUM_IRQ0 + 64)
16#define INT_NUM_IM3_IRL0 (INT_NUM_IRQ0 + 96)
17#define INT_NUM_IM4_IRL0 (INT_NUM_IRQ0 + 128)
18#define INT_NUM_IM_OFFSET (INT_NUM_IM1_IRL0 - INT_NUM_IM0_IRL0)
19
20#define LTQ_ASC_TIR(x) (INT_NUM_IM3_IRL0 + (x * 8))
21#define LTQ_ASC_RIR(x) (INT_NUM_IM3_IRL0 + (x * 8) + 1)
22#define LTQ_ASC_EIR(x) (INT_NUM_IM3_IRL0 + (x * 8) + 2)
23
24#define LTQ_ASC_ASE_TIR INT_NUM_IM2_IRL0
25#define LTQ_ASC_ASE_RIR (INT_NUM_IM2_IRL0 + 2)
26#define LTQ_ASC_ASE_EIR (INT_NUM_IM2_IRL0 + 3)
27
28#define LTQ_SSC_TIR (INT_NUM_IM0_IRL0 + 15)
29#define LTQ_SSC_RIR (INT_NUM_IM0_IRL0 + 14)
30#define LTQ_SSC_EIR (INT_NUM_IM0_IRL0 + 16)
31
32#define LTQ_MEI_DYING_GASP_INT (INT_NUM_IM1_IRL0 + 21)
33#define LTQ_MEI_INT (INT_NUM_IM1_IRL0 + 23)
34
35#define LTQ_TIMER6_INT (INT_NUM_IM1_IRL0 + 23)
36#define LTQ_USB_INT (INT_NUM_IM1_IRL0 + 22)
37#define LTQ_USB_OC_INT (INT_NUM_IM4_IRL0 + 23)
38
39#define MIPS_CPU_TIMER_IRQ 7
40
41#define LTQ_DMA_CH0_INT (INT_NUM_IM2_IRL0)
42#define LTQ_DMA_CH1_INT (INT_NUM_IM2_IRL0 + 1)
43#define LTQ_DMA_CH2_INT (INT_NUM_IM2_IRL0 + 2)
44#define LTQ_DMA_CH3_INT (INT_NUM_IM2_IRL0 + 3)
45#define LTQ_DMA_CH4_INT (INT_NUM_IM2_IRL0 + 4)
46#define LTQ_DMA_CH5_INT (INT_NUM_IM2_IRL0 + 5)
47#define LTQ_DMA_CH6_INT (INT_NUM_IM2_IRL0 + 6)
48#define LTQ_DMA_CH7_INT (INT_NUM_IM2_IRL0 + 7)
49#define LTQ_DMA_CH8_INT (INT_NUM_IM2_IRL0 + 8)
50#define LTQ_DMA_CH9_INT (INT_NUM_IM2_IRL0 + 9)
51#define LTQ_DMA_CH10_INT (INT_NUM_IM2_IRL0 + 10)
52#define LTQ_DMA_CH11_INT (INT_NUM_IM2_IRL0 + 11)
53#define LTQ_DMA_CH12_INT (INT_NUM_IM2_IRL0 + 25)
54#define LTQ_DMA_CH13_INT (INT_NUM_IM2_IRL0 + 26)
55#define LTQ_DMA_CH14_INT (INT_NUM_IM2_IRL0 + 27)
56#define LTQ_DMA_CH15_INT (INT_NUM_IM2_IRL0 + 28)
57#define LTQ_DMA_CH16_INT (INT_NUM_IM2_IRL0 + 29)
58#define LTQ_DMA_CH17_INT (INT_NUM_IM2_IRL0 + 30)
59#define LTQ_DMA_CH18_INT (INT_NUM_IM2_IRL0 + 16)
60#define LTQ_DMA_CH19_INT (INT_NUM_IM2_IRL0 + 21)
61
62#define LTQ_PPE_MBOX_INT (INT_NUM_IM2_IRL0 + 24)
63
64#define INT_NUM_IM4_IRL14 (INT_NUM_IM4_IRL0 + 14)
65
66#endif
diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
new file mode 100644
index 000000000000..343e82cbf601
--- /dev/null
+++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
@@ -0,0 +1,140 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
5 *
6 * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
7 */
8
9#ifndef _LTQ_XWAY_H__
10#define _LTQ_XWAY_H__
11
12#ifdef CONFIG_SOC_TYPE_XWAY
13
14#include <lantiq.h>
15
16/* Chip IDs */
17#define SOC_ID_DANUBE1 0x129
18#define SOC_ID_DANUBE2 0x12B
19#define SOC_ID_TWINPASS 0x12D
20#define SOC_ID_AMAZON_SE 0x152
21#define SOC_ID_ARX188 0x16C
22#define SOC_ID_ARX168 0x16D
23#define SOC_ID_ARX182 0x16F
24
25/* SoC Types */
26#define SOC_TYPE_DANUBE 0x01
27#define SOC_TYPE_TWINPASS 0x02
28#define SOC_TYPE_AR9 0x03
29#define SOC_TYPE_VR9 0x04
30#define SOC_TYPE_AMAZON_SE 0x05
31
32/* ASC0/1 - serial port */
33#define LTQ_ASC0_BASE_ADDR 0x1E100400
34#define LTQ_ASC1_BASE_ADDR 0x1E100C00
35#define LTQ_ASC_SIZE 0x400
36
37/* RCU - reset control unit */
38#define LTQ_RCU_BASE_ADDR 0x1F203000
39#define LTQ_RCU_SIZE 0x1000
40
41/* GPTU - general purpose timer unit */
42#define LTQ_GPTU_BASE_ADDR 0x18000300
43#define LTQ_GPTU_SIZE 0x100
44
45/* EBU - external bus unit */
46#define LTQ_EBU_GPIO_START 0x14000000
47#define LTQ_EBU_GPIO_SIZE 0x1000
48
49#define LTQ_EBU_BASE_ADDR 0x1E105300
50#define LTQ_EBU_SIZE 0x100
51
52#define LTQ_EBU_BUSCON0 0x0060
53#define LTQ_EBU_PCC_CON 0x0090
54#define LTQ_EBU_PCC_IEN 0x00A4
55#define LTQ_EBU_PCC_ISTAT 0x00A0
56#define LTQ_EBU_BUSCON1 0x0064
57#define LTQ_EBU_ADDRSEL1 0x0024
58#define EBU_WRDIS 0x80000000
59
60/* CGU - clock generation unit */
61#define LTQ_CGU_BASE_ADDR 0x1F103000
62#define LTQ_CGU_SIZE 0x1000
63
64/* ICU - interrupt control unit */
65#define LTQ_ICU_BASE_ADDR 0x1F880200
66#define LTQ_ICU_SIZE 0x100
67
68/* EIU - external interrupt unit */
69#define LTQ_EIU_BASE_ADDR 0x1F101000
70#define LTQ_EIU_SIZE 0x1000
71
72/* PMU - power management unit */
73#define LTQ_PMU_BASE_ADDR 0x1F102000
74#define LTQ_PMU_SIZE 0x1000
75
76#define PMU_DMA 0x0020
77#define PMU_USB 0x8041
78#define PMU_LED 0x0800
79#define PMU_GPT 0x1000
80#define PMU_PPE 0x2000
81#define PMU_FPI 0x4000
82#define PMU_SWITCH 0x10000000
83
84/* ETOP - ethernet */
85#define LTQ_PPE32_BASE_ADDR 0xBE180000
86#define LTQ_PPE32_SIZE 0x40000
87
88/* DMA */
89#define LTQ_DMA_BASE_ADDR 0xBE104100
90
91/* PCI */
92#define PCI_CR_BASE_ADDR 0x1E105400
93#define PCI_CR_SIZE 0x400
94
95/* WDT */
96#define LTQ_WDT_BASE_ADDR 0x1F8803F0
97#define LTQ_WDT_SIZE 0x10
98
99/* STP - serial to parallel conversion unit */
100#define LTQ_STP_BASE_ADDR 0x1E100BB0
101#define LTQ_STP_SIZE 0x40
102
103/* GPIO */
104#define LTQ_GPIO0_BASE_ADDR 0x1E100B10
105#define LTQ_GPIO1_BASE_ADDR 0x1E100B40
106#define LTQ_GPIO2_BASE_ADDR 0x1E100B70
107#define LTQ_GPIO_SIZE 0x30
108
109/* SSC */
110#define LTQ_SSC_BASE_ADDR 0x1e100800
111#define LTQ_SSC_SIZE 0x100
112
113/* MEI - dsl core */
114#define LTQ_MEI_BASE_ADDR 0x1E116000
115
116/* DEU - data encryption unit */
117#define LTQ_DEU_BASE_ADDR 0x1E103100
118
119/* MPS - multi processor unit (voice) */
120#define LTQ_MPS_BASE_ADDR (KSEG1 + 0x1F107000)
121#define LTQ_MPS_CHIPID ((u32 *)(LTQ_MPS_BASE_ADDR + 0x0344))
122
123/* request a non-gpio and set the PIO config */
124extern int ltq_gpio_request(unsigned int pin, unsigned int alt0,
125 unsigned int alt1, unsigned int dir, const char *name);
126extern void ltq_pmu_enable(unsigned int module);
127extern void ltq_pmu_disable(unsigned int module);
128
129static inline int ltq_is_ar9(void)
130{
131 return (ltq_get_soc_type() == SOC_TYPE_AR9);
132}
133
134static inline int ltq_is_vr9(void)
135{
136 return (ltq_get_soc_type() == SOC_TYPE_VR9);
137}
138
139#endif /* CONFIG_SOC_TYPE_XWAY */
140#endif /* _LTQ_XWAY_H__ */
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-01 23:53:03 -0500