6 files changed, 27 insertions, 17 deletions

diff --git a/arch/mips/include/asm/compat.h b/arch/mips/include/asm/compat.h
index ac5d541368e9..6c5b40905dd6 100644
--- a/arch/mips/include/asm/compat.h
+++ b/arch/mips/include/asm/compat.h
@@ -3,6 +3,8 @@
 /*
  * Architecture specific compatibility types
  */
+#include <linux/seccomp.h>
+#include <linux/thread_info.h>
 #include <linux/types.h>
 #include <asm/page.h>
 #include <asm/ptrace.h>
@@ -218,4 +220,9 @@ struct compat_shmid64_ds {
         compat_ulong_t  __unused2;
 };
 
+static inline int is_compat_task(void)
+{
+        return test_thread_flag(TIF_32BIT);
+}
+
 #endif /* _ASM_COMPAT_H */
diff --git a/arch/mips/include/asm/hazards.h b/arch/mips/include/asm/hazards.h
index 43baed16a109..134e1fc8f4d6 100644
--- a/arch/mips/include/asm/hazards.h
+++ b/arch/mips/include/asm/hazards.h
@@ -138,7 +138,8 @@ do {									\
                 __instruction_hazard();                                 \
 } while (0)
 
-#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_CAVIUM_OCTEON)
+#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_CAVIUM_OCTEON) || \
+      defined(CONFIG_CPU_R5500)
 
 /*
  * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer.
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 0417516503f6..526f327475ce 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -1391,11 +1391,11 @@ static inline void tlb_write_random(void)
 static inline unsigned int                                      \
 set_c0_##name(unsigned int set)                                 \
 {                                                               \
-        unsigned int res;                                       \
+        unsigned int res, new;                                  \
                                                                 \
         res = read_c0_##name();                                 \
-        res |= set;                                             \
-        write_c0_##name(res);                                   \
+        new = res | set;                                        \
+        write_c0_##name(new);                                   \
                                                                 \
         return res;                                             \
 }                                                               \
@@ -1403,24 +1403,24 @@ set_c0_##name(unsigned int set)					\
 static inline unsigned int                                      \
 clear_c0_##name(unsigned int clear)                             \
 {                                                               \
-        unsigned int res;                                       \
+        unsigned int res, new;                                  \
                                                                 \
         res = read_c0_##name();                                 \
-        res &= ~clear;                                          \
-        write_c0_##name(res);                                   \
+        new = res & ~clear;                                     \
+        write_c0_##name(new);                                   \
                                                                 \
         return res;                                             \
 }                                                               \
                                                                 \
 static inline unsigned int                                      \
-change_c0_##name(unsigned int change, unsigned int new)         \
+change_c0_##name(unsigned int change, unsigned int val)         \
 {                                                               \
-        unsigned int res;                                       \
+        unsigned int res, new;                                  \
                                                                 \
         res = read_c0_##name();                                 \
-        res &= ~change;                                         \
-        res |= (new & change);                                  \
-        write_c0_##name(res);                                   \
+        new = res & ~change;                                    \
+        new |= (val & change);                                  \
+        write_c0_##name(new);                                   \
                                                                 \
         return res;                                             \
 }
diff --git a/arch/mips/include/asm/prefetch.h b/arch/mips/include/asm/prefetch.h
index 17850834ccb0..a56594f360ee 100644
--- a/arch/mips/include/asm/prefetch.h
+++ b/arch/mips/include/asm/prefetch.h
@@ -26,7 +26,7 @@
  * Pref_WriteBackInvalidate is a nop and Pref_PrepareForStore is broken in
  * current versions due to erratum G105.
  *
- * VR7701 only implements the Load prefetch.
+ * VR5500 (including VR5701 and VR7701) only implement load prefetch.
  *
  * Finally MIPS32 and MIPS64 implement all of the following hints.
  */
diff --git a/arch/mips/include/asm/seccomp.h b/arch/mips/include/asm/seccomp.h
index a6772e9507f5..ae6306ebdcad 100644
--- a/arch/mips/include/asm/seccomp.h
+++ b/arch/mips/include/asm/seccomp.h
@@ -15,8 +15,6 @@
  */
 #ifdef CONFIG_MIPS32_O32
 
-#define TIF_32BIT TIF_32BIT_REGS
-
 #define __NR_seccomp_read_32            4003
 #define __NR_seccomp_write_32           4004
 #define __NR_seccomp_exit_32            4001
@@ -24,8 +22,6 @@
 
 #elif defined(CONFIG_MIPS32_N32)
 
-#define TIF_32BIT _TIF_32BIT_ADDR
-
 #define __NR_seccomp_read_32            6000
 #define __NR_seccomp_write_32           6001
 #define __NR_seccomp_exit_32            6058
diff --git a/arch/mips/include/asm/thread_info.h b/arch/mips/include/asm/thread_info.h
index 3f76de73c943..676aa2ae1913 100644
--- a/arch/mips/include/asm/thread_info.h
+++ b/arch/mips/include/asm/thread_info.h
@@ -127,6 +127,12 @@ register struct thread_info *__current_thread_info __asm__("$28");
 #define TIF_LOAD_WATCH          25      /* If set, load watch registers */
 #define TIF_SYSCALL_TRACE       31      /* syscall trace active */
 
+#ifdef CONFIG_MIPS32_O32
+#define TIF_32BIT TIF_32BIT_REGS
+#elif defined(CONFIG_MIPS32_N32)
+#define TIF_32BIT _TIF_32BIT_ADDR
+#endif /* CONFIG_MIPS32_O32 */
+
 #define _TIF_SYSCALL_TRACE      (1<<TIF_SYSCALL_TRACE)
 #define _TIF_SIGPENDING         (1<<TIF_SIGPENDING)
 #define _TIF_NEED_RESCHED       (1<<TIF_NEED_RESCHED)