62 files changed, 1537 insertions, 340 deletions
diff --git a/arch/mips/include/asm/cache.h b/arch/mips/include/asm/cache.h
index 650ac9ba734c..b4db69fbc40c 100644
--- a/arch/mips/include/asm/cache.h
+++ b/arch/mips/include/asm/cache.h
@@ -17,6 +17,6 @@
 #define SMP_CACHE_SHIFT         L1_CACHE_SHIFT
 #define SMP_CACHE_BYTES         L1_CACHE_BYTES
-#define __read_mostly __attribute__((__section__(".data.read_mostly")))
+#define __read_mostly __attribute__((__section__(".data..read_mostly")))
 #endif /* _ASM_CACHE_H */
diff --git a/arch/mips/include/asm/cevt-r4k.h b/arch/mips/include/asm/cevt-r4k.h
index fa4328f9124f..65f9bdd02f1f 100644
--- a/arch/mips/include/asm/cevt-r4k.h
+++ b/arch/mips/include/asm/cevt-r4k.h
@@ -14,6 +14,9 @@
 #ifndef __ASM_CEVT_R4K_H
 #define __ASM_CEVT_R4K_H
+#include <linux/clockchips.h>
+#include <asm/time.h>
 DECLARE_PER_CPU(struct clock_event_device, mips_clockevent_device);
 void mips_event_handler(struct clock_event_device *dev);
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index 86877539c6e8..34c0d3cb116f 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -33,6 +33,7 @@
 #define PRID_COMP_TOSHIBA       0x070000
 #define PRID_COMP_LSI           0x080000
 #define PRID_COMP_LEXRA         0x0b0000
+#define PRID_COMP_NETLOGIC      0x0c0000
 #define PRID_COMP_CAVIUM        0x0d0000
 #define PRID_COMP_INGENIC       0xd00000
@@ -142,6 +143,31 @@
 #define PRID_IMP_JZRISC        0x0200
 /*
+ * These are the PRID's for when 23:16 == PRID_COMP_NETLOGIC
+ */
+#define PRID_IMP_NETLOGIC_XLR732        0x0000
+#define PRID_IMP_NETLOGIC_XLR716        0x0200
+#define PRID_IMP_NETLOGIC_XLR532        0x0900
+#define PRID_IMP_NETLOGIC_XLR308        0x0600
+#define PRID_IMP_NETLOGIC_XLR532C       0x0800
+#define PRID_IMP_NETLOGIC_XLR516C       0x0a00
+#define PRID_IMP_NETLOGIC_XLR508C       0x0b00
+#define PRID_IMP_NETLOGIC_XLR308C       0x0f00
+#define PRID_IMP_NETLOGIC_XLS608        0x8000
+#define PRID_IMP_NETLOGIC_XLS408        0x8800
+#define PRID_IMP_NETLOGIC_XLS404        0x8c00
+#define PRID_IMP_NETLOGIC_XLS208        0x8e00
+#define PRID_IMP_NETLOGIC_XLS204        0x8f00
+#define PRID_IMP_NETLOGIC_XLS108        0xce00
+#define PRID_IMP_NETLOGIC_XLS104        0xcf00
+#define PRID_IMP_NETLOGIC_XLS616B       0x4000
+#define PRID_IMP_NETLOGIC_XLS608B       0x4a00
+#define PRID_IMP_NETLOGIC_XLS416B       0x4400
+#define PRID_IMP_NETLOGIC_XLS412B       0x4c00
+#define PRID_IMP_NETLOGIC_XLS408B       0x4e00
+#define PRID_IMP_NETLOGIC_XLS404B       0x4f00
+/*
 * Definitions for 7:0 on legacy processors
 */
@@ -234,6 +260,7 @@ enum cpu_type_enum {
         */
        CPU_5KC, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2,
        CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS, CPU_CAVIUM_OCTEON2,
+        CPU_XLR,
        CPU_LAST
 };
diff --git a/arch/mips/include/asm/dec/prom.h b/arch/mips/include/asm/dec/prom.h
index b9c8203688d5..c0ead6313845 100644
--- a/arch/mips/include/asm/dec/prom.h
+++ b/arch/mips/include/asm/dec/prom.h
@@ -108,7 +108,7 @@ extern int (*__pmax_close)(int);
 /*
 * On MIPS64 we have to call PROM functions via a helper
- * dispatcher to accomodate ABI incompatibilities.
+ * dispatcher to accommodate ABI incompatibilities.
 */
 #define __DEC_PROM_O32(fun, arg) fun arg __asm__(#fun); \
                                 __asm__(#fun " = call_o32")
diff --git a/arch/mips/include/asm/dma-mapping.h b/arch/mips/include/asm/dma-mapping.h
index 655f849bd08d..7aa37ddfca4b 100644
--- a/arch/mips/include/asm/dma-mapping.h
+++ b/arch/mips/include/asm/dma-mapping.h
@@ -5,7 +5,9 @@
 #include <asm/cache.h>
 #include <asm-generic/dma-coherent.h>
+#ifndef CONFIG_SGI_IP27 /* Kludge to fix 2.6.39 build for IP27 */
 #include <dma-coherence.h>
+#endif
 extern struct dma_map_ops *mips_dma_map_ops;
diff --git a/arch/mips/include/asm/floppy.h b/arch/mips/include/asm/floppy.h
index 992d232adc83..c5c7c0e6064c 100644
--- a/arch/mips/include/asm/floppy.h
+++ b/arch/mips/include/asm/floppy.h
@@ -24,7 +24,7 @@ static inline void fd_cacheflush(char * addr, long size)
 * And on Mips's the CMOS info fails also ...
 *
 * FIXME: This information should come from the ARC configuration tree
- *        or whereever a particular machine has stored this ...
+ *        or wherever a particular machine has stored this ...
 */
 #define FLOPPY0_TYPE            fd_drive_type(0)
 #define FLOPPY1_TYPE            fd_drive_type(1)
diff --git a/arch/mips/include/asm/hugetlb.h b/arch/mips/include/asm/hugetlb.h
index f5e856015329..c565b7c3f0b5 100644
--- a/arch/mips/include/asm/hugetlb.h
+++ b/arch/mips/include/asm/hugetlb.h
@@ -70,6 +70,7 @@ static inline pte_t huge_ptep_get_and_clear(struct mm_struct *mm,
 static inline void huge_ptep_clear_flush(struct vm_area_struct *vma,
                                         unsigned long addr, pte_t *ptep)
 {
+        flush_tlb_mm(vma->vm_mm);
 }
 static inline int huge_pte_none(pte_t pte)
diff --git a/arch/mips/include/asm/hw_irq.h b/arch/mips/include/asm/hw_irq.h
index aca05a43a97b..77adda297ad9 100644
--- a/arch/mips/include/asm/hw_irq.h
+++ b/arch/mips/include/asm/hw_irq.h
@@ -13,7 +13,7 @@
 extern atomic_t irq_err_count;
 /*
- * interrupt-retrigger: NOP for now. This may not be apropriate for all
+ * interrupt-retrigger: NOP for now. This may not be appropriate for all
 * machines, we'll see ...
 */
diff --git a/arch/mips/include/asm/i8253.h b/arch/mips/include/asm/i8253.h
index 48bb82372994..9ad011366f73 100644
--- a/arch/mips/include/asm/i8253.h
+++ b/arch/mips/include/asm/i8253.h
@@ -12,8 +12,13 @@
 #define PIT_CH0                 0x40
 #define PIT_CH2                 0x42
+#define PIT_LATCH               LATCH
 extern raw_spinlock_t i8253_lock;
 extern void setup_pit_timer(void);
+#define inb_pit inb_p
+#define outb_pit outb_p
 #endif /* __ASM_I8253_H */
diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
index 5b017f23e243..b04e4de5dd2e 100644
--- a/arch/mips/include/asm/io.h
+++ b/arch/mips/include/asm/io.h
@@ -242,7 +242,7 @@ static inline void __iomem * __ioremap_mode(phys_t offset, unsigned long size,
 * This version of ioremap ensures that the memory is marked uncachable
 * on the CPU as well as honouring existing caching rules from things like
 * the PCI bus. Note that there are other caches and buffers on many
- * busses. In paticular driver authors should read up on PCI writes
+ * busses. In particular driver authors should read up on PCI writes
 *
 * It's useful if some control registers are in such an area and
 * write combining or read caching is not desirable:
diff --git a/arch/mips/include/asm/irqflags.h b/arch/mips/include/asm/irqflags.h
index 9ef3b0d17896..309cbcd6909c 100644
--- a/arch/mips/include/asm/irqflags.h
+++ b/arch/mips/include/asm/irqflags.h
@@ -174,7 +174,7 @@ __asm__(
        "mtc0   \\flags, $2, 1                                          \n"
 #elif defined(CONFIG_CPU_MIPSR2) && defined(CONFIG_IRQ_CPU)
        /*
-         * Slow, but doesn't suffer from a relativly unlikely race
+         * Slow, but doesn't suffer from a relatively unlikely race
         * condition we're having since days 1.
         */
        "       beqz    \\flags, 1f                                     \n"
diff --git a/arch/mips/include/asm/jump_label.h b/arch/mips/include/asm/jump_label.h
index 7622ccf75076..1881b316ca45 100644
--- a/arch/mips/include/asm/jump_label.h
+++ b/arch/mips/include/asm/jump_label.h
@@ -20,16 +20,18 @@
 #define WORD_INSN ".word"
 #endif
-#define JUMP_LABEL(key, label)                                          \
+static __always_inline bool arch_static_branch(struct jump_label_key *key)
-        do {                                                            \
+{
-                asm goto("1:\tnop\n\t"                                  \
+        asm goto("1:\tnop\n\t"
-                        "nop\n\t"                                       \
+                "nop\n\t"
-                        ".pushsection __jump_table,  \"a\"\n\t"         \
+                ".pushsection __jump_table,  \"aw\"\n\t"
-                        WORD_INSN " 1b, %l[" #label "], %0\n\t"         \
+                WORD_INSN " 1b, %l[l_yes], %0\n\t"
-                        ".popsection\n\t"                               \
+                ".popsection\n\t"
-                        : :  "i" (key) :  : label);                     \
+                : :  "i" (key) : : l_yes);
-        } while (0)
+        return false;
+l_yes:
+        return true;
+}
 #endif /* __KERNEL__ */
diff --git a/arch/mips/include/asm/mach-au1x00/au1000.h b/arch/mips/include/asm/mach-au1x00/au1000.h
index a6976619160a..f260ebed713b 100644
--- a/arch/mips/include/asm/mach-au1x00/au1000.h
+++ b/arch/mips/include/asm/mach-au1x00/au1000.h
@@ -161,6 +161,45 @@ static inline int alchemy_get_cputype(void)
        return ALCHEMY_CPU_UNKNOWN;
 }
+/* return number of uarts on a given cputype */
+static inline int alchemy_get_uarts(int type)
+{
+        switch (type) {
+        case ALCHEMY_CPU_AU1000:
+                return 4;
+        case ALCHEMY_CPU_AU1500:
+        case ALCHEMY_CPU_AU1200:
+                return 2;
+        case ALCHEMY_CPU_AU1100:
+        case ALCHEMY_CPU_AU1550:
+                return 3;
+        }
+        return 0;
+}
+/* enable an UART block if it isn't already */
+static inline void alchemy_uart_enable(u32 uart_phys)
+{
+        void __iomem *addr = (void __iomem *)KSEG1ADDR(uart_phys);
+        /* reset, enable clock, deassert reset */
+        if ((__raw_readl(addr + 0x100) & 3) != 3) {
+                __raw_writel(0, addr + 0x100);
+                wmb();
+                __raw_writel(1, addr + 0x100);
+                wmb();
+        }
+        __raw_writel(3, addr + 0x100);
+        wmb();
+}
+static inline void alchemy_uart_disable(u32 uart_phys)
+{
+        void __iomem *addr = (void __iomem *)KSEG1ADDR(uart_phys);
+        __raw_writel(0, addr + 0x100);  /* UART_MOD_CNTRL */
+        wmb();
+}
 static inline void alchemy_uart_putchar(u32 uart_phys, u8 c)
 {
        void __iomem *base = (void __iomem *)KSEG1ADDR(uart_phys);
@@ -180,6 +219,20 @@ static inline void alchemy_uart_putchar(u32 uart_phys, u8 c)
        wmb();
 }
+/* return number of ethernet MACs on a given cputype */
+static inline int alchemy_get_macs(int type)
+{
+        switch (type) {
+        case ALCHEMY_CPU_AU1000:
+        case ALCHEMY_CPU_AU1500:
+        case ALCHEMY_CPU_AU1550:
+                return 2;
+        case ALCHEMY_CPU_AU1100:
+                return 1;
+        }
+        return 0;
+}
 /* arch/mips/au1000/common/clocks.c */
 extern void set_au1x00_speed(unsigned int new_freq);
 extern unsigned int get_au1x00_speed(void);
@@ -630,38 +683,42 @@ enum soc_au1200_ints {
 /*
 * Physical base addresses for integrated peripherals
+ * 0..au1000 1..au1500 2..au1100 3..au1550 4..au1200
 */
+#define AU1000_AC97_PHYS_ADDR           0x10000000 /* 012 */
+#define AU1000_USBD_PHYS_ADDR           0x10200000 /* 0123 */
+#define AU1000_IC0_PHYS_ADDR            0x10400000 /* 01234 */
+#define AU1000_MAC0_PHYS_ADDR           0x10500000 /* 023 */
+#define AU1000_MAC1_PHYS_ADDR           0x10510000 /* 023 */
+#define AU1000_MACEN_PHYS_ADDR          0x10520000 /* 023 */
+#define AU1100_SD0_PHYS_ADDR            0x10600000 /* 24 */
+#define AU1100_SD1_PHYS_ADDR            0x10680000 /* 24 */
+#define AU1000_I2S_PHYS_ADDR            0x11000000 /* 02 */
+#define AU1500_MAC0_PHYS_ADDR           0x11500000 /* 1 */
+#define AU1500_MAC1_PHYS_ADDR           0x11510000 /* 1 */
+#define AU1500_MACEN_PHYS_ADDR          0x11520000 /* 1 */
+#define AU1000_UART0_PHYS_ADDR          0x11100000 /* 01234 */
+#define AU1000_UART1_PHYS_ADDR          0x11200000 /* 0234 */
+#define AU1000_UART2_PHYS_ADDR          0x11300000 /* 0 */
+#define AU1000_UART3_PHYS_ADDR          0x11400000 /* 0123 */
+#define AU1500_GPIO2_PHYS_ADDR          0x11700000 /* 1234 */
+#define AU1000_IC1_PHYS_ADDR            0x11800000 /* 01234 */
+#define AU1000_SYS_PHYS_ADDR            0x11900000 /* 01234 */
+#define AU1000_DMA_PHYS_ADDR            0x14002000 /* 012 */
+#define AU1550_DBDMA_PHYS_ADDR          0x14002000 /* 34 */
+#define AU1550_DBDMA_CONF_PHYS_ADDR     0x14003000 /* 34 */
+#define AU1000_MACDMA0_PHYS_ADDR        0x14004000 /* 0123 */
+#define AU1000_MACDMA1_PHYS_ADDR        0x14004200 /* 0123 */
 #ifdef CONFIG_SOC_AU1000
 #define MEM_PHYS_ADDR           0x14000000
 #define STATIC_MEM_PHYS_ADDR    0x14001000
-#define DMA0_PHYS_ADDR          0x14002000
-#define DMA1_PHYS_ADDR          0x14002100
-#define DMA2_PHYS_ADDR          0x14002200
-#define DMA3_PHYS_ADDR          0x14002300
-#define DMA4_PHYS_ADDR          0x14002400
-#define DMA5_PHYS_ADDR          0x14002500
-#define DMA6_PHYS_ADDR          0x14002600
-#define DMA7_PHYS_ADDR          0x14002700
-#define IC0_PHYS_ADDR           0x10400000
-#define IC1_PHYS_ADDR           0x11800000
-#define AC97_PHYS_ADDR          0x10000000
 #define USBH_PHYS_ADDR          0x10100000
-#define USBD_PHYS_ADDR          0x10200000
 #define IRDA_PHYS_ADDR          0x10300000
-#define MAC0_PHYS_ADDR          0x10500000
-#define MAC1_PHYS_ADDR          0x10510000
-#define MACEN_PHYS_ADDR         0x10520000
-#define MACDMA0_PHYS_ADDR       0x14004000
-#define MACDMA1_PHYS_ADDR       0x14004200
-#define I2S_PHYS_ADDR           0x11000000
-#define UART0_PHYS_ADDR         0x11100000
-#define UART1_PHYS_ADDR         0x11200000
-#define UART2_PHYS_ADDR         0x11300000
-#define UART3_PHYS_ADDR         0x11400000
 #define SSI0_PHYS_ADDR          0x11600000
 #define SSI1_PHYS_ADDR          0x11680000
-#define SYS_PHYS_ADDR           0x11900000
 #define PCMCIA_IO_PHYS_ADDR     0xF00000000ULL
 #define PCMCIA_ATTR_PHYS_ADDR   0xF40000000ULL
 #define PCMCIA_MEM_PHYS_ADDR    0xF80000000ULL
@@ -672,30 +729,8 @@ enum soc_au1200_ints {
 #ifdef CONFIG_SOC_AU1500
 #define MEM_PHYS_ADDR           0x14000000
 #define STATIC_MEM_PHYS_ADDR    0x14001000
-#define DMA0_PHYS_ADDR          0x14002000
-#define DMA1_PHYS_ADDR          0x14002100
-#define DMA2_PHYS_ADDR          0x14002200
-#define DMA3_PHYS_ADDR          0x14002300
-#define DMA4_PHYS_ADDR          0x14002400
-#define DMA5_PHYS_ADDR          0x14002500
-#define DMA6_PHYS_ADDR          0x14002600
-#define DMA7_PHYS_ADDR          0x14002700
-#define IC0_PHYS_ADDR           0x10400000
-#define IC1_PHYS_ADDR           0x11800000
-#define AC97_PHYS_ADDR          0x10000000
 #define USBH_PHYS_ADDR          0x10100000
-#define USBD_PHYS_ADDR          0x10200000
 #define PCI_PHYS_ADDR           0x14005000
-#define MAC0_PHYS_ADDR          0x11500000
-#define MAC1_PHYS_ADDR          0x11510000
-#define MACEN_PHYS_ADDR         0x11520000
-#define MACDMA0_PHYS_ADDR       0x14004000
-#define MACDMA1_PHYS_ADDR       0x14004200
-#define I2S_PHYS_ADDR           0x11000000
-#define UART0_PHYS_ADDR         0x11100000
-#define UART3_PHYS_ADDR         0x11400000
-#define GPIO2_PHYS_ADDR         0x11700000
-#define SYS_PHYS_ADDR           0x11900000
 #define PCI_MEM_PHYS_ADDR       0x400000000ULL
 #define PCI_IO_PHYS_ADDR        0x500000000ULL
 #define PCI_CONFIG0_PHYS_ADDR   0x600000000ULL
@@ -710,34 +745,10 @@ enum soc_au1200_ints {
 #ifdef CONFIG_SOC_AU1100
 #define MEM_PHYS_ADDR           0x14000000
 #define STATIC_MEM_PHYS_ADDR    0x14001000
-#define DMA0_PHYS_ADDR          0x14002000
-#define DMA1_PHYS_ADDR          0x14002100
-#define DMA2_PHYS_ADDR          0x14002200
-#define DMA3_PHYS_ADDR          0x14002300
-#define DMA4_PHYS_ADDR          0x14002400
-#define DMA5_PHYS_ADDR          0x14002500
-#define DMA6_PHYS_ADDR          0x14002600
-#define DMA7_PHYS_ADDR          0x14002700
-#define IC0_PHYS_ADDR           0x10400000
-#define SD0_PHYS_ADDR           0x10600000
-#define SD1_PHYS_ADDR           0x10680000
-#define IC1_PHYS_ADDR           0x11800000
-#define AC97_PHYS_ADDR          0x10000000
 #define USBH_PHYS_ADDR          0x10100000
-#define USBD_PHYS_ADDR          0x10200000
 #define IRDA_PHYS_ADDR          0x10300000
-#define MAC0_PHYS_ADDR          0x10500000
-#define MACEN_PHYS_ADDR         0x10520000
-#define MACDMA0_PHYS_ADDR       0x14004000
-#define MACDMA1_PHYS_ADDR       0x14004200
-#define I2S_PHYS_ADDR           0x11000000
-#define UART0_PHYS_ADDR         0x11100000
-#define UART1_PHYS_ADDR         0x11200000
-#define UART3_PHYS_ADDR         0x11400000
 #define SSI0_PHYS_ADDR          0x11600000
 #define SSI1_PHYS_ADDR          0x11680000
-#define GPIO2_PHYS_ADDR         0x11700000
-#define SYS_PHYS_ADDR           0x11900000
 #define LCD_PHYS_ADDR           0x15000000
 #define PCMCIA_IO_PHYS_ADDR     0xF00000000ULL
 #define PCMCIA_ATTR_PHYS_ADDR   0xF40000000ULL
@@ -749,22 +760,8 @@ enum soc_au1200_ints {
 #ifdef CONFIG_SOC_AU1550
 #define MEM_PHYS_ADDR           0x14000000
 #define STATIC_MEM_PHYS_ADDR    0x14001000
-#define IC0_PHYS_ADDR           0x10400000
-#define IC1_PHYS_ADDR           0x11800000
 #define USBH_PHYS_ADDR          0x14020000
-#define USBD_PHYS_ADDR          0x10200000
 #define PCI_PHYS_ADDR           0x14005000
-#define MAC0_PHYS_ADDR          0x10500000
-#define MAC1_PHYS_ADDR          0x10510000
-#define MACEN_PHYS_ADDR         0x10520000
-#define MACDMA0_PHYS_ADDR       0x14004000
-#define MACDMA1_PHYS_ADDR       0x14004200
-#define UART0_PHYS_ADDR         0x11100000
-#define UART1_PHYS_ADDR         0x11200000
-#define UART3_PHYS_ADDR         0x11400000
-#define GPIO2_PHYS_ADDR         0x11700000
-#define SYS_PHYS_ADDR           0x11900000
-#define DDMA_PHYS_ADDR          0x14002000
 #define PE_PHYS_ADDR            0x14008000
 #define PSC0_PHYS_ADDR          0x11A00000
 #define PSC1_PHYS_ADDR          0x11B00000
@@ -786,19 +783,10 @@ enum soc_au1200_ints {
 #define STATIC_MEM_PHYS_ADDR    0x14001000
 #define AES_PHYS_ADDR           0x10300000
 #define CIM_PHYS_ADDR           0x14004000
-#define IC0_PHYS_ADDR           0x10400000
-#define IC1_PHYS_ADDR           0x11800000
 #define USBM_PHYS_ADDR          0x14020000
 #define USBH_PHYS_ADDR          0x14020100
-#define UART0_PHYS_ADDR         0x11100000
-#define UART1_PHYS_ADDR         0x11200000
-#define GPIO2_PHYS_ADDR         0x11700000
-#define SYS_PHYS_ADDR           0x11900000
-#define DDMA_PHYS_ADDR          0x14002000
 #define PSC0_PHYS_ADDR          0x11A00000
 #define PSC1_PHYS_ADDR          0x11B00000
-#define SD0_PHYS_ADDR           0x10600000
-#define SD1_PHYS_ADDR           0x10680000
 #define LCD_PHYS_ADDR           0x15000000
 #define SWCNT_PHYS_ADDR         0x1110010C
 #define MAEFE_PHYS_ADDR         0x14012000
@@ -835,183 +823,43 @@ enum soc_au1200_ints {
 #endif
-/* Interrupt Controller register offsets */
-#define IC_CFG0RD               0x40
-#define IC_CFG0SET              0x40
-#define IC_CFG0CLR              0x44
-#define IC_CFG1RD               0x48
-#define IC_CFG1SET              0x48
-#define IC_CFG1CLR              0x4C
-#define IC_CFG2RD               0x50
-#define IC_CFG2SET              0x50
-#define IC_CFG2CLR              0x54
-#define IC_REQ0INT              0x54
-#define IC_SRCRD                0x58
-#define IC_SRCSET               0x58
-#define IC_SRCCLR               0x5C
-#define IC_REQ1INT              0x5C
-#define IC_ASSIGNRD             0x60
-#define IC_ASSIGNSET            0x60
-#define IC_ASSIGNCLR            0x64
-#define IC_WAKERD               0x68
-#define IC_WAKESET              0x68
-#define IC_WAKECLR              0x6C
-#define IC_MASKRD               0x70
-#define IC_MASKSET              0x70
-#define IC_MASKCLR              0x74
-#define IC_RISINGRD             0x78
-#define IC_RISINGCLR            0x78
-#define IC_FALLINGRD            0x7C
-#define IC_FALLINGCLR           0x7C
-#define IC_TESTBIT              0x80
-/* Interrupt Controller 0 */
-#define IC0_CFG0RD              0xB0400040
-#define IC0_CFG0SET             0xB0400040
-#define IC0_CFG0CLR             0xB0400044
-#define IC0_CFG1RD              0xB0400048
-#define IC0_CFG1SET             0xB0400048
-#define IC0_CFG1CLR             0xB040004C
-#define IC0_CFG2RD              0xB0400050
-#define IC0_CFG2SET             0xB0400050
-#define IC0_CFG2CLR             0xB0400054
-#define IC0_REQ0INT             0xB0400054
-#define IC0_SRCRD               0xB0400058
-#define IC0_SRCSET              0xB0400058
-#define IC0_SRCCLR              0xB040005C
-#define IC0_REQ1INT             0xB040005C
-#define IC0_ASSIGNRD            0xB0400060
-#define IC0_ASSIGNSET           0xB0400060
-#define IC0_ASSIGNCLR           0xB0400064
-#define IC0_WAKERD              0xB0400068
-#define IC0_WAKESET             0xB0400068
-#define IC0_WAKECLR             0xB040006C
-#define IC0_MASKRD              0xB0400070
-#define IC0_MASKSET             0xB0400070
-#define IC0_MASKCLR             0xB0400074
-#define IC0_RISINGRD            0xB0400078
-#define IC0_RISINGCLR           0xB0400078
-#define IC0_FALLINGRD           0xB040007C
-#define IC0_FALLINGCLR          0xB040007C
-#define IC0_TESTBIT             0xB0400080
-/* Interrupt Controller 1 */
-#define IC1_CFG0RD              0xB1800040
-#define IC1_CFG0SET             0xB1800040
-#define IC1_CFG0CLR             0xB1800044
-#define IC1_CFG1RD              0xB1800048
-#define IC1_CFG1SET             0xB1800048
-#define IC1_CFG1CLR             0xB180004C
-#define IC1_CFG2RD              0xB1800050
-#define IC1_CFG2SET             0xB1800050
-#define IC1_CFG2CLR             0xB1800054
-#define IC1_REQ0INT             0xB1800054
-#define IC1_SRCRD               0xB1800058
-#define IC1_SRCSET              0xB1800058
-#define IC1_SRCCLR              0xB180005C
-#define IC1_REQ1INT             0xB180005C
-#define IC1_ASSIGNRD            0xB1800060
-#define IC1_ASSIGNSET           0xB1800060
-#define IC1_ASSIGNCLR           0xB1800064
-#define IC1_WAKERD              0xB1800068
-#define IC1_WAKESET             0xB1800068
-#define IC1_WAKECLR             0xB180006C
-#define IC1_MASKRD              0xB1800070
-#define IC1_MASKSET             0xB1800070
-#define IC1_MASKCLR             0xB1800074
-#define IC1_RISINGRD            0xB1800078
-#define IC1_RISINGCLR           0xB1800078
-#define IC1_FALLINGRD           0xB180007C
-#define IC1_FALLINGCLR          0xB180007C
-#define IC1_TESTBIT             0xB1800080
 /* Au1000 */
 #ifdef CONFIG_SOC_AU1000
-#define UART0_ADDR              0xB1100000
-#define UART3_ADDR              0xB1400000
 #define USB_OHCI_BASE           0x10100000      /* phys addr for ioremap */
 #define USB_HOST_CONFIG         0xB017FFFC
 #define FOR_PLATFORM_C_USB_HOST_INT AU1000_USB_HOST_INT
-#define AU1000_ETH0_BASE        0xB0500000
-#define AU1000_ETH1_BASE        0xB0510000
-#define AU1000_MAC0_ENABLE      0xB0520000
-#define AU1000_MAC1_ENABLE      0xB0520004
-#define NUM_ETH_INTERFACES 2
 #endif /* CONFIG_SOC_AU1000 */
 /* Au1500 */
 #ifdef CONFIG_SOC_AU1500
-#define UART0_ADDR              0xB1100000
-#define UART3_ADDR              0xB1400000
 #define USB_OHCI_BASE           0x10100000      /* phys addr for ioremap */
 #define USB_HOST_CONFIG         0xB017fffc
 #define FOR_PLATFORM_C_USB_HOST_INT AU1500_USB_HOST_INT
-#define AU1500_ETH0_BASE        0xB1500000
-#define AU1500_ETH1_BASE        0xB1510000
-#define AU1500_MAC0_ENABLE      0xB1520000
-#define AU1500_MAC1_ENABLE      0xB1520004
-#define NUM_ETH_INTERFACES 2
 #endif /* CONFIG_SOC_AU1500 */
 /* Au1100 */
 #ifdef CONFIG_SOC_AU1100
-#define UART0_ADDR              0xB1100000
-#define UART3_ADDR              0xB1400000
 #define USB_OHCI_BASE           0x10100000      /* phys addr for ioremap */
 #define USB_HOST_CONFIG         0xB017FFFC
 #define FOR_PLATFORM_C_USB_HOST_INT AU1100_USB_HOST_INT
-#define AU1100_ETH0_BASE        0xB0500000
-#define AU1100_MAC0_ENABLE      0xB0520000
-#define NUM_ETH_INTERFACES 1
 #endif /* CONFIG_SOC_AU1100 */
 #ifdef CONFIG_SOC_AU1550
-#define UART0_ADDR              0xB1100000
 #define USB_OHCI_BASE           0x14020000      /* phys addr for ioremap */
 #define USB_OHCI_LEN            0x00060000
 #define USB_HOST_CONFIG         0xB4027ffc
 #define FOR_PLATFORM_C_USB_HOST_INT AU1550_USB_HOST_INT
-#define AU1550_ETH0_BASE        0xB0500000
-#define AU1550_ETH1_BASE        0xB0510000
-#define AU1550_MAC0_ENABLE      0xB0520000
-#define AU1550_MAC1_ENABLE      0xB0520004
-#define NUM_ETH_INTERFACES 2
 #endif /* CONFIG_SOC_AU1550 */
 #ifdef CONFIG_SOC_AU1200
-#define UART0_ADDR              0xB1100000
 #define USB_UOC_BASE            0x14020020
 #define USB_UOC_LEN             0x20
 #define USB_OHCI_BASE           0x14020100
@@ -1504,22 +1352,6 @@ enum soc_au1200_ints {
 #define SYS_PINFUNC_S1B         (1 << 2)
 #endif
-#define SYS_TRIOUTRD            0xB1900100
-#define SYS_TRIOUTCLR           0xB1900100
-#define SYS_OUTPUTRD            0xB1900108
-#define SYS_OUTPUTSET           0xB1900108
-#define SYS_OUTPUTCLR           0xB190010C
-#define SYS_PINSTATERD          0xB1900110
-#define SYS_PININPUTEN          0xB1900110
-/* GPIO2, Au1500, Au1550 only */
-#define GPIO2_BASE              0xB1700000
-#define GPIO2_DIR               (GPIO2_BASE + 0)
-#define GPIO2_OUTPUT            (GPIO2_BASE + 8)
-#define GPIO2_PINSTATE          (GPIO2_BASE + 0xC)
-#define GPIO2_INTENABLE         (GPIO2_BASE + 0x10)
-#define GPIO2_ENABLE            (GPIO2_BASE + 0x14)
 /* Power Management */
 #define SYS_SCRATCH0            0xB1900018
 #define SYS_SCRATCH1            0xB190001C
@@ -1635,12 +1467,6 @@ enum soc_au1200_ints {
 #  define AC97C_RS              (1 << 1)
 #  define AC97C_CE              (1 << 0)
-/* Secure Digital (SD) Controller */
-#define SD0_XMIT_FIFO   0xB0600000
-#define SD0_RECV_FIFO   0xB0600004
-#define SD1_XMIT_FIFO   0xB0680000
-#define SD1_RECV_FIFO   0xB0680004
 #if defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550)
 /* Au1500 PCI Controller */
 #define Au1500_CFG_BASE         0xB4005000      /* virtual, KSEG1 addr */
diff --git a/arch/mips/include/asm/mach-au1x00/au1000_dma.h b/arch/mips/include/asm/mach-au1x00/au1000_dma.h
index c333b4e1cd44..59f5b55b2200 100644
--- a/arch/mips/include/asm/mach-au1x00/au1000_dma.h
+++ b/arch/mips/include/asm/mach-au1x00/au1000_dma.h
@@ -37,10 +37,6 @@
 #define NUM_AU1000_DMA_CHANNELS 8
-/* DMA Channel Base Addresses */
-#define DMA_CHANNEL_BASE        0xB4002000
-#define DMA_CHANNEL_LEN         0x00000100
 /* DMA Channel Register Offsets */
 #define DMA_MODE_SET            0x00000000
 #define DMA_MODE_READ           DMA_MODE_SET
diff --git a/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h b/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h
index c8a553a36ba4..2fdacfe85e23 100644
--- a/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h
+++ b/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h
@@ -37,14 +37,6 @@
 #ifndef _LANGUAGE_ASSEMBLY
-/*
- * The DMA base addresses.
- * The channels are every 256 bytes (0x0100) from the channel 0 base.
- * Interrupt status/enable is bits 15:0 for channels 15 to zero.
- */
-#define DDMA_GLOBAL_BASE        0xb4003000
-#define DDMA_CHANNEL_BASE       0xb4002000
 typedef volatile struct dbdma_global {
        u32     ddma_config;
        u32     ddma_intstat;
diff --git a/arch/mips/include/asm/mach-au1x00/gpio-au1000.h b/arch/mips/include/asm/mach-au1x00/gpio-au1000.h
index 62d2f136d941..1f41a522906d 100644
--- a/arch/mips/include/asm/mach-au1x00/gpio-au1000.h
+++ b/arch/mips/include/asm/mach-au1x00/gpio-au1000.h
@@ -24,6 +24,23 @@
 #define MAKE_IRQ(intc, off)     (AU1000_INTC##intc##_INT_BASE + (off))
+/* GPIO1 registers within SYS_ area */
+#define SYS_TRIOUTRD            0x100
+#define SYS_TRIOUTCLR           0x100
+#define SYS_OUTPUTRD            0x108
+#define SYS_OUTPUTSET           0x108
+#define SYS_OUTPUTCLR           0x10C
+#define SYS_PINSTATERD          0x110
+#define SYS_PININPUTEN          0x110
+/* register offsets within GPIO2 block */
+#define GPIO2_DIR               0x00
+#define GPIO2_OUTPUT            0x08
+#define GPIO2_PINSTATE          0x0C
+#define GPIO2_INTENABLE         0x10
+#define GPIO2_ENABLE            0x14
+struct gpio;
 static inline int au1000_gpio1_to_irq(int gpio)
 {
@@ -200,23 +217,26 @@ static inline int au1200_irq_to_gpio(int irq)
 */
 static inline void alchemy_gpio1_set_value(int gpio, int v)
 {
+        void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_SYS_PHYS_ADDR);
        unsigned long mask = 1 << (gpio - ALCHEMY_GPIO1_BASE);
        unsigned long r = v ? SYS_OUTPUTSET : SYS_OUTPUTCLR;
-        au_writel(mask, r);
+        __raw_writel(mask, base + r);
-        au_sync();
+        wmb();
 }
 static inline int alchemy_gpio1_get_value(int gpio)
 {
+        void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_SYS_PHYS_ADDR);
        unsigned long mask = 1 << (gpio - ALCHEMY_GPIO1_BASE);
-        return au_readl(SYS_PINSTATERD) & mask;
+        return __raw_readl(base + SYS_PINSTATERD) & mask;
 }
 static inline int alchemy_gpio1_direction_input(int gpio)
 {
+        void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_SYS_PHYS_ADDR);
        unsigned long mask = 1 << (gpio - ALCHEMY_GPIO1_BASE);
-        au_writel(mask, SYS_TRIOUTCLR);
+        __raw_writel(mask, base + SYS_TRIOUTCLR);
-        au_sync();
+        wmb();
        return 0;
 }
@@ -257,27 +277,31 @@ static inline int alchemy_gpio1_to_irq(int gpio)
 */
 static inline void __alchemy_gpio2_mod_dir(int gpio, int to_out)
 {
+        void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR);
        unsigned long mask = 1 << (gpio - ALCHEMY_GPIO2_BASE);
-        unsigned long d = au_readl(GPIO2_DIR);
+        unsigned long d = __raw_readl(base + GPIO2_DIR);
        if (to_out)
                d |= mask;
        else
                d &= ~mask;
-        au_writel(d, GPIO2_DIR);
+        __raw_writel(d, base + GPIO2_DIR);
-        au_sync();
+        wmb();
 }
 static inline void alchemy_gpio2_set_value(int gpio, int v)
 {
+        void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR);
        unsigned long mask;
        mask = ((v) ? 0x00010001 : 0x00010000) << (gpio - ALCHEMY_GPIO2_BASE);
-        au_writel(mask, GPIO2_OUTPUT);
+        __raw_writel(mask, base + GPIO2_OUTPUT);
-        au_sync();
+        wmb();
 }
 static inline int alchemy_gpio2_get_value(int gpio)
 {
-        return au_readl(GPIO2_PINSTATE) & (1 << (gpio - ALCHEMY_GPIO2_BASE));
+        void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR);
+        return __raw_readl(base + GPIO2_PINSTATE) & (1 << (gpio - ALCHEMY_GPIO2_BASE));
 }
 static inline int alchemy_gpio2_direction_input(int gpio)
@@ -329,21 +353,23 @@ static inline int alchemy_gpio2_to_irq(int gpio)
 */
 static inline void alchemy_gpio1_input_enable(void)
 {
-        au_writel(0, SYS_PININPUTEN);   /* the write op is key */
+        void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_SYS_PHYS_ADDR);
-        au_sync();
+        __raw_writel(0, base + SYS_PININPUTEN); /* the write op is key */
+        wmb();
 }
 /* GPIO2 shared interrupts and control */
 static inline void __alchemy_gpio2_mod_int(int gpio2, int en)
 {
-        unsigned long r = au_readl(GPIO2_INTENABLE);
+        void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR);
+        unsigned long r = __raw_readl(base + GPIO2_INTENABLE);
        if (en)
                r |= 1 << gpio2;
        else
                r &= ~(1 << gpio2);
-        au_writel(r, GPIO2_INTENABLE);
+        __raw_writel(r, base + GPIO2_INTENABLE);
-        au_sync();
+        wmb();
 }
 /**
@@ -418,10 +444,11 @@ static inline void alchemy_gpio2_disable_int(int gpio2)
 */
 static inline void alchemy_gpio2_enable(void)
 {
-        au_writel(3, GPIO2_ENABLE);     /* reset, clock enabled */
+        void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR);
-        au_sync();
+        __raw_writel(3, base + GPIO2_ENABLE);   /* reset, clock enabled */
-        au_writel(1, GPIO2_ENABLE);     /* clock enabled */
+        wmb();
-        au_sync();
+        __raw_writel(1, base + GPIO2_ENABLE);   /* clock enabled */
+        wmb();
 }
 /**
@@ -431,8 +458,9 @@ static inline void alchemy_gpio2_enable(void)
 */
 static inline void alchemy_gpio2_disable(void)
 {
-        au_writel(2, GPIO2_ENABLE);     /* reset, clock disabled */
+        void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR);
-        au_sync();
+        __raw_writel(2, base + GPIO2_ENABLE);   /* reset, clock disabled */
+        wmb();
 }
 /**********************************************************************/
@@ -556,6 +584,16 @@ static inline void gpio_set_value(int gpio, int v)
        alchemy_gpio_set_value(gpio, v);
 }
+static inline int gpio_get_value_cansleep(unsigned gpio)
+{
+        return gpio_get_value(gpio);
+}
+static inline void gpio_set_value_cansleep(unsigned gpio, int value)
+{
+        gpio_set_value(gpio, value);
+}
 static inline int gpio_is_valid(int gpio)
 {
        return alchemy_gpio_is_valid(gpio);
@@ -581,10 +619,50 @@ static inline int gpio_request(unsigned gpio, const char *label)
        return 0;
 }
+static inline int gpio_request_one(unsigned gpio,
+                                        unsigned long flags, const char *label)
+{
+        return 0;
+}
+static inline int gpio_request_array(struct gpio *array, size_t num)
+{
+        return 0;
+}
 static inline void gpio_free(unsigned gpio)
 {
 }
+static inline void gpio_free_array(struct gpio *array, size_t num)
+{
+}
+static inline int gpio_set_debounce(unsigned gpio, unsigned debounce)
+{
+        return -ENOSYS;
+}
+static inline int gpio_export(unsigned gpio, bool direction_may_change)
+{
+        return -ENOSYS;
+}
+static inline int gpio_export_link(struct device *dev, const char *name,
+                                   unsigned gpio)
+{
+        return -ENOSYS;
+}
+static inline int gpio_sysfs_set_active_low(unsigned gpio, int value)
+{
+        return -ENOSYS;
+}
+static inline void gpio_unexport(unsigned gpio)
+{
+}
 #endif  /* !CONFIG_ALCHEMY_GPIO_INDIRECT */
diff --git a/arch/mips/include/asm/mach-bcm47xx/nvram.h b/arch/mips/include/asm/mach-bcm47xx/nvram.h
index 9759588ba3cf..184d5ecb5f51 100644
--- a/arch/mips/include/asm/mach-bcm47xx/nvram.h
+++ b/arch/mips/include/asm/mach-bcm47xx/nvram.h
@@ -39,8 +39,16 @@ extern int nvram_getenv(char *name, char *val, size_t val_len);
 static inline void nvram_parse_macaddr(char *buf, u8 *macaddr)
 {
-        sscanf(buf, "%hhx:%hhx:%hhx:%hhx:%hhx:%hhx", &macaddr[0], &macaddr[1],
+        if (strchr(buf, ':'))
-               &macaddr[2], &macaddr[3], &macaddr[4], &macaddr[5]);
+                sscanf(buf, "%hhx:%hhx:%hhx:%hhx:%hhx:%hhx", &macaddr[0],
+                        &macaddr[1], &macaddr[2], &macaddr[3], &macaddr[4],
+                        &macaddr[5]);
+        else if (strchr(buf, '-'))
+                sscanf(buf, "%hhx-%hhx-%hhx-%hhx-%hhx-%hhx", &macaddr[0],
+                        &macaddr[1], &macaddr[2], &macaddr[3], &macaddr[4],
+                        &macaddr[5]);
+        else
+                printk(KERN_WARNING "Can not parse mac address: %s\n", buf);
 }
 #endif
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm963xx_tag.h b/arch/mips/include/asm/mach-bcm63xx/bcm963xx_tag.h
index 5325084d5c48..ed72e6a26b73 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm963xx_tag.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm963xx_tag.h
@@ -4,7 +4,7 @@
 #define TAGVER_LEN              4       /* Length of Tag Version */
 #define TAGLAYOUT_LEN           4       /* Length of FlashLayoutVer */
 #define SIG1_LEN                20      /* Company Signature 1 Length */
-#define SIG2_LEN                14      /* Company Signature 2 Lenght */
+#define SIG2_LEN                14      /* Company Signature 2 Length */
 #define BOARDID_LEN             16      /* Length of BoardId */
 #define ENDIANFLAG_LEN          2       /* Endian Flag Length */
 #define CHIPID_LEN              6       /* Chip Id Length */
@@ -88,7 +88,7 @@ struct bcm_tag {
        char kernel_crc[CRC_LEN];
        /* 228-235: Unused at present */
        char reserved1[8];
-        /* 236-239: CRC32 of header excluding tagVersion */
+        /* 236-239: CRC32 of header excluding last 20 bytes */
        char header_crc[CRC_LEN];
        /* 240-255: Unused at present */
        char reserved2[16];
diff --git a/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h b/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
index 0b2b5eb22e9b..dedef7d2b01f 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
@@ -63,6 +63,11 @@
        # CN30XX Disable instruction prefetching
        or  v0, v0, 0x2000
 skip:
+        # First clear off CvmCtl[IPPCI] bit and move the performance
+        # counters interrupt to IRQ 6
+        li      v1, ~(7 << 7)
+        and     v0, v0, v1
+        ori     v0, v0, (6 << 7)
        # Write the cavium control register
        dmtc0   v0, CP0_CVMCTL_REG
        sync
diff --git a/arch/mips/include/asm/mach-ip32/mc146818rtc.h b/arch/mips/include/asm/mach-ip32/mc146818rtc.h
index c28ba8d84076..6b6bab43d5c1 100644
--- a/arch/mips/include/asm/mach-ip32/mc146818rtc.h
+++ b/arch/mips/include/asm/mach-ip32/mc146818rtc.h
@@ -26,7 +26,7 @@ static inline void CMOS_WRITE(unsigned char data, unsigned long addr)
 }
 /*
- * FIXME: Do it right. For now just assume that noone lives in 20th century
+ * FIXME: Do it right. For now just assume that no one lives in 20th century
 * and no O2 user in 22th century ;-)
 */
 #define mc146818_decode_year(year) ((year) + 2000)
diff --git a/arch/mips/include/asm/mach-lantiq/lantiq.h b/arch/mips/include/asm/mach-lantiq/lantiq.h
new file mode 100644
index 000000000000..ce2f02929d22
--- /dev/null
+++ b/arch/mips/include/asm/mach-lantiq/lantiq.h
@@ -0,0 +1,63 @@
+/*
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ *
+ *  Copyright (C) 2010 John Crispin <blogic@openwrt.org>
+ */
+#ifndef _LANTIQ_H__
+#define _LANTIQ_H__
+#include <linux/irq.h>
+/* generic reg access functions */
+#define ltq_r32(reg)            __raw_readl(reg)
+#define ltq_w32(val, reg)       __raw_writel(val, reg)
+#define ltq_w32_mask(clear, set, reg)   \
+        ltq_w32((ltq_r32(reg) & ~(clear)) | (set), reg)
+#define ltq_r8(reg)             __raw_readb(reg)
+#define ltq_w8(val, reg)        __raw_writeb(val, reg)
+/* register access macros for EBU and CGU */
+#define ltq_ebu_w32(x, y)       ltq_w32((x), ltq_ebu_membase + (y))
+#define ltq_ebu_r32(x)          ltq_r32(ltq_ebu_membase + (x))
+#define ltq_cgu_w32(x, y)       ltq_w32((x), ltq_cgu_membase + (y))
+#define ltq_cgu_r32(x)          ltq_r32(ltq_cgu_membase + (x))
+extern __iomem void *ltq_ebu_membase;
+extern __iomem void *ltq_cgu_membase;
+extern unsigned int ltq_get_cpu_ver(void);
+extern unsigned int ltq_get_soc_type(void);
+/* clock speeds */
+#define CLOCK_60M       60000000
+#define CLOCK_83M       83333333
+#define CLOCK_111M      111111111
+#define CLOCK_133M      133333333
+#define CLOCK_167M      166666667
+#define CLOCK_200M      200000000
+#define CLOCK_266M      266666666
+#define CLOCK_333M      333333333
+#define CLOCK_400M      400000000
+/* spinlock all ebu i/o */
+extern spinlock_t ebu_lock;
+/* some irq helpers */
+extern void ltq_disable_irq(struct irq_data *data);
+extern void ltq_mask_and_ack_irq(struct irq_data *data);
+extern void ltq_enable_irq(struct irq_data *data);
+/* find out what caused the last cpu reset */
+extern int ltq_reset_cause(void);
+#define LTQ_RST_CAUSE_WDTRST    0x20
+#define IOPORT_RESOURCE_START   0x10000000
+#define IOPORT_RESOURCE_END     0xffffffff
+#define IOMEM_RESOURCE_START    0x10000000
+#define IOMEM_RESOURCE_END      0xffffffff
+#define LTQ_FLASH_START         0x10000000
+#define LTQ_FLASH_MAX           0x04000000
+#endif
diff --git a/arch/mips/include/asm/mach-lantiq/lantiq_platform.h b/arch/mips/include/asm/mach-lantiq/lantiq_platform.h
new file mode 100644
index 000000000000..a305f1d0259e
--- /dev/null
+++ b/arch/mips/include/asm/mach-lantiq/lantiq_platform.h
@@ -0,0 +1,53 @@
+/*
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ *
+ *  Copyright (C) 2010 John Crispin <blogic@openwrt.org>
+ */
+#ifndef _LANTIQ_PLATFORM_H__
+#define _LANTIQ_PLATFORM_H__
+#include <linux/mtd/partitions.h>
+#include <linux/socket.h>
+/* struct used to pass info to the pci core */
+enum {
+        PCI_CLOCK_INT = 0,
+        PCI_CLOCK_EXT
+};
+#define PCI_EXIN0       0x0001
+#define PCI_EXIN1       0x0002
+#define PCI_EXIN2       0x0004
+#define PCI_EXIN3       0x0008
+#define PCI_EXIN4       0x0010
+#define PCI_EXIN5       0x0020
+#define PCI_EXIN_MAX    6
+#define PCI_GNT1        0x0040
+#define PCI_GNT2        0x0080
+#define PCI_GNT3        0x0100
+#define PCI_GNT4        0x0200
+#define PCI_REQ1        0x0400
+#define PCI_REQ2        0x0800
+#define PCI_REQ3        0x1000
+#define PCI_REQ4        0x2000
+#define PCI_REQ_SHIFT   10
+#define PCI_REQ_MASK    0xf
+struct ltq_pci_data {
+        int clock;
+        int gpio;
+        int irq[16];
+};
+/* struct used to pass info to network drivers */
+struct ltq_eth_data {
+        struct sockaddr mac;
+        int mii_mode;
+};
+#endif
diff --git a/arch/mips/include/asm/mach-lantiq/war.h b/arch/mips/include/asm/mach-lantiq/war.h
new file mode 100644
index 000000000000..01b08ef368d1
--- /dev/null
+++ b/arch/mips/include/asm/mach-lantiq/war.h
@@ -0,0 +1,24 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ */
+#ifndef __ASM_MIPS_MACH_LANTIQ_WAR_H
+#define __ASM_MIPS_MACH_LANTIQ_WAR_H
+#define R4600_V1_INDEX_ICACHEOP_WAR     0
+#define R4600_V1_HIT_CACHEOP_WAR        0
+#define R4600_V2_HIT_CACHEOP_WAR        0
+#define R5432_CP0_INTERRUPT_WAR         0
+#define BCM1250_M3_WAR                  0
+#define SIBYTE_1956_WAR                 0
+#define MIPS4K_ICACHE_REFILL_WAR        0
+#define MIPS_CACHE_SYNC_WAR             0
+#define TX49XX_ICACHE_INDEX_INV_WAR     0
+#define RM9000_CDEX_SMP_WAR             0
+#define ICACHE_REFILLS_WORKAROUND_WAR   0
+#define R10000_LLSC_WAR                 0
+#define MIPS34K_MISSED_ITLB_WAR         0
+#endif
diff --git a/arch/mips/include/asm/mach-lantiq/xway/irq.h b/arch/mips/include/asm/mach-lantiq/xway/irq.h
new file mode 100644
index 000000000000..a1471d2dd0d2
--- /dev/null
+++ b/arch/mips/include/asm/mach-lantiq/xway/irq.h
@@ -0,0 +1,18 @@
+/*
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ *
+ *  Copyright (C) 2010 John Crispin <blogic@openwrt.org>
+ */
+#ifndef __LANTIQ_IRQ_H
+#define __LANTIQ_IRQ_H
+#include <lantiq_irq.h>
+#define NR_IRQS 256
+#include_next <irq.h>
+#endif
diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h
new file mode 100644
index 000000000000..b4465a888e20
--- /dev/null
+++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h
@@ -0,0 +1,66 @@
+/*
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ *
+ *  Copyright (C) 2010 John Crispin <blogic@openwrt.org>
+ */
+#ifndef _LANTIQ_XWAY_IRQ_H__
+#define _LANTIQ_XWAY_IRQ_H__
+#define INT_NUM_IRQ0            8
+#define INT_NUM_IM0_IRL0        (INT_NUM_IRQ0 + 0)
+#define INT_NUM_IM1_IRL0        (INT_NUM_IRQ0 + 32)
+#define INT_NUM_IM2_IRL0        (INT_NUM_IRQ0 + 64)
+#define INT_NUM_IM3_IRL0        (INT_NUM_IRQ0 + 96)
+#define INT_NUM_IM4_IRL0        (INT_NUM_IRQ0 + 128)
+#define INT_NUM_IM_OFFSET       (INT_NUM_IM1_IRL0 - INT_NUM_IM0_IRL0)
+#define LTQ_ASC_TIR(x)          (INT_NUM_IM3_IRL0 + (x * 8))
+#define LTQ_ASC_RIR(x)          (INT_NUM_IM3_IRL0 + (x * 8) + 1)
+#define LTQ_ASC_EIR(x)          (INT_NUM_IM3_IRL0 + (x * 8) + 2)
+#define LTQ_ASC_ASE_TIR         INT_NUM_IM2_IRL0
+#define LTQ_ASC_ASE_RIR         (INT_NUM_IM2_IRL0 + 2)
+#define LTQ_ASC_ASE_EIR         (INT_NUM_IM2_IRL0 + 3)
+#define LTQ_SSC_TIR             (INT_NUM_IM0_IRL0 + 15)
+#define LTQ_SSC_RIR             (INT_NUM_IM0_IRL0 + 14)
+#define LTQ_SSC_EIR             (INT_NUM_IM0_IRL0 + 16)
+#define LTQ_MEI_DYING_GASP_INT  (INT_NUM_IM1_IRL0 + 21)
+#define LTQ_MEI_INT             (INT_NUM_IM1_IRL0 + 23)
+#define LTQ_TIMER6_INT          (INT_NUM_IM1_IRL0 + 23)
+#define LTQ_USB_INT             (INT_NUM_IM1_IRL0 + 22)
+#define LTQ_USB_OC_INT          (INT_NUM_IM4_IRL0 + 23)
+#define MIPS_CPU_TIMER_IRQ              7
+#define LTQ_DMA_CH0_INT         (INT_NUM_IM2_IRL0)
+#define LTQ_DMA_CH1_INT         (INT_NUM_IM2_IRL0 + 1)
+#define LTQ_DMA_CH2_INT         (INT_NUM_IM2_IRL0 + 2)
+#define LTQ_DMA_CH3_INT         (INT_NUM_IM2_IRL0 + 3)
+#define LTQ_DMA_CH4_INT         (INT_NUM_IM2_IRL0 + 4)
+#define LTQ_DMA_CH5_INT         (INT_NUM_IM2_IRL0 + 5)
+#define LTQ_DMA_CH6_INT         (INT_NUM_IM2_IRL0 + 6)
+#define LTQ_DMA_CH7_INT         (INT_NUM_IM2_IRL0 + 7)
+#define LTQ_DMA_CH8_INT         (INT_NUM_IM2_IRL0 + 8)
+#define LTQ_DMA_CH9_INT         (INT_NUM_IM2_IRL0 + 9)
+#define LTQ_DMA_CH10_INT        (INT_NUM_IM2_IRL0 + 10)
+#define LTQ_DMA_CH11_INT        (INT_NUM_IM2_IRL0 + 11)
+#define LTQ_DMA_CH12_INT        (INT_NUM_IM2_IRL0 + 25)
+#define LTQ_DMA_CH13_INT        (INT_NUM_IM2_IRL0 + 26)
+#define LTQ_DMA_CH14_INT        (INT_NUM_IM2_IRL0 + 27)
+#define LTQ_DMA_CH15_INT        (INT_NUM_IM2_IRL0 + 28)
+#define LTQ_DMA_CH16_INT        (INT_NUM_IM2_IRL0 + 29)
+#define LTQ_DMA_CH17_INT        (INT_NUM_IM2_IRL0 + 30)
+#define LTQ_DMA_CH18_INT        (INT_NUM_IM2_IRL0 + 16)
+#define LTQ_DMA_CH19_INT        (INT_NUM_IM2_IRL0 + 21)
+#define LTQ_PPE_MBOX_INT        (INT_NUM_IM2_IRL0 + 24)
+#define INT_NUM_IM4_IRL14       (INT_NUM_IM4_IRL0 + 14)
+#endif
diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
new file mode 100644
index 000000000000..8a3c6be669d2
--- /dev/null
+++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
@@ -0,0 +1,141 @@
+/*
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ *
+ *  Copyright (C) 2010 John Crispin <blogic@openwrt.org>
+ */
+#ifndef _LTQ_XWAY_H__
+#define _LTQ_XWAY_H__
+#ifdef CONFIG_SOC_TYPE_XWAY
+#include <lantiq.h>
+/* Chip IDs */
+#define SOC_ID_DANUBE1          0x129
+#define SOC_ID_DANUBE2          0x12B
+#define SOC_ID_TWINPASS         0x12D
+#define SOC_ID_AMAZON_SE        0x152
+#define SOC_ID_ARX188           0x16C
+#define SOC_ID_ARX168           0x16D
+#define SOC_ID_ARX182           0x16F
+/* SoC Types */
+#define SOC_TYPE_DANUBE         0x01
+#define SOC_TYPE_TWINPASS       0x02
+#define SOC_TYPE_AR9            0x03
+#define SOC_TYPE_VR9            0x04
+#define SOC_TYPE_AMAZON_SE      0x05
+/* ASC0/1 - serial port */
+#define LTQ_ASC0_BASE_ADDR      0x1E100400
+#define LTQ_ASC1_BASE_ADDR      0x1E100C00
+#define LTQ_ASC_SIZE            0x400
+/* RCU - reset control unit */
+#define LTQ_RCU_BASE_ADDR       0x1F203000
+#define LTQ_RCU_SIZE            0x1000
+/* GPTU - general purpose timer unit */
+#define LTQ_GPTU_BASE_ADDR      0x18000300
+#define LTQ_GPTU_SIZE           0x100
+/* EBU - external bus unit */
+#define LTQ_EBU_GPIO_START      0x14000000
+#define LTQ_EBU_GPIO_SIZE       0x1000
+#define LTQ_EBU_BASE_ADDR       0x1E105300
+#define LTQ_EBU_SIZE            0x100
+#define LTQ_EBU_BUSCON0         0x0060
+#define LTQ_EBU_PCC_CON         0x0090
+#define LTQ_EBU_PCC_IEN         0x00A4
+#define LTQ_EBU_PCC_ISTAT       0x00A0
+#define LTQ_EBU_BUSCON1         0x0064
+#define LTQ_EBU_ADDRSEL1        0x0024
+#define EBU_WRDIS               0x80000000
+/* CGU - clock generation unit */
+#define LTQ_CGU_BASE_ADDR       0x1F103000
+#define LTQ_CGU_SIZE            0x1000
+/* ICU - interrupt control unit */
+#define LTQ_ICU_BASE_ADDR       0x1F880200
+#define LTQ_ICU_SIZE            0x100
+/* EIU - external interrupt unit */
+#define LTQ_EIU_BASE_ADDR       0x1F101000
+#define LTQ_EIU_SIZE            0x1000
+/* PMU - power management unit */
+#define LTQ_PMU_BASE_ADDR       0x1F102000
+#define LTQ_PMU_SIZE            0x1000
+#define PMU_DMA                 0x0020
+#define PMU_USB                 0x8041
+#define PMU_LED                 0x0800
+#define PMU_GPT                 0x1000
+#define PMU_PPE                 0x2000
+#define PMU_FPI                 0x4000
+#define PMU_SWITCH              0x10000000
+/* ETOP - ethernet */
+#define LTQ_ETOP_BASE_ADDR      0x1E180000
+#define LTQ_ETOP_SIZE           0x40000
+/* DMA */
+#define LTQ_DMA_BASE_ADDR       0x1E104100
+#define LTQ_DMA_SIZE            0x800
+/* PCI */
+#define PCI_CR_BASE_ADDR        0x1E105400
+#define PCI_CR_SIZE             0x400
+/* WDT */
+#define LTQ_WDT_BASE_ADDR       0x1F8803F0
+#define LTQ_WDT_SIZE            0x10
+/* STP - serial to parallel conversion unit */
+#define LTQ_STP_BASE_ADDR       0x1E100BB0
+#define LTQ_STP_SIZE            0x40
+/* GPIO */
+#define LTQ_GPIO0_BASE_ADDR     0x1E100B10
+#define LTQ_GPIO1_BASE_ADDR     0x1E100B40
+#define LTQ_GPIO2_BASE_ADDR     0x1E100B70
+#define LTQ_GPIO_SIZE           0x30
+/* SSC */
+#define LTQ_SSC_BASE_ADDR       0x1e100800
+#define LTQ_SSC_SIZE            0x100
+/* MEI - dsl core */
+#define LTQ_MEI_BASE_ADDR       0x1E116000
+/* DEU - data encryption unit */
+#define LTQ_DEU_BASE_ADDR       0x1E103100
+/* MPS - multi processor unit (voice) */
+#define LTQ_MPS_BASE_ADDR       (KSEG1 + 0x1F107000)
+#define LTQ_MPS_CHIPID          ((u32 *)(LTQ_MPS_BASE_ADDR + 0x0344))
+/* request a non-gpio and set the PIO config */
+extern int  ltq_gpio_request(unsigned int pin, unsigned int alt0,
+        unsigned int alt1, unsigned int dir, const char *name);
+extern void ltq_pmu_enable(unsigned int module);
+extern void ltq_pmu_disable(unsigned int module);
+static inline int ltq_is_ar9(void)
+{
+        return (ltq_get_soc_type() == SOC_TYPE_AR9);
+}
+static inline int ltq_is_vr9(void)
+{
+        return (ltq_get_soc_type() == SOC_TYPE_VR9);
+}
+#endif /* CONFIG_SOC_TYPE_XWAY */
+#endif /* _LTQ_XWAY_H__ */
diff --git a/arch/mips/include/asm/mach-lantiq/xway/xway_dma.h b/arch/mips/include/asm/mach-lantiq/xway/xway_dma.h
new file mode 100644
index 000000000000..872943a4b90e
--- /dev/null
+++ b/arch/mips/include/asm/mach-lantiq/xway/xway_dma.h
@@ -0,0 +1,60 @@
+/*
+ *   This program is free software; you can redistribute it and/or modify it
+ *   under the terms of the GNU General Public License version 2 as published
+ *   by the Free Software Foundation.
+ *
+ *   This program is distributed in the hope that it will be useful,
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *   GNU General Public License for more details.
+ *
+ *   You should have received a copy of the GNU General Public License
+ *   along with this program; if not, write to the Free Software
+ *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
+ *
+ *   Copyright (C) 2011 John Crispin <blogic@openwrt.org>
+ */
+#ifndef LTQ_DMA_H__
+#define LTQ_DMA_H__
+#define LTQ_DESC_SIZE           0x08    /* each descriptor is 64bit */
+#define LTQ_DESC_NUM            0x40    /* 64 descriptors / channel */
+#define LTQ_DMA_OWN             BIT(31) /* owner bit */
+#define LTQ_DMA_C               BIT(30) /* complete bit */
+#define LTQ_DMA_SOP             BIT(29) /* start of packet */
+#define LTQ_DMA_EOP             BIT(28) /* end of packet */
+#define LTQ_DMA_TX_OFFSET(x)    ((x & 0x1f) << 23) /* data bytes offset */
+#define LTQ_DMA_RX_OFFSET(x)    ((x & 0x7) << 23) /* data bytes offset */
+#define LTQ_DMA_SIZE_MASK       (0xffff) /* the size field is 16 bit */
+struct ltq_dma_desc {
+        u32 ctl;
+        u32 addr;
+};
+struct ltq_dma_channel {
+        int nr;                         /* the channel number */
+        int irq;                        /* the mapped irq */
+        int desc;                       /* the current descriptor */
+        struct ltq_dma_desc *desc_base; /* the descriptor base */
+        int phys;                       /* physical addr */
+};
+enum {
+        DMA_PORT_ETOP = 0,
+        DMA_PORT_DEU,
+};
+extern void ltq_dma_enable_irq(struct ltq_dma_channel *ch);
+extern void ltq_dma_disable_irq(struct ltq_dma_channel *ch);
+extern void ltq_dma_ack_irq(struct ltq_dma_channel *ch);
+extern void ltq_dma_open(struct ltq_dma_channel *ch);
+extern void ltq_dma_close(struct ltq_dma_channel *ch);
+extern void ltq_dma_alloc_tx(struct ltq_dma_channel *ch);
+extern void ltq_dma_alloc_rx(struct ltq_dma_channel *ch);
+extern void ltq_dma_free(struct ltq_dma_channel *ch);
+extern void ltq_dma_init_port(int p);
+#endif
diff --git a/arch/mips/include/asm/mach-loongson/cs5536/cs5536.h b/arch/mips/include/asm/mach-loongson/cs5536/cs5536.h
index 021f77ca59ec..2a8e2bb5d539 100644
--- a/arch/mips/include/asm/mach-loongson/cs5536/cs5536.h
+++ b/arch/mips/include/asm/mach-loongson/cs5536/cs5536.h
@@ -1,5 +1,5 @@
 /*
- * The header file of cs5536 sourth bridge.
+ * The header file of cs5536 south bridge.
 *
 * Copyright (C) 2007 Lemote, Inc.
 * Author : jlliu <liujl@lemote.com>
diff --git a/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h b/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h
new file mode 100644
index 000000000000..3b728275b9b0
--- /dev/null
+++ b/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h
@@ -0,0 +1,47 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2011 Netlogic Microsystems
+ * Copyright (C) 2003 Ralf Baechle
+ */
+#ifndef __ASM_MACH_NETLOGIC_CPU_FEATURE_OVERRIDES_H
+#define __ASM_MACH_NETLOGIC_CPU_FEATURE_OVERRIDES_H
+#define cpu_has_4kex            1
+#define cpu_has_4k_cache        1
+#define cpu_has_watch           1
+#define cpu_has_mips16          0
+#define cpu_has_counter         1
+#define cpu_has_divec           1
+#define cpu_has_vce             0
+#define cpu_has_cache_cdex_p    0
+#define cpu_has_cache_cdex_s    0
+#define cpu_has_prefetch        1
+#define cpu_has_mcheck          1
+#define cpu_has_ejtag           1
+#define cpu_has_llsc            1
+#define cpu_has_vtag_icache     0
+#define cpu_has_dc_aliases      0
+#define cpu_has_ic_fills_f_dc   0
+#define cpu_has_dsp             0
+#define cpu_has_mipsmt          0
+#define cpu_has_userlocal       0
+#define cpu_icache_snoops_remote_store  0
+#define cpu_has_nofpuex         0
+#define cpu_has_64bits          1
+#define cpu_has_mips32r1        1
+#define cpu_has_mips32r2        0
+#define cpu_has_mips64r1        1
+#define cpu_has_mips64r2        0
+#define cpu_has_inclusive_pcaches       0
+#define cpu_dcache_line_size()  32
+#define cpu_icache_line_size()  32
+#endif /* __ASM_MACH_NETLOGIC_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mach-netlogic/irq.h b/arch/mips/include/asm/mach-netlogic/irq.h
new file mode 100644
index 000000000000..b5902458e7c1
--- /dev/null
+++ b/arch/mips/include/asm/mach-netlogic/irq.h
@@ -0,0 +1,14 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2011 Netlogic Microsystems.
+ */
+#ifndef __ASM_NETLOGIC_IRQ_H
+#define __ASM_NETLOGIC_IRQ_H
+#define NR_IRQS                 64
+#define MIPS_CPU_IRQ_BASE       0
+#endif /* __ASM_NETLOGIC_IRQ_H */
diff --git a/arch/mips/include/asm/mach-netlogic/war.h b/arch/mips/include/asm/mach-netlogic/war.h
new file mode 100644
index 000000000000..22da89327352
--- /dev/null
+++ b/arch/mips/include/asm/mach-netlogic/war.h
@@ -0,0 +1,26 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2011 Netlogic Microsystems.
+ * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
+ */
+#ifndef __ASM_MIPS_MACH_NLM_WAR_H
+#define __ASM_MIPS_MACH_NLM_WAR_H
+#define R4600_V1_INDEX_ICACHEOP_WAR     0
+#define R4600_V1_HIT_CACHEOP_WAR        0
+#define R4600_V2_HIT_CACHEOP_WAR        0
+#define R5432_CP0_INTERRUPT_WAR         0
+#define BCM1250_M3_WAR                  0
+#define SIBYTE_1956_WAR                 0
+#define MIPS4K_ICACHE_REFILL_WAR        0
+#define MIPS_CACHE_SYNC_WAR             0
+#define TX49XX_ICACHE_INDEX_INV_WAR     0
+#define RM9000_CDEX_SMP_WAR             0
+#define ICACHE_REFILLS_WORKAROUND_WAR   0
+#define R10000_LLSC_WAR                 0
+#define MIPS34K_MISSED_ITLB_WAR         0
+#endif /* __ASM_MIPS_MACH_NLM_WAR_H */
diff --git a/arch/mips/include/asm/mach-pb1x00/pb1000.h b/arch/mips/include/asm/mach-pb1x00/pb1000.h
index 6d1ff9060e44..65059255dc1e 100644
--- a/arch/mips/include/asm/mach-pb1x00/pb1000.h
+++ b/arch/mips/include/asm/mach-pb1x00/pb1000.h
@@ -1,5 +1,5 @@
 /*
- * Alchemy Semi Pb1000 Referrence Board
+ * Alchemy Semi Pb1000 Reference Board
 *
 * Copyright 2001, 2008 MontaVista Software Inc.
 * Author: MontaVista Software, Inc. <source@mvista.com>
diff --git a/arch/mips/include/asm/mach-pb1x00/pb1200.h b/arch/mips/include/asm/mach-pb1x00/pb1200.h
index 962eb55dc880..fce4332ebb7f 100644
--- a/arch/mips/include/asm/mach-pb1x00/pb1200.h
+++ b/arch/mips/include/asm/mach-pb1x00/pb1200.h
@@ -1,5 +1,5 @@
 /*
- * AMD Alchemy Pb1200 Referrence Board
+ * AMD Alchemy Pb1200 Reference Board
 * Board Registers defines.
 *
 * ########################################################################
diff --git a/arch/mips/include/asm/mach-pb1x00/pb1550.h b/arch/mips/include/asm/mach-pb1x00/pb1550.h
index fc4d766641ce..f835c88e9593 100644
--- a/arch/mips/include/asm/mach-pb1x00/pb1550.h
+++ b/arch/mips/include/asm/mach-pb1x00/pb1550.h
@@ -1,5 +1,5 @@
 /*
- * AMD Alchemy Semi PB1550 Referrence Board
+ * AMD Alchemy Semi PB1550 Reference Board
 * Board Registers defines.
 *
 * Copyright 2004 Embedded Edge LLC.
diff --git a/arch/mips/include/asm/mach-powertv/dma-coherence.h b/arch/mips/include/asm/mach-powertv/dma-coherence.h
index f76029c2406e..a8e72cf12142 100644
--- a/arch/mips/include/asm/mach-powertv/dma-coherence.h
+++ b/arch/mips/include/asm/mach-powertv/dma-coherence.h
@@ -48,7 +48,7 @@ static inline unsigned long virt_to_phys_from_pte(void *addr)
                                /* check for a valid page */
                                if (pte_present(pte)) {
                                        /* get the physical address the page is
-                                         * refering to */
+                                         * referring to */
                                        phys_addr = (unsigned long)
                                                page_to_phys(pte_page(pte));
                                        /* add the offset within the page */
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 4d9870975382..6a6f8a8f542d 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -922,7 +922,7 @@ do {									\
 #define write_c0_config7(val)   __write_32bit_c0_register($16, 7, val)
 /*
- * The WatchLo register.  There may be upto 8 of them.
+ * The WatchLo register.  There may be up to 8 of them.
 */
 #define read_c0_watchlo0()      __read_ulong_c0_register($18, 0)
 #define read_c0_watchlo1()      __read_ulong_c0_register($18, 1)
@@ -942,7 +942,7 @@ do {									\
 #define write_c0_watchlo7(val)  __write_ulong_c0_register($18, 7, val)
 /*
- * The WatchHi register.  There may be upto 8 of them.
+ * The WatchHi register.  There may be up to 8 of them.
 */
 #define read_c0_watchhi0()      __read_32bit_c0_register($19, 0)
 #define read_c0_watchhi1()      __read_32bit_c0_register($19, 1)
diff --git a/arch/mips/include/asm/module.h b/arch/mips/include/asm/module.h
index d94085a3eafb..bc01a02cacd8 100644
--- a/arch/mips/include/asm/module.h
+++ b/arch/mips/include/asm/module.h
@@ -118,6 +118,8 @@ search_module_dbetables(unsigned long addr)
 #define MODULE_PROC_FAMILY "LOONGSON2 "
 #elif defined CONFIG_CPU_CAVIUM_OCTEON
 #define MODULE_PROC_FAMILY "OCTEON "
+#elif defined CONFIG_CPU_XLR
+#define MODULE_PROC_FAMILY "XLR "
 #else
 #error MODULE_PROC_FAMILY undefined for your processor configuration
 #endif
diff --git a/arch/mips/include/asm/netlogic/interrupt.h b/arch/mips/include/asm/netlogic/interrupt.h
new file mode 100644
index 000000000000..a85aadb6cfd7
--- /dev/null
+++ b/arch/mips/include/asm/netlogic/interrupt.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
+ * reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the NetLogic
+ * license below:
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _ASM_NLM_INTERRUPT_H
+#define _ASM_NLM_INTERRUPT_H
+/* Defines for the IRQ numbers */
+#define IRQ_IPI_SMP_FUNCTION    3
+#define IRQ_IPI_SMP_RESCHEDULE  4
+#define IRQ_MSGRING             6
+#define IRQ_TIMER               7
+#endif
diff --git a/arch/mips/include/asm/netlogic/mips-extns.h b/arch/mips/include/asm/netlogic/mips-extns.h
new file mode 100644
index 000000000000..8c53d0ba4bf2
--- /dev/null
+++ b/arch/mips/include/asm/netlogic/mips-extns.h
@@ -0,0 +1,76 @@
+/*
+ * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
+ * reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the NetLogic
+ * license below:
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _ASM_NLM_MIPS_EXTS_H
+#define _ASM_NLM_MIPS_EXTS_H
+/*
+ * XLR and XLP interrupt request and interrupt mask registers
+ */
+#define read_c0_eirr()          __read_64bit_c0_register($9, 6)
+#define read_c0_eimr()          __read_64bit_c0_register($9, 7)
+#define write_c0_eirr(val)      __write_64bit_c0_register($9, 6, val)
+/*
+ * Writing EIMR in 32 bit is a special case, the lower 8 bit of the
+ * EIMR is shadowed in the status register, so we cannot save and
+ * restore status register for split read.
+ */
+#define write_c0_eimr(val)                                              \
+do {                                                                    \
+        if (sizeof(unsigned long) == 4) {                               \
+                unsigned long __flags;                                  \
+                                                                        \
+                local_irq_save(__flags);                                \
+                __asm__ __volatile__(                                   \
+                        ".set\tmips64\n\t"                              \
+                        "dsll\t%L0, %L0, 32\n\t"                        \
+                        "dsrl\t%L0, %L0, 32\n\t"                        \
+                        "dsll\t%M0, %M0, 32\n\t"                        \
+                        "or\t%L0, %L0, %M0\n\t"                         \
+                        "dmtc0\t%L0, $9, 7\n\t"                         \
+                        ".set\tmips0"                                   \
+                        : : "r" (val));                                 \
+                __flags = (__flags & 0xffff00ff) | (((val) & 0xff) << 8);\
+                local_irq_restore(__flags);                             \
+        } else                                                          \
+                __write_64bit_c0_register($9, 7, (val));                \
+} while (0)
+static inline int hard_smp_processor_id(void)
+{
+        return __read_32bit_c0_register($15, 1) & 0x3ff;
+}
+#endif /*_ASM_NLM_MIPS_EXTS_H */
diff --git a/arch/mips/include/asm/netlogic/psb-bootinfo.h b/arch/mips/include/asm/netlogic/psb-bootinfo.h
new file mode 100644
index 000000000000..6878307f0ee6
--- /dev/null
+++ b/arch/mips/include/asm/netlogic/psb-bootinfo.h
@@ -0,0 +1,109 @@
+/*
+ * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
+ * reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the NetLogic
+ * license below:
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _ASM_NETLOGIC_BOOTINFO_H
+#define _ASM_NETLOGIC_BOOTINFO_H
+struct psb_info {
+        uint64_t boot_level;
+        uint64_t io_base;
+        uint64_t output_device;
+        uint64_t uart_print;
+        uint64_t led_output;
+        uint64_t init;
+        uint64_t exit;
+        uint64_t warm_reset;
+        uint64_t wakeup;
+        uint64_t online_cpu_map;
+        uint64_t master_reentry_sp;
+        uint64_t master_reentry_gp;
+        uint64_t master_reentry_fn;
+        uint64_t slave_reentry_fn;
+        uint64_t magic_dword;
+        uint64_t uart_putchar;
+        uint64_t size;
+        uint64_t uart_getchar;
+        uint64_t nmi_handler;
+        uint64_t psb_version;
+        uint64_t mac_addr;
+        uint64_t cpu_frequency;
+        uint64_t board_version;
+        uint64_t malloc;
+        uint64_t free;
+        uint64_t global_shmem_addr;
+        uint64_t global_shmem_size;
+        uint64_t psb_os_cpu_map;
+        uint64_t userapp_cpu_map;
+        uint64_t wakeup_os;
+        uint64_t psb_mem_map;
+        uint64_t board_major_version;
+        uint64_t board_minor_version;
+        uint64_t board_manf_revision;
+        uint64_t board_serial_number;
+        uint64_t psb_physaddr_map;
+        uint64_t xlr_loaderip_config;
+        uint64_t bldr_envp;
+        uint64_t avail_mem_map;
+};
+enum {
+        NETLOGIC_IO_SPACE = 0x10,
+        PCIX_IO_SPACE,
+        PCIX_CFG_SPACE,
+        PCIX_MEMORY_SPACE,
+        HT_IO_SPACE,
+        HT_CFG_SPACE,
+        HT_MEMORY_SPACE,
+        SRAM_SPACE,
+        FLASH_CONTROLLER_SPACE
+};
+#define NLM_MAX_ARGS    64
+#define NLM_MAX_ENVS    32
+/* This is what netlboot passes and linux boot_mem_map is subtly different */
+#define NLM_BOOT_MEM_MAP_MAX    32
+struct nlm_boot_mem_map {
+        int nr_map;
+        struct nlm_boot_mem_map_entry {
+                uint64_t addr;          /* start of memory segment */
+                uint64_t size;          /* size of memory segment */
+                uint32_t type;          /* type of memory segment */
+        } map[NLM_BOOT_MEM_MAP_MAX];
+};
+/* Pointer to saved boot loader info */
+extern struct psb_info nlm_prom_info;
+#endif
diff --git a/arch/mips/include/asm/netlogic/xlr/gpio.h b/arch/mips/include/asm/netlogic/xlr/gpio.h
new file mode 100644
index 000000000000..51f6ad4aeb14
--- /dev/null
+++ b/arch/mips/include/asm/netlogic/xlr/gpio.h
@@ -0,0 +1,73 @@
+/*
+ * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
+ * reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the NetLogic
+ * license below:
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _ASM_NLM_GPIO_H
+#define _ASM_NLM_GPIO_H
+#define NETLOGIC_GPIO_INT_EN_REG                0
+#define NETLOGIC_GPIO_INPUT_INVERSION_REG       1
+#define NETLOGIC_GPIO_IO_DIR_REG                2
+#define NETLOGIC_GPIO_IO_DATA_WR_REG            3
+#define NETLOGIC_GPIO_IO_DATA_RD_REG            4
+#define NETLOGIC_GPIO_SWRESET_REG               8
+#define NETLOGIC_GPIO_DRAM1_CNTRL_REG           9
+#define NETLOGIC_GPIO_DRAM1_RATIO_REG           10
+#define NETLOGIC_GPIO_DRAM1_RESET_REG           11
+#define NETLOGIC_GPIO_DRAM1_STATUS_REG          12
+#define NETLOGIC_GPIO_DRAM2_CNTRL_REG           13
+#define NETLOGIC_GPIO_DRAM2_RATIO_REG           14
+#define NETLOGIC_GPIO_DRAM2_RESET_REG           15
+#define NETLOGIC_GPIO_DRAM2_STATUS_REG          16
+#define NETLOGIC_GPIO_PWRON_RESET_CFG_REG       21
+#define NETLOGIC_GPIO_BIST_ALL_GO_STATUS_REG    24
+#define NETLOGIC_GPIO_BIST_CPU_GO_STATUS_REG    25
+#define NETLOGIC_GPIO_BIST_DEV_GO_STATUS_REG    26
+#define NETLOGIC_GPIO_FUSE_BANK_REG             35
+#define NETLOGIC_GPIO_CPU_RESET_REG             40
+#define NETLOGIC_GPIO_RNG_REG                   43
+#define NETLOGIC_PWRON_RESET_PCMCIA_BOOT        17
+#define NETLOGIC_GPIO_LED_BITMAP        0x1700000
+#define NETLOGIC_GPIO_LED_0_SHIFT               20
+#define NETLOGIC_GPIO_LED_1_SHIFT               24
+#define NETLOGIC_GPIO_LED_OUTPUT_CODE_RESET     0x01
+#define NETLOGIC_GPIO_LED_OUTPUT_CODE_HARD_RESET 0x02
+#define NETLOGIC_GPIO_LED_OUTPUT_CODE_SOFT_RESET 0x03
+#define NETLOGIC_GPIO_LED_OUTPUT_CODE_MAIN      0x04
+#endif
diff --git a/arch/mips/include/asm/netlogic/xlr/iomap.h b/arch/mips/include/asm/netlogic/xlr/iomap.h
new file mode 100644
index 000000000000..2e3a4dd53045
--- /dev/null
+++ b/arch/mips/include/asm/netlogic/xlr/iomap.h
@@ -0,0 +1,131 @@
+/*
+ * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
+ * reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the NetLogic
+ * license below:
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _ASM_NLM_IOMAP_H
+#define _ASM_NLM_IOMAP_H
+#define DEFAULT_NETLOGIC_IO_BASE           CKSEG1ADDR(0x1ef00000)
+#define NETLOGIC_IO_DDR2_CHN0_OFFSET       0x01000
+#define NETLOGIC_IO_DDR2_CHN1_OFFSET       0x02000
+#define NETLOGIC_IO_DDR2_CHN2_OFFSET       0x03000
+#define NETLOGIC_IO_DDR2_CHN3_OFFSET       0x04000
+#define NETLOGIC_IO_PIC_OFFSET             0x08000
+#define NETLOGIC_IO_UART_0_OFFSET          0x14000
+#define NETLOGIC_IO_UART_1_OFFSET          0x15100
+#define NETLOGIC_IO_SIZE                   0x1000
+#define NETLOGIC_IO_BRIDGE_OFFSET          0x00000
+#define NETLOGIC_IO_RLD2_CHN0_OFFSET       0x05000
+#define NETLOGIC_IO_RLD2_CHN1_OFFSET       0x06000
+#define NETLOGIC_IO_SRAM_OFFSET            0x07000
+#define NETLOGIC_IO_PCIX_OFFSET            0x09000
+#define NETLOGIC_IO_HT_OFFSET              0x0A000
+#define NETLOGIC_IO_SECURITY_OFFSET        0x0B000
+#define NETLOGIC_IO_GMAC_0_OFFSET          0x0C000
+#define NETLOGIC_IO_GMAC_1_OFFSET          0x0D000
+#define NETLOGIC_IO_GMAC_2_OFFSET          0x0E000
+#define NETLOGIC_IO_GMAC_3_OFFSET          0x0F000
+/* XLS devices */
+#define NETLOGIC_IO_GMAC_4_OFFSET          0x20000
+#define NETLOGIC_IO_GMAC_5_OFFSET          0x21000
+#define NETLOGIC_IO_GMAC_6_OFFSET          0x22000
+#define NETLOGIC_IO_GMAC_7_OFFSET          0x23000
+#define NETLOGIC_IO_PCIE_0_OFFSET          0x1E000
+#define NETLOGIC_IO_PCIE_1_OFFSET          0x1F000
+#define NETLOGIC_IO_SRIO_0_OFFSET          0x1E000
+#define NETLOGIC_IO_SRIO_1_OFFSET          0x1F000
+#define NETLOGIC_IO_USB_0_OFFSET           0x24000
+#define NETLOGIC_IO_USB_1_OFFSET           0x25000
+#define NETLOGIC_IO_COMP_OFFSET            0x1D000
+/* end XLS devices */
+/* XLR devices */
+#define NETLOGIC_IO_SPI4_0_OFFSET          0x10000
+#define NETLOGIC_IO_XGMAC_0_OFFSET         0x11000
+#define NETLOGIC_IO_SPI4_1_OFFSET          0x12000
+#define NETLOGIC_IO_XGMAC_1_OFFSET         0x13000
+/* end XLR devices */
+#define NETLOGIC_IO_I2C_0_OFFSET           0x16000
+#define NETLOGIC_IO_I2C_1_OFFSET           0x17000
+#define NETLOGIC_IO_GPIO_OFFSET            0x18000
+#define NETLOGIC_IO_FLASH_OFFSET           0x19000
+#define NETLOGIC_IO_TB_OFFSET              0x1C000
+#define NETLOGIC_CPLD_OFFSET               KSEG1ADDR(0x1d840000)
+/*
+ * Base Address (Virtual) of the PCI Config address space
+ * For now, choose 256M phys in kseg1 = 0xA0000000 + (1<<28)
+ * Config space spans 256 (num of buses) * 256 (num functions) * 256 bytes
+ * ie 1<<24 = 16M
+ */
+#define DEFAULT_PCI_CONFIG_BASE         0x18000000
+#define DEFAULT_HT_TYPE0_CFG_BASE       0x16000000
+#define DEFAULT_HT_TYPE1_CFG_BASE       0x17000000
+#ifndef __ASSEMBLY__
+#include <linux/types.h>
+#include <asm/byteorder.h>
+typedef volatile __u32 nlm_reg_t;
+extern unsigned long netlogic_io_base;
+/* FIXME read once in write_reg */
+#ifdef CONFIG_CPU_LITTLE_ENDIAN
+#define netlogic_read_reg(base, offset)         ((base)[(offset)])
+#define netlogic_write_reg(base, offset, value) ((base)[(offset)] = (value))
+#else
+#define netlogic_read_reg(base, offset)         (be32_to_cpu((base)[(offset)]))
+#define netlogic_write_reg(base, offset, value) \
+                                ((base)[(offset)] = cpu_to_be32((value)))
+#endif
+#define netlogic_read_reg_le32(base, offset) (le32_to_cpu((base)[(offset)]))
+#define netlogic_write_reg_le32(base, offset, value) \
+                                ((base)[(offset)] = cpu_to_le32((value)))
+#define netlogic_io_mmio(offset) ((nlm_reg_t *)(netlogic_io_base+(offset)))
+#endif /* __ASSEMBLY__ */
+#endif
diff --git a/arch/mips/include/asm/netlogic/xlr/pic.h b/arch/mips/include/asm/netlogic/xlr/pic.h
new file mode 100644
index 000000000000..5cceb746f080
--- /dev/null
+++ b/arch/mips/include/asm/netlogic/xlr/pic.h
@@ -0,0 +1,231 @@
+/*
+ * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
+ * reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the NetLogic
+ * license below:
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _ASM_NLM_XLR_PIC_H
+#define _ASM_NLM_XLR_PIC_H
+#define PIC_CLKS_PER_SEC                66666666ULL
+/* PIC hardware interrupt numbers */
+#define PIC_IRT_WD_INDEX                0
+#define PIC_IRT_TIMER_0_INDEX           1
+#define PIC_IRT_TIMER_1_INDEX           2
+#define PIC_IRT_TIMER_2_INDEX           3
+#define PIC_IRT_TIMER_3_INDEX           4
+#define PIC_IRT_TIMER_4_INDEX           5
+#define PIC_IRT_TIMER_5_INDEX           6
+#define PIC_IRT_TIMER_6_INDEX           7
+#define PIC_IRT_TIMER_7_INDEX           8
+#define PIC_IRT_CLOCK_INDEX             PIC_IRT_TIMER_7_INDEX
+#define PIC_IRT_UART_0_INDEX            9
+#define PIC_IRT_UART_1_INDEX            10
+#define PIC_IRT_I2C_0_INDEX             11
+#define PIC_IRT_I2C_1_INDEX             12
+#define PIC_IRT_PCMCIA_INDEX            13
+#define PIC_IRT_GPIO_INDEX              14
+#define PIC_IRT_HYPER_INDEX             15
+#define PIC_IRT_PCIX_INDEX              16
+/* XLS */
+#define PIC_IRT_CDE_INDEX               15
+#define PIC_IRT_BRIDGE_TB_XLS_INDEX     16
+/* XLS */
+#define PIC_IRT_GMAC0_INDEX             17
+#define PIC_IRT_GMAC1_INDEX             18
+#define PIC_IRT_GMAC2_INDEX             19
+#define PIC_IRT_GMAC3_INDEX             20
+#define PIC_IRT_XGS0_INDEX              21
+#define PIC_IRT_XGS1_INDEX              22
+#define PIC_IRT_HYPER_FATAL_INDEX       23
+#define PIC_IRT_PCIX_FATAL_INDEX        24
+#define PIC_IRT_BRIDGE_AERR_INDEX       25
+#define PIC_IRT_BRIDGE_BERR_INDEX       26
+#define PIC_IRT_BRIDGE_TB_XLR_INDEX     27
+#define PIC_IRT_BRIDGE_AERR_NMI_INDEX   28
+/* XLS */
+#define PIC_IRT_GMAC4_INDEX             21
+#define PIC_IRT_GMAC5_INDEX             22
+#define PIC_IRT_GMAC6_INDEX             23
+#define PIC_IRT_GMAC7_INDEX             24
+#define PIC_IRT_BRIDGE_ERR_INDEX        25
+#define PIC_IRT_PCIE_LINK0_INDEX        26
+#define PIC_IRT_PCIE_LINK1_INDEX        27
+#define PIC_IRT_PCIE_LINK2_INDEX        23
+#define PIC_IRT_PCIE_LINK3_INDEX        24
+#define PIC_IRT_PCIE_XLSB0_LINK2_INDEX  28
+#define PIC_IRT_PCIE_XLSB0_LINK3_INDEX  29
+#define PIC_IRT_SRIO_LINK0_INDEX        26
+#define PIC_IRT_SRIO_LINK1_INDEX        27
+#define PIC_IRT_SRIO_LINK2_INDEX        28
+#define PIC_IRT_SRIO_LINK3_INDEX        29
+#define PIC_IRT_PCIE_INT_INDEX          28
+#define PIC_IRT_PCIE_FATAL_INDEX        29
+#define PIC_IRT_GPIO_B_INDEX            30
+#define PIC_IRT_USB_INDEX               31
+/* XLS */
+#define PIC_NUM_IRTS                    32
+#define PIC_CLOCK_TIMER                 7
+/* PIC Registers */
+#define PIC_CTRL                        0x00
+#define PIC_IPI                         0x04
+#define PIC_INT_ACK                     0x06
+#define WD_MAX_VAL_0                    0x08
+#define WD_MAX_VAL_1                    0x09
+#define WD_MASK_0                       0x0a
+#define WD_MASK_1                       0x0b
+#define WD_HEARBEAT_0                   0x0c
+#define WD_HEARBEAT_1                   0x0d
+#define PIC_IRT_0_BASE                  0x40
+#define PIC_IRT_1_BASE                  0x80
+#define PIC_TIMER_MAXVAL_0_BASE         0x100
+#define PIC_TIMER_MAXVAL_1_BASE         0x110
+#define PIC_TIMER_COUNT_0_BASE          0x120
+#define PIC_TIMER_COUNT_1_BASE          0x130
+#define PIC_IRT_0(picintr)      (PIC_IRT_0_BASE + (picintr))
+#define PIC_IRT_1(picintr)      (PIC_IRT_1_BASE + (picintr))
+#define PIC_TIMER_MAXVAL_0(i)   (PIC_TIMER_MAXVAL_0_BASE + (i))
+#define PIC_TIMER_MAXVAL_1(i)   (PIC_TIMER_MAXVAL_1_BASE + (i))
+#define PIC_TIMER_COUNT_0(i)    (PIC_TIMER_COUNT_0_BASE + (i))
+#define PIC_TIMER_COUNT_1(i)    (PIC_TIMER_COUNT_0_BASE + (i))
+/*
+ * Mapping between hardware interrupt numbers and IRQs on CPU
+ * we use a simple scheme to map PIC interrupts 0-31 to IRQs
+ * 8-39. This leaves the IRQ 0-7 for cpu interrupts like
+ * count/compare and FMN
+ */
+#define PIC_IRQ_BASE            8
+#define PIC_INTR_TO_IRQ(i)      (PIC_IRQ_BASE + (i))
+#define PIC_IRQ_TO_INTR(i)      ((i) - PIC_IRQ_BASE)
+#define PIC_IRT_FIRST_IRQ       PIC_IRQ_BASE
+#define PIC_WD_IRQ              PIC_INTR_TO_IRQ(PIC_IRT_WD_INDEX)
+#define PIC_TIMER_0_IRQ         PIC_INTR_TO_IRQ(PIC_IRT_TIMER_0_INDEX)
+#define PIC_TIMER_1_IRQ         PIC_INTR_TO_IRQ(PIC_IRT_TIMER_1_INDEX)
+#define PIC_TIMER_2_IRQ         PIC_INTR_TO_IRQ(PIC_IRT_TIMER_2_INDEX)
+#define PIC_TIMER_3_IRQ         PIC_INTR_TO_IRQ(PIC_IRT_TIMER_3_INDEX)
+#define PIC_TIMER_4_IRQ         PIC_INTR_TO_IRQ(PIC_IRT_TIMER_4_INDEX)
+#define PIC_TIMER_5_IRQ         PIC_INTR_TO_IRQ(PIC_IRT_TIMER_5_INDEX)
+#define PIC_TIMER_6_IRQ         PIC_INTR_TO_IRQ(PIC_IRT_TIMER_6_INDEX)
+#define PIC_TIMER_7_IRQ         PIC_INTR_TO_IRQ(PIC_IRT_TIMER_7_INDEX)
+#define PIC_CLOCK_IRQ           (PIC_TIMER_7_IRQ)
+#define PIC_UART_0_IRQ          PIC_INTR_TO_IRQ(PIC_IRT_UART_0_INDEX)
+#define PIC_UART_1_IRQ          PIC_INTR_TO_IRQ(PIC_IRT_UART_1_INDEX)
+#define PIC_I2C_0_IRQ           PIC_INTR_TO_IRQ(PIC_IRT_I2C_0_INDEX)
+#define PIC_I2C_1_IRQ           PIC_INTR_TO_IRQ(PIC_IRT_I2C_1_INDEX)
+#define PIC_PCMCIA_IRQ          PIC_INTR_TO_IRQ(PIC_IRT_PCMCIA_INDEX)
+#define PIC_GPIO_IRQ            PIC_INTR_TO_IRQ(PIC_IRT_GPIO_INDEX)
+#define PIC_HYPER_IRQ           PIC_INTR_TO_IRQ(PIC_IRT_HYPER_INDEX)
+#define PIC_PCIX_IRQ            PIC_INTR_TO_IRQ(PIC_IRT_PCIX_INDEX)
+/* XLS */
+#define PIC_CDE_IRQ             PIC_INTR_TO_IRQ(PIC_IRT_CDE_INDEX)
+#define PIC_BRIDGE_TB_XLS_IRQ   PIC_INTR_TO_IRQ(PIC_IRT_BRIDGE_TB_XLS_INDEX)
+/* end XLS */
+#define PIC_GMAC_0_IRQ          PIC_INTR_TO_IRQ(PIC_IRT_GMAC0_INDEX)
+#define PIC_GMAC_1_IRQ          PIC_INTR_TO_IRQ(PIC_IRT_GMAC1_INDEX)
+#define PIC_GMAC_2_IRQ          PIC_INTR_TO_IRQ(PIC_IRT_GMAC2_INDEX)
+#define PIC_GMAC_3_IRQ          PIC_INTR_TO_IRQ(PIC_IRT_GMAC3_INDEX)
+#define PIC_XGS_0_IRQ           PIC_INTR_TO_IRQ(PIC_IRT_XGS0_INDEX)
+#define PIC_XGS_1_IRQ           PIC_INTR_TO_IRQ(PIC_IRT_XGS1_INDEX)
+#define PIC_HYPER_FATAL_IRQ     PIC_INTR_TO_IRQ(PIC_IRT_HYPER_FATAL_INDEX)
+#define PIC_PCIX_FATAL_IRQ      PIC_INTR_TO_IRQ(PIC_IRT_PCIX_FATAL_INDEX)
+#define PIC_BRIDGE_AERR_IRQ     PIC_INTR_TO_IRQ(PIC_IRT_BRIDGE_AERR_INDEX)
+#define PIC_BRIDGE_BERR_IRQ     PIC_INTR_TO_IRQ(PIC_IRT_BRIDGE_BERR_INDEX)
+#define PIC_BRIDGE_TB_XLR_IRQ   PIC_INTR_TO_IRQ(PIC_IRT_BRIDGE_TB_XLR_INDEX)
+#define PIC_BRIDGE_AERR_NMI_IRQ PIC_INTR_TO_IRQ(PIC_IRT_BRIDGE_AERR_NMI_INDEX)
+/* XLS defines */
+#define PIC_GMAC_4_IRQ          PIC_INTR_TO_IRQ(PIC_IRT_GMAC4_INDEX)
+#define PIC_GMAC_5_IRQ          PIC_INTR_TO_IRQ(PIC_IRT_GMAC5_INDEX)
+#define PIC_GMAC_6_IRQ          PIC_INTR_TO_IRQ(PIC_IRT_GMAC6_INDEX)
+#define PIC_GMAC_7_IRQ          PIC_INTR_TO_IRQ(PIC_IRT_GMAC7_INDEX)
+#define PIC_BRIDGE_ERR_IRQ      PIC_INTR_TO_IRQ(PIC_IRT_BRIDGE_ERR_INDEX)
+#define PIC_PCIE_LINK0_IRQ      PIC_INTR_TO_IRQ(PIC_IRT_PCIE_LINK0_INDEX)
+#define PIC_PCIE_LINK1_IRQ      PIC_INTR_TO_IRQ(PIC_IRT_PCIE_LINK1_INDEX)
+#define PIC_PCIE_LINK2_IRQ      PIC_INTR_TO_IRQ(PIC_IRT_PCIE_LINK2_INDEX)
+#define PIC_PCIE_LINK3_IRQ      PIC_INTR_TO_IRQ(PIC_IRT_PCIE_LINK3_INDEX)
+#define PIC_PCIE_XLSB0_LINK2_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIE_XLSB0_LINK2_INDEX)
+#define PIC_PCIE_XLSB0_LINK3_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIE_XLSB0_LINK3_INDEX)
+#define PIC_SRIO_LINK0_IRQ      PIC_INTR_TO_IRQ(PIC_IRT_SRIO_LINK0_INDEX)
+#define PIC_SRIO_LINK1_IRQ      PIC_INTR_TO_IRQ(PIC_IRT_SRIO_LINK1_INDEX)
+#define PIC_SRIO_LINK2_IRQ      PIC_INTR_TO_IRQ(PIC_IRT_SRIO_LINK2_INDEX)
+#define PIC_SRIO_LINK3_IRQ      PIC_INTR_TO_IRQ(PIC_IRT_SRIO_LINK3_INDEX)
+#define PIC_PCIE_INT_IRQ        PIC_INTR_TO_IRQ(PIC_IRT_PCIE_INT__INDEX)
+#define PIC_PCIE_FATAL_IRQ      PIC_INTR_TO_IRQ(PIC_IRT_PCIE_FATAL_INDEX)
+#define PIC_GPIO_B_IRQ          PIC_INTR_TO_IRQ(PIC_IRT_GPIO_B_INDEX)
+#define PIC_USB_IRQ             PIC_INTR_TO_IRQ(PIC_IRT_USB_INDEX)
+#define PIC_IRT_LAST_IRQ        PIC_USB_IRQ
+/* end XLS */
+#ifndef __ASSEMBLY__
+static inline void pic_send_ipi(u32 ipi)
+{
+        nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET);
+        netlogic_write_reg(mmio, PIC_IPI, ipi);
+}
+static inline u32 pic_read_control(void)
+{
+        nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET);
+        return netlogic_read_reg(mmio, PIC_CTRL);
+}
+static inline void pic_write_control(u32 control)
+{
+        nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET);
+        netlogic_write_reg(mmio, PIC_CTRL, control);
+}
+static inline void pic_update_control(u32 control)
+{
+        nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET);
+        netlogic_write_reg(mmio, PIC_CTRL,
+                (control | netlogic_read_reg(mmio, PIC_CTRL)));
+}
+#define PIC_IRQ_IS_EDGE_TRIGGERED(irq)  (((irq) >= PIC_TIMER_0_IRQ) && \
+                                        ((irq) <= PIC_TIMER_7_IRQ))
+#define PIC_IRQ_IS_IRT(irq)             (((irq) >= PIC_IRT_FIRST_IRQ) && \
+                                        ((irq) <= PIC_IRT_LAST_IRQ))
+#endif
+#endif /* _ASM_NLM_XLR_PIC_H */
diff --git a/arch/mips/include/asm/netlogic/xlr/xlr.h b/arch/mips/include/asm/netlogic/xlr/xlr.h
new file mode 100644
index 000000000000..3e6372692a04
--- /dev/null
+++ b/arch/mips/include/asm/netlogic/xlr/xlr.h
@@ -0,0 +1,75 @@
+/*
+ * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
+ * reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the NetLogic
+ * license below:
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _ASM_NLM_XLR_H
+#define _ASM_NLM_XLR_H
+/* Platform UART functions */
+struct uart_port;
+unsigned int nlm_xlr_uart_in(struct uart_port *, int);
+void nlm_xlr_uart_out(struct uart_port *, int, int);
+/* SMP support functions */
+struct irq_desc;
+void nlm_smp_function_ipi_handler(unsigned int irq, struct irq_desc *desc);
+void nlm_smp_resched_ipi_handler(unsigned int irq, struct irq_desc *desc);
+int nlm_wakeup_secondary_cpus(u32 wakeup_mask);
+void nlm_smp_irq_init(void);
+void nlm_boot_smp_nmi(void);
+void prom_pre_boot_secondary_cpus(void);
+extern struct plat_smp_ops nlm_smp_ops;
+extern unsigned long nlm_common_ebase;
+/* XLS B silicon "Rook" */
+static inline unsigned int nlm_chip_is_xls_b(void)
+{
+        uint32_t prid = read_c0_prid();
+        return ((prid & 0xf000) == 0x4000);
+}
+/*
+ *  XLR chip types
+ */
+ /* The XLS product line has chip versions 0x[48c]? */
+static inline unsigned int nlm_chip_is_xls(void)
+{
+        uint32_t prid = read_c0_prid();
+        return ((prid & 0xf000) == 0x8000 || (prid & 0xf000) == 0x4000 ||
+                (prid & 0xf000) == 0xc000);
+}
+#endif /* _ASM_NLM_XLR_H */
diff --git a/arch/mips/include/asm/octeon/cvmx-bootinfo.h b/arch/mips/include/asm/octeon/cvmx-bootinfo.h
index f3c23a43f845..4e4c3a8282d6 100644
--- a/arch/mips/include/asm/octeon/cvmx-bootinfo.h
+++ b/arch/mips/include/asm/octeon/cvmx-bootinfo.h
@@ -200,7 +200,7 @@ enum cvmx_chip_types_enum {
        CVMX_CHIP_TYPE_MAX,
 };
-/* Compatability alias for NAC38 name change, planned to be removed
+/* Compatibility alias for NAC38 name change, planned to be removed
 * from SDK 1.7 */
 #define CVMX_BOARD_TYPE_NAO38   CVMX_BOARD_TYPE_NAC38
diff --git a/arch/mips/include/asm/octeon/cvmx-bootmem.h b/arch/mips/include/asm/octeon/cvmx-bootmem.h
index 8e708bdb43f7..877845b84b14 100644
--- a/arch/mips/include/asm/octeon/cvmx-bootmem.h
+++ b/arch/mips/include/asm/octeon/cvmx-bootmem.h
@@ -67,7 +67,7 @@ struct cvmx_bootmem_block_header {
 /*
 * Structure for named memory blocks.  Number of descriptors available
- * can be changed without affecting compatiblity, but name length
+ * can be changed without affecting compatibility, but name length
 * changes require a bump in the bootmem descriptor version Note: This
 * structure must be naturally 64 bit aligned, as a single memory
 * image will be used by both 32 and 64 bit programs.
diff --git a/arch/mips/include/asm/octeon/cvmx-l2c.h b/arch/mips/include/asm/octeon/cvmx-l2c.h
index 0b32c5b118e2..2c8ff9e33ec3 100644
--- a/arch/mips/include/asm/octeon/cvmx-l2c.h
+++ b/arch/mips/include/asm/octeon/cvmx-l2c.h
@@ -157,7 +157,7 @@ enum cvmx_l2c_tad_event {
 /**
 * Configure one of the four L2 Cache performance counters to capture event
- * occurences.
+ * occurrences.
 *
 * @counter:        The counter to configure. Range 0..3.
 * @event:          The type of L2 Cache event occurrence to count.
diff --git a/arch/mips/include/asm/octeon/cvmx.h b/arch/mips/include/asm/octeon/cvmx.h
index 9d9381e2e3d8..7e1286706d46 100644
--- a/arch/mips/include/asm/octeon/cvmx.h
+++ b/arch/mips/include/asm/octeon/cvmx.h
@@ -151,7 +151,7 @@ enum cvmx_mips_space {
 #endif
 /**
- * Convert a memory pointer (void*) into a hardware compatable
+ * Convert a memory pointer (void*) into a hardware compatible
 * memory address (uint64_t). Octeon hardware widgets don't
 * understand logical addresses.
 *
diff --git a/arch/mips/include/asm/paccess.h b/arch/mips/include/asm/paccess.h
index c2394f8b0fe1..9ce5a1e7e14c 100644
--- a/arch/mips/include/asm/paccess.h
+++ b/arch/mips/include/asm/paccess.h
@@ -7,7 +7,7 @@
 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
 *
 * Protected memory access.  Used for everything that might take revenge
- * by sending a DBE error like accessing possibly non-existant memory or
+ * by sending a DBE error like accessing possibly non-existent memory or
 * devices.
 */
 #ifndef _ASM_PACCESS_H
diff --git a/arch/mips/include/asm/pci/bridge.h b/arch/mips/include/asm/pci/bridge.h
index f1f508e4f971..be44fb0266da 100644
--- a/arch/mips/include/asm/pci/bridge.h
+++ b/arch/mips/include/asm/pci/bridge.h
@@ -262,7 +262,7 @@ typedef volatile struct bridge_s {
 } bridge_t;
 /*
- * Field formats for Error Command Word and Auxillary Error Command Word
+ * Field formats for Error Command Word and Auxiliary Error Command Word
 * of bridge.
 */
 typedef struct bridge_err_cmdword_s {
diff --git a/arch/mips/include/asm/pmc-sierra/msp71xx/msp_regops.h b/arch/mips/include/asm/pmc-sierra/msp71xx/msp_regops.h
index 60a5a38dd5b2..7d41474e5488 100644
--- a/arch/mips/include/asm/pmc-sierra/msp71xx/msp_regops.h
+++ b/arch/mips/include/asm/pmc-sierra/msp71xx/msp_regops.h
@@ -205,7 +205,7 @@ static inline u32 blocking_read_reg32(volatile u32 *const addr)
 *   custom_read_reg32(address, tmp);   <-- Reads the address and put the value
 *                                              in the 'tmp' variable given
 *
- *      From here on out, you are (basicly) atomic, so don't do anything too
+ *      From here on out, you are (basically) atomic, so don't do anything too
 *      fancy!
 *      Also, this code may loop if the end of this block fails to write
 *      everything back safely due do the other CPU, so do NOT do anything
diff --git a/arch/mips/include/asm/processor.h b/arch/mips/include/asm/processor.h
index ead6928fa6b8..c104f1039a69 100644
--- a/arch/mips/include/asm/processor.h
+++ b/arch/mips/include/asm/processor.h
@@ -337,7 +337,7 @@ unsigned long get_wchan(struct task_struct *p);
 /*
 * Return_address is a replacement for __builtin_return_address(count)
 * which on certain architectures cannot reasonably be implemented in GCC
- * (MIPS, Alpha) or is unuseable with -fomit-frame-pointer (i386).
+ * (MIPS, Alpha) or is unusable with -fomit-frame-pointer (i386).
 * Note that __builtin_return_address(x>=1) is forbidden because GCC
 * aborts compilation on some CPUs.  It's simply not possible to unwind
 * some CPU's stackframes.
diff --git a/arch/mips/include/asm/ptrace.h b/arch/mips/include/asm/ptrace.h
index 9f1b8dba2c81..de39b1f343ea 100644
--- a/arch/mips/include/asm/ptrace.h
+++ b/arch/mips/include/asm/ptrace.h
@@ -141,7 +141,8 @@ extern int ptrace_set_watch_regs(struct task_struct *child,
 #define instruction_pointer(regs) ((regs)->cp0_epc)
 #define profile_pc(regs) instruction_pointer(regs)
-extern asmlinkage void do_syscall_trace(struct pt_regs *regs, int entryexit);
+extern asmlinkage void syscall_trace_enter(struct pt_regs *regs);
+extern asmlinkage void syscall_trace_leave(struct pt_regs *regs);
 extern NORET_TYPE void die(const char *, struct pt_regs *) ATTRIB_NORET;
diff --git a/arch/mips/include/asm/sgi/ioc.h b/arch/mips/include/asm/sgi/ioc.h
index 57a971904cfe..380347b648e2 100644
--- a/arch/mips/include/asm/sgi/ioc.h
+++ b/arch/mips/include/asm/sgi/ioc.h
@@ -17,7 +17,7 @@
 #include <asm/sgi/pi1.h>
 /*
- * All registers are 8-bit wide alligned on 32-bit boundary. Bad things
+ * All registers are 8-bit wide aligned on 32-bit boundary. Bad things
 * happen if you try word access them. You have been warned.
 */
diff --git a/arch/mips/include/asm/sibyte/sb1250_mac.h b/arch/mips/include/asm/sibyte/sb1250_mac.h
index 591b9061fd8e..77f787284235 100644
--- a/arch/mips/include/asm/sibyte/sb1250_mac.h
+++ b/arch/mips/include/asm/sibyte/sb1250_mac.h
@@ -520,7 +520,7 @@
 #define G_MAC_RX_EOP_COUNTER(x)     _SB_GETVALUE(x, S_MAC_RX_EOP_COUNTER, M_MAC_RX_EOP_COUNTER)
 /*
- * MAC Recieve Address Filter Exact Match Registers (Table 9-21)
+ * MAC Receive Address Filter Exact Match Registers (Table 9-21)
 * Registers: MAC_ADDR0_0 through MAC_ADDR7_0
 * Registers: MAC_ADDR0_1 through MAC_ADDR7_1
 * Registers: MAC_ADDR0_2 through MAC_ADDR7_2
@@ -538,7 +538,7 @@
 /* No bitfields */
 /*
- * MAC Recieve Address Filter Hash Match Registers (Table 9-22)
+ * MAC Receive Address Filter Hash Match Registers (Table 9-22)
 * Registers: MAC_HASH0_0 through MAC_HASH7_0
 * Registers: MAC_HASH0_1 through MAC_HASH7_1
 * Registers: MAC_HASH0_2 through MAC_HASH7_2
diff --git a/arch/mips/include/asm/siginfo.h b/arch/mips/include/asm/siginfo.h
index 1ca64b4d33d9..20ebeb875ee6 100644
--- a/arch/mips/include/asm/siginfo.h
+++ b/arch/mips/include/asm/siginfo.h
@@ -101,7 +101,7 @@ typedef struct siginfo {
 /*
 * si_code values
- * Again these have been choosen to be IRIX compatible.
+ * Again these have been chosen to be IRIX compatible.
 */
 #undef SI_ASYNCIO
 #undef SI_TIMER
diff --git a/arch/mips/include/asm/sn/klconfig.h b/arch/mips/include/asm/sn/klconfig.h
index 09e590daca17..fe02900b930d 100644
--- a/arch/mips/include/asm/sn/klconfig.h
+++ b/arch/mips/include/asm/sn/klconfig.h
@@ -78,7 +78,7 @@ typedef s32 klconf_off_t;
 */
 #define MAX_SLOTS_PER_NODE      (1 + 2 + 6 + 2)
-/* XXX if each node is guranteed to have some memory */
+/* XXX if each node is guaranteed to have some memory */
 #define MAX_PCI_DEVS            8
@@ -539,7 +539,7 @@ typedef struct klinfo_s {                  /* Generic info */
 #define KLSTRUCT_IOC3_TTY       24
 /* Early Access IO proms are compatible
-   only with KLSTRUCT values upto 24. */
+   only with KLSTRUCT values up to 24. */
 #define KLSTRUCT_FIBERCHANNEL   25
 #define KLSTRUCT_MOD_SERIAL_NUM 26
diff --git a/arch/mips/include/asm/sn/sn0/hubio.h b/arch/mips/include/asm/sn/sn0/hubio.h
index 31c76c021bb6..46286d8302a7 100644
--- a/arch/mips/include/asm/sn/sn0/hubio.h
+++ b/arch/mips/include/asm/sn/sn0/hubio.h
@@ -622,7 +622,7 @@ typedef union h1_icrbb_u {
 */
 #define IIO_ICRB_PROC0          0       /* Source of request is Proc 0 */
 #define IIO_ICRB_PROC1          1       /* Source of request is Proc 1 */
-#define IIO_ICRB_GB_REQ         2       /* Source is Guranteed BW request */
+#define IIO_ICRB_GB_REQ         2       /* Source is Guaranteed BW request */
 #define IIO_ICRB_IO_REQ         3       /* Source is Normal IO request  */
 /*
diff --git a/arch/mips/include/asm/stackframe.h b/arch/mips/include/asm/stackframe.h
index 58730c5ce4bf..b4ba2449444b 100644
--- a/arch/mips/include/asm/stackframe.h
+++ b/arch/mips/include/asm/stackframe.h
@@ -346,7 +346,7 @@
                 * we can't dispatch it directly without trashing
                 * some registers, so we'll try to detect this unlikely
                 * case and program a software interrupt in the VPE,
-                 * as would be done for a cross-VPE IPI.  To accomodate
+                 * as would be done for a cross-VPE IPI.  To accommodate
                 * the handling of that case, we're doing a DVPE instead
                 * of just a DMT here to protect against other threads.
                 * This is a lot of cruft to cover a tiny window.
diff --git a/arch/mips/include/asm/thread_info.h b/arch/mips/include/asm/thread_info.h
index d71160de4d10..97f8bf6639e7 100644
--- a/arch/mips/include/asm/thread_info.h
+++ b/arch/mips/include/asm/thread_info.h
@@ -149,6 +149,9 @@ register struct thread_info *__current_thread_info __asm__("$28");
 #define _TIF_FPUBOUND           (1<<TIF_FPUBOUND)
 #define _TIF_LOAD_WATCH         (1<<TIF_LOAD_WATCH)
+/* work to do in syscall_trace_leave() */
+#define _TIF_WORK_SYSCALL_EXIT  (_TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT)
 /* work to do on interrupt/exception return */
 #define _TIF_WORK_MASK          (0x0000ffef &                           \
                                        ~(_TIF_SECCOMP | _TIF_SYSCALL_AUDIT))
diff --git a/arch/mips/include/asm/time.h b/arch/mips/include/asm/time.h
index c7f1bfef1574..bc14447e69b5 100644
--- a/arch/mips/include/asm/time.h
+++ b/arch/mips/include/asm/time.h
@@ -84,12 +84,6 @@ static inline int init_mips_clocksource(void)
 #endif
 }
-static inline void clocksource_set_clock(struct clocksource *cs,
-                                         unsigned int clock)
-{
-        clocksource_calc_mult_shift(cs, clock, 4);
-}
 static inline void clockevent_set_clock(struct clock_event_device *cd,
                                        unsigned int clock)
 {
diff --git a/arch/mips/include/asm/war.h b/arch/mips/include/asm/war.h
index 22361d5e3bf0..fa133c1bc1f9 100644
--- a/arch/mips/include/asm/war.h
+++ b/arch/mips/include/asm/war.h
@@ -227,7 +227,7 @@
 #endif
 /*
- * On the R10000 upto version 2.6 (not sure about 2.7) there is a bug that
+ * On the R10000 up to version 2.6 (not sure about 2.7) there is a bug that
 * may cause ll / sc and lld / scd sequences to execute non-atomically.
 */
 #ifndef R10000_LLSC_WAR