49 files changed, 1300 insertions, 284 deletions

diff --git a/arch/mips/include/asm/arch_hweight.h b/arch/mips/include/asm/arch_hweight.h
new file mode 100644
index 000000000000..712a7445ee93
--- /dev/null
+++ b/arch/mips/include/asm/arch_hweight.h
@@ -0,0 +1,38 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ */
+#ifndef _ASM_ARCH_HWEIGHT_H
+#define _ASM_ARCH_HWEIGHT_H
+
+#ifdef ARCH_HAS_USABLE_BUILTIN_POPCOUNT
+
+#include <asm/types.h>
+
+static inline unsigned int __arch_hweight32(unsigned int w)
+{
+        return __builtin_popcount(w);
+}
+
+static inline unsigned int __arch_hweight16(unsigned int w)
+{
+        return __builtin_popcount(w & 0xffff);
+}
+
+static inline unsigned int __arch_hweight8(unsigned int w)
+{
+        return __builtin_popcount(w & 0xff);
+}
+
+static inline unsigned long __arch_hweight64(__u64 w)
+{
+        return __builtin_popcountll(w);
+}
+
+#else
+#include <asm-generic/bitops/arch_hweight.h>
+#endif
+
+#endif /* _ASM_ARCH_HWEIGHT_H */
diff --git a/arch/mips/include/asm/bitops.h b/arch/mips/include/asm/bitops.h
index 9255cfbee459..b0ce7ca2851f 100644
--- a/arch/mips/include/asm/bitops.h
+++ b/arch/mips/include/asm/bitops.h
@@ -700,7 +700,10 @@ static inline int ffs(int word)
 #ifdef __KERNEL__
 
 #include <asm-generic/bitops/sched.h>
-#include <asm-generic/bitops/hweight.h>
+
+#include <asm/arch_hweight.h>
+#include <asm-generic/bitops/const_hweight.h>
+
 #include <asm-generic/bitops/ext2-non-atomic.h>
 #include <asm-generic/bitops/ext2-atomic.h>
 #include <asm-generic/bitops/minix.h>
diff --git a/arch/mips/include/asm/bootinfo.h b/arch/mips/include/asm/bootinfo.h
index 09eee09780f2..15a8ef0707c6 100644
--- a/arch/mips/include/asm/bootinfo.h
+++ b/arch/mips/include/asm/bootinfo.h
@@ -71,6 +71,12 @@
 #define MACH_LEMOTE_LL2F       7
 #define MACH_LOONGSON_END      8
 
+/*
+ * Valid machtype for group INGENIC
+ */
+#define  MACH_INGENIC_JZ4730    0       /* JZ4730 SOC           */
+#define  MACH_INGENIC_JZ4740    1       /* JZ4740 SOC           */
+
 extern char *system_type;
 const char *get_system_type(void);
 
diff --git a/arch/mips/include/asm/break.h b/arch/mips/include/asm/break.h
index 44437ed765e8..9161e684cb4c 100644
--- a/arch/mips/include/asm/break.h
+++ b/arch/mips/include/asm/break.h
@@ -30,6 +30,8 @@
 #define BRK_BUG         512     /* Used by BUG() */
 #define BRK_KDB         513     /* Used in KDB_ENTER() */
 #define BRK_MEMU        514     /* Used by FPU emulator */
+#define BRK_KPROBE_BP   515     /* Kprobe break */
+#define BRK_KPROBE_SSTEPBP 516  /* Kprobe single step software implementation */
 #define BRK_MULOVF      1023    /* Multiply overflow */
 
 #endif /* __ASM_BREAK_H */
diff --git a/arch/mips/include/asm/cacheops.h b/arch/mips/include/asm/cacheops.h
index 256ad2cc6eb8..8f99c11ab665 100644
--- a/arch/mips/include/asm/cacheops.h
+++ b/arch/mips/include/asm/cacheops.h
@@ -62,6 +62,8 @@
  * RM7000-specific cacheops
  */
 #define Page_Invalidate_T       0x16
+#define Index_Store_Tag_T       0x0a
+#define Index_Load_Tag_T        0x06
 
 /*
  * R10000-specific cacheops
diff --git a/arch/mips/include/asm/cop2.h b/arch/mips/include/asm/cop2.h
index 6b04c98b7fad..2cb2f0c2c4f8 100644
--- a/arch/mips/include/asm/cop2.h
+++ b/arch/mips/include/asm/cop2.h
@@ -9,6 +9,8 @@
 #ifndef __ASM_COP2_H
 #define __ASM_COP2_H
 
+#include <linux/notifier.h>
+
 enum cu2_ops {
         CU2_EXCEPTION,
         CU2_LWC2_OP,
@@ -20,4 +22,14 @@ enum cu2_ops {
 extern int register_cu2_notifier(struct notifier_block *nb);
 extern int cu2_notifier_call_chain(unsigned long val, void *v);
 
+#define cu2_notifier(fn, pri)                                           \
+({                                                                      \
+        static struct notifier_block fn##_nb __cpuinitdata = {          \
+                .notifier_call = fn,                                    \
+                .priority = pri                                         \
+        };                                                              \
+                                                                        \
+        register_cu2_notifier(&fn##_nb);                                \
+})
+
 #endif /* __ASM_COP2_H */
diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
index ac73cede3a0a..ca400f7c3f59 100644
--- a/arch/mips/include/asm/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
@@ -159,7 +159,8 @@
 
 /*
  * MIPS32, MIPS64, VR5500, IDT32332, IDT32334 and maybe a few other
- * pre-MIPS32/MIPS53 processors have CLO, CLZ.  For 64-bit kernels
+ * pre-MIPS32/MIPS53 processors have CLO, CLZ.  The IDT RC64574 is 64-bit and
+ * has CLO and CLZ but not DCLO nor DCLZ.  For 64-bit kernels
  * cpu_has_clo_clz also indicates the availability of DCLO and DCLZ.
  */
 # ifndef cpu_has_clo_clz
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index a5acda416946..b201a8f5b127 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -34,7 +34,7 @@
 #define PRID_COMP_LSI           0x080000
 #define PRID_COMP_LEXRA         0x0b0000
 #define PRID_COMP_CAVIUM        0x0d0000
-
+#define PRID_COMP_INGENIC       0xd00000
 
 /*
  * Assigned values for the product ID register.  In order to detect a
@@ -133,6 +133,12 @@
 #define PRID_IMP_CAVIUM_CN52XX 0x0700
 
 /*
+ * These are the PRID's for when 23:16 == PRID_COMP_INGENIC
+ */
+
+#define PRID_IMP_JZRISC        0x0200
+
+/*
  * Definitions for 7:0 on legacy processors
  */
 
@@ -219,6 +225,7 @@ enum cpu_type_enum {
         CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K,
         CPU_ALCHEMY, CPU_PR4450, CPU_BCM3302, CPU_BCM4710,
         CPU_BCM6338, CPU_BCM6345, CPU_BCM6348, CPU_BCM6358,
+        CPU_JZRISC,
 
         /*
          * MIPS64 class processors
diff --git a/arch/mips/include/asm/elf.h b/arch/mips/include/asm/elf.h
index ea77a42c5f8c..fd1d39eb7431 100644
--- a/arch/mips/include/asm/elf.h
+++ b/arch/mips/include/asm/elf.h
@@ -372,4 +372,9 @@ extern const char *__elf_platform;
 struct linux_binprm;
 extern int arch_setup_additional_pages(struct linux_binprm *bprm,
                                        int uses_interp);
+
+struct mm_struct;
+extern unsigned long arch_randomize_brk(struct mm_struct *mm);
+#define arch_randomize_brk arch_randomize_brk
+
 #endif /* _ASM_ELF_H */
diff --git a/arch/mips/include/asm/emma/emma2rh.h b/arch/mips/include/asm/emma/emma2rh.h
index 2afb2fe11b30..c1449d20ef0e 100644
--- a/arch/mips/include/asm/emma/emma2rh.h
+++ b/arch/mips/include/asm/emma/emma2rh.h
@@ -99,88 +99,22 @@
 #define EMMA2RH_PCI_CONFIG_BASE EMMA2RH_PCI_IO_BASE
 #define EMMA2RH_PCI_CONFIG_SIZE EMMA2RH_PCI_IO_SIZE
 
-#define NUM_CPU_IRQ             8
 #define NUM_EMMA2RH_IRQ         96
 
-#define CPU_EMMA2RH_CASCADE     2
-#define CPU_IRQ_BASE            MIPS_CPU_IRQ_BASE
-#define EMMA2RH_IRQ_BASE        (CPU_IRQ_BASE + NUM_CPU_IRQ)
+#define EMMA2RH_IRQ_BASE        (MIPS_CPU_IRQ_BASE + 8)
 
 /*
  * emma2rh irq defs
  */
 
-#define EMMA2RH_IRQ_INT0        (0 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT1        (1 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT2        (2 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT3        (3 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT4        (4 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT5        (5 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT6        (6 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT7        (7 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT8        (8 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT9        (9 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT10       (10 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT11       (11 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT12       (12 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT13       (13 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT14       (14 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT15       (15 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT16       (16 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT17       (17 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT18       (18 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT19       (19 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT20       (20 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT21       (21 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT22       (22 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT23       (23 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT24       (24 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT25       (25 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT26       (26 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT27       (27 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT28       (28 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT29       (29 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT30       (30 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT31       (31 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT32       (32 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT33       (33 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT34       (34 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT35       (35 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT36       (36 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT37       (37 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT38       (38 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT39       (39 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT40       (40 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT41       (41 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT42       (42 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT43       (43 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT44       (44 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT45       (45 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT46       (46 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT47       (47 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT48       (48 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT49       (49 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT50       (50 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT51       (51 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT52       (52 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT53       (53 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT54       (54 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT55       (55 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT56       (56 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT57       (57 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT58       (58 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT59       (59 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT60       (60 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT61       (61 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT62       (62 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT63       (63 + EMMA2RH_IRQ_BASE)
-
-#define EMMA2RH_IRQ_PFUR0       EMMA2RH_IRQ_INT49
-#define EMMA2RH_IRQ_PFUR1       EMMA2RH_IRQ_INT50
-#define EMMA2RH_IRQ_PFUR2       EMMA2RH_IRQ_INT51
-#define EMMA2RH_IRQ_PIIC0       EMMA2RH_IRQ_INT56
-#define EMMA2RH_IRQ_PIIC1       EMMA2RH_IRQ_INT57
-#define EMMA2RH_IRQ_PIIC2       EMMA2RH_IRQ_INT58
+#define EMMA2RH_IRQ_INT(n)      (EMMA2RH_IRQ_BASE + (n))
+
+#define EMMA2RH_IRQ_PFUR0       EMMA2RH_IRQ_INT(49)
+#define EMMA2RH_IRQ_PFUR1       EMMA2RH_IRQ_INT(50)
+#define EMMA2RH_IRQ_PFUR2       EMMA2RH_IRQ_INT(51)
+#define EMMA2RH_IRQ_PIIC0       EMMA2RH_IRQ_INT(56)
+#define EMMA2RH_IRQ_PIIC1       EMMA2RH_IRQ_INT(57)
+#define EMMA2RH_IRQ_PIIC2       EMMA2RH_IRQ_INT(58)
 
 /*
  *  EMMA2RH Register Access
diff --git a/arch/mips/include/asm/emma/markeins.h b/arch/mips/include/asm/emma/markeins.h
index 2618bf230248..bf2d229c2dae 100644
--- a/arch/mips/include/asm/emma/markeins.h
+++ b/arch/mips/include/asm/emma/markeins.h
@@ -25,44 +25,13 @@
 #define NUM_EMMA2RH_IRQ_SW      32
 #define NUM_EMMA2RH_IRQ_GPIO    32
 
-#define EMMA2RH_SW_CASCADE      (EMMA2RH_IRQ_INT7 - EMMA2RH_IRQ_INT0)
-#define EMMA2RH_GPIO_CASCADE    (EMMA2RH_IRQ_INT46 - EMMA2RH_IRQ_INT0)
+#define EMMA2RH_SW_CASCADE      (EMMA2RH_IRQ_INT(7) - EMMA2RH_IRQ_INT(0))
+#define EMMA2RH_GPIO_CASCADE    (EMMA2RH_IRQ_INT(46) - EMMA2RH_IRQ_INT(0))
 
 #define EMMA2RH_SW_IRQ_BASE     (EMMA2RH_IRQ_BASE + NUM_EMMA2RH_IRQ)
 #define EMMA2RH_GPIO_IRQ_BASE   (EMMA2RH_SW_IRQ_BASE + NUM_EMMA2RH_IRQ_SW)
 
-#define EMMA2RH_SW_IRQ_INT0     (0+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT1     (1+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT2     (2+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT3     (3+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT4     (4+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT5     (5+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT6     (6+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT7     (7+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT8     (8+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT9     (9+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT10    (10+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT11    (11+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT12    (12+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT13    (13+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT14    (14+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT15    (15+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT16    (16+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT17    (17+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT18    (18+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT19    (19+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT20    (20+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT21    (21+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT22    (22+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT23    (23+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT24    (24+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT25    (25+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT26    (26+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT27    (27+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT28    (28+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT29    (29+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT30    (30+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT31    (31+EMMA2RH_SW_IRQ_BASE)
+#define EMMA2RH_SW_IRQ_INT(n)   (EMMA2RH_SW_IRQ_BASE + (n))
 
 #define MARKEINS_PCI_IRQ_INTA   EMMA2RH_GPIO_IRQ_BASE+15
 #define MARKEINS_PCI_IRQ_INTB   EMMA2RH_GPIO_IRQ_BASE+16
diff --git a/arch/mips/include/asm/hazards.h b/arch/mips/include/asm/hazards.h
index 0eaf77ffbc4f..4e332165d7b7 100644
--- a/arch/mips/include/asm/hazards.h
+++ b/arch/mips/include/asm/hazards.h
@@ -87,7 +87,7 @@ do {									\
         : "=r" (tmp));                                                  \
 } while (0)
 
-#elif defined(CONFIG_CPU_MIPSR1) && !defined(CONFIG_MACH_ALCHEMY)
+#elif defined(CONFIG_CPU_MIPSR1) && !defined(CONFIG_MIPS_ALCHEMY)
 
 /*
  * These are slightly complicated by the fact that we guarantee R1 kernels to
@@ -138,7 +138,7 @@ do {									\
                 __instruction_hazard();                                 \
 } while (0)
 
-#elif defined(CONFIG_MACH_ALCHEMY) || defined(CONFIG_CPU_CAVIUM_OCTEON) || \
+#elif defined(CONFIG_MIPS_ALCHEMY) || defined(CONFIG_CPU_CAVIUM_OCTEON) || \
       defined(CONFIG_CPU_LOONGSON2) || defined(CONFIG_CPU_R10000) || \
       defined(CONFIG_CPU_R5500)
 
diff --git a/arch/mips/include/asm/inst.h b/arch/mips/include/asm/inst.h
index 6489f00731ca..444ff71aa0e8 100644
--- a/arch/mips/include/asm/inst.h
+++ b/arch/mips/include/asm/inst.h
@@ -247,6 +247,12 @@ struct ma_format {	/* FPU multipy and add format (MIPS IV) */
         unsigned int fmt : 2;
 };
 
+struct b_format { /* BREAK and SYSCALL */
+        unsigned int opcode:6;
+        unsigned int code:20;
+        unsigned int func:6;
+};
+
 #elif defined(__MIPSEL__)
 
 struct j_format {       /* Jump format */
@@ -314,6 +320,12 @@ struct ma_format {	/* FPU multipy and add format (MIPS IV) */
         unsigned int opcode : 6;
 };
 
+struct b_format { /* BREAK and SYSCALL */
+        unsigned int func:6;
+        unsigned int code:20;
+        unsigned int opcode:6;
+};
+
 #else /* !defined (__MIPSEB__) && !defined (__MIPSEL__) */
 #error "MIPS but neither __MIPSEL__ nor __MIPSEB__?"
 #endif
@@ -328,7 +340,8 @@ union mips_instruction {
         struct c_format c_format;
         struct r_format r_format;
         struct f_format f_format;
-        struct ma_format ma_format;
+        struct ma_format ma_format;
+        struct b_format b_format;
 };
 
 /* HACHACHAHCAHC ...  */
diff --git a/arch/mips/include/asm/kdebug.h b/arch/mips/include/asm/kdebug.h
index 5bf62aafc890..6a9af5fcb5d7 100644
--- a/arch/mips/include/asm/kdebug.h
+++ b/arch/mips/include/asm/kdebug.h
@@ -8,6 +8,9 @@ enum die_val {
         DIE_FP,
         DIE_TRAP,
         DIE_RI,
+        DIE_PAGE_FAULT,
+        DIE_BREAK,
+        DIE_SSTEPBP
 };
 
 #endif /* _ASM_MIPS_KDEBUG_H */
diff --git a/arch/mips/include/asm/kgdb.h b/arch/mips/include/asm/kgdb.h
index 19002d605ac4..e6c0b0e14ccb 100644
--- a/arch/mips/include/asm/kgdb.h
+++ b/arch/mips/include/asm/kgdb.h
@@ -8,28 +8,27 @@
 #if (_MIPS_ISA == _MIPS_ISA_MIPS1) || (_MIPS_ISA == _MIPS_ISA_MIPS2) || \
         (_MIPS_ISA == _MIPS_ISA_MIPS32)
 
-#define KGDB_GDB_REG_SIZE 32
+#define KGDB_GDB_REG_SIZE       32
+#define GDB_SIZEOF_REG          sizeof(u32)
 
 #elif (_MIPS_ISA == _MIPS_ISA_MIPS3) || (_MIPS_ISA == _MIPS_ISA_MIPS4) || \
         (_MIPS_ISA == _MIPS_ISA_MIPS64)
 
 #ifdef CONFIG_32BIT
-#define KGDB_GDB_REG_SIZE 32
+#define KGDB_GDB_REG_SIZE       32
+#define GDB_SIZEOF_REG          sizeof(u32)
 #else /* CONFIG_CPU_32BIT */
-#define KGDB_GDB_REG_SIZE 64
+#define KGDB_GDB_REG_SIZE       64
+#define GDB_SIZEOF_REG          sizeof(u64)
 #endif
 #else
 #error "Need to set KGDB_GDB_REG_SIZE for MIPS ISA"
 #endif /* _MIPS_ISA */
 
 #define BUFMAX                  2048
-#if (KGDB_GDB_REG_SIZE == 32)
-#define NUMREGBYTES             (90*sizeof(u32))
-#define NUMCRITREGBYTES         (12*sizeof(u32))
-#else
-#define NUMREGBYTES             (90*sizeof(u64))
-#define NUMCRITREGBYTES         (12*sizeof(u64))
-#endif
+#define DBG_MAX_REG_NUM         72
+#define NUMREGBYTES             (DBG_MAX_REG_NUM * sizeof(GDB_SIZEOF_REG))
+#define NUMCRITREGBYTES         (12 * sizeof(GDB_SIZEOF_REG))
 #define BREAK_INSTR_SIZE        4
 #define CACHE_FLUSH_IS_SAFE     0
 
diff --git a/arch/mips/include/asm/kprobes.h b/arch/mips/include/asm/kprobes.h
new file mode 100644
index 000000000000..e6ea4d4d7205
--- /dev/null
+++ b/arch/mips/include/asm/kprobes.h
@@ -0,0 +1,92 @@
+/*
+ *  Kernel Probes (KProbes)
+ *  include/asm-mips/kprobes.h
+ *
+ *  Copyright 2006 Sony Corp.
+ *  Copyright 2010 Cavium Networks
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; version 2 of the License.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef _ASM_KPROBES_H
+#define _ASM_KPROBES_H
+
+#include <linux/ptrace.h>
+#include <linux/types.h>
+
+#include <asm/cacheflush.h>
+#include <asm/kdebug.h>
+#include <asm/inst.h>
+
+#define  __ARCH_WANT_KPROBES_INSN_SLOT
+
+struct kprobe;
+struct pt_regs;
+
+typedef union mips_instruction kprobe_opcode_t;
+
+#define MAX_INSN_SIZE 2
+
+#define flush_insn_slot(p)                                              \
+do {                                                                    \
+        flush_icache_range((unsigned long)p->addr,                      \
+                           (unsigned long)p->addr +                     \
+                           (MAX_INSN_SIZE * sizeof(kprobe_opcode_t)));  \
+} while (0)
+
+
+#define kretprobe_blacklist_size 0
+
+void arch_remove_kprobe(struct kprobe *p);
+
+/* Architecture specific copy of original instruction*/
+struct arch_specific_insn {
+        /* copy of the original instruction */
+        kprobe_opcode_t *insn;
+};
+
+struct prev_kprobe {
+        struct kprobe *kp;
+        unsigned long status;
+        unsigned long old_SR;
+        unsigned long saved_SR;
+        unsigned long saved_epc;
+};
+
+#define MAX_JPROBES_STACK_SIZE 128
+#define MAX_JPROBES_STACK_ADDR \
+        (((unsigned long)current_thread_info()) + THREAD_SIZE - 32 - sizeof(struct pt_regs))
+
+#define MIN_JPROBES_STACK_SIZE(ADDR)                                    \
+        ((((ADDR) + MAX_JPROBES_STACK_SIZE) > MAX_JPROBES_STACK_ADDR)   \
+                ? MAX_JPROBES_STACK_ADDR - (ADDR)                       \
+                : MAX_JPROBES_STACK_SIZE)
+
+
+/* per-cpu kprobe control block */
+struct kprobe_ctlblk {
+        unsigned long kprobe_status;
+        unsigned long kprobe_old_SR;
+        unsigned long kprobe_saved_SR;
+        unsigned long kprobe_saved_epc;
+        unsigned long jprobe_saved_sp;
+        struct pt_regs jprobe_saved_regs;
+        u8 jprobes_stack[MAX_JPROBES_STACK_SIZE];
+        struct prev_kprobe prev_kprobe;
+};
+
+extern int kprobe_exceptions_notify(struct notifier_block *self,
+                                    unsigned long val, void *data);
+
+#endif                          /* _ASM_KPROBES_H */
diff --git a/arch/mips/include/asm/mach-au1x00/au1xxx_eth.h b/arch/mips/include/asm/mach-au1x00/au1xxx_eth.h
index bae9b758fcde..49dc8d9db186 100644
--- a/arch/mips/include/asm/mach-au1x00/au1xxx_eth.h
+++ b/arch/mips/include/asm/mach-au1x00/au1xxx_eth.h
@@ -9,6 +9,7 @@ struct au1000_eth_platform_data {
         int phy_addr;
         int phy_busid;
         int phy_irq;
+        char mac[6];
 };
 
 void __init au1xxx_override_eth_cfg(unsigned port,
diff --git a/arch/mips/include/asm/mach-bcm47xx/nvram.h b/arch/mips/include/asm/mach-bcm47xx/nvram.h
index 0d8cc146f7a4..c58ebd8bc155 100644
--- a/arch/mips/include/asm/mach-bcm47xx/nvram.h
+++ b/arch/mips/include/asm/mach-bcm47xx/nvram.h
@@ -31,6 +31,9 @@ struct nvram_header {
 #define NVRAM_MAX_VALUE_LEN 255
 #define NVRAM_MAX_PARAM_LEN 64
 
+#define NVRAM_ERR_INV_PARAM     -8
+#define NVRAM_ERR_ENVNOTFOUND   -9
+
 extern int nvram_getenv(char *name, char *val, size_t val_len);
 
 #endif
diff --git a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
index bbf054042395..b952fc7215e2 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
@@ -61,21 +61,18 @@
 
 #define kernel_uses_smartmips_rixi (cpu_data[0].cputype == CPU_CAVIUM_OCTEON_PLUS)
 
-#define ARCH_HAS_READ_CURRENT_TIMER 1
 #define ARCH_HAS_IRQ_PER_CPU    1
 #define ARCH_HAS_SPINLOCK_PREFETCH 1
 #define spin_lock_prefetch(x) prefetch(x)
 #define PREFETCH_STRIDE 128
 
-static inline int read_current_timer(unsigned long *result)
-{
-        asm volatile ("rdhwr %0,$31\n"
-#ifndef CONFIG_64BIT
-                      "\tsll %0, 0"
+#ifdef __OCTEON__
+/*
+ * All gcc versions that have OCTEON support define __OCTEON__ and have the
+ *  __builtin_popcount support.
+ */
+#define ARCH_HAS_USABLE_BUILTIN_POPCOUNT 1
 #endif
-                      : "=r" (*result));
-        return 0;
-}
 
 static inline int octeon_has_saa(void)
 {
diff --git a/arch/mips/include/asm/mach-cavium-octeon/irq.h b/arch/mips/include/asm/mach-cavium-octeon/irq.h
index d32220fbf4f1..6ddab8aef644 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/irq.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/irq.h
@@ -172,71 +172,9 @@
 #ifdef CONFIG_PCI_MSI
 /* 152 - 215 represent the MSI interrupts 0-63 */
 #define OCTEON_IRQ_MSI_BIT0     152
-#define OCTEON_IRQ_MSI_BIT1     153
-#define OCTEON_IRQ_MSI_BIT2     154
-#define OCTEON_IRQ_MSI_BIT3     155
-#define OCTEON_IRQ_MSI_BIT4     156
-#define OCTEON_IRQ_MSI_BIT5     157
-#define OCTEON_IRQ_MSI_BIT6     158
-#define OCTEON_IRQ_MSI_BIT7     159
-#define OCTEON_IRQ_MSI_BIT8     160
-#define OCTEON_IRQ_MSI_BIT9     161
-#define OCTEON_IRQ_MSI_BIT10    162
-#define OCTEON_IRQ_MSI_BIT11    163
-#define OCTEON_IRQ_MSI_BIT12    164
-#define OCTEON_IRQ_MSI_BIT13    165
-#define OCTEON_IRQ_MSI_BIT14    166
-#define OCTEON_IRQ_MSI_BIT15    167
-#define OCTEON_IRQ_MSI_BIT16    168
-#define OCTEON_IRQ_MSI_BIT17    169
-#define OCTEON_IRQ_MSI_BIT18    170
-#define OCTEON_IRQ_MSI_BIT19    171
-#define OCTEON_IRQ_MSI_BIT20    172
-#define OCTEON_IRQ_MSI_BIT21    173
-#define OCTEON_IRQ_MSI_BIT22    174
-#define OCTEON_IRQ_MSI_BIT23    175
-#define OCTEON_IRQ_MSI_BIT24    176
-#define OCTEON_IRQ_MSI_BIT25    177
-#define OCTEON_IRQ_MSI_BIT26    178
-#define OCTEON_IRQ_MSI_BIT27    179
-#define OCTEON_IRQ_MSI_BIT28    180
-#define OCTEON_IRQ_MSI_BIT29    181
-#define OCTEON_IRQ_MSI_BIT30    182
-#define OCTEON_IRQ_MSI_BIT31    183
-#define OCTEON_IRQ_MSI_BIT32    184
-#define OCTEON_IRQ_MSI_BIT33    185
-#define OCTEON_IRQ_MSI_BIT34    186
-#define OCTEON_IRQ_MSI_BIT35    187
-#define OCTEON_IRQ_MSI_BIT36    188
-#define OCTEON_IRQ_MSI_BIT37    189
-#define OCTEON_IRQ_MSI_BIT38    190
-#define OCTEON_IRQ_MSI_BIT39    191
-#define OCTEON_IRQ_MSI_BIT40    192
-#define OCTEON_IRQ_MSI_BIT41    193
-#define OCTEON_IRQ_MSI_BIT42    194
-#define OCTEON_IRQ_MSI_BIT43    195
-#define OCTEON_IRQ_MSI_BIT44    196
-#define OCTEON_IRQ_MSI_BIT45    197
-#define OCTEON_IRQ_MSI_BIT46    198
-#define OCTEON_IRQ_MSI_BIT47    199
-#define OCTEON_IRQ_MSI_BIT48    200
-#define OCTEON_IRQ_MSI_BIT49    201
-#define OCTEON_IRQ_MSI_BIT50    202
-#define OCTEON_IRQ_MSI_BIT51    203
-#define OCTEON_IRQ_MSI_BIT52    204
-#define OCTEON_IRQ_MSI_BIT53    205
-#define OCTEON_IRQ_MSI_BIT54    206
-#define OCTEON_IRQ_MSI_BIT55    207
-#define OCTEON_IRQ_MSI_BIT56    208
-#define OCTEON_IRQ_MSI_BIT57    209
-#define OCTEON_IRQ_MSI_BIT58    210
-#define OCTEON_IRQ_MSI_BIT59    211
-#define OCTEON_IRQ_MSI_BIT60    212
-#define OCTEON_IRQ_MSI_BIT61    213
-#define OCTEON_IRQ_MSI_BIT62    214
-#define OCTEON_IRQ_MSI_BIT63    215
+#define OCTEON_IRQ_MSI_LAST     (OCTEON_IRQ_MSI_BIT0 + 255)
 
-#define OCTEON_IRQ_LAST         216
+#define OCTEON_IRQ_LAST         (OCTEON_IRQ_MSI_LAST + 1)
 #else
 #define OCTEON_IRQ_LAST         152
 #endif
diff --git a/arch/mips/include/asm/mach-jz4740/base.h b/arch/mips/include/asm/mach-jz4740/base.h
new file mode 100644
index 000000000000..f37318605452
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4740/base.h
@@ -0,0 +1,26 @@
+#ifndef __ASM_MACH_JZ4740_BASE_H__
+#define __ASM_MACH_JZ4740_BASE_H__
+
+#define JZ4740_CPM_BASE_ADDR    0x10000000
+#define JZ4740_INTC_BASE_ADDR   0x10001000
+#define JZ4740_WDT_BASE_ADDR    0x10002000
+#define JZ4740_TCU_BASE_ADDR    0x10002010
+#define JZ4740_RTC_BASE_ADDR    0x10003000
+#define JZ4740_GPIO_BASE_ADDR   0x10010000
+#define JZ4740_AIC_BASE_ADDR    0x10020000
+#define JZ4740_MSC_BASE_ADDR    0x10021000
+#define JZ4740_UART0_BASE_ADDR  0x10030000
+#define JZ4740_UART1_BASE_ADDR  0x10031000
+#define JZ4740_I2C_BASE_ADDR    0x10042000
+#define JZ4740_SSI_BASE_ADDR    0x10043000
+#define JZ4740_SADC_BASE_ADDR   0x10070000
+#define JZ4740_EMC_BASE_ADDR    0x13010000
+#define JZ4740_DMAC_BASE_ADDR   0x13020000
+#define JZ4740_UHC_BASE_ADDR    0x13030000
+#define JZ4740_UDC_BASE_ADDR    0x13040000
+#define JZ4740_LCD_BASE_ADDR    0x13050000
+#define JZ4740_SLCD_BASE_ADDR   0x13050000
+#define JZ4740_CIM_BASE_ADDR    0x13060000
+#define JZ4740_IPU_BASE_ADDR    0x13080000
+
+#endif
diff --git a/arch/mips/include/asm/mach-jz4740/clock.h b/arch/mips/include/asm/mach-jz4740/clock.h
new file mode 100644
index 000000000000..1b7408dd0e23
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4740/clock.h
@@ -0,0 +1,28 @@
+/*
+ *  Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under  the terms of the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the License, or (at your
+ *  option) any later version.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#ifndef __ASM_JZ4740_CLOCK_H__
+#define __ASM_JZ4740_CLOCK_H__
+
+enum jz4740_wait_mode {
+        JZ4740_WAIT_MODE_IDLE,
+        JZ4740_WAIT_MODE_SLEEP,
+};
+
+void jz4740_clock_set_wait_mode(enum jz4740_wait_mode mode);
+
+void jz4740_clock_udc_enable_auto_suspend(void);
+void jz4740_clock_udc_disable_auto_suspend(void);
+
+#endif
diff --git a/arch/mips/include/asm/mach-jz4740/cpu-feature-overrides.h b/arch/mips/include/asm/mach-jz4740/cpu-feature-overrides.h
new file mode 100644
index 000000000000..d12e5c6477b9
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4740/cpu-feature-overrides.h
@@ -0,0 +1,51 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ */
+#ifndef __ASM_MACH_JZ4740_CPU_FEATURE_OVERRIDES_H
+#define __ASM_MACH_JZ4740_CPU_FEATURE_OVERRIDES_H
+
+#define cpu_has_tlb 1
+#define cpu_has_4kex            1
+#define cpu_has_3k_cache        0
+#define cpu_has_4k_cache        1
+#define cpu_has_tx39_cache      0
+#define cpu_has_fpu             0
+#define cpu_has_32fpr   0
+#define cpu_has_counter         0
+#define cpu_has_watch           1
+#define cpu_has_divec           1
+#define cpu_has_vce             0
+#define cpu_has_cache_cdex_p    0
+#define cpu_has_cache_cdex_s    0
+#define cpu_has_prefetch        1
+#define cpu_has_mcheck 1
+#define cpu_has_ejtag 1
+#define cpu_has_llsc            1
+#define cpu_has_mips16 0
+#define cpu_has_mdmx 0
+#define cpu_has_mips3d 0
+#define cpu_has_smartmips 0
+#define kernel_uses_llsc        1
+#define cpu_has_vtag_icache     1
+#define cpu_has_dc_aliases      0
+#define cpu_has_ic_fills_f_dc   0
+#define cpu_has_pindexed_dcache 0
+#define cpu_has_mips32r1        1
+#define cpu_has_mips32r2        0
+#define cpu_has_mips64r1        0
+#define cpu_has_mips64r2        0
+#define cpu_has_dsp             0
+#define cpu_has_mipsmt          0
+#define cpu_has_userlocal       0
+#define cpu_has_nofpuex 0
+#define cpu_has_64bits          0
+#define cpu_has_64bit_zero_reg 0
+#define cpu_has_inclusive_pcaches 0
+
+#define cpu_dcache_line_size()  32
+#define cpu_icache_line_size()  32
+
+#endif
diff --git a/arch/mips/include/asm/mach-jz4740/dma.h b/arch/mips/include/asm/mach-jz4740/dma.h
new file mode 100644
index 000000000000..a3be12183599
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4740/dma.h
@@ -0,0 +1,90 @@
+/*
+ *  Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
+ *  JZ7420/JZ4740 DMA definitions
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under  the terms of the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the License, or (at your
+ *  option) any later version.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#ifndef __ASM_MACH_JZ4740_DMA_H__
+#define __ASM_MACH_JZ4740_DMA_H__
+
+struct jz4740_dma_chan;
+
+enum jz4740_dma_request_type {
+        JZ4740_DMA_TYPE_AUTO_REQUEST    = 8,
+        JZ4740_DMA_TYPE_UART_TRANSMIT   = 20,
+        JZ4740_DMA_TYPE_UART_RECEIVE    = 21,
+        JZ4740_DMA_TYPE_SPI_TRANSMIT    = 22,
+        JZ4740_DMA_TYPE_SPI_RECEIVE     = 23,
+        JZ4740_DMA_TYPE_AIC_TRANSMIT    = 24,
+        JZ4740_DMA_TYPE_AIC_RECEIVE     = 25,
+        JZ4740_DMA_TYPE_MMC_TRANSMIT    = 26,
+        JZ4740_DMA_TYPE_MMC_RECEIVE     = 27,
+        JZ4740_DMA_TYPE_TCU             = 28,
+        JZ4740_DMA_TYPE_SADC            = 29,
+        JZ4740_DMA_TYPE_SLCD            = 30,
+};
+
+enum jz4740_dma_width {
+        JZ4740_DMA_WIDTH_32BIT  = 0,
+        JZ4740_DMA_WIDTH_8BIT   = 1,
+        JZ4740_DMA_WIDTH_16BIT  = 2,
+};
+
+enum jz4740_dma_transfer_size {
+        JZ4740_DMA_TRANSFER_SIZE_4BYTE  = 0,
+        JZ4740_DMA_TRANSFER_SIZE_1BYTE  = 1,
+        JZ4740_DMA_TRANSFER_SIZE_2BYTE  = 2,
+        JZ4740_DMA_TRANSFER_SIZE_16BYTE = 3,
+        JZ4740_DMA_TRANSFER_SIZE_32BYTE = 4,
+};
+
+enum jz4740_dma_flags {
+        JZ4740_DMA_SRC_AUTOINC = 0x2,
+        JZ4740_DMA_DST_AUTOINC = 0x1,
+};
+
+enum jz4740_dma_mode {
+        JZ4740_DMA_MODE_SINGLE  = 0,
+        JZ4740_DMA_MODE_BLOCK   = 1,
+};
+
+struct jz4740_dma_config {
+        enum jz4740_dma_width src_width;
+        enum jz4740_dma_width dst_width;
+        enum jz4740_dma_transfer_size transfer_size;
+        enum jz4740_dma_request_type request_type;
+        enum jz4740_dma_flags flags;
+        enum jz4740_dma_mode mode;
+};
+
+typedef void (*jz4740_dma_complete_callback_t)(struct jz4740_dma_chan *, int, void *);
+
+struct jz4740_dma_chan *jz4740_dma_request(void *dev, const char *name);
+void jz4740_dma_free(struct jz4740_dma_chan *dma);
+
+void jz4740_dma_configure(struct jz4740_dma_chan *dma,
+        const struct jz4740_dma_config *config);
+
+
+void jz4740_dma_enable(struct jz4740_dma_chan *dma);
+void jz4740_dma_disable(struct jz4740_dma_chan *dma);
+
+void jz4740_dma_set_src_addr(struct jz4740_dma_chan *dma, dma_addr_t src);
+void jz4740_dma_set_dst_addr(struct jz4740_dma_chan *dma, dma_addr_t dst);
+void jz4740_dma_set_transfer_count(struct jz4740_dma_chan *dma, uint32_t count);
+
+uint32_t jz4740_dma_get_residue(const struct jz4740_dma_chan *dma);
+
+void jz4740_dma_set_complete_cb(struct jz4740_dma_chan *dma,
+        jz4740_dma_complete_callback_t cb);
+
+#endif  /* __ASM_JZ4740_DMA_H__ */
diff --git a/arch/mips/include/asm/mach-jz4740/gpio.h b/arch/mips/include/asm/mach-jz4740/gpio.h
new file mode 100644
index 000000000000..7b74703745bb
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4740/gpio.h
@@ -0,0 +1,398 @@
+/*
+ *  Copyright (C) 2009, Lars-Peter Clausen <lars@metafoo.de>
+ *  JZ4740 GPIO pin definitions
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under  the terms of the GNU General Public License as published by the
+ *  Free Software Foundation;  either version 2 of the License, or (at your
+ *  option) any later version.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#ifndef _JZ_GPIO_H
+#define _JZ_GPIO_H
+
+#include <linux/types.h>
+
+enum jz_gpio_function {
+    JZ_GPIO_FUNC_NONE,
+    JZ_GPIO_FUNC1,
+    JZ_GPIO_FUNC2,
+    JZ_GPIO_FUNC3,
+};
+
+
+/*
+ Usually a driver for a SoC component has to request several gpio pins and
+ configure them as funcion pins.
+ jz_gpio_bulk_request can be used to ease this process.
+ Usually one would do something like:
+
+ const static struct jz_gpio_bulk_request i2c_pins[] = {
+        JZ_GPIO_BULK_PIN(I2C_SDA),
+        JZ_GPIO_BULK_PIN(I2C_SCK),
+ };
+
+ inside the probe function:
+
+    ret = jz_gpio_bulk_request(i2c_pins, ARRAY_SIZE(i2c_pins));
+    if (ret) {
+        ...
+
+ inside the remove function:
+
+    jz_gpio_bulk_free(i2c_pins, ARRAY_SIZE(i2c_pins));
+
+
+*/
+struct jz_gpio_bulk_request {
+        int gpio;
+        const char *name;
+        enum jz_gpio_function function;
+};
+
+#define JZ_GPIO_BULK_PIN(pin) { \
+    .gpio = JZ_GPIO_ ## pin, \
+    .name = #pin, \
+    .function = JZ_GPIO_FUNC_ ## pin \
+}
+
+int jz_gpio_bulk_request(const struct jz_gpio_bulk_request *request, size_t num);
+void jz_gpio_bulk_free(const struct jz_gpio_bulk_request *request, size_t num);
+void jz_gpio_bulk_suspend(const struct jz_gpio_bulk_request *request, size_t num);
+void jz_gpio_bulk_resume(const struct jz_gpio_bulk_request *request, size_t num);
+void jz_gpio_enable_pullup(unsigned gpio);
+void jz_gpio_disable_pullup(unsigned gpio);
+int jz_gpio_set_function(int gpio, enum jz_gpio_function function);
+
+int jz_gpio_port_direction_input(int port, uint32_t mask);
+int jz_gpio_port_direction_output(int port, uint32_t mask);
+void jz_gpio_port_set_value(int port, uint32_t value, uint32_t mask);
+uint32_t jz_gpio_port_get_value(int port, uint32_t mask);
+
+#include <asm/mach-generic/gpio.h>
+
+#define JZ_GPIO_PORTA(x) ((x) + 32 * 0)
+#define JZ_GPIO_PORTB(x) ((x) + 32 * 1)
+#define JZ_GPIO_PORTC(x) ((x) + 32 * 2)
+#define JZ_GPIO_PORTD(x) ((x) + 32 * 3)
+
+/* Port A function pins */
+#define JZ_GPIO_MEM_DATA0               JZ_GPIO_PORTA(0)
+#define JZ_GPIO_MEM_DATA1               JZ_GPIO_PORTA(1)
+#define JZ_GPIO_MEM_DATA2               JZ_GPIO_PORTA(2)
+#define JZ_GPIO_MEM_DATA3               JZ_GPIO_PORTA(3)
+#define JZ_GPIO_MEM_DATA4               JZ_GPIO_PORTA(4)
+#define JZ_GPIO_MEM_DATA5               JZ_GPIO_PORTA(5)
+#define JZ_GPIO_MEM_DATA6               JZ_GPIO_PORTA(6)
+#define JZ_GPIO_MEM_DATA7               JZ_GPIO_PORTA(7)
+#define JZ_GPIO_MEM_DATA8               JZ_GPIO_PORTA(8)
+#define JZ_GPIO_MEM_DATA9               JZ_GPIO_PORTA(9)
+#define JZ_GPIO_MEM_DATA10              JZ_GPIO_PORTA(10)
+#define JZ_GPIO_MEM_DATA11              JZ_GPIO_PORTA(11)
+#define JZ_GPIO_MEM_DATA12              JZ_GPIO_PORTA(12)
+#define JZ_GPIO_MEM_DATA13              JZ_GPIO_PORTA(13)
+#define JZ_GPIO_MEM_DATA14              JZ_GPIO_PORTA(14)
+#define JZ_GPIO_MEM_DATA15              JZ_GPIO_PORTA(15)
+#define JZ_GPIO_MEM_DATA16              JZ_GPIO_PORTA(16)
+#define JZ_GPIO_MEM_DATA17              JZ_GPIO_PORTA(17)
+#define JZ_GPIO_MEM_DATA18              JZ_GPIO_PORTA(18)
+#define JZ_GPIO_MEM_DATA19              JZ_GPIO_PORTA(19)
+#define JZ_GPIO_MEM_DATA20              JZ_GPIO_PORTA(20)
+#define JZ_GPIO_MEM_DATA21              JZ_GPIO_PORTA(21)
+#define JZ_GPIO_MEM_DATA22              JZ_GPIO_PORTA(22)
+#define JZ_GPIO_MEM_DATA23              JZ_GPIO_PORTA(23)
+#define JZ_GPIO_MEM_DATA24              JZ_GPIO_PORTA(24)
+#define JZ_GPIO_MEM_DATA25              JZ_GPIO_PORTA(25)
+#define JZ_GPIO_MEM_DATA26              JZ_GPIO_PORTA(26)
+#define JZ_GPIO_MEM_DATA27              JZ_GPIO_PORTA(27)
+#define JZ_GPIO_MEM_DATA28              JZ_GPIO_PORTA(28)
+#define JZ_GPIO_MEM_DATA29              JZ_GPIO_PORTA(29)
+#define JZ_GPIO_MEM_DATA30              JZ_GPIO_PORTA(30)
+#define JZ_GPIO_MEM_DATA31              JZ_GPIO_PORTA(31)
+
+#define JZ_GPIO_FUNC_MEM_DATA0          JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA1          JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA2          JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA3          JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA4          JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA5          JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA6          JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA7          JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA8          JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA9          JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA10         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA11         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA12         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA13         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA14         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA15         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA16         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA17         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA18         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA19         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA20         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA21         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA22         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA23         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA24         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA25         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA26         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA27         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA28         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA29         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA30         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA31         JZ_GPIO_FUNC1
+
+/* Port B function pins */
+#define JZ_GPIO_MEM_ADDR0               JZ_GPIO_PORTB(0)
+#define JZ_GPIO_MEM_ADDR1               JZ_GPIO_PORTB(1)
+#define JZ_GPIO_MEM_ADDR2               JZ_GPIO_PORTB(2)
+#define JZ_GPIO_MEM_ADDR3               JZ_GPIO_PORTB(3)
+#define JZ_GPIO_MEM_ADDR4               JZ_GPIO_PORTB(4)
+#define JZ_GPIO_MEM_ADDR5               JZ_GPIO_PORTB(5)
+#define JZ_GPIO_MEM_ADDR6               JZ_GPIO_PORTB(6)
+#define JZ_GPIO_MEM_ADDR7               JZ_GPIO_PORTB(7)
+#define JZ_GPIO_MEM_ADDR8               JZ_GPIO_PORTB(8)
+#define JZ_GPIO_MEM_ADDR9               JZ_GPIO_PORTB(9)
+#define JZ_GPIO_MEM_ADDR10              JZ_GPIO_PORTB(10)
+#define JZ_GPIO_MEM_ADDR11              JZ_GPIO_PORTB(11)
+#define JZ_GPIO_MEM_ADDR12              JZ_GPIO_PORTB(12)
+#define JZ_GPIO_MEM_ADDR13              JZ_GPIO_PORTB(13)
+#define JZ_GPIO_MEM_ADDR14              JZ_GPIO_PORTB(14)
+#define JZ_GPIO_MEM_ADDR15              JZ_GPIO_PORTB(15)
+#define JZ_GPIO_MEM_ADDR16              JZ_GPIO_PORTB(16)
+#define JZ_GPIO_LCD_CLS                 JZ_GPIO_PORTB(17)
+#define JZ_GPIO_LCD_SPL                 JZ_GPIO_PORTB(18)
+#define JZ_GPIO_MEM_DCS                 JZ_GPIO_PORTB(19)
+#define JZ_GPIO_MEM_RAS                 JZ_GPIO_PORTB(20)
+#define JZ_GPIO_MEM_CAS                 JZ_GPIO_PORTB(21)
+#define JZ_GPIO_MEM_SDWE                JZ_GPIO_PORTB(22)
+#define JZ_GPIO_MEM_CKE                 JZ_GPIO_PORTB(23)
+#define JZ_GPIO_MEM_CKO                 JZ_GPIO_PORTB(24)
+#define JZ_GPIO_MEM_CS0                 JZ_GPIO_PORTB(25)
+#define JZ_GPIO_MEM_CS1                 JZ_GPIO_PORTB(26)
+#define JZ_GPIO_MEM_CS2                 JZ_GPIO_PORTB(27)
+#define JZ_GPIO_MEM_CS3                 JZ_GPIO_PORTB(28)
+#define JZ_GPIO_MEM_RD                  JZ_GPIO_PORTB(29)
+#define JZ_GPIO_MEM_WR                  JZ_GPIO_PORTB(30)
+#define JZ_GPIO_MEM_WE0                 JZ_GPIO_PORTB(31)
+
+#define JZ_GPIO_FUNC_MEM_ADDR0          JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_ADDR1          JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_ADDR2          JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_ADDR3          JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_ADDR4          JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_ADDR5          JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_ADDR6          JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_ADDR7          JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_ADDR8          JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_ADDR9          JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_ADDR10         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_ADDR11         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_ADDR12         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_ADDR13         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_ADDR14         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_ADDR15         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_ADDR16         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_LCD_CLS            JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_LCD_SPL            JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DCS            JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_RAS            JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_CAS            JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_SDWE           JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_CKE            JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_CKO            JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_CS0            JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_CS1            JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_CS2            JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_CS3            JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_RD             JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_WR             JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_WE0            JZ_GPIO_FUNC1
+
+
+#define JZ_GPIO_MEM_ADDR21              JZ_GPIO_PORTB(17)
+#define JZ_GPIO_MEM_ADDR22              JZ_GPIO_PORTB(18)
+
+#define JZ_GPIO_FUNC_MEM_ADDR21         JZ_GPIO_FUNC2
+#define JZ_GPIO_FUNC_MEM_ADDR22         JZ_GPIO_FUNC2
+
+/* Port C function pins */
+#define JZ_GPIO_LCD_DATA0               JZ_GPIO_PORTC(0)
+#define JZ_GPIO_LCD_DATA1               JZ_GPIO_PORTC(1)
+#define JZ_GPIO_LCD_DATA2               JZ_GPIO_PORTC(2)
+#define JZ_GPIO_LCD_DATA3               JZ_GPIO_PORTC(3)
+#define JZ_GPIO_LCD_DATA4               JZ_GPIO_PORTC(4)
+#define JZ_GPIO_LCD_DATA5               JZ_GPIO_PORTC(5)
+#define JZ_GPIO_LCD_DATA6               JZ_GPIO_PORTC(6)
+#define JZ_GPIO_LCD_DATA7               JZ_GPIO_PORTC(7)
+#define JZ_GPIO_LCD_DATA8               JZ_GPIO_PORTC(8)
+#define JZ_GPIO_LCD_DATA9               JZ_GPIO_PORTC(9)
+#define JZ_GPIO_LCD_DATA10              JZ_GPIO_PORTC(10)
+#define JZ_GPIO_LCD_DATA11              JZ_GPIO_PORTC(11)
+#define JZ_GPIO_LCD_DATA12              JZ_GPIO_PORTC(12)
+#define JZ_GPIO_LCD_DATA13              JZ_GPIO_PORTC(13)
+#define JZ_GPIO_LCD_DATA14              JZ_GPIO_PORTC(14)
+#define JZ_GPIO_LCD_DATA15              JZ_GPIO_PORTC(15)
+#define JZ_GPIO_LCD_DATA16              JZ_GPIO_PORTC(16)
+#define JZ_GPIO_LCD_DATA17              JZ_GPIO_PORTC(17)
+#define JZ_GPIO_LCD_PCLK                JZ_GPIO_PORTC(18)
+#define JZ_GPIO_LCD_HSYNC               JZ_GPIO_PORTC(19)
+#define JZ_GPIO_LCD_VSYNC               JZ_GPIO_PORTC(20)
+#define JZ_GPIO_LCD_DE                  JZ_GPIO_PORTC(21)
+#define JZ_GPIO_LCD_PS                  JZ_GPIO_PORTC(22)
+#define JZ_GPIO_LCD_REV                 JZ_GPIO_PORTC(23)
+#define JZ_GPIO_MEM_WE1                 JZ_GPIO_PORTC(24)
+#define JZ_GPIO_MEM_WE2                 JZ_GPIO_PORTC(25)
+#define JZ_GPIO_MEM_WE3                 JZ_GPIO_PORTC(26)
+#define JZ_GPIO_MEM_WAIT                JZ_GPIO_PORTC(27)
+#define JZ_GPIO_MEM_FRE                 JZ_GPIO_PORTC(28)
+#define JZ_GPIO_MEM_FWE                 JZ_GPIO_PORTC(29)
+
+#define JZ_GPIO_FUNC_LCD_DATA0          JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_LCD_DATA1          JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_LCD_DATA2          JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_LCD_DATA3          JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_LCD_DATA4          JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_LCD_DATA5          JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_LCD_DATA6          JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_LCD_DATA7          JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_LCD_DATA8          JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_LCD_DATA9          JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_LCD_DATA10         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_LCD_DATA11         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_LCD_DATA12         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_LCD_DATA13         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_LCD_DATA14         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_LCD_DATA15         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_LCD_DATA16         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_LCD_DATA17         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_LCD_PCLK           JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_LCD_VSYNC          JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_LCD_HSYNC          JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_LCD_DE             JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_LCD_PS             JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_LCD_REV            JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_WE1            JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_WE2            JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_WE3            JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_WAIT           JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_FRE            JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_FWE            JZ_GPIO_FUNC1
+
+
+#define JZ_GPIO_MEM_ADDR19              JZ_GPIO_PORTB(22)
+#define JZ_GPIO_MEM_ADDR20              JZ_GPIO_PORTB(23)
+
+#define JZ_GPIO_FUNC_MEM_ADDR19         JZ_GPIO_FUNC2
+#define JZ_GPIO_FUNC_MEM_ADDR20         JZ_GPIO_FUNC2
+
+/* Port D function pins */
+#define JZ_GPIO_CIM_DATA0               JZ_GPIO_PORTD(0)
+#define JZ_GPIO_CIM_DATA1               JZ_GPIO_PORTD(1)
+#define JZ_GPIO_CIM_DATA2               JZ_GPIO_PORTD(2)
+#define JZ_GPIO_CIM_DATA3               JZ_GPIO_PORTD(3)
+#define JZ_GPIO_CIM_DATA4               JZ_GPIO_PORTD(4)
+#define JZ_GPIO_CIM_DATA5               JZ_GPIO_PORTD(5)
+#define JZ_GPIO_CIM_DATA6               JZ_GPIO_PORTD(6)
+#define JZ_GPIO_CIM_DATA7               JZ_GPIO_PORTD(7)
+#define JZ_GPIO_MSC_CMD                 JZ_GPIO_PORTD(8)
+#define JZ_GPIO_MSC_CLK                 JZ_GPIO_PORTD(9)
+#define JZ_GPIO_MSC_DATA0               JZ_GPIO_PORTD(10)
+#define JZ_GPIO_MSC_DATA1               JZ_GPIO_PORTD(11)
+#define JZ_GPIO_MSC_DATA2               JZ_GPIO_PORTD(12)
+#define JZ_GPIO_MSC_DATA3               JZ_GPIO_PORTD(13)
+#define JZ_GPIO_CIM_MCLK                JZ_GPIO_PORTD(14)
+#define JZ_GPIO_CIM_PCLK                JZ_GPIO_PORTD(15)
+#define JZ_GPIO_CIM_VSYNC               JZ_GPIO_PORTD(16)
+#define JZ_GPIO_CIM_HSYNC               JZ_GPIO_PORTD(17)
+#define JZ_GPIO_SPI_CLK                 JZ_GPIO_PORTD(18)
+#define JZ_GPIO_SPI_CE0                 JZ_GPIO_PORTD(19)
+#define JZ_GPIO_SPI_DT                  JZ_GPIO_PORTD(20)
+#define JZ_GPIO_SPI_DR                  JZ_GPIO_PORTD(21)
+#define JZ_GPIO_SPI_CE1                 JZ_GPIO_PORTD(22)
+#define JZ_GPIO_PWM0                    JZ_GPIO_PORTD(23)
+#define JZ_GPIO_PWM1                    JZ_GPIO_PORTD(24)
+#define JZ_GPIO_PWM2                    JZ_GPIO_PORTD(25)
+#define JZ_GPIO_PWM3                    JZ_GPIO_PORTD(26)
+#define JZ_GPIO_PWM4                    JZ_GPIO_PORTD(27)
+#define JZ_GPIO_PWM5                    JZ_GPIO_PORTD(28)
+#define JZ_GPIO_PWM6                    JZ_GPIO_PORTD(30)
+#define JZ_GPIO_PWM7                    JZ_GPIO_PORTD(31)
+
+#define JZ_GPIO_FUNC_CIM_DATA           JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_CIM_DATA0          JZ_GPIO_FUNC_CIM_DATA
+#define JZ_GPIO_FUNC_CIM_DATA1          JZ_GPIO_FUNC_CIM_DATA
+#define JZ_GPIO_FUNC_CIM_DATA2          JZ_GPIO_FUNC_CIM_DATA
+#define JZ_GPIO_FUNC_CIM_DATA3          JZ_GPIO_FUNC_CIM_DATA
+#define JZ_GPIO_FUNC_CIM_DATA4          JZ_GPIO_FUNC_CIM_DATA
+#define JZ_GPIO_FUNC_CIM_DATA5          JZ_GPIO_FUNC_CIM_DATA
+#define JZ_GPIO_FUNC_CIM_DATA6          JZ_GPIO_FUNC_CIM_DATA
+#define JZ_GPIO_FUNC_CIM_DATA7          JZ_GPIO_FUNC_CIM_DATA
+#define JZ_GPIO_FUNC_MSC_CMD            JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MSC_CLK            JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MSC_DATA           JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MSC_DATA0          JZ_GPIO_FUNC_MSC_DATA
+#define JZ_GPIO_FUNC_MSC_DATA1          JZ_GPIO_FUNC_MSC_DATA
+#define JZ_GPIO_FUNC_MSC_DATA2          JZ_GPIO_FUNC_MSC_DATA
+#define JZ_GPIO_FUNC_MSC_DATA3          JZ_GPIO_FUNC_MSC_DATA
+#define JZ_GPIO_FUNC_CIM_MCLK           JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_CIM_PCLK           JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_CIM_VSYNC          JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_CIM_HSYNC          JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_SPI_CLK            JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_SPI_CE0            JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_SPI_DT             JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_SPI_DR             JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_SPI_CE1            JZ_GPIO_FUNC1
+
+#define JZ_GPIO_FUNC_PWM                JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_PWM0               JZ_GPIO_FUNC_PWM
+#define JZ_GPIO_FUNC_PWM1               JZ_GPIO_FUNC_PWM
+#define JZ_GPIO_FUNC_PWM2               JZ_GPIO_FUNC_PWM
+#define JZ_GPIO_FUNC_PWM3               JZ_GPIO_FUNC_PWM
+#define JZ_GPIO_FUNC_PWM4               JZ_GPIO_FUNC_PWM
+#define JZ_GPIO_FUNC_PWM5               JZ_GPIO_FUNC_PWM
+#define JZ_GPIO_FUNC_PWM6               JZ_GPIO_FUNC_PWM
+#define JZ_GPIO_FUNC_PWM7               JZ_GPIO_FUNC_PWM
+
+#define JZ_GPIO_MEM_SCLK_RSTN           JZ_GPIO_PORTD(18)
+#define JZ_GPIO_MEM_BCLK                JZ_GPIO_PORTD(19)
+#define JZ_GPIO_MEM_SDATO               JZ_GPIO_PORTD(20)
+#define JZ_GPIO_MEM_SDATI               JZ_GPIO_PORTD(21)
+#define JZ_GPIO_MEM_SYNC                JZ_GPIO_PORTD(22)
+#define JZ_GPIO_I2C_SDA                 JZ_GPIO_PORTD(23)
+#define JZ_GPIO_I2C_SCK                 JZ_GPIO_PORTD(24)
+#define JZ_GPIO_UART0_TXD               JZ_GPIO_PORTD(25)
+#define JZ_GPIO_UART0_RXD               JZ_GPIO_PORTD(26)
+#define JZ_GPIO_MEM_ADDR17              JZ_GPIO_PORTD(27)
+#define JZ_GPIO_MEM_ADDR18              JZ_GPIO_PORTD(28)
+#define JZ_GPIO_UART0_CTS               JZ_GPIO_PORTD(30)
+#define JZ_GPIO_UART0_RTS               JZ_GPIO_PORTD(31)
+
+#define JZ_GPIO_FUNC_MEM_SCLK_RSTN      JZ_GPIO_FUNC2
+#define JZ_GPIO_FUNC_MEM_BCLK           JZ_GPIO_FUNC2
+#define JZ_GPIO_FUNC_MEM_SDATO          JZ_GPIO_FUNC2
+#define JZ_GPIO_FUNC_MEM_SDATI          JZ_GPIO_FUNC2
+#define JZ_GPIO_FUNC_MEM_SYNC           JZ_GPIO_FUNC2
+#define JZ_GPIO_FUNC_I2C_SDA            JZ_GPIO_FUNC2
+#define JZ_GPIO_FUNC_I2C_SCK            JZ_GPIO_FUNC2
+#define JZ_GPIO_FUNC_UART0_TXD          JZ_GPIO_FUNC2
+#define JZ_GPIO_FUNC_UART0_RXD          JZ_GPIO_FUNC2
+#define JZ_GPIO_FUNC_MEM_ADDR17         JZ_GPIO_FUNC2
+#define JZ_GPIO_FUNC_MEM_ADDR18         JZ_GPIO_FUNC2
+#define JZ_GPIO_FUNC_UART0_CTS          JZ_GPIO_FUNC2
+#define JZ_GPIO_FUNC_UART0_RTS          JZ_GPIO_FUNC2
+
+#define JZ_GPIO_UART1_RXD               JZ_GPIO_PORTD(30)
+#define JZ_GPIO_UART1_TXD               JZ_GPIO_PORTD(31)
+
+#define JZ_GPIO_FUNC_UART1_RXD          JZ_GPIO_FUNC3
+#define JZ_GPIO_FUNC_UART1_TXD          JZ_GPIO_FUNC3
+
+#endif
diff --git a/arch/mips/include/asm/mach-jz4740/irq.h b/arch/mips/include/asm/mach-jz4740/irq.h
new file mode 100644
index 000000000000..a865c983c70a
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4740/irq.h
@@ -0,0 +1,57 @@
+/*
+ *  Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
+ *  JZ4740 IRQ definitions
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under  the terms of the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the License, or (at your
+ *  option) any later version.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#ifndef __ASM_MACH_JZ4740_IRQ_H__
+#define __ASM_MACH_JZ4740_IRQ_H__
+
+#define MIPS_CPU_IRQ_BASE 0
+#define JZ4740_IRQ_BASE 8
+
+/* 1st-level interrupts */
+#define JZ4740_IRQ(x)           (JZ4740_IRQ_BASE + (x))
+#define JZ4740_IRQ_I2C          JZ4740_IRQ(1)
+#define JZ4740_IRQ_UHC          JZ4740_IRQ(3)
+#define JZ4740_IRQ_UART1        JZ4740_IRQ(8)
+#define JZ4740_IRQ_UART0        JZ4740_IRQ(9)
+#define JZ4740_IRQ_SADC         JZ4740_IRQ(12)
+#define JZ4740_IRQ_MSC          JZ4740_IRQ(14)
+#define JZ4740_IRQ_RTC          JZ4740_IRQ(15)
+#define JZ4740_IRQ_SSI          JZ4740_IRQ(16)
+#define JZ4740_IRQ_CIM          JZ4740_IRQ(17)
+#define JZ4740_IRQ_AIC          JZ4740_IRQ(18)
+#define JZ4740_IRQ_ETH          JZ4740_IRQ(19)
+#define JZ4740_IRQ_DMAC         JZ4740_IRQ(20)
+#define JZ4740_IRQ_TCU2         JZ4740_IRQ(21)
+#define JZ4740_IRQ_TCU1         JZ4740_IRQ(22)
+#define JZ4740_IRQ_TCU0         JZ4740_IRQ(23)
+#define JZ4740_IRQ_UDC          JZ4740_IRQ(24)
+#define JZ4740_IRQ_GPIO3        JZ4740_IRQ(25)
+#define JZ4740_IRQ_GPIO2        JZ4740_IRQ(26)
+#define JZ4740_IRQ_GPIO1        JZ4740_IRQ(27)
+#define JZ4740_IRQ_GPIO0        JZ4740_IRQ(28)
+#define JZ4740_IRQ_IPU          JZ4740_IRQ(29)
+#define JZ4740_IRQ_LCD          JZ4740_IRQ(30)
+
+/* 2nd-level interrupts */
+#define JZ4740_IRQ_DMA(x)       (JZ4740_IRQ(32) + (X))
+
+#define JZ4740_IRQ_INTC_GPIO(x) (JZ4740_IRQ_GPIO0 - (x))
+#define JZ4740_IRQ_GPIO(x)      (JZ4740_IRQ(48) + (x))
+
+#define JZ4740_IRQ_ADC_BASE     JZ4740_IRQ(176)
+
+#define NR_IRQS (JZ4740_IRQ_ADC_BASE + 6)
+
+#endif
diff --git a/arch/mips/include/asm/mach-jz4740/jz4740_fb.h b/arch/mips/include/asm/mach-jz4740/jz4740_fb.h
new file mode 100644
index 000000000000..6a50e6f7a21a
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4740/jz4740_fb.h
@@ -0,0 +1,67 @@
+/*
+ *  Copyright (C) 2009, Lars-Peter Clausen <lars@metafoo.de>
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#ifndef __ASM_MACH_JZ4740_JZ4740_FB_H__
+#define __ASM_MACH_JZ4740_JZ4740_FB_H__
+
+#include <linux/fb.h>
+
+enum jz4740_fb_lcd_type {
+        JZ_LCD_TYPE_GENERIC_16_BIT = 0,
+        JZ_LCD_TYPE_GENERIC_18_BIT = 0 | (1 << 4),
+        JZ_LCD_TYPE_SPECIAL_TFT_1 = 1,
+        JZ_LCD_TYPE_SPECIAL_TFT_2 = 2,
+        JZ_LCD_TYPE_SPECIAL_TFT_3 = 3,
+        JZ_LCD_TYPE_NON_INTERLACED_CCIR656 = 5,
+        JZ_LCD_TYPE_INTERLACED_CCIR656 = 7,
+        JZ_LCD_TYPE_SINGLE_COLOR_STN = 8,
+        JZ_LCD_TYPE_SINGLE_MONOCHROME_STN = 9,
+        JZ_LCD_TYPE_DUAL_COLOR_STN = 10,
+        JZ_LCD_TYPE_DUAL_MONOCHROME_STN = 11,
+        JZ_LCD_TYPE_8BIT_SERIAL = 12,
+};
+
+#define JZ4740_FB_SPECIAL_TFT_CONFIG(start, stop) (((start) << 16) | (stop))
+
+/*
+* width: width of the lcd display in mm
+* height: height of the lcd display in mm
+* num_modes: size of modes
+* modes: list of valid video modes
+* bpp: bits per pixel for the lcd
+* lcd_type: lcd type
+*/
+
+struct jz4740_fb_platform_data {
+        unsigned int width;
+        unsigned int height;
+
+        size_t num_modes;
+        struct fb_videomode *modes;
+
+        unsigned int bpp;
+        enum jz4740_fb_lcd_type lcd_type;
+
+        struct {
+                uint32_t spl;
+                uint32_t cls;
+                uint32_t ps;
+                uint32_t rev;
+        } special_tft_config;
+
+        unsigned pixclk_falling_edge:1;
+        unsigned date_enable_active_low:1;
+};
+
+#endif
diff --git a/arch/mips/include/asm/mach-jz4740/jz4740_mmc.h b/arch/mips/include/asm/mach-jz4740/jz4740_mmc.h
new file mode 100644
index 000000000000..8543f432b4b3
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4740/jz4740_mmc.h
@@ -0,0 +1,15 @@
+#ifndef __LINUX_MMC_JZ4740_MMC
+#define __LINUX_MMC_JZ4740_MMC
+
+struct jz4740_mmc_platform_data {
+        int gpio_power;
+        int gpio_card_detect;
+        int gpio_read_only;
+        unsigned card_detect_active_low:1;
+        unsigned read_only_active_low:1;
+        unsigned power_active_low:1;
+
+        unsigned data_1bit:1;
+};
+
+#endif
diff --git a/arch/mips/include/asm/mach-jz4740/jz4740_nand.h b/arch/mips/include/asm/mach-jz4740/jz4740_nand.h
new file mode 100644
index 000000000000..bb5b9a4e29c8
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4740/jz4740_nand.h
@@ -0,0 +1,34 @@
+/*
+ *  Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
+ *  JZ4740 SoC NAND controller driver
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#ifndef __ASM_MACH_JZ4740_JZ4740_NAND_H__
+#define __ASM_MACH_JZ4740_JZ4740_NAND_H__
+
+#include <linux/mtd/nand.h>
+#include <linux/mtd/partitions.h>
+
+struct jz_nand_platform_data {
+        int                     num_partitions;
+        struct mtd_partition    *partitions;
+
+        struct nand_ecclayout   *ecc_layout;
+
+        unsigned int busy_gpio;
+
+        void (*ident_callback)(struct platform_device *, struct nand_chip *,
+                                struct mtd_partition **, int *num_partitions);
+};
+
+#endif
diff --git a/arch/mips/include/asm/mach-jz4740/platform.h b/arch/mips/include/asm/mach-jz4740/platform.h
new file mode 100644
index 000000000000..8987a76e9676
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4740/platform.h
@@ -0,0 +1,36 @@
+/*
+ *  Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
+ *  JZ4740 platform device definitions
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under  the terms of the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the License, or (at your
+ *  option) any later version.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+
+#ifndef __JZ4740_PLATFORM_H
+#define __JZ4740_PLATFORM_H
+
+#include <linux/platform_device.h>
+
+extern struct platform_device jz4740_usb_ohci_device;
+extern struct platform_device jz4740_udc_device;
+extern struct platform_device jz4740_mmc_device;
+extern struct platform_device jz4740_rtc_device;
+extern struct platform_device jz4740_i2c_device;
+extern struct platform_device jz4740_nand_device;
+extern struct platform_device jz4740_framebuffer_device;
+extern struct platform_device jz4740_i2s_device;
+extern struct platform_device jz4740_pcm_device;
+extern struct platform_device jz4740_codec_device;
+extern struct platform_device jz4740_adc_device;
+
+void jz4740_serial_device_register(void);
+
+#endif
diff --git a/arch/mips/include/asm/mach-jz4740/timer.h b/arch/mips/include/asm/mach-jz4740/timer.h
new file mode 100644
index 000000000000..9baa03ce748c
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4740/timer.h
@@ -0,0 +1,22 @@
+/*
+ *  Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
+ *  JZ4740 platform timer support
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under  the terms of the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the License, or (at your
+ *  option) any later version.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#ifndef __ASM_MACH_JZ4740_TIMER
+#define __ASM_MACH_JZ4740_TIMER
+
+void jz4740_timer_enable_watchdog(void);
+void jz4740_timer_disable_watchdog(void);
+
+#endif
diff --git a/arch/mips/include/asm/mach-jz4740/war.h b/arch/mips/include/asm/mach-jz4740/war.h
new file mode 100644
index 000000000000..3a5bc17e28fe
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4740/war.h
@@ -0,0 +1,25 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
+ */
+#ifndef __ASM_MIPS_MACH_JZ4740_WAR_H
+#define __ASM_MIPS_MACH_JZ4740_WAR_H
+
+#define R4600_V1_INDEX_ICACHEOP_WAR     0
+#define R4600_V1_HIT_CACHEOP_WAR        0
+#define R4600_V2_HIT_CACHEOP_WAR        0
+#define R5432_CP0_INTERRUPT_WAR         0
+#define BCM1250_M3_WAR                  0
+#define SIBYTE_1956_WAR                 0
+#define MIPS4K_ICACHE_REFILL_WAR        0
+#define MIPS_CACHE_SYNC_WAR             0
+#define TX49XX_ICACHE_INDEX_INV_WAR     0
+#define RM9000_CDEX_SMP_WAR             0
+#define ICACHE_REFILLS_WORKAROUND_WAR   0
+#define R10000_LLSC_WAR                 0
+#define MIPS34K_MISSED_ITLB_WAR         0
+
+#endif /* __ASM_MIPS_MACH_JZ4740_WAR_H */
diff --git a/arch/mips/include/asm/mach-loongson/loongson.h b/arch/mips/include/asm/mach-loongson/loongson.h
index fcdbe3a4ce1f..cb6985f24303 100644
--- a/arch/mips/include/asm/mach-loongson/loongson.h
+++ b/arch/mips/include/asm/mach-loongson/loongson.h
@@ -45,7 +45,6 @@ static inline void prom_init_uart_base(void)
 /* irq operation functions */
 extern void bonito_irqdispatch(void);
 extern void __init bonito_irq_init(void);
-extern void __init set_irq_trigger_mode(void);
 extern void __init mach_init_irq(void);
 extern void mach_irq_dispatch(unsigned int pending);
 extern int mach_i8259_irq(void);
@@ -63,6 +62,14 @@ extern int mach_i8259_irq(void);
 #define LOONGSON_IRQ_BASE       32
 #define LOONGSON2_PERFCNT_IRQ   (MIPS_CPU_IRQ_BASE + 6) /* cpu perf counter */
 
+#include <linux/interrupt.h>
+static inline void do_perfcnt_IRQ(void)
+{
+#if defined(CONFIG_OPROFILE) || defined(CONFIG_OPROFILE_MODULE)
+        do_IRQ(LOONGSON2_PERFCNT_IRQ);
+#endif
+}
+
 #define LOONGSON_FLASH_BASE     0x1c000000
 #define LOONGSON_FLASH_SIZE     0x02000000      /* 32M */
 #define LOONGSON_FLASH_TOP      (LOONGSON_FLASH_BASE+LOONGSON_FLASH_SIZE-1)
diff --git a/arch/mips/include/asm/mach-pb1x00/pb1550.h b/arch/mips/include/asm/mach-pb1x00/pb1550.h
index 58796410bd6e..fc4d766641ce 100644
--- a/arch/mips/include/asm/mach-pb1x00/pb1550.h
+++ b/arch/mips/include/asm/mach-pb1x00/pb1550.h
@@ -40,14 +40,6 @@
 #define SMBUS_PSC_BASE          PSC2_BASE_ADDR
 #define I2S_PSC_BASE            PSC3_BASE_ADDR
 
-#if defined(CONFIG_MTD_PB1550_BOOT) && defined(CONFIG_MTD_PB1550_USER)
-#define PB1550_BOTH_BANKS
-#elif defined(CONFIG_MTD_PB1550_BOOT) && !defined(CONFIG_MTD_PB1550_USER)
-#define PB1550_BOOT_ONLY
-#elif !defined(CONFIG_MTD_PB1550_BOOT) && defined(CONFIG_MTD_PB1550_USER)
-#define PB1550_USER_ONLY
-#endif
-
 /*
  * Timing values as described in databook, * ns value stripped of
  * lower 2 bits.
diff --git a/arch/mips/include/asm/mach-powertv/asic.h b/arch/mips/include/asm/mach-powertv/asic.h
index bcad43a93ebf..c7077a64b9a7 100644
--- a/arch/mips/include/asm/mach-powertv/asic.h
+++ b/arch/mips/include/asm/mach-powertv/asic.h
@@ -20,6 +20,7 @@
 #define _ASM_MACH_POWERTV_ASIC_H
 
 #include <linux/ioport.h>
+#include <linux/platform_device.h>
 #include <asm/mach-powertv/asic_regs.h>
 
 #define DVR_CAPABLE     (1<<0)
@@ -40,19 +41,23 @@ enum family_type {
         FAMILY_8600VZB,
         FAMILY_1500VZE,
         FAMILY_1500VZF,
+        FAMILY_8700,
         FAMILIES
 };
 
 /* Register maps for each ASIC */
 extern const struct register_map calliope_register_map;
 extern const struct register_map cronus_register_map;
+extern const struct register_map gaia_register_map;
 extern const struct register_map zeus_register_map;
 
 extern struct resource dvr_cronus_resources[];
+extern struct resource dvr_gaia_resources[];
 extern struct resource dvr_zeus_resources[];
 extern struct resource non_dvr_calliope_resources[];
 extern struct resource non_dvr_cronus_resources[];
 extern struct resource non_dvr_cronuslite_resources[];
+extern struct resource non_dvr_gaia_resources[];
 extern struct resource non_dvr_vz_calliope_resources[];
 extern struct resource non_dvr_vze_calliope_resources[];
 extern struct resource non_dvr_vzf_calliope_resources[];
@@ -67,16 +72,24 @@ extern int platform_supports_ffs(void);
 extern int platform_supports_pcie(void);
 extern int platform_supports_display(void);
 extern void configure_platform(void);
-extern void platform_configure_usb_ehci(void);
-extern void platform_unconfigure_usb_ehci(void);
-extern void platform_configure_usb_ohci(void);
-extern void platform_unconfigure_usb_ohci(void);
 
 /* Platform Resources */
 #define ASIC_RESOURCE_GET_EXISTS 1
 extern struct resource *asic_resource_get(const char *name);
 extern void platform_release_memory(void *baddr, int size);
 
+/* USB configuration */
+struct usb_hcd;                 /* Forward reference */
+extern void platform_configure_usb_ehci(void);
+extern void platform_unconfigure_usb_ehci(void);
+extern void platform_configure_usb_ohci(void);
+extern void platform_unconfigure_usb_ohci(void);
+
+/* Resource for ASIC registers */
+extern struct resource asic_resource;
+extern int platform_usb_devices_init(struct platform_device **echi_dev,
+        struct platform_device **ohci_dev);
+
 /* Reboot Cause */
 extern void set_reboot_cause(char code, unsigned int data, unsigned int data2);
 extern void set_locked_reboot_cause(char code, unsigned int data,
diff --git a/arch/mips/include/asm/mach-powertv/asic_reg_map.h b/arch/mips/include/asm/mach-powertv/asic_reg_map.h
index 6f26cb09828e..20348e817b09 100644
--- a/arch/mips/include/asm/mach-powertv/asic_reg_map.h
+++ b/arch/mips/include/asm/mach-powertv/asic_reg_map.h
@@ -64,7 +64,7 @@ REGISTER_MAP_ELEMENT(int_level_0_1)
 REGISTER_MAP_ELEMENT(int_level_0_0)
 REGISTER_MAP_ELEMENT(int_docsis_en)
 REGISTER_MAP_ELEMENT(mips_pll_setup)
-REGISTER_MAP_ELEMENT(usb_fs)
+REGISTER_MAP_ELEMENT(fs432x4b4_usb_ctl)
 REGISTER_MAP_ELEMENT(test_bus)
 REGISTER_MAP_ELEMENT(crt_spare)
 REGISTER_MAP_ELEMENT(usb2_ohci_int_mask)
diff --git a/arch/mips/include/asm/mach-powertv/asic_regs.h b/arch/mips/include/asm/mach-powertv/asic_regs.h
index 1e11236c6dbc..deecb26a077e 100644
--- a/arch/mips/include/asm/mach-powertv/asic_regs.h
+++ b/arch/mips/include/asm/mach-powertv/asic_regs.h
@@ -27,7 +27,8 @@ enum asic_type {
         ASIC_CALLIOPE,
         ASIC_CRONUS,
         ASIC_CRONUSLITE,
-        ASICS
+        ASIC_GAIA,
+        ASICS                   /* Number of supported ASICs */
 };
 
 /* hardcoded values read from Chip Version registers */
@@ -37,6 +38,7 @@ enum asic_type {
 
 #define NAND_FLASH_BASE         0x03000000
 #define CALLIOPE_IO_BASE        0x08000000
+#define GAIA_IO_BASE            0x09000000
 #define CRONUS_IO_BASE          0x09000000
 #define ZEUS_IO_BASE            0x09000000
 
@@ -99,6 +101,7 @@ static inline void register_map_virtualize(struct register_map *map)
 }
 
 extern struct register_map _asic_register_map;
+extern unsigned long asic_phy_base;
 
 /*
  * Macros to interface to registers through their ioremapped address
diff --git a/arch/mips/include/asm/mach-powertv/dma-coherence.h b/arch/mips/include/asm/mach-powertv/dma-coherence.h
index 5b8d5ebeb838..f76029c2406e 100644
--- a/arch/mips/include/asm/mach-powertv/dma-coherence.h
+++ b/arch/mips/include/asm/mach-powertv/dma-coherence.h
@@ -65,21 +65,21 @@ static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr,
         size_t size)
 {
         if (is_kseg2(addr))
-                return phys_to_bus(virt_to_phys_from_pte(addr));
+                return phys_to_dma(virt_to_phys_from_pte(addr));
         else
-                return phys_to_bus(virt_to_phys(addr));
+                return phys_to_dma(virt_to_phys(addr));
 }
 
 static inline dma_addr_t plat_map_dma_mem_page(struct device *dev,
         struct page *page)
 {
-        return phys_to_bus(page_to_phys(page));
+        return phys_to_dma(page_to_phys(page));
 }
 
 static inline unsigned long plat_dma_addr_to_phys(struct device *dev,
         dma_addr_t dma_addr)
 {
-        return bus_to_phys(dma_addr);
+        return dma_to_phys(dma_addr);
 }
 
 static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr,
diff --git a/arch/mips/include/asm/mach-powertv/ioremap.h b/arch/mips/include/asm/mach-powertv/ioremap.h
index e6276d5146e8..076f2eeaa575 100644
--- a/arch/mips/include/asm/mach-powertv/ioremap.h
+++ b/arch/mips/include/asm/mach-powertv/ioremap.h
@@ -10,64 +10,101 @@
 #define __ASM_MACH_POWERTV_IOREMAP_H
 
 #include <linux/types.h>
+#include <linux/log2.h>
+#include <linux/compiler.h>
 
-#define LOW_MEM_BOUNDARY_PHYS   0x20000000
-#define LOW_MEM_BOUNDARY_MASK   (~(LOW_MEM_BOUNDARY_PHYS - 1))
+#include <asm/pgtable-bits.h>
+#include <asm/addrspace.h>
+
+/* We're going to mess with bits, so get sizes */
+#define IOR_BPC                 8                       /* Bits per char */
+#define IOR_PHYS_BITS           (IOR_BPC * sizeof(phys_addr_t))
+#define IOR_DMA_BITS            (IOR_BPC * sizeof(dma_addr_t))
 
 /*
- * The bus addresses are different than the physical addresses that
- * the processor sees by an offset. This offset varies by ASIC
- * version. Define a variable to hold the offset and some macros to
- * make the conversion simpler. */
-extern unsigned long phys_to_bus_offset;
-
-#ifdef CONFIG_HIGHMEM
-#define MEM_GAP_PHYS            0x60000000
+ * Define the granularity of physical/DMA mapping in terms of the number
+ * of bits that defines the offset within a grain. These will be the
+ * least significant bits of the address. The rest of a physical or DMA
+ * address will be used to index into an appropriate table to find the
+ * offset to add to the address to yield the corresponding DMA or physical
+ * address, respectively.
+ */
+#define IOR_LSBITS              22                      /* Bits in a grain */
+
 /*
- * TODO: We will use the hard code for conversion between physical and
- * bus until the bootloader releases their device tree to us.
+ * Compute the number of most significant address bits after removing those
+ * used for the offset within a grain and then compute the number of table
+ * entries for the conversion.
  */
-#define phys_to_bus(x) (((x) < LOW_MEM_BOUNDARY_PHYS) ? \
-        ((x) + phys_to_bus_offset) : (x))
-#define bus_to_phys(x) (((x) < MEM_GAP_PHYS_ADDR) ? \
-        ((x) - phys_to_bus_offset) : (x))
-#else
-#define phys_to_bus(x) ((x) + phys_to_bus_offset)
-#define bus_to_phys(x) ((x) - phys_to_bus_offset)
-#endif
+#define IOR_PHYS_MSBITS         (IOR_PHYS_BITS - IOR_LSBITS)
+#define IOR_NUM_PHYS_TO_DMA     ((phys_addr_t) 1 << IOR_PHYS_MSBITS)
+
+#define IOR_DMA_MSBITS          (IOR_DMA_BITS - IOR_LSBITS)
+#define IOR_NUM_DMA_TO_PHYS     ((dma_addr_t) 1 << IOR_DMA_MSBITS)
 
 /*
- * Determine whether the address we are given is for an ASIC device
- * Params:  addr    Address to check
- * Returns: Zero if the address is not for ASIC devices, non-zero
- *      if it is.
+ * Define data structures used as elements in the arrays for the conversion
+ * between physical and DMA addresses. We do some slightly fancy math to
+ * compute the width of the offset element of the conversion tables so
+ * that we can have the smallest conversion tables. Next, round up the
+ * sizes to the next higher power of two, i.e. the offset element will have
+ * 8, 16, 32, 64, etc. bits. This eliminates the need to mask off any
+ * bits.  Finally, we compute a shift value that puts the most significant
+ * bits of the offset into the most significant bits of the offset element.
+ * This makes it more efficient on processors without barrel shifters and
+ * easier to see the values if the conversion table is dumped in binary.
  */
-static inline int asic_is_device_addr(phys_t addr)
+#define _IOR_OFFSET_WIDTH(n)    (1 << order_base_2(n))
+#define IOR_OFFSET_WIDTH(n) \
+        (_IOR_OFFSET_WIDTH(n) < 8 ? 8 : _IOR_OFFSET_WIDTH(n))
+
+#define IOR_PHYS_OFFSET_BITS    IOR_OFFSET_WIDTH(IOR_PHYS_MSBITS)
+#define IOR_PHYS_SHIFT          (IOR_PHYS_BITS - IOR_PHYS_OFFSET_BITS)
+
+#define IOR_DMA_OFFSET_BITS     IOR_OFFSET_WIDTH(IOR_DMA_MSBITS)
+#define IOR_DMA_SHIFT           (IOR_DMA_BITS - IOR_DMA_OFFSET_BITS)
+
+struct ior_phys_to_dma {
+        dma_addr_t offset:IOR_DMA_OFFSET_BITS __packed
+                __aligned((IOR_DMA_OFFSET_BITS / IOR_BPC));
+};
+
+struct ior_dma_to_phys {
+        dma_addr_t offset:IOR_PHYS_OFFSET_BITS __packed
+                __aligned((IOR_PHYS_OFFSET_BITS / IOR_BPC));
+};
+
+extern struct ior_phys_to_dma _ior_phys_to_dma[IOR_NUM_PHYS_TO_DMA];
+extern struct ior_dma_to_phys _ior_dma_to_phys[IOR_NUM_DMA_TO_PHYS];
+
+static inline dma_addr_t _phys_to_dma_offset_raw(phys_addr_t phys)
 {
-        return !((phys_t)addr & (phys_t) LOW_MEM_BOUNDARY_MASK);
+        return (dma_addr_t)_ior_phys_to_dma[phys >> IOR_LSBITS].offset;
 }
 
-/*
- * Determine whether the address we are given is external RAM mappable
- * into KSEG1.
- * Params:  addr    Address to check
- * Returns: Zero if the address is not for external RAM and
- */
-static inline int asic_is_lowmem_ram_addr(phys_t addr)
+static inline dma_addr_t _dma_to_phys_offset_raw(dma_addr_t dma)
 {
-        /*
-         * The RAM always starts at the following address in the processor's
-         * physical address space
-         */
-        static const phys_t phys_ram_base = 0x10000000;
-        phys_t bus_ram_base;
+        return (dma_addr_t)_ior_dma_to_phys[dma >> IOR_LSBITS].offset;
+}
 
-        bus_ram_base = phys_to_bus_offset + phys_ram_base;
+/* These are not portable and should not be used in drivers. Drivers should
+ * be using ioremap() and friends to map physical addreses to virtual
+ * addresses and dma_map*() and friends to map virtual addresses into DMA
+ * addresses and back.
+ */
+static inline dma_addr_t phys_to_dma(phys_addr_t phys)
+{
+        return phys + (_phys_to_dma_offset_raw(phys) << IOR_PHYS_SHIFT);
+}
 
-        return addr >= bus_ram_base &&
-                addr < (bus_ram_base + (LOW_MEM_BOUNDARY_PHYS - phys_ram_base));
+static inline phys_addr_t dma_to_phys(dma_addr_t dma)
+{
+        return dma + (_dma_to_phys_offset_raw(dma) << IOR_DMA_SHIFT);
 }
 
+extern void ioremap_add_map(dma_addr_t phys, phys_addr_t alias,
+        dma_addr_t size);
+
 /*
  * Allow physical addresses to be fixed up to help peripherals located
  * outside the low 32-bit range -- generic pass-through version.
@@ -77,10 +114,50 @@ static inline phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size)
         return phys_addr;
 }
 
-static inline void __iomem *plat_ioremap(phys_t offset, unsigned long size,
+/*
+ * Handle the special case of addresses the area aliased into the first
+ * 512 MiB of the processor's physical address space. These turn into either
+ * kseg0 or kseg1 addresses, depending on flags.
+ */
+static inline void __iomem *plat_ioremap(phys_t start, unsigned long size,
         unsigned long flags)
 {
-        return NULL;
+        phys_addr_t start_offset;
+        void __iomem *result = NULL;
+
+        /* Start by checking to see whether this is an aliased address */
+        start_offset = _dma_to_phys_offset_raw(start);
+
+        /*
+         * If:
+         * o    the memory is aliased into the first 512 MiB, and
+         * o    the start and end are in the same RAM bank, and
+         * o    we don't have a zero size or wrap around, and
+         * o    we are supposed to create an uncached mapping,
+         *      handle this is a kseg0 or kseg1 address
+         */
+        if (start_offset != 0) {
+                phys_addr_t last;
+                dma_addr_t dma_to_phys_offset;
+
+                last = start + size - 1;
+                dma_to_phys_offset =
+                        _dma_to_phys_offset_raw(last) << IOR_DMA_SHIFT;
+
+                if (dma_to_phys_offset == start_offset &&
+                        size != 0 && start <= last) {
+                        phys_t adjusted_start;
+                        adjusted_start = start + start_offset;
+                        if (flags == _CACHE_UNCACHED)
+                                result = (void __iomem *) (unsigned long)
+                                        CKSEG1ADDR(adjusted_start);
+                        else
+                                result = (void __iomem *) (unsigned long)
+                                        CKSEG0ADDR(adjusted_start);
+                }
+        }
+
+        return result;
 }
 
 static inline int plat_iounmap(const volatile void __iomem *addr)
diff --git a/arch/mips/include/asm/mach-tx49xx/kmalloc.h b/arch/mips/include/asm/mach-tx49xx/kmalloc.h
index 913ff196259d..b74caf65482b 100644
--- a/arch/mips/include/asm/mach-tx49xx/kmalloc.h
+++ b/arch/mips/include/asm/mach-tx49xx/kmalloc.h
@@ -1,8 +1,6 @@
 #ifndef __ASM_MACH_TX49XX_KMALLOC_H
 #define __ASM_MACH_TX49XX_KMALLOC_H
 
-/*
- * All happy, no need to define ARCH_KMALLOC_MINALIGN
- */
+#define ARCH_KMALLOC_MINALIGN   L1_CACHE_BYTES
 
 #endif /* __ASM_MACH_TX49XX_KMALLOC_H */
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index c6e3c93ce7c7..335474c155f6 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -408,6 +408,7 @@
 #define  STATUSB_IP15           7
 #define  STATUSF_IP15           (_ULCAST_(1) <<  7)
 #define ST0_CH                  0x00040000
+#define ST0_NMI                 0x00080000
 #define ST0_SR                  0x00100000
 #define ST0_TS                  0x00200000
 #define ST0_BEV                 0x00400000
diff --git a/arch/mips/include/asm/octeon/octeon.h b/arch/mips/include/asm/octeon/octeon.h
index ca6214b5ccb9..917a6c413b1a 100644
--- a/arch/mips/include/asm/octeon/octeon.h
+++ b/arch/mips/include/asm/octeon/octeon.h
@@ -50,6 +50,7 @@ extern void octeon_crypto_disable(struct octeon_cop2_state *state,
 extern asmlinkage void octeon_cop2_restore(struct octeon_cop2_state *task);
 
 extern void octeon_init_cvmcount(void);
+extern void octeon_setup_delays(void);
 
 #define OCTEON_ARGV_MAX_ARGS    64
 #define OCTOEN_SERIAL_LEN       20
@@ -253,4 +254,6 @@ static inline uint32_t octeon_npi_read32(uint64_t address)
 
 extern struct cvmx_bootinfo *octeon_bootinfo;
 
+extern uint64_t octeon_bootloader_entry_addr;
+
 #endif /* __ASM_OCTEON_OCTEON_H */
diff --git a/arch/mips/include/asm/octeon/pci-octeon.h b/arch/mips/include/asm/octeon/pci-octeon.h
index 6ac5d3e3398e..ece78043acf6 100644
--- a/arch/mips/include/asm/octeon/pci-octeon.h
+++ b/arch/mips/include/asm/octeon/pci-octeon.h
@@ -15,6 +15,19 @@
 #define PCI_CONFIG_SPACE_DELAY 10000
 
 /*
+ * The physical memory base mapped by BAR1.  256MB at the end of the
+ * first 4GB.
+ */
+#define CVMX_PCIE_BAR1_PHYS_BASE ((1ull << 32) - (1ull << 28))
+#define CVMX_PCIE_BAR1_PHYS_SIZE (1ull << 28)
+
+/*
+ * The RC base of BAR1.  gen1 has a 39-bit BAR2, gen2 has 41-bit BAR2,
+ * place BAR1 so it is the same for both.
+ */
+#define CVMX_PCIE_BAR1_RC_BASE (1ull << 41)
+
+/*
  * pcibios_map_irq() is defined inside pci-octeon.c. All it does is
  * call the Octeon specific version pointed to by this variable. This
  * function needs to change for PCI or PCIe based hosts.
diff --git a/arch/mips/include/asm/pci.h b/arch/mips/include/asm/pci.h
index 3beea1479b43..576397c69920 100644
--- a/arch/mips/include/asm/pci.h
+++ b/arch/mips/include/asm/pci.h
@@ -140,6 +140,11 @@ static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
         return channel ? 15 : 14;
 }
 
+#ifdef CONFIG_CPU_CAVIUM_OCTEON
+/* MSI arch hook for OCTEON */
+#define arch_setup_msi_irqs arch_setup_msi_irqs
+#endif
+
 extern int pci_probe_only;
 
 extern char * (*pcibios_plat_setup)(char *str);
diff --git a/arch/mips/include/asm/pmc-sierra/msp71xx/msp_prom.h b/arch/mips/include/asm/pmc-sierra/msp71xx/msp_prom.h
index 54ef1a96d7ce..786d82daf8d6 100644
--- a/arch/mips/include/asm/pmc-sierra/msp71xx/msp_prom.h
+++ b/arch/mips/include/asm/pmc-sierra/msp71xx/msp_prom.h
@@ -124,10 +124,6 @@ extern void prom_meminit(void);
 extern void prom_fixup_mem_map(unsigned long start_mem,
                                unsigned long end_mem);
 
-#ifdef CONFIG_MTD_PMC_MSP_RAMROOT
-extern bool get_ramroot(void **start, unsigned long *size);
-#endif
-
 extern int get_ethernet_addr(char *ethaddr_name, char *ethernet_addr);
 extern unsigned long get_deviceid(void);
 extern char identify_enet(unsigned long interface_num);
diff --git a/arch/mips/include/asm/processor.h b/arch/mips/include/asm/processor.h
index 5d33b727acf5..0d629bb93cbe 100644
--- a/arch/mips/include/asm/processor.h
+++ b/arch/mips/include/asm/processor.h
@@ -34,6 +34,11 @@ extern void (*cpu_wait)(void);
 extern unsigned int vced_count, vcei_count;
 
 /*
+ * MIPS does have an arch_pick_mmap_layout()
+ */
+#define HAVE_ARCH_PICK_MMAP_LAYOUT 1
+
+/*
  * A special page (the vdso) is mapped into all processes at the very
  * top of the virtual memory space.
  */
@@ -52,6 +57,9 @@ extern unsigned int vced_count, vcei_count;
  * space during mmap's.
  */
 #define TASK_UNMAPPED_BASE      ((TASK_SIZE / 3) & ~(PAGE_SIZE))
+
+#define TASK_IS_32BIT_ADDR 1
+
 #endif
 
 #ifdef CONFIG_64BIT
@@ -77,6 +85,9 @@ extern unsigned int vced_count, vcei_count;
                 PAGE_ALIGN(TASK_SIZE32 / 3) : PAGE_ALIGN(TASK_SIZE / 3))
 #define TASK_SIZE_OF(tsk)                                               \
         (test_tsk_thread_flag(tsk, TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE)
+
+#define TASK_IS_32BIT_ADDR test_thread_flag(TIF_32BIT_ADDR)
+
 #endif
 
 #ifdef __KERNEL__
@@ -218,7 +229,6 @@ struct thread_struct {
         unsigned long cp0_badvaddr;     /* Last user fault */
         unsigned long cp0_baduaddr;     /* Last kernel fault accessing USEG */
         unsigned long error_code;
-        unsigned long trap_no;
         unsigned long irix_trampoline;  /* Wheee... */
         unsigned long irix_oldctx;
 #ifdef CONFIG_CPU_CAVIUM_OCTEON
@@ -290,7 +300,6 @@ struct thread_struct {
         .cp0_badvaddr           = 0,                            \
         .cp0_baduaddr           = 0,                            \
         .error_code             = 0,                            \
-        .trap_no                = 0,                            \
         .irix_trampoline        = 0,                            \
         .irix_oldctx            = 0,                            \
         /*                                                      \
diff --git a/arch/mips/include/asm/ptrace.h b/arch/mips/include/asm/ptrace.h
index cdc6a46efd98..9f1b8dba2c81 100644
--- a/arch/mips/include/asm/ptrace.h
+++ b/arch/mips/include/asm/ptrace.h
@@ -137,6 +137,7 @@ extern int ptrace_set_watch_regs(struct task_struct *child,
  */
 #define user_mode(regs) (((regs)->cp0_status & KU_MASK) == KU_USER)
 
+#define regs_return_value(_regs) ((_regs)->regs[2])
 #define instruction_pointer(regs) ((regs)->cp0_epc)
 #define profile_pc(regs) instruction_pointer(regs)
 
diff --git a/arch/mips/include/asm/sn/agent.h b/arch/mips/include/asm/sn/agent.h
index ac4ea85c3a5c..dc81114d4742 100644
--- a/arch/mips/include/asm/sn/agent.h
+++ b/arch/mips/include/asm/sn/agent.h
@@ -11,7 +11,6 @@
 #ifndef _ASM_SGI_SN_AGENT_H
 #define _ASM_SGI_SN_AGENT_H
 
-#include <linux/topology.h>
 #include <asm/sn/addrs.h>
 #include <asm/sn/arch.h>
 
diff --git a/arch/mips/include/asm/uasm.h b/arch/mips/include/asm/uasm.h
index 697e40c06497..892062d6d748 100644
--- a/arch/mips/include/asm/uasm.h
+++ b/arch/mips/include/asm/uasm.h
@@ -10,44 +10,55 @@
 
 #include <linux/types.h>
 
+#ifdef CONFIG_EXPORT_UASM
+#include <linux/module.h>
+#define __uasminit
+#define __uasminitdata
+#define UASM_EXPORT_SYMBOL(sym) EXPORT_SYMBOL(sym)
+#else
+#define __uasminit __cpuinit
+#define __uasminitdata __cpuinitdata
+#define UASM_EXPORT_SYMBOL(sym)
+#endif
+
 #define Ip_u1u2u3(op)                                                   \
-void __cpuinit                                                          \
+void __uasminit                                                         \
 uasm_i##op(u32 **buf, unsigned int a, unsigned int b, unsigned int c)
 
 #define Ip_u2u1u3(op)                                                   \
-void __cpuinit                                                          \
+void __uasminit                                                         \
 uasm_i##op(u32 **buf, unsigned int a, unsigned int b, unsigned int c)
 
 #define Ip_u3u1u2(op)                                                   \
-void __cpuinit                                                          \
+void __uasminit                                                         \
 uasm_i##op(u32 **buf, unsigned int a, unsigned int b, unsigned int c)
 
 #define Ip_u1u2s3(op)                                                   \
-void __cpuinit                                                          \
+void __uasminit                                                         \
 uasm_i##op(u32 **buf, unsigned int a, unsigned int b, signed int c)
 
 #define Ip_u2s3u1(op)                                                   \
-void __cpuinit                                                          \
+void __uasminit                                                         \
 uasm_i##op(u32 **buf, unsigned int a, signed int b, unsigned int c)
 
 #define Ip_u2u1s3(op)                                                   \
-void __cpuinit                                                          \
+void __uasminit                                                         \
 uasm_i##op(u32 **buf, unsigned int a, unsigned int b, signed int c)
 
 #define Ip_u2u1msbu3(op)                                                \
-void __cpuinit                                                          \
+void __uasminit                                                         \
 uasm_i##op(u32 **buf, unsigned int a, unsigned int b, unsigned int c,   \
            unsigned int d)
 
 #define Ip_u1u2(op)                                                     \
-void __cpuinit uasm_i##op(u32 **buf, unsigned int a, unsigned int b)
+void __uasminit uasm_i##op(u32 **buf, unsigned int a, unsigned int b)
 
 #define Ip_u1s2(op)                                                     \
-void __cpuinit uasm_i##op(u32 **buf, unsigned int a, signed int b)
+void __uasminit uasm_i##op(u32 **buf, unsigned int a, signed int b)
 
-#define Ip_u1(op) void __cpuinit uasm_i##op(u32 **buf, unsigned int a)
+#define Ip_u1(op) void __uasminit uasm_i##op(u32 **buf, unsigned int a)
 
-#define Ip_0(op) void __cpuinit uasm_i##op(u32 **buf)
+#define Ip_0(op) void __uasminit uasm_i##op(u32 **buf)
 
 Ip_u2u1s3(_addiu);
 Ip_u3u1u2(_addu);
@@ -71,6 +82,7 @@ Ip_u2u1u3(_dsra);
 Ip_u2u1u3(_dsrl);
 Ip_u2u1u3(_dsrl32);
 Ip_u2u1u3(_drotr);
+Ip_u2u1u3(_drotr32);
 Ip_u3u1u2(_dsubu);
 Ip_0(_eret);
 Ip_u1(_j);
@@ -111,7 +123,7 @@ struct uasm_label {
         int lab;
 };
 
-void __cpuinit uasm_build_label(struct uasm_label **lab, u32 *addr, int lid);
+void __uasminit uasm_build_label(struct uasm_label **lab, u32 *addr, int lid);
 #ifdef CONFIG_64BIT
 int uasm_in_compat_space_p(long addr);
 #endif
@@ -121,7 +133,7 @@ void UASM_i_LA_mostly(u32 **buf, unsigned int rs, long addr);
 void UASM_i_LA(u32 **buf, unsigned int rs, long addr);
 
 #define UASM_L_LA(lb)                                                   \
-static inline void __cpuinit uasm_l##lb(struct uasm_label **lab, u32 *addr) \
+static inline void __uasminit uasm_l##lb(struct uasm_label **lab, u32 *addr) \
 {                                                                       \
         uasm_build_label(lab, addr, label##lb);                         \
 }
@@ -176,6 +188,15 @@ static inline void uasm_i_dsrl_safe(u32 **p, unsigned int a1,
                 uasm_i_dsrl32(p, a1, a2, a3 - 32);
 }
 
+static inline void uasm_i_drotr_safe(u32 **p, unsigned int a1,
+                                     unsigned int a2, unsigned int a3)
+{
+        if (a3 < 32)
+                uasm_i_drotr(p, a1, a2, a3);
+        else
+                uasm_i_drotr32(p, a1, a2, a3 - 32);
+}
+
 static inline void uasm_i_dsll_safe(u32 **p, unsigned int a1,
                                     unsigned int a2, unsigned int a3)
 {
@@ -213,3 +234,7 @@ void uasm_il_bne(u32 **p, struct uasm_reloc **r, unsigned int reg1,
 void uasm_il_bnez(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid);
 void uasm_il_bgezl(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid);
 void uasm_il_bgez(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid);
+void uasm_il_bbit0(u32 **p, struct uasm_reloc **r, unsigned int reg,
+                   unsigned int bit, int lid);
+void uasm_il_bbit1(u32 **p, struct uasm_reloc **r, unsigned int reg,
+                   unsigned int bit, int lid);