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-rw-r--r--arch/mips/include/asm/Kbuild1
-rw-r--r--arch/mips/include/asm/abi.h10
-rw-r--r--arch/mips/include/asm/addrspace.h2
-rw-r--r--arch/mips/include/asm/asmmacro.h31
-rw-r--r--arch/mips/include/asm/bitops.h8
-rw-r--r--arch/mips/include/asm/cop2.h8
-rw-r--r--arch/mips/include/asm/cpu-features.h9
-rw-r--r--arch/mips/include/asm/cpu-info.h5
-rw-r--r--arch/mips/include/asm/cpu.h61
-rw-r--r--arch/mips/include/asm/elf.h17
-rw-r--r--arch/mips/include/asm/fpu.h19
-rw-r--r--arch/mips/include/asm/gic.h41
-rw-r--r--arch/mips/include/asm/maar.h109
-rw-r--r--arch/mips/include/asm/mach-au1x00/au1000.h1529
-rw-r--r--arch/mips/include/asm/mach-au1x00/au1000_dma.h50
-rw-r--r--arch/mips/include/asm/mach-au1x00/gpio-au1000.h56
-rw-r--r--arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h7
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h198
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h46
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h31
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h16
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/cpu-feature-overrides.h2
-rw-r--r--arch/mips/include/asm/mach-loongson/boot_param.h4
-rw-r--r--arch/mips/include/asm/mach-loongson/kernel-entry-init.h52
-rw-r--r--arch/mips/include/asm/mach-loongson/loongson.h11
-rw-r--r--arch/mips/include/asm/mach-loongson/machine.h4
-rw-r--r--arch/mips/include/asm/mach-loongson/mmzone.h53
-rw-r--r--arch/mips/include/asm/mach-loongson/topology.h23
-rw-r--r--arch/mips/include/asm/mach-malta/irq.h1
-rw-r--r--arch/mips/include/asm/mach-sead3/irq.h1
-rw-r--r--arch/mips/include/asm/mips-boards/bonito64.h1
-rw-r--r--arch/mips/include/asm/mipsregs.h58
-rw-r--r--arch/mips/include/asm/mmu_context.h10
-rw-r--r--arch/mips/include/asm/msa.h31
-rw-r--r--arch/mips/include/asm/octeon/cvmx-bootinfo.h2
-rw-r--r--arch/mips/include/asm/pgtable-32.h12
-rw-r--r--arch/mips/include/asm/pgtable.h27
-rw-r--r--arch/mips/include/asm/processor.h10
-rw-r--r--arch/mips/include/asm/ptrace.h8
-rw-r--r--arch/mips/include/asm/reg.h129
-rw-r--r--arch/mips/include/asm/smp-cps.h12
-rw-r--r--arch/mips/include/asm/smp.h6
-rw-r--r--arch/mips/include/asm/sparsemem.h2
-rw-r--r--arch/mips/include/asm/user.h58
44 files changed, 1225 insertions, 1546 deletions
diff --git a/arch/mips/include/asm/Kbuild b/arch/mips/include/asm/Kbuild
index 05439187891d..335e5290ec75 100644
--- a/arch/mips/include/asm/Kbuild
+++ b/arch/mips/include/asm/Kbuild
@@ -15,4 +15,5 @@ generic-y += segment.h
15generic-y += serial.h 15generic-y += serial.h
16generic-y += trace_clock.h 16generic-y += trace_clock.h
17generic-y += ucontext.h 17generic-y += ucontext.h
18generic-y += user.h
18generic-y += xor.h 19generic-y += xor.h
diff --git a/arch/mips/include/asm/abi.h b/arch/mips/include/asm/abi.h
index 909bb6984866..7186bb51b89b 100644
--- a/arch/mips/include/asm/abi.h
+++ b/arch/mips/include/asm/abi.h
@@ -13,13 +13,11 @@
13#include <asm/siginfo.h> 13#include <asm/siginfo.h>
14 14
15struct mips_abi { 15struct mips_abi {
16 int (* const setup_frame)(void *sig_return, struct k_sigaction *ka, 16 int (* const setup_frame)(void *sig_return, struct ksignal *ksig,
17 struct pt_regs *regs, int signr, 17 struct pt_regs *regs, sigset_t *set);
18 sigset_t *set);
19 const unsigned long signal_return_offset; 18 const unsigned long signal_return_offset;
20 int (* const setup_rt_frame)(void *sig_return, struct k_sigaction *ka, 19 int (* const setup_rt_frame)(void *sig_return, struct ksignal *ksig,
21 struct pt_regs *regs, int signr, 20 struct pt_regs *regs, sigset_t *set);
22 sigset_t *set, siginfo_t *info);
23 const unsigned long rt_signal_return_offset; 21 const unsigned long rt_signal_return_offset;
24 const unsigned long restart; 22 const unsigned long restart;
25}; 23};
diff --git a/arch/mips/include/asm/addrspace.h b/arch/mips/include/asm/addrspace.h
index 3f745459fdb5..3b0e51d5a613 100644
--- a/arch/mips/include/asm/addrspace.h
+++ b/arch/mips/include/asm/addrspace.h
@@ -52,7 +52,7 @@
52 */ 52 */
53#define CPHYSADDR(a) ((_ACAST32_(a)) & 0x1fffffff) 53#define CPHYSADDR(a) ((_ACAST32_(a)) & 0x1fffffff)
54#define XPHYSADDR(a) ((_ACAST64_(a)) & \ 54#define XPHYSADDR(a) ((_ACAST64_(a)) & \
55 _CONST64_(0x000000ffffffffff)) 55 _CONST64_(0x0000ffffffffffff))
56 56
57#ifdef CONFIG_64BIT 57#ifdef CONFIG_64BIT
58 58
diff --git a/arch/mips/include/asm/asmmacro.h b/arch/mips/include/asm/asmmacro.h
index 935543f14538..cd9a98bc8f60 100644
--- a/arch/mips/include/asm/asmmacro.h
+++ b/arch/mips/include/asm/asmmacro.h
@@ -10,6 +10,7 @@
10 10
11#include <asm/hazards.h> 11#include <asm/hazards.h>
12#include <asm/asm-offsets.h> 12#include <asm/asm-offsets.h>
13#include <asm/msa.h>
13 14
14#ifdef CONFIG_32BIT 15#ifdef CONFIG_32BIT
15#include <asm/asmmacro-32.h> 16#include <asm/asmmacro-32.h>
@@ -378,9 +379,19 @@
378 st_d 29, THREAD_FPR29, \thread 379 st_d 29, THREAD_FPR29, \thread
379 st_d 30, THREAD_FPR30, \thread 380 st_d 30, THREAD_FPR30, \thread
380 st_d 31, THREAD_FPR31, \thread 381 st_d 31, THREAD_FPR31, \thread
382 .set push
383 .set noat
384 cfcmsa $1, MSA_CSR
385 sw $1, THREAD_MSA_CSR(\thread)
386 .set pop
381 .endm 387 .endm
382 388
383 .macro msa_restore_all thread 389 .macro msa_restore_all thread
390 .set push
391 .set noat
392 lw $1, THREAD_MSA_CSR(\thread)
393 ctcmsa MSA_CSR, $1
394 .set pop
384 ld_d 0, THREAD_FPR0, \thread 395 ld_d 0, THREAD_FPR0, \thread
385 ld_d 1, THREAD_FPR1, \thread 396 ld_d 1, THREAD_FPR1, \thread
386 ld_d 2, THREAD_FPR2, \thread 397 ld_d 2, THREAD_FPR2, \thread
@@ -415,4 +426,24 @@
415 ld_d 31, THREAD_FPR31, \thread 426 ld_d 31, THREAD_FPR31, \thread
416 .endm 427 .endm
417 428
429 .macro msa_init_upper wd
430#ifdef CONFIG_64BIT
431 insert_d \wd, 1
432#else
433 insert_w \wd, 2
434 insert_w \wd, 3
435#endif
436 .if 31-\wd
437 msa_init_upper (\wd+1)
438 .endif
439 .endm
440
441 .macro msa_init_all_upper
442 .set push
443 .set noat
444 not $1, zero
445 msa_init_upper 0
446 .set pop
447 .endm
448
418#endif /* _ASM_ASMMACRO_H */ 449#endif /* _ASM_ASMMACRO_H */
diff --git a/arch/mips/include/asm/bitops.h b/arch/mips/include/asm/bitops.h
index 7c8816f7b7c4..bae6b0fa8ab5 100644
--- a/arch/mips/include/asm/bitops.h
+++ b/arch/mips/include/asm/bitops.h
@@ -559,7 +559,13 @@ static inline int fls(int x)
559 int r; 559 int r;
560 560
561 if (__builtin_constant_p(cpu_has_clo_clz) && cpu_has_clo_clz) { 561 if (__builtin_constant_p(cpu_has_clo_clz) && cpu_has_clo_clz) {
562 __asm__("clz %0, %1" : "=r" (x) : "r" (x)); 562 __asm__(
563 " .set push \n"
564 " .set mips32 \n"
565 " clz %0, %1 \n"
566 " .set pop \n"
567 : "=r" (x)
568 : "r" (x));
563 569
564 return 32 - x; 570 return 32 - x;
565 } 571 }
diff --git a/arch/mips/include/asm/cop2.h b/arch/mips/include/asm/cop2.h
index c1516cc0285f..d0352983b94d 100644
--- a/arch/mips/include/asm/cop2.h
+++ b/arch/mips/include/asm/cop2.h
@@ -32,6 +32,14 @@ extern void nlm_cop2_restore(struct nlm_cop2_state *);
32#define cop2_present 1 32#define cop2_present 1
33#define cop2_lazy_restore 0 33#define cop2_lazy_restore 0
34 34
35#elif defined(CONFIG_CPU_LOONGSON3)
36
37#define cop2_save(r)
38#define cop2_restore(r)
39
40#define cop2_present 1
41#define cop2_lazy_restore 1
42
35#else 43#else
36 44
37#define cop2_present 0 45#define cop2_present 0
diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
index c7d8c997d93e..e079598ae051 100644
--- a/arch/mips/include/asm/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
@@ -29,6 +29,15 @@
29#ifndef cpu_has_eva 29#ifndef cpu_has_eva
30#define cpu_has_eva (cpu_data[0].options & MIPS_CPU_EVA) 30#define cpu_has_eva (cpu_data[0].options & MIPS_CPU_EVA)
31#endif 31#endif
32#ifndef cpu_has_htw
33#define cpu_has_htw (cpu_data[0].options & MIPS_CPU_HTW)
34#endif
35#ifndef cpu_has_rixiex
36#define cpu_has_rixiex (cpu_data[0].options & MIPS_CPU_RIXIEX)
37#endif
38#ifndef cpu_has_maar
39#define cpu_has_maar (cpu_data[0].options & MIPS_CPU_MAAR)
40#endif
32 41
33/* 42/*
34 * For the moment we don't consider R6000 and R8000 so we can assume that 43 * For the moment we don't consider R6000 and R8000 so we can assume that
diff --git a/arch/mips/include/asm/cpu-info.h b/arch/mips/include/asm/cpu-info.h
index 47d5967ce7ef..d5f42c168001 100644
--- a/arch/mips/include/asm/cpu-info.h
+++ b/arch/mips/include/asm/cpu-info.h
@@ -44,8 +44,8 @@ struct cpuinfo_mips {
44 /* 44 /*
45 * Capability and feature descriptor structure for MIPS CPU 45 * Capability and feature descriptor structure for MIPS CPU
46 */ 46 */
47 unsigned long options;
48 unsigned long ases; 47 unsigned long ases;
48 unsigned long long options;
49 unsigned int udelay_val; 49 unsigned int udelay_val;
50 unsigned int processor_id; 50 unsigned int processor_id;
51 unsigned int fpu_id; 51 unsigned int fpu_id;
@@ -61,6 +61,7 @@ struct cpuinfo_mips {
61 struct cache_desc scache; /* Secondary cache */ 61 struct cache_desc scache; /* Secondary cache */
62 struct cache_desc tcache; /* Tertiary/split secondary cache */ 62 struct cache_desc tcache; /* Tertiary/split secondary cache */
63 int srsets; /* Shadow register sets */ 63 int srsets; /* Shadow register sets */
64 int package;/* physical package number */
64 int core; /* physical core number */ 65 int core; /* physical core number */
65#ifdef CONFIG_64BIT 66#ifdef CONFIG_64BIT
66 int vmbits; /* Virtual memory size in bits */ 67 int vmbits; /* Virtual memory size in bits */
@@ -115,7 +116,7 @@ struct proc_cpuinfo_notifier_args {
115#ifdef CONFIG_MIPS_MT_SMP 116#ifdef CONFIG_MIPS_MT_SMP
116# define cpu_vpe_id(cpuinfo) ((cpuinfo)->vpe_id) 117# define cpu_vpe_id(cpuinfo) ((cpuinfo)->vpe_id)
117#else 118#else
118# define cpu_vpe_id(cpuinfo) 0 119# define cpu_vpe_id(cpuinfo) ({ (void)cpuinfo; 0; })
119#endif 120#endif
120 121
121#endif /* __ASM_CPU_INFO_H */ 122#endif /* __ASM_CPU_INFO_H */
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index 129d08701e91..dfdc77ed1839 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -233,6 +233,8 @@
233#define PRID_REV_LOONGSON2E 0x0002 233#define PRID_REV_LOONGSON2E 0x0002
234#define PRID_REV_LOONGSON2F 0x0003 234#define PRID_REV_LOONGSON2F 0x0003
235#define PRID_REV_LOONGSON3A 0x0005 235#define PRID_REV_LOONGSON3A 0x0005
236#define PRID_REV_LOONGSON3B_R1 0x0006
237#define PRID_REV_LOONGSON3B_R2 0x0007
236 238
237/* 239/*
238 * Older processors used to encode processor version and revision in two 240 * Older processors used to encode processor version and revision in two
@@ -335,34 +337,37 @@ enum cpu_type_enum {
335/* 337/*
336 * CPU Option encodings 338 * CPU Option encodings
337 */ 339 */
338#define MIPS_CPU_TLB 0x00000001 /* CPU has TLB */ 340#define MIPS_CPU_TLB 0x00000001ull /* CPU has TLB */
339#define MIPS_CPU_4KEX 0x00000002 /* "R4K" exception model */ 341#define MIPS_CPU_4KEX 0x00000002ull /* "R4K" exception model */
340#define MIPS_CPU_3K_CACHE 0x00000004 /* R3000-style caches */ 342#define MIPS_CPU_3K_CACHE 0x00000004ull /* R3000-style caches */
341#define MIPS_CPU_4K_CACHE 0x00000008 /* R4000-style caches */ 343#define MIPS_CPU_4K_CACHE 0x00000008ull /* R4000-style caches */
342#define MIPS_CPU_TX39_CACHE 0x00000010 /* TX3900-style caches */ 344#define MIPS_CPU_TX39_CACHE 0x00000010ull /* TX3900-style caches */
343#define MIPS_CPU_FPU 0x00000020 /* CPU has FPU */ 345#define MIPS_CPU_FPU 0x00000020ull /* CPU has FPU */
344#define MIPS_CPU_32FPR 0x00000040 /* 32 dbl. prec. FP registers */ 346#define MIPS_CPU_32FPR 0x00000040ull /* 32 dbl. prec. FP registers */
345#define MIPS_CPU_COUNTER 0x00000080 /* Cycle count/compare */ 347#define MIPS_CPU_COUNTER 0x00000080ull /* Cycle count/compare */
346#define MIPS_CPU_WATCH 0x00000100 /* watchpoint registers */ 348#define MIPS_CPU_WATCH 0x00000100ull /* watchpoint registers */
347#define MIPS_CPU_DIVEC 0x00000200 /* dedicated interrupt vector */ 349#define MIPS_CPU_DIVEC 0x00000200ull /* dedicated interrupt vector */
348#define MIPS_CPU_VCE 0x00000400 /* virt. coherence conflict possible */ 350#define MIPS_CPU_VCE 0x00000400ull /* virt. coherence conflict possible */
349#define MIPS_CPU_CACHE_CDEX_P 0x00000800 /* Create_Dirty_Exclusive CACHE op */ 351#define MIPS_CPU_CACHE_CDEX_P 0x00000800ull /* Create_Dirty_Exclusive CACHE op */
350#define MIPS_CPU_CACHE_CDEX_S 0x00001000 /* ... same for seconary cache ... */ 352#define MIPS_CPU_CACHE_CDEX_S 0x00001000ull /* ... same for seconary cache ... */
351#define MIPS_CPU_MCHECK 0x00002000 /* Machine check exception */ 353#define MIPS_CPU_MCHECK 0x00002000ull /* Machine check exception */
352#define MIPS_CPU_EJTAG 0x00004000 /* EJTAG exception */ 354#define MIPS_CPU_EJTAG 0x00004000ull /* EJTAG exception */
353#define MIPS_CPU_NOFPUEX 0x00008000 /* no FPU exception */ 355#define MIPS_CPU_NOFPUEX 0x00008000ull /* no FPU exception */
354#define MIPS_CPU_LLSC 0x00010000 /* CPU has ll/sc instructions */ 356#define MIPS_CPU_LLSC 0x00010000ull /* CPU has ll/sc instructions */
355#define MIPS_CPU_INCLUSIVE_CACHES 0x00020000 /* P-cache subset enforced */ 357#define MIPS_CPU_INCLUSIVE_CACHES 0x00020000ull /* P-cache subset enforced */
356#define MIPS_CPU_PREFETCH 0x00040000 /* CPU has usable prefetch */ 358#define MIPS_CPU_PREFETCH 0x00040000ull /* CPU has usable prefetch */
357#define MIPS_CPU_VINT 0x00080000 /* CPU supports MIPSR2 vectored interrupts */ 359#define MIPS_CPU_VINT 0x00080000ull /* CPU supports MIPSR2 vectored interrupts */
358#define MIPS_CPU_VEIC 0x00100000 /* CPU supports MIPSR2 external interrupt controller mode */ 360#define MIPS_CPU_VEIC 0x00100000ull /* CPU supports MIPSR2 external interrupt controller mode */
359#define MIPS_CPU_ULRI 0x00200000 /* CPU has ULRI feature */ 361#define MIPS_CPU_ULRI 0x00200000ull /* CPU has ULRI feature */
360#define MIPS_CPU_PCI 0x00400000 /* CPU has Perf Ctr Int indicator */ 362#define MIPS_CPU_PCI 0x00400000ull /* CPU has Perf Ctr Int indicator */
361#define MIPS_CPU_RIXI 0x00800000 /* CPU has TLB Read/eXec Inhibit */ 363#define MIPS_CPU_RIXI 0x00800000ull /* CPU has TLB Read/eXec Inhibit */
362#define MIPS_CPU_MICROMIPS 0x01000000 /* CPU has microMIPS capability */ 364#define MIPS_CPU_MICROMIPS 0x01000000ull /* CPU has microMIPS capability */
363#define MIPS_CPU_TLBINV 0x02000000 /* CPU supports TLBINV/F */ 365#define MIPS_CPU_TLBINV 0x02000000ull /* CPU supports TLBINV/F */
364#define MIPS_CPU_SEGMENTS 0x04000000 /* CPU supports Segmentation Control registers */ 366#define MIPS_CPU_SEGMENTS 0x04000000ull /* CPU supports Segmentation Control registers */
365#define MIPS_CPU_EVA 0x80000000 /* CPU supports Enhanced Virtual Addressing */ 367#define MIPS_CPU_EVA 0x80000000ull /* CPU supports Enhanced Virtual Addressing */
368#define MIPS_CPU_HTW 0x100000000ull /* CPU support Hardware Page Table Walker */
369#define MIPS_CPU_RIXIEX 0x200000000ull /* CPU has unique exception codes for {Read, Execute}-Inhibit exceptions */
370#define MIPS_CPU_MAAR 0x400000000ull /* MAAR(I) registers are present */
366 371
367/* 372/*
368 * CPU ASE encodings 373 * CPU ASE encodings
diff --git a/arch/mips/include/asm/elf.h b/arch/mips/include/asm/elf.h
index d4144056e928..1d38fe0edd2d 100644
--- a/arch/mips/include/asm/elf.h
+++ b/arch/mips/include/asm/elf.h
@@ -339,23 +339,6 @@ do { \
339 339
340#endif /* CONFIG_64BIT */ 340#endif /* CONFIG_64BIT */
341 341
342struct pt_regs;
343struct task_struct;
344
345extern void elf_dump_regs(elf_greg_t *, struct pt_regs *regs);
346extern int dump_task_regs(struct task_struct *, elf_gregset_t *);
347extern int dump_task_fpu(struct task_struct *, elf_fpregset_t *);
348
349#ifndef ELF_CORE_COPY_REGS
350#define ELF_CORE_COPY_REGS(elf_regs, regs) \
351 elf_dump_regs((elf_greg_t *)&(elf_regs), regs);
352#endif
353#ifndef ELF_CORE_COPY_TASK_REGS
354#define ELF_CORE_COPY_TASK_REGS(tsk, elf_regs) dump_task_regs(tsk, elf_regs)
355#endif
356#define ELF_CORE_COPY_FPREGS(tsk, elf_fpregs) \
357 dump_task_fpu(tsk, elf_fpregs)
358
359#define CORE_DUMP_USE_REGSET 342#define CORE_DUMP_USE_REGSET
360#define ELF_EXEC_PAGESIZE PAGE_SIZE 343#define ELF_EXEC_PAGESIZE PAGE_SIZE
361 344
diff --git a/arch/mips/include/asm/fpu.h b/arch/mips/include/asm/fpu.h
index a939574f8293..4d0aeda68397 100644
--- a/arch/mips/include/asm/fpu.h
+++ b/arch/mips/include/asm/fpu.h
@@ -21,6 +21,7 @@
21#include <asm/hazards.h> 21#include <asm/hazards.h>
22#include <asm/processor.h> 22#include <asm/processor.h>
23#include <asm/current.h> 23#include <asm/current.h>
24#include <asm/msa.h>
24 25
25#ifdef CONFIG_MIPS_MT_FPAFF 26#ifdef CONFIG_MIPS_MT_FPAFF
26#include <asm/mips_mt.h> 27#include <asm/mips_mt.h>
@@ -141,13 +142,21 @@ static inline int own_fpu(int restore)
141static inline void lose_fpu(int save) 142static inline void lose_fpu(int save)
142{ 143{
143 preempt_disable(); 144 preempt_disable();
144 if (is_fpu_owner()) { 145 if (is_msa_enabled()) {
146 if (save) {
147 save_msa(current);
148 asm volatile("cfc1 %0, $31"
149 : "=r"(current->thread.fpu.fcr31));
150 }
151 disable_msa();
152 clear_thread_flag(TIF_USEDMSA);
153 } else if (is_fpu_owner()) {
145 if (save) 154 if (save)
146 _save_fp(current); 155 _save_fp(current);
147 KSTK_STATUS(current) &= ~ST0_CU1;
148 clear_thread_flag(TIF_USEDFPU);
149 __disable_fpu(); 156 __disable_fpu();
150 } 157 }
158 KSTK_STATUS(current) &= ~ST0_CU1;
159 clear_thread_flag(TIF_USEDFPU);
151 preempt_enable(); 160 preempt_enable();
152} 161}
153 162
@@ -155,8 +164,6 @@ static inline int init_fpu(void)
155{ 164{
156 int ret = 0; 165 int ret = 0;
157 166
158 preempt_disable();
159
160 if (cpu_has_fpu) { 167 if (cpu_has_fpu) {
161 ret = __own_fpu(); 168 ret = __own_fpu();
162 if (!ret) 169 if (!ret)
@@ -164,8 +171,6 @@ static inline int init_fpu(void)
164 } else 171 } else
165 fpu_emulator_init_fpu(); 172 fpu_emulator_init_fpu();
166 173
167 preempt_enable();
168
169 return ret; 174 return ret;
170} 175}
171 176
diff --git a/arch/mips/include/asm/gic.h b/arch/mips/include/asm/gic.h
index 10f6a99f92c2..3f20b2111d56 100644
--- a/arch/mips/include/asm/gic.h
+++ b/arch/mips/include/asm/gic.h
@@ -14,6 +14,8 @@
14#include <linux/bitmap.h> 14#include <linux/bitmap.h>
15#include <linux/threads.h> 15#include <linux/threads.h>
16 16
17#include <irq.h>
18
17#undef GICISBYTELITTLEENDIAN 19#undef GICISBYTELITTLEENDIAN
18 20
19/* Constants */ 21/* Constants */
@@ -22,8 +24,6 @@
22#define GIC_TRIG_EDGE 1 24#define GIC_TRIG_EDGE 1
23#define GIC_TRIG_LEVEL 0 25#define GIC_TRIG_LEVEL 0
24 26
25#define GIC_NUM_INTRS (24 + NR_CPUS * 2)
26
27#define MSK(n) ((1 << (n)) - 1) 27#define MSK(n) ((1 << (n)) - 1)
28#define REG32(addr) (*(volatile unsigned int *) (addr)) 28#define REG32(addr) (*(volatile unsigned int *) (addr))
29#define REG(base, offs) REG32((unsigned long)(base) + offs##_##OFS) 29#define REG(base, offs) REG32((unsigned long)(base) + offs##_##OFS)
@@ -43,18 +43,17 @@
43#ifdef GICISBYTELITTLEENDIAN 43#ifdef GICISBYTELITTLEENDIAN
44#define GICREAD(reg, data) ((data) = (reg), (data) = le32_to_cpu(data)) 44#define GICREAD(reg, data) ((data) = (reg), (data) = le32_to_cpu(data))
45#define GICWRITE(reg, data) ((reg) = cpu_to_le32(data)) 45#define GICWRITE(reg, data) ((reg) = cpu_to_le32(data))
46#define GICBIS(reg, bits) \
47 ({unsigned int data; \
48 GICREAD(reg, data); \
49 data |= bits; \
50 GICWRITE(reg, data); \
51 })
52
53#else 46#else
54#define GICREAD(reg, data) ((data) = (reg)) 47#define GICREAD(reg, data) ((data) = (reg))
55#define GICWRITE(reg, data) ((reg) = (data)) 48#define GICWRITE(reg, data) ((reg) = (data))
56#define GICBIS(reg, bits) ((reg) |= (bits))
57#endif 49#endif
50#define GICBIS(reg, mask, bits) \
51 do { u32 data; \
52 GICREAD((reg), data); \
53 data &= ~(mask); \
54 data |= ((bits) & (mask)); \
55 GICWRITE((reg), data); \
56 } while (0)
58 57
59 58
60/* GIC Address Space */ 59/* GIC Address Space */
@@ -170,13 +169,15 @@
170#define GIC_SH_SET_POLARITY_OFS 0x0100 169#define GIC_SH_SET_POLARITY_OFS 0x0100
171#define GIC_SET_POLARITY(intr, pol) \ 170#define GIC_SET_POLARITY(intr, pol) \
172 GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_POLARITY_OFS + \ 171 GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_POLARITY_OFS + \
173 GIC_INTR_OFS(intr)), (pol) << GIC_INTR_BIT(intr)) 172 GIC_INTR_OFS(intr)), (1 << GIC_INTR_BIT(intr)), \
173 (pol) << GIC_INTR_BIT(intr))
174 174
175/* Triggering : Reset Value is always 0 */ 175/* Triggering : Reset Value is always 0 */
176#define GIC_SH_SET_TRIGGER_OFS 0x0180 176#define GIC_SH_SET_TRIGGER_OFS 0x0180
177#define GIC_SET_TRIGGER(intr, trig) \ 177#define GIC_SET_TRIGGER(intr, trig) \
178 GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_TRIGGER_OFS + \ 178 GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_TRIGGER_OFS + \
179 GIC_INTR_OFS(intr)), (trig) << GIC_INTR_BIT(intr)) 179 GIC_INTR_OFS(intr)), (1 << GIC_INTR_BIT(intr)), \
180 (trig) << GIC_INTR_BIT(intr))
180 181
181/* Mask manipulation */ 182/* Mask manipulation */
182#define GIC_SH_SMASK_OFS 0x0380 183#define GIC_SH_SMASK_OFS 0x0380
@@ -306,18 +307,6 @@
306 GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_MAP_TO_VPE_REG_OFF(intr, vpe)), \ 307 GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_MAP_TO_VPE_REG_OFF(intr, vpe)), \
307 GIC_SH_MAP_TO_VPE_REG_BIT(vpe)) 308 GIC_SH_MAP_TO_VPE_REG_BIT(vpe))
308 309
309struct gic_pcpu_mask {
310 DECLARE_BITMAP(pcpu_mask, GIC_NUM_INTRS);
311};
312
313struct gic_pending_regs {
314 DECLARE_BITMAP(pending, GIC_NUM_INTRS);
315};
316
317struct gic_intrmask_regs {
318 DECLARE_BITMAP(intrmask, GIC_NUM_INTRS);
319};
320
321/* 310/*
322 * Interrupt Meta-data specification. The ipiflag helps 311 * Interrupt Meta-data specification. The ipiflag helps
323 * in building ipi_map. 312 * in building ipi_map.
@@ -329,8 +318,7 @@ struct gic_intr_map {
329 unsigned int polarity; /* Polarity : +/- */ 318 unsigned int polarity; /* Polarity : +/- */
330 unsigned int trigtype; /* Trigger : Edge/Levl */ 319 unsigned int trigtype; /* Trigger : Edge/Levl */
331 unsigned int flags; /* Misc flags */ 320 unsigned int flags; /* Misc flags */
332#define GIC_FLAG_IPI 0x01 321#define GIC_FLAG_TRANSPARENT 0x01
333#define GIC_FLAG_TRANSPARENT 0x02
334}; 322};
335 323
336/* 324/*
@@ -386,6 +374,7 @@ extern unsigned int plat_ipi_call_int_xlate(unsigned int);
386extern unsigned int plat_ipi_resched_int_xlate(unsigned int); 374extern unsigned int plat_ipi_resched_int_xlate(unsigned int);
387extern void gic_bind_eic_interrupt(int irq, int set); 375extern void gic_bind_eic_interrupt(int irq, int set);
388extern unsigned int gic_get_timer_pending(void); 376extern unsigned int gic_get_timer_pending(void);
377extern void gic_get_int_mask(unsigned long *dst, const unsigned long *src);
389extern unsigned int gic_get_int(void); 378extern unsigned int gic_get_int(void);
390extern void gic_enable_interrupt(int irq_vec); 379extern void gic_enable_interrupt(int irq_vec);
391extern void gic_disable_interrupt(int irq_vec); 380extern void gic_disable_interrupt(int irq_vec);
diff --git a/arch/mips/include/asm/maar.h b/arch/mips/include/asm/maar.h
new file mode 100644
index 000000000000..6c62b0f899c0
--- /dev/null
+++ b/arch/mips/include/asm/maar.h
@@ -0,0 +1,109 @@
1/*
2 * Copyright (C) 2014 Imagination Technologies
3 * Author: Paul Burton <paul.burton@imgtec.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 */
10
11#ifndef __MIPS_ASM_MIPS_MAAR_H__
12#define __MIPS_ASM_MIPS_MAAR_H__
13
14#include <asm/hazards.h>
15#include <asm/mipsregs.h>
16
17/**
18 * platform_maar_init() - perform platform-level MAAR configuration
19 * @num_pairs: The number of MAAR pairs present in the system.
20 *
21 * Platforms should implement this function such that it configures as many
22 * MAAR pairs as required, from 0 up to the maximum of num_pairs-1, and returns
23 * the number that were used. Any further MAARs will be configured to be
24 * invalid. The default implementation of this function will simply indicate
25 * that it has configured 0 MAAR pairs.
26 *
27 * Return: The number of MAAR pairs configured.
28 */
29unsigned __weak platform_maar_init(unsigned num_pairs);
30
31/**
32 * write_maar_pair() - write to a pair of MAARs
33 * @idx: The index of the pair (ie. use MAARs idx*2 & (idx*2)+1).
34 * @lower: The lowest address that the MAAR pair will affect. Must be
35 * aligned to a 2^16 byte boundary.
36 * @upper: The highest address that the MAAR pair will affect. Must be
37 * aligned to one byte before a 2^16 byte boundary.
38 * @attrs: The accessibility attributes to program, eg. MIPS_MAAR_S. The
39 * MIPS_MAAR_V attribute will automatically be set.
40 *
41 * Program the pair of MAAR registers specified by idx to apply the attributes
42 * specified by attrs to the range of addresses from lower to higher.
43 */
44static inline void write_maar_pair(unsigned idx, phys_addr_t lower,
45 phys_addr_t upper, unsigned attrs)
46{
47 /* Addresses begin at bit 16, but are shifted right 4 bits */
48 BUG_ON(lower & (0xffff | ~(MIPS_MAAR_ADDR << 4)));
49 BUG_ON(((upper & 0xffff) != 0xffff)
50 || ((upper & ~0xffffull) & ~(MIPS_MAAR_ADDR << 4)));
51
52 /* Automatically set MIPS_MAAR_V */
53 attrs |= MIPS_MAAR_V;
54
55 /* Write the upper address & attributes (only MIPS_MAAR_V matters) */
56 write_c0_maari(idx << 1);
57 back_to_back_c0_hazard();
58 write_c0_maar(((upper >> 4) & MIPS_MAAR_ADDR) | attrs);
59 back_to_back_c0_hazard();
60
61 /* Write the lower address & attributes */
62 write_c0_maari((idx << 1) | 0x1);
63 back_to_back_c0_hazard();
64 write_c0_maar((lower >> 4) | attrs);
65 back_to_back_c0_hazard();
66}
67
68/**
69 * struct maar_config - MAAR configuration data
70 * @lower: The lowest address that the MAAR pair will affect. Must be
71 * aligned to a 2^16 byte boundary.
72 * @upper: The highest address that the MAAR pair will affect. Must be
73 * aligned to one byte before a 2^16 byte boundary.
74 * @attrs: The accessibility attributes to program, eg. MIPS_MAAR_S. The
75 * MIPS_MAAR_V attribute will automatically be set.
76 *
77 * Describes the configuration of a pair of Memory Accessibility Attribute
78 * Registers - applying attributes from attrs to the range of physical
79 * addresses from lower to upper inclusive.
80 */
81struct maar_config {
82 phys_addr_t lower;
83 phys_addr_t upper;
84 unsigned attrs;
85};
86
87/**
88 * maar_config() - configure MAARs according to provided data
89 * @cfg: Pointer to an array of struct maar_config.
90 * @num_cfg: The number of structs in the cfg array.
91 * @num_pairs: The number of MAAR pairs present in the system.
92 *
93 * Configures as many MAARs as are present and specified in the cfg
94 * array with the values taken from the cfg array.
95 *
96 * Return: The number of MAAR pairs configured.
97 */
98static inline unsigned maar_config(const struct maar_config *cfg,
99 unsigned num_cfg, unsigned num_pairs)
100{
101 unsigned i;
102
103 for (i = 0; i < min(num_cfg, num_pairs); i++)
104 write_maar_pair(i, cfg[i].lower, cfg[i].upper, cfg[i].attrs);
105
106 return i;
107}
108
109#endif /* __MIPS_ASM_MIPS_MAAR_H__ */
diff --git a/arch/mips/include/asm/mach-au1x00/au1000.h b/arch/mips/include/asm/mach-au1x00/au1000.h
index b4c3ecb17d48..a7eec3364a64 100644
--- a/arch/mips/include/asm/mach-au1x00/au1000.h
+++ b/arch/mips/include/asm/mach-au1x00/au1000.h
@@ -34,6 +34,558 @@
34#ifndef _AU1000_H_ 34#ifndef _AU1000_H_
35#define _AU1000_H_ 35#define _AU1000_H_
36 36
37/* SOC Interrupt numbers */
38/* Au1000-style (IC0/1): 2 controllers with 32 sources each */
39#define AU1000_INTC0_INT_BASE (MIPS_CPU_IRQ_BASE + 8)
40#define AU1000_INTC0_INT_LAST (AU1000_INTC0_INT_BASE + 31)
41#define AU1000_INTC1_INT_BASE (AU1000_INTC0_INT_LAST + 1)
42#define AU1000_INTC1_INT_LAST (AU1000_INTC1_INT_BASE + 31)
43#define AU1000_MAX_INTR AU1000_INTC1_INT_LAST
44
45/* Au1300-style (GPIC): 1 controller with up to 128 sources */
46#define ALCHEMY_GPIC_INT_BASE (MIPS_CPU_IRQ_BASE + 8)
47#define ALCHEMY_GPIC_INT_NUM 128
48#define ALCHEMY_GPIC_INT_LAST (ALCHEMY_GPIC_INT_BASE + ALCHEMY_GPIC_INT_NUM - 1)
49
50/* common clock names, shared among all variants. AUXPLL2 is Au1300 */
51#define ALCHEMY_ROOT_CLK "root_clk"
52#define ALCHEMY_CPU_CLK "cpu_clk"
53#define ALCHEMY_AUXPLL_CLK "auxpll_clk"
54#define ALCHEMY_AUXPLL2_CLK "auxpll2_clk"
55#define ALCHEMY_SYSBUS_CLK "sysbus_clk"
56#define ALCHEMY_PERIPH_CLK "periph_clk"
57#define ALCHEMY_MEM_CLK "mem_clk"
58#define ALCHEMY_LR_CLK "lr_clk"
59#define ALCHEMY_FG0_CLK "fg0_clk"
60#define ALCHEMY_FG1_CLK "fg1_clk"
61#define ALCHEMY_FG2_CLK "fg2_clk"
62#define ALCHEMY_FG3_CLK "fg3_clk"
63#define ALCHEMY_FG4_CLK "fg4_clk"
64#define ALCHEMY_FG5_CLK "fg5_clk"
65
66/* Au1300 peripheral interrupt numbers */
67#define AU1300_FIRST_INT (ALCHEMY_GPIC_INT_BASE)
68#define AU1300_UART1_INT (AU1300_FIRST_INT + 17)
69#define AU1300_UART2_INT (AU1300_FIRST_INT + 25)
70#define AU1300_UART3_INT (AU1300_FIRST_INT + 27)
71#define AU1300_SD1_INT (AU1300_FIRST_INT + 32)
72#define AU1300_SD2_INT (AU1300_FIRST_INT + 38)
73#define AU1300_PSC0_INT (AU1300_FIRST_INT + 48)
74#define AU1300_PSC1_INT (AU1300_FIRST_INT + 52)
75#define AU1300_PSC2_INT (AU1300_FIRST_INT + 56)
76#define AU1300_PSC3_INT (AU1300_FIRST_INT + 60)
77#define AU1300_NAND_INT (AU1300_FIRST_INT + 62)
78#define AU1300_DDMA_INT (AU1300_FIRST_INT + 75)
79#define AU1300_MMU_INT (AU1300_FIRST_INT + 76)
80#define AU1300_MPU_INT (AU1300_FIRST_INT + 77)
81#define AU1300_GPU_INT (AU1300_FIRST_INT + 78)
82#define AU1300_UDMA_INT (AU1300_FIRST_INT + 79)
83#define AU1300_TOY_INT (AU1300_FIRST_INT + 80)
84#define AU1300_TOY_MATCH0_INT (AU1300_FIRST_INT + 81)
85#define AU1300_TOY_MATCH1_INT (AU1300_FIRST_INT + 82)
86#define AU1300_TOY_MATCH2_INT (AU1300_FIRST_INT + 83)
87#define AU1300_RTC_INT (AU1300_FIRST_INT + 84)
88#define AU1300_RTC_MATCH0_INT (AU1300_FIRST_INT + 85)
89#define AU1300_RTC_MATCH1_INT (AU1300_FIRST_INT + 86)
90#define AU1300_RTC_MATCH2_INT (AU1300_FIRST_INT + 87)
91#define AU1300_UART0_INT (AU1300_FIRST_INT + 88)
92#define AU1300_SD0_INT (AU1300_FIRST_INT + 89)
93#define AU1300_USB_INT (AU1300_FIRST_INT + 90)
94#define AU1300_LCD_INT (AU1300_FIRST_INT + 91)
95#define AU1300_BSA_INT (AU1300_FIRST_INT + 92)
96#define AU1300_MPE_INT (AU1300_FIRST_INT + 93)
97#define AU1300_ITE_INT (AU1300_FIRST_INT + 94)
98#define AU1300_AES_INT (AU1300_FIRST_INT + 95)
99#define AU1300_CIM_INT (AU1300_FIRST_INT + 96)
100
101/**********************************************************************/
102
103/*
104 * Physical base addresses for integrated peripherals
105 * 0..au1000 1..au1500 2..au1100 3..au1550 4..au1200 5..au1300
106 */
107
108#define AU1000_AC97_PHYS_ADDR 0x10000000 /* 012 */
109#define AU1300_ROM_PHYS_ADDR 0x10000000 /* 5 */
110#define AU1300_OTP_PHYS_ADDR 0x10002000 /* 5 */
111#define AU1300_VSS_PHYS_ADDR 0x10003000 /* 5 */
112#define AU1300_UART0_PHYS_ADDR 0x10100000 /* 5 */
113#define AU1300_UART1_PHYS_ADDR 0x10101000 /* 5 */
114#define AU1300_UART2_PHYS_ADDR 0x10102000 /* 5 */
115#define AU1300_UART3_PHYS_ADDR 0x10103000 /* 5 */
116#define AU1000_USB_OHCI_PHYS_ADDR 0x10100000 /* 012 */
117#define AU1000_USB_UDC_PHYS_ADDR 0x10200000 /* 0123 */
118#define AU1300_GPIC_PHYS_ADDR 0x10200000 /* 5 */
119#define AU1000_IRDA_PHYS_ADDR 0x10300000 /* 02 */
120#define AU1200_AES_PHYS_ADDR 0x10300000 /* 45 */
121#define AU1000_IC0_PHYS_ADDR 0x10400000 /* 01234 */
122#define AU1300_GPU_PHYS_ADDR 0x10500000 /* 5 */
123#define AU1000_MAC0_PHYS_ADDR 0x10500000 /* 023 */
124#define AU1000_MAC1_PHYS_ADDR 0x10510000 /* 023 */
125#define AU1000_MACEN_PHYS_ADDR 0x10520000 /* 023 */
126#define AU1100_SD0_PHYS_ADDR 0x10600000 /* 245 */
127#define AU1300_SD1_PHYS_ADDR 0x10601000 /* 5 */
128#define AU1300_SD2_PHYS_ADDR 0x10602000 /* 5 */
129#define AU1100_SD1_PHYS_ADDR 0x10680000 /* 24 */
130#define AU1300_SYS_PHYS_ADDR 0x10900000 /* 5 */
131#define AU1550_PSC2_PHYS_ADDR 0x10A00000 /* 3 */
132#define AU1550_PSC3_PHYS_ADDR 0x10B00000 /* 3 */
133#define AU1300_PSC0_PHYS_ADDR 0x10A00000 /* 5 */
134#define AU1300_PSC1_PHYS_ADDR 0x10A01000 /* 5 */
135#define AU1300_PSC2_PHYS_ADDR 0x10A02000 /* 5 */
136#define AU1300_PSC3_PHYS_ADDR 0x10A03000 /* 5 */
137#define AU1000_I2S_PHYS_ADDR 0x11000000 /* 02 */
138#define AU1500_MAC0_PHYS_ADDR 0x11500000 /* 1 */
139#define AU1500_MAC1_PHYS_ADDR 0x11510000 /* 1 */
140#define AU1500_MACEN_PHYS_ADDR 0x11520000 /* 1 */
141#define AU1000_UART0_PHYS_ADDR 0x11100000 /* 01234 */
142#define AU1200_SWCNT_PHYS_ADDR 0x1110010C /* 4 */
143#define AU1000_UART1_PHYS_ADDR 0x11200000 /* 0234 */
144#define AU1000_UART2_PHYS_ADDR 0x11300000 /* 0 */
145#define AU1000_UART3_PHYS_ADDR 0x11400000 /* 0123 */
146#define AU1000_SSI0_PHYS_ADDR 0x11600000 /* 02 */
147#define AU1000_SSI1_PHYS_ADDR 0x11680000 /* 02 */
148#define AU1500_GPIO2_PHYS_ADDR 0x11700000 /* 1234 */
149#define AU1000_IC1_PHYS_ADDR 0x11800000 /* 01234 */
150#define AU1000_SYS_PHYS_ADDR 0x11900000 /* 012345 */
151#define AU1550_PSC0_PHYS_ADDR 0x11A00000 /* 34 */
152#define AU1550_PSC1_PHYS_ADDR 0x11B00000 /* 34 */
153#define AU1000_MEM_PHYS_ADDR 0x14000000 /* 01234 */
154#define AU1000_STATIC_MEM_PHYS_ADDR 0x14001000 /* 01234 */
155#define AU1300_UDMA_PHYS_ADDR 0x14001800 /* 5 */
156#define AU1000_DMA_PHYS_ADDR 0x14002000 /* 012 */
157#define AU1550_DBDMA_PHYS_ADDR 0x14002000 /* 345 */
158#define AU1550_DBDMA_CONF_PHYS_ADDR 0x14003000 /* 345 */
159#define AU1000_MACDMA0_PHYS_ADDR 0x14004000 /* 0123 */
160#define AU1000_MACDMA1_PHYS_ADDR 0x14004200 /* 0123 */
161#define AU1200_CIM_PHYS_ADDR 0x14004000 /* 45 */
162#define AU1500_PCI_PHYS_ADDR 0x14005000 /* 13 */
163#define AU1550_PE_PHYS_ADDR 0x14008000 /* 3 */
164#define AU1200_MAEBE_PHYS_ADDR 0x14010000 /* 4 */
165#define AU1200_MAEFE_PHYS_ADDR 0x14012000 /* 4 */
166#define AU1300_MAEITE_PHYS_ADDR 0x14010000 /* 5 */
167#define AU1300_MAEMPE_PHYS_ADDR 0x14014000 /* 5 */
168#define AU1550_USB_OHCI_PHYS_ADDR 0x14020000 /* 3 */
169#define AU1200_USB_CTL_PHYS_ADDR 0x14020000 /* 4 */
170#define AU1200_USB_OTG_PHYS_ADDR 0x14020020 /* 4 */
171#define AU1200_USB_OHCI_PHYS_ADDR 0x14020100 /* 4 */
172#define AU1200_USB_EHCI_PHYS_ADDR 0x14020200 /* 4 */
173#define AU1200_USB_UDC_PHYS_ADDR 0x14022000 /* 4 */
174#define AU1300_USB_EHCI_PHYS_ADDR 0x14020000 /* 5 */
175#define AU1300_USB_OHCI0_PHYS_ADDR 0x14020400 /* 5 */
176#define AU1300_USB_OHCI1_PHYS_ADDR 0x14020800 /* 5 */
177#define AU1300_USB_CTL_PHYS_ADDR 0x14021000 /* 5 */
178#define AU1300_USB_OTG_PHYS_ADDR 0x14022000 /* 5 */
179#define AU1300_MAEBSA_PHYS_ADDR 0x14030000 /* 5 */
180#define AU1100_LCD_PHYS_ADDR 0x15000000 /* 2 */
181#define AU1200_LCD_PHYS_ADDR 0x15000000 /* 45 */
182#define AU1500_PCI_MEM_PHYS_ADDR 0x400000000ULL /* 13 */
183#define AU1500_PCI_IO_PHYS_ADDR 0x500000000ULL /* 13 */
184#define AU1500_PCI_CONFIG0_PHYS_ADDR 0x600000000ULL /* 13 */
185#define AU1500_PCI_CONFIG1_PHYS_ADDR 0x680000000ULL /* 13 */
186#define AU1000_PCMCIA_IO_PHYS_ADDR 0xF00000000ULL /* 012345 */
187#define AU1000_PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL /* 012345 */
188#define AU1000_PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL /* 012345 */
189
190/**********************************************************************/
191
192
193/*
194 * Au1300 GPIO+INT controller (GPIC) register offsets and bits
195 * Registers are 128bits (0x10 bytes), divided into 4 "banks".
196 */
197#define AU1300_GPIC_PINVAL 0x0000
198#define AU1300_GPIC_PINVALCLR 0x0010
199#define AU1300_GPIC_IPEND 0x0020
200#define AU1300_GPIC_PRIENC 0x0030
201#define AU1300_GPIC_IEN 0x0040 /* int_mask in manual */
202#define AU1300_GPIC_IDIS 0x0050 /* int_maskclr in manual */
203#define AU1300_GPIC_DMASEL 0x0060
204#define AU1300_GPIC_DEVSEL 0x0080
205#define AU1300_GPIC_DEVCLR 0x0090
206#define AU1300_GPIC_RSTVAL 0x00a0
207/* pin configuration space. one 32bit register for up to 128 IRQs */
208#define AU1300_GPIC_PINCFG 0x1000
209
210#define GPIC_GPIO_TO_BIT(gpio) \
211 (1 << ((gpio) & 0x1f))
212
213#define GPIC_GPIO_BANKOFF(gpio) \
214 (((gpio) >> 5) * 4)
215
216/* Pin Control bits: who owns the pin, what does it do */
217#define GPIC_CFG_PC_GPIN 0
218#define GPIC_CFG_PC_DEV 1
219#define GPIC_CFG_PC_GPOLOW 2
220#define GPIC_CFG_PC_GPOHIGH 3
221#define GPIC_CFG_PC_MASK 3
222
223/* assign pin to MIPS IRQ line */
224#define GPIC_CFG_IL_SET(x) (((x) & 3) << 2)
225#define GPIC_CFG_IL_MASK (3 << 2)
226
227/* pin interrupt type setup */
228#define GPIC_CFG_IC_OFF (0 << 4)
229#define GPIC_CFG_IC_LEVEL_LOW (1 << 4)
230#define GPIC_CFG_IC_LEVEL_HIGH (2 << 4)
231#define GPIC_CFG_IC_EDGE_FALL (5 << 4)
232#define GPIC_CFG_IC_EDGE_RISE (6 << 4)
233#define GPIC_CFG_IC_EDGE_BOTH (7 << 4)
234#define GPIC_CFG_IC_MASK (7 << 4)
235
236/* allow interrupt to wake cpu from 'wait' */
237#define GPIC_CFG_IDLEWAKE (1 << 7)
238
239/***********************************************************************/
240
241/* Au1000 SDRAM memory controller register offsets */
242#define AU1000_MEM_SDMODE0 0x0000
243#define AU1000_MEM_SDMODE1 0x0004
244#define AU1000_MEM_SDMODE2 0x0008
245#define AU1000_MEM_SDADDR0 0x000C
246#define AU1000_MEM_SDADDR1 0x0010
247#define AU1000_MEM_SDADDR2 0x0014
248#define AU1000_MEM_SDREFCFG 0x0018
249#define AU1000_MEM_SDPRECMD 0x001C
250#define AU1000_MEM_SDAUTOREF 0x0020
251#define AU1000_MEM_SDWRMD0 0x0024
252#define AU1000_MEM_SDWRMD1 0x0028
253#define AU1000_MEM_SDWRMD2 0x002C
254#define AU1000_MEM_SDSLEEP 0x0030
255#define AU1000_MEM_SDSMCKE 0x0034
256
257/* MEM_SDMODE register content definitions */
258#define MEM_SDMODE_F (1 << 22)
259#define MEM_SDMODE_SR (1 << 21)
260#define MEM_SDMODE_BS (1 << 20)
261#define MEM_SDMODE_RS (3 << 18)
262#define MEM_SDMODE_CS (7 << 15)
263#define MEM_SDMODE_TRAS (15 << 11)
264#define MEM_SDMODE_TMRD (3 << 9)
265#define MEM_SDMODE_TWR (3 << 7)
266#define MEM_SDMODE_TRP (3 << 5)
267#define MEM_SDMODE_TRCD (3 << 3)
268#define MEM_SDMODE_TCL (7 << 0)
269
270#define MEM_SDMODE_BS_2Bank (0 << 20)
271#define MEM_SDMODE_BS_4Bank (1 << 20)
272#define MEM_SDMODE_RS_11Row (0 << 18)
273#define MEM_SDMODE_RS_12Row (1 << 18)
274#define MEM_SDMODE_RS_13Row (2 << 18)
275#define MEM_SDMODE_RS_N(N) ((N) << 18)
276#define MEM_SDMODE_CS_7Col (0 << 15)
277#define MEM_SDMODE_CS_8Col (1 << 15)
278#define MEM_SDMODE_CS_9Col (2 << 15)
279#define MEM_SDMODE_CS_10Col (3 << 15)
280#define MEM_SDMODE_CS_11Col (4 << 15)
281#define MEM_SDMODE_CS_N(N) ((N) << 15)
282#define MEM_SDMODE_TRAS_N(N) ((N) << 11)
283#define MEM_SDMODE_TMRD_N(N) ((N) << 9)
284#define MEM_SDMODE_TWR_N(N) ((N) << 7)
285#define MEM_SDMODE_TRP_N(N) ((N) << 5)
286#define MEM_SDMODE_TRCD_N(N) ((N) << 3)
287#define MEM_SDMODE_TCL_N(N) ((N) << 0)
288
289/* MEM_SDADDR register contents definitions */
290#define MEM_SDADDR_E (1 << 20)
291#define MEM_SDADDR_CSBA (0x03FF << 10)
292#define MEM_SDADDR_CSMASK (0x03FF << 0)
293#define MEM_SDADDR_CSBA_N(N) ((N) & (0x03FF << 22) >> 12)
294#define MEM_SDADDR_CSMASK_N(N) ((N)&(0x03FF << 22) >> 22)
295
296/* MEM_SDREFCFG register content definitions */
297#define MEM_SDREFCFG_TRC (15 << 28)
298#define MEM_SDREFCFG_TRPM (3 << 26)
299#define MEM_SDREFCFG_E (1 << 25)
300#define MEM_SDREFCFG_RE (0x1ffffff << 0)
301#define MEM_SDREFCFG_TRC_N(N) ((N) << MEM_SDREFCFG_TRC)
302#define MEM_SDREFCFG_TRPM_N(N) ((N) << MEM_SDREFCFG_TRPM)
303#define MEM_SDREFCFG_REF_N(N) (N)
304
305/* Au1550 SDRAM Register Offsets */
306#define AU1550_MEM_SDMODE0 0x0800
307#define AU1550_MEM_SDMODE1 0x0808
308#define AU1550_MEM_SDMODE2 0x0810
309#define AU1550_MEM_SDADDR0 0x0820
310#define AU1550_MEM_SDADDR1 0x0828
311#define AU1550_MEM_SDADDR2 0x0830
312#define AU1550_MEM_SDCONFIGA 0x0840
313#define AU1550_MEM_SDCONFIGB 0x0848
314#define AU1550_MEM_SDSTAT 0x0850
315#define AU1550_MEM_SDERRADDR 0x0858
316#define AU1550_MEM_SDSTRIDE0 0x0860
317#define AU1550_MEM_SDSTRIDE1 0x0868
318#define AU1550_MEM_SDSTRIDE2 0x0870
319#define AU1550_MEM_SDWRMD0 0x0880
320#define AU1550_MEM_SDWRMD1 0x0888
321#define AU1550_MEM_SDWRMD2 0x0890
322#define AU1550_MEM_SDPRECMD 0x08C0
323#define AU1550_MEM_SDAUTOREF 0x08C8
324#define AU1550_MEM_SDSREF 0x08D0
325#define AU1550_MEM_SDSLEEP MEM_SDSREF
326
327/* Static Bus Controller register offsets */
328#define AU1000_MEM_STCFG0 0x000
329#define AU1000_MEM_STTIME0 0x004
330#define AU1000_MEM_STADDR0 0x008
331#define AU1000_MEM_STCFG1 0x010
332#define AU1000_MEM_STTIME1 0x014
333#define AU1000_MEM_STADDR1 0x018
334#define AU1000_MEM_STCFG2 0x020
335#define AU1000_MEM_STTIME2 0x024
336#define AU1000_MEM_STADDR2 0x028
337#define AU1000_MEM_STCFG3 0x030
338#define AU1000_MEM_STTIME3 0x034
339#define AU1000_MEM_STADDR3 0x038
340#define AU1000_MEM_STNDCTL 0x100
341#define AU1000_MEM_STSTAT 0x104
342
343#define MEM_STNAND_CMD 0x0
344#define MEM_STNAND_ADDR 0x4
345#define MEM_STNAND_DATA 0x20
346
347
348/* Programmable Counters 0 and 1 */
349#define AU1000_SYS_CNTRCTRL 0x14
350# define SYS_CNTRL_E1S (1 << 23)
351# define SYS_CNTRL_T1S (1 << 20)
352# define SYS_CNTRL_M21 (1 << 19)
353# define SYS_CNTRL_M11 (1 << 18)
354# define SYS_CNTRL_M01 (1 << 17)
355# define SYS_CNTRL_C1S (1 << 16)
356# define SYS_CNTRL_BP (1 << 14)
357# define SYS_CNTRL_EN1 (1 << 13)
358# define SYS_CNTRL_BT1 (1 << 12)
359# define SYS_CNTRL_EN0 (1 << 11)
360# define SYS_CNTRL_BT0 (1 << 10)
361# define SYS_CNTRL_E0 (1 << 8)
362# define SYS_CNTRL_E0S (1 << 7)
363# define SYS_CNTRL_32S (1 << 5)
364# define SYS_CNTRL_T0S (1 << 4)
365# define SYS_CNTRL_M20 (1 << 3)
366# define SYS_CNTRL_M10 (1 << 2)
367# define SYS_CNTRL_M00 (1 << 1)
368# define SYS_CNTRL_C0S (1 << 0)
369
370/* Programmable Counter 0 Registers */
371#define AU1000_SYS_TOYTRIM 0x00
372#define AU1000_SYS_TOYWRITE 0x04
373#define AU1000_SYS_TOYMATCH0 0x08
374#define AU1000_SYS_TOYMATCH1 0x0c
375#define AU1000_SYS_TOYMATCH2 0x10
376#define AU1000_SYS_TOYREAD 0x40
377
378/* Programmable Counter 1 Registers */
379#define AU1000_SYS_RTCTRIM 0x44
380#define AU1000_SYS_RTCWRITE 0x48
381#define AU1000_SYS_RTCMATCH0 0x4c
382#define AU1000_SYS_RTCMATCH1 0x50
383#define AU1000_SYS_RTCMATCH2 0x54
384#define AU1000_SYS_RTCREAD 0x58
385
386
387/* GPIO */
388#define AU1000_SYS_PINFUNC 0x2C
389# define SYS_PF_USB (1 << 15) /* 2nd USB device/host */
390# define SYS_PF_U3 (1 << 14) /* GPIO23/U3TXD */
391# define SYS_PF_U2 (1 << 13) /* GPIO22/U2TXD */
392# define SYS_PF_U1 (1 << 12) /* GPIO21/U1TXD */
393# define SYS_PF_SRC (1 << 11) /* GPIO6/SROMCKE */
394# define SYS_PF_CK5 (1 << 10) /* GPIO3/CLK5 */
395# define SYS_PF_CK4 (1 << 9) /* GPIO2/CLK4 */
396# define SYS_PF_IRF (1 << 8) /* GPIO15/IRFIRSEL */
397# define SYS_PF_UR3 (1 << 7) /* GPIO[14:9]/UART3 */
398# define SYS_PF_I2D (1 << 6) /* GPIO8/I2SDI */
399# define SYS_PF_I2S (1 << 5) /* I2S/GPIO[29:31] */
400# define SYS_PF_NI2 (1 << 4) /* NI2/GPIO[24:28] */
401# define SYS_PF_U0 (1 << 3) /* U0TXD/GPIO20 */
402# define SYS_PF_RD (1 << 2) /* IRTXD/GPIO19 */
403# define SYS_PF_A97 (1 << 1) /* AC97/SSL1 */
404# define SYS_PF_S0 (1 << 0) /* SSI_0/GPIO[16:18] */
405
406/* Au1100 only */
407# define SYS_PF_PC (1 << 18) /* PCMCIA/GPIO[207:204] */
408# define SYS_PF_LCD (1 << 17) /* extern lcd/GPIO[203:200] */
409# define SYS_PF_CS (1 << 16) /* EXTCLK0/32KHz to gpio2 */
410# define SYS_PF_EX0 (1 << 9) /* GPIO2/clock */
411
412/* Au1550 only. Redefines lots of pins */
413# define SYS_PF_PSC2_MASK (7 << 17)
414# define SYS_PF_PSC2_AC97 0
415# define SYS_PF_PSC2_SPI 0
416# define SYS_PF_PSC2_I2S (1 << 17)
417# define SYS_PF_PSC2_SMBUS (3 << 17)
418# define SYS_PF_PSC2_GPIO (7 << 17)
419# define SYS_PF_PSC3_MASK (7 << 20)
420# define SYS_PF_PSC3_AC97 0
421# define SYS_PF_PSC3_SPI 0
422# define SYS_PF_PSC3_I2S (1 << 20)
423# define SYS_PF_PSC3_SMBUS (3 << 20)
424# define SYS_PF_PSC3_GPIO (7 << 20)
425# define SYS_PF_PSC1_S1 (1 << 1)
426# define SYS_PF_MUST_BE_SET ((1 << 5) | (1 << 2))
427
428/* Au1200 only */
429#define SYS_PINFUNC_DMA (1 << 31)
430#define SYS_PINFUNC_S0A (1 << 30)
431#define SYS_PINFUNC_S1A (1 << 29)
432#define SYS_PINFUNC_LP0 (1 << 28)
433#define SYS_PINFUNC_LP1 (1 << 27)
434#define SYS_PINFUNC_LD16 (1 << 26)
435#define SYS_PINFUNC_LD8 (1 << 25)
436#define SYS_PINFUNC_LD1 (1 << 24)
437#define SYS_PINFUNC_LD0 (1 << 23)
438#define SYS_PINFUNC_P1A (3 << 21)
439#define SYS_PINFUNC_P1B (1 << 20)
440#define SYS_PINFUNC_FS3 (1 << 19)
441#define SYS_PINFUNC_P0A (3 << 17)
442#define SYS_PINFUNC_CS (1 << 16)
443#define SYS_PINFUNC_CIM (1 << 15)
444#define SYS_PINFUNC_P1C (1 << 14)
445#define SYS_PINFUNC_U1T (1 << 12)
446#define SYS_PINFUNC_U1R (1 << 11)
447#define SYS_PINFUNC_EX1 (1 << 10)
448#define SYS_PINFUNC_EX0 (1 << 9)
449#define SYS_PINFUNC_U0R (1 << 8)
450#define SYS_PINFUNC_MC (1 << 7)
451#define SYS_PINFUNC_S0B (1 << 6)
452#define SYS_PINFUNC_S0C (1 << 5)
453#define SYS_PINFUNC_P0B (1 << 4)
454#define SYS_PINFUNC_U0T (1 << 3)
455#define SYS_PINFUNC_S1B (1 << 2)
456
457/* Power Management */
458#define AU1000_SYS_SCRATCH0 0x18
459#define AU1000_SYS_SCRATCH1 0x1c
460#define AU1000_SYS_WAKEMSK 0x34
461#define AU1000_SYS_ENDIAN 0x38
462#define AU1000_SYS_POWERCTRL 0x3c
463#define AU1000_SYS_WAKESRC 0x5c
464#define AU1000_SYS_SLPPWR 0x78
465#define AU1000_SYS_SLEEP 0x7c
466
467#define SYS_WAKEMSK_D2 (1 << 9)
468#define SYS_WAKEMSK_M2 (1 << 8)
469#define SYS_WAKEMSK_GPIO(x) (1 << (x))
470
471/* Clock Controller */
472#define AU1000_SYS_FREQCTRL0 0x20
473#define AU1000_SYS_FREQCTRL1 0x24
474#define AU1000_SYS_CLKSRC 0x28
475#define AU1000_SYS_CPUPLL 0x60
476#define AU1000_SYS_AUXPLL 0x64
477#define AU1300_SYS_AUXPLL2 0x68
478
479
480/**********************************************************************/
481
482
483/* The PCI chip selects are outside the 32bit space, and since we can't
484 * just program the 36bit addresses into BARs, we have to take a chunk
485 * out of the 32bit space and reserve it for PCI. When these addresses
486 * are ioremap()ed, they'll be fixed up to the real 36bit address before
487 * being passed to the real ioremap function.
488 */
489#define ALCHEMY_PCI_MEMWIN_START (AU1500_PCI_MEM_PHYS_ADDR >> 4)
490#define ALCHEMY_PCI_MEMWIN_END (ALCHEMY_PCI_MEMWIN_START + 0x0FFFFFFF)
491
492/* for PCI IO it's simpler because we get to do the ioremap ourselves and then
493 * adjust the device's resources.
494 */
495#define ALCHEMY_PCI_IOWIN_START 0x00001000
496#define ALCHEMY_PCI_IOWIN_END 0x0000FFFF
497
498#ifdef CONFIG_PCI
499
500#define IOPORT_RESOURCE_START 0x00001000 /* skip legacy probing */
501#define IOPORT_RESOURCE_END 0xffffffff
502#define IOMEM_RESOURCE_START 0x10000000
503#define IOMEM_RESOURCE_END 0xfffffffffULL
504
505#else
506
507/* Don't allow any legacy ports probing */
508#define IOPORT_RESOURCE_START 0x10000000
509#define IOPORT_RESOURCE_END 0xffffffff
510#define IOMEM_RESOURCE_START 0x10000000
511#define IOMEM_RESOURCE_END 0xfffffffffULL
512
513#endif
514
515/* PCI controller block register offsets */
516#define PCI_REG_CMEM 0x0000
517#define PCI_REG_CONFIG 0x0004
518#define PCI_REG_B2BMASK_CCH 0x0008
519#define PCI_REG_B2BBASE0_VID 0x000C
520#define PCI_REG_B2BBASE1_SID 0x0010
521#define PCI_REG_MWMASK_DEV 0x0014
522#define PCI_REG_MWBASE_REV_CCL 0x0018
523#define PCI_REG_ERR_ADDR 0x001C
524#define PCI_REG_SPEC_INTACK 0x0020
525#define PCI_REG_ID 0x0100
526#define PCI_REG_STATCMD 0x0104
527#define PCI_REG_CLASSREV 0x0108
528#define PCI_REG_PARAM 0x010C
529#define PCI_REG_MBAR 0x0110
530#define PCI_REG_TIMEOUT 0x0140
531
532/* PCI controller block register bits */
533#define PCI_CMEM_E (1 << 28) /* enable cacheable memory */
534#define PCI_CMEM_CMBASE(x) (((x) & 0x3fff) << 14)
535#define PCI_CMEM_CMMASK(x) ((x) & 0x3fff)
536#define PCI_CONFIG_ERD (1 << 27) /* pci error during R/W */
537#define PCI_CONFIG_ET (1 << 26) /* error in target mode */
538#define PCI_CONFIG_EF (1 << 25) /* fatal error */
539#define PCI_CONFIG_EP (1 << 24) /* parity error */
540#define PCI_CONFIG_EM (1 << 23) /* multiple errors */
541#define PCI_CONFIG_BM (1 << 22) /* bad master error */
542#define PCI_CONFIG_PD (1 << 20) /* PCI Disable */
543#define PCI_CONFIG_BME (1 << 19) /* Byte Mask Enable for reads */
544#define PCI_CONFIG_NC (1 << 16) /* mark mem access non-coherent */
545#define PCI_CONFIG_IA (1 << 15) /* INTA# enabled (target mode) */
546#define PCI_CONFIG_IP (1 << 13) /* int on PCI_PERR# */
547#define PCI_CONFIG_IS (1 << 12) /* int on PCI_SERR# */
548#define PCI_CONFIG_IMM (1 << 11) /* int on master abort */
549#define PCI_CONFIG_ITM (1 << 10) /* int on target abort (as master) */
550#define PCI_CONFIG_ITT (1 << 9) /* int on target abort (as target) */
551#define PCI_CONFIG_IPB (1 << 8) /* int on PERR# in bus master acc */
552#define PCI_CONFIG_SIC_NO (0 << 6) /* no byte mask changes */
553#define PCI_CONFIG_SIC_BA_ADR (1 << 6) /* on byte/hw acc, invert adr bits */
554#define PCI_CONFIG_SIC_HWA_DAT (2 << 6) /* on halfword acc, swap data */
555#define PCI_CONFIG_SIC_ALL (3 << 6) /* swap data bytes on all accesses */
556#define PCI_CONFIG_ST (1 << 5) /* swap data by target transactions */
557#define PCI_CONFIG_SM (1 << 4) /* swap data from PCI ctl */
558#define PCI_CONFIG_AEN (1 << 3) /* enable internal arbiter */
559#define PCI_CONFIG_R2H (1 << 2) /* REQ2# to hi-prio arbiter */
560#define PCI_CONFIG_R1H (1 << 1) /* REQ1# to hi-prio arbiter */
561#define PCI_CONFIG_CH (1 << 0) /* PCI ctl to hi-prio arbiter */
562#define PCI_B2BMASK_B2BMASK(x) (((x) & 0xffff) << 16)
563#define PCI_B2BMASK_CCH(x) ((x) & 0xffff) /* 16 upper bits of class code */
564#define PCI_B2BBASE0_VID_B0(x) (((x) & 0xffff) << 16)
565#define PCI_B2BBASE0_VID_SV(x) ((x) & 0xffff)
566#define PCI_B2BBASE1_SID_B1(x) (((x) & 0xffff) << 16)
567#define PCI_B2BBASE1_SID_SI(x) ((x) & 0xffff)
568#define PCI_MWMASKDEV_MWMASK(x) (((x) & 0xffff) << 16)
569#define PCI_MWMASKDEV_DEVID(x) ((x) & 0xffff)
570#define PCI_MWBASEREVCCL_BASE(x) (((x) & 0xffff) << 16)
571#define PCI_MWBASEREVCCL_REV(x) (((x) & 0xff) << 8)
572#define PCI_MWBASEREVCCL_CCL(x) ((x) & 0xff)
573#define PCI_ID_DID(x) (((x) & 0xffff) << 16)
574#define PCI_ID_VID(x) ((x) & 0xffff)
575#define PCI_STATCMD_STATUS(x) (((x) & 0xffff) << 16)
576#define PCI_STATCMD_CMD(x) ((x) & 0xffff)
577#define PCI_CLASSREV_CLASS(x) (((x) & 0x00ffffff) << 8)
578#define PCI_CLASSREV_REV(x) ((x) & 0xff)
579#define PCI_PARAM_BIST(x) (((x) & 0xff) << 24)
580#define PCI_PARAM_HT(x) (((x) & 0xff) << 16)
581#define PCI_PARAM_LT(x) (((x) & 0xff) << 8)
582#define PCI_PARAM_CLS(x) ((x) & 0xff)
583#define PCI_TIMEOUT_RETRIES(x) (((x) & 0xff) << 8) /* max retries */
584#define PCI_TIMEOUT_TO(x) ((x) & 0xff) /* target ready timeout */
585
586
587/**********************************************************************/
588
37 589
38#ifndef _LANGUAGE_ASSEMBLY 590#ifndef _LANGUAGE_ASSEMBLY
39 591
@@ -45,52 +597,36 @@
45 597
46#include <asm/cpu.h> 598#include <asm/cpu.h>
47 599
48/* cpu pipeline flush */ 600/* helpers to access the SYS_* registers */
49void static inline au_sync(void) 601static inline unsigned long alchemy_rdsys(int regofs)
50{ 602{
51 __asm__ volatile ("sync"); 603 void __iomem *b = (void __iomem *)KSEG1ADDR(AU1000_SYS_PHYS_ADDR);
52}
53 604
54void static inline au_sync_udelay(int us) 605 return __raw_readl(b + regofs);
55{
56 __asm__ volatile ("sync");
57 udelay(us);
58} 606}
59 607
60void static inline au_sync_delay(int ms) 608static inline void alchemy_wrsys(unsigned long v, int regofs)
61{ 609{
62 __asm__ volatile ("sync"); 610 void __iomem *b = (void __iomem *)KSEG1ADDR(AU1000_SYS_PHYS_ADDR);
63 mdelay(ms);
64}
65 611
66void static inline au_writeb(u8 val, unsigned long reg) 612 __raw_writel(v, b + regofs);
67{ 613 wmb(); /* drain writebuffer */
68 *(volatile u8 *)reg = val;
69} 614}
70 615
71void static inline au_writew(u16 val, unsigned long reg) 616/* helpers to access static memctrl registers */
617static inline unsigned long alchemy_rdsmem(int regofs)
72{ 618{
73 *(volatile u16 *)reg = val; 619 void __iomem *b = (void __iomem *)KSEG1ADDR(AU1000_STATIC_MEM_PHYS_ADDR);
74}
75 620
76void static inline au_writel(u32 val, unsigned long reg) 621 return __raw_readl(b + regofs);
77{
78 *(volatile u32 *)reg = val;
79} 622}
80 623
81static inline u8 au_readb(unsigned long reg) 624static inline void alchemy_wrsmem(unsigned long v, int regofs)
82{ 625{
83 return *(volatile u8 *)reg; 626 void __iomem *b = (void __iomem *)KSEG1ADDR(AU1000_STATIC_MEM_PHYS_ADDR);
84}
85 627
86static inline u16 au_readw(unsigned long reg) 628 __raw_writel(v, b + regofs);
87{ 629 wmb(); /* drain writebuffer */
88 return *(volatile u16 *)reg;
89}
90
91static inline u32 au_readl(unsigned long reg)
92{
93 return *(volatile u32 *)reg;
94} 630}
95 631
96/* Early Au1000 have a write-only SYS_CPUPLL register. */ 632/* Early Au1000 have a write-only SYS_CPUPLL register. */
@@ -192,19 +728,20 @@ static inline void alchemy_uart_enable(u32 uart_phys)
192 /* reset, enable clock, deassert reset */ 728 /* reset, enable clock, deassert reset */
193 if ((__raw_readl(addr + 0x100) & 3) != 3) { 729 if ((__raw_readl(addr + 0x100) & 3) != 3) {
194 __raw_writel(0, addr + 0x100); 730 __raw_writel(0, addr + 0x100);
195 wmb(); 731 wmb(); /* drain writebuffer */
196 __raw_writel(1, addr + 0x100); 732 __raw_writel(1, addr + 0x100);
197 wmb(); 733 wmb(); /* drain writebuffer */
198 } 734 }
199 __raw_writel(3, addr + 0x100); 735 __raw_writel(3, addr + 0x100);
200 wmb(); 736 wmb(); /* drain writebuffer */
201} 737}
202 738
203static inline void alchemy_uart_disable(u32 uart_phys) 739static inline void alchemy_uart_disable(u32 uart_phys)
204{ 740{
205 void __iomem *addr = (void __iomem *)KSEG1ADDR(uart_phys); 741 void __iomem *addr = (void __iomem *)KSEG1ADDR(uart_phys);
742
206 __raw_writel(0, addr + 0x100); /* UART_MOD_CNTRL */ 743 __raw_writel(0, addr + 0x100); /* UART_MOD_CNTRL */
207 wmb(); 744 wmb(); /* drain writebuffer */
208} 745}
209 746
210static inline void alchemy_uart_putchar(u32 uart_phys, u8 c) 747static inline void alchemy_uart_putchar(u32 uart_phys, u8 c)
@@ -223,7 +760,7 @@ static inline void alchemy_uart_putchar(u32 uart_phys, u8 c)
223 } while (--timeout); 760 } while (--timeout);
224 761
225 __raw_writel(c, base + 0x04); /* tx */ 762 __raw_writel(c, base + 0x04); /* tx */
226 wmb(); 763 wmb(); /* drain writebuffer */
227} 764}
228 765
229/* return number of ethernet MACs on a given cputype */ 766/* return number of ethernet MACs on a given cputype */
@@ -240,20 +777,13 @@ static inline int alchemy_get_macs(int type)
240 return 0; 777 return 0;
241} 778}
242 779
243/* arch/mips/au1000/common/clocks.c */
244extern void set_au1x00_speed(unsigned int new_freq);
245extern unsigned int get_au1x00_speed(void);
246extern void set_au1x00_uart_baud_base(unsigned long new_baud_base);
247extern unsigned long get_au1x00_uart_baud_base(void);
248extern unsigned long au1xxx_calc_clock(void);
249
250/* PM: arch/mips/alchemy/common/sleeper.S, power.c, irq.c */ 780/* PM: arch/mips/alchemy/common/sleeper.S, power.c, irq.c */
251void alchemy_sleep_au1000(void); 781void alchemy_sleep_au1000(void);
252void alchemy_sleep_au1550(void); 782void alchemy_sleep_au1550(void);
253void alchemy_sleep_au1300(void); 783void alchemy_sleep_au1300(void);
254void au_sleep(void); 784void au_sleep(void);
255 785
256/* USB: drivers/usb/host/alchemy-common.c */ 786/* USB: arch/mips/alchemy/common/usb.c */
257enum alchemy_usb_block { 787enum alchemy_usb_block {
258 ALCHEMY_USB_OHCI0, 788 ALCHEMY_USB_OHCI0,
259 ALCHEMY_USB_UDC0, 789 ALCHEMY_USB_UDC0,
@@ -272,6 +802,20 @@ struct alchemy_pci_platdata {
272 unsigned long pci_cfg_clr; 802 unsigned long pci_cfg_clr;
273}; 803};
274 804
805/* The IrDA peripheral has an IRFIRSEL pin, but on the DB/PB boards it's
806 * not used to select FIR/SIR mode on the transceiver but as a GPIO.
807 * Instead a CPLD has to be told about the mode. The driver calls the
808 * set_phy_mode() function in addition to driving the IRFIRSEL pin.
809 */
810#define AU1000_IRDA_PHY_MODE_OFF 0
811#define AU1000_IRDA_PHY_MODE_SIR 1
812#define AU1000_IRDA_PHY_MODE_FIR 2
813
814struct au1k_irda_platform_data {
815 void (*set_phy_mode)(int mode);
816};
817
818
275/* Multifunction pins: Each of these pins can either be assigned to the 819/* Multifunction pins: Each of these pins can either be assigned to the
276 * GPIO controller or a on-chip peripheral. 820 * GPIO controller or a on-chip peripheral.
277 * Call "au1300_pinfunc_to_dev()" or "au1300_pinfunc_to_gpio()" to 821 * Call "au1300_pinfunc_to_dev()" or "au1300_pinfunc_to_gpio()" to
@@ -344,20 +888,6 @@ enum au1300_vss_block {
344 888
345extern void au1300_vss_block_control(int block, int enable); 889extern void au1300_vss_block_control(int block, int enable);
346 890
347
348/* SOC Interrupt numbers */
349/* Au1000-style (IC0/1): 2 controllers with 32 sources each */
350#define AU1000_INTC0_INT_BASE (MIPS_CPU_IRQ_BASE + 8)
351#define AU1000_INTC0_INT_LAST (AU1000_INTC0_INT_BASE + 31)
352#define AU1000_INTC1_INT_BASE (AU1000_INTC0_INT_LAST + 1)
353#define AU1000_INTC1_INT_LAST (AU1000_INTC1_INT_BASE + 31)
354#define AU1000_MAX_INTR AU1000_INTC1_INT_LAST
355
356/* Au1300-style (GPIC): 1 controller with up to 128 sources */
357#define ALCHEMY_GPIC_INT_BASE (MIPS_CPU_IRQ_BASE + 8)
358#define ALCHEMY_GPIC_INT_NUM 128
359#define ALCHEMY_GPIC_INT_LAST (ALCHEMY_GPIC_INT_BASE + ALCHEMY_GPIC_INT_NUM - 1)
360
361enum soc_au1000_ints { 891enum soc_au1000_ints {
362 AU1000_FIRST_INT = AU1000_INTC0_INT_BASE, 892 AU1000_FIRST_INT = AU1000_INTC0_INT_BASE,
363 AU1000_UART0_INT = AU1000_FIRST_INT, 893 AU1000_UART0_INT = AU1000_FIRST_INT,
@@ -678,885 +1208,4 @@ enum soc_au1200_ints {
678 1208
679#endif /* !defined (_LANGUAGE_ASSEMBLY) */ 1209#endif /* !defined (_LANGUAGE_ASSEMBLY) */
680 1210
681/* Au1300 peripheral interrupt numbers */
682#define AU1300_FIRST_INT (ALCHEMY_GPIC_INT_BASE)
683#define AU1300_UART1_INT (AU1300_FIRST_INT + 17)
684#define AU1300_UART2_INT (AU1300_FIRST_INT + 25)
685#define AU1300_UART3_INT (AU1300_FIRST_INT + 27)
686#define AU1300_SD1_INT (AU1300_FIRST_INT + 32)
687#define AU1300_SD2_INT (AU1300_FIRST_INT + 38)
688#define AU1300_PSC0_INT (AU1300_FIRST_INT + 48)
689#define AU1300_PSC1_INT (AU1300_FIRST_INT + 52)
690#define AU1300_PSC2_INT (AU1300_FIRST_INT + 56)
691#define AU1300_PSC3_INT (AU1300_FIRST_INT + 60)
692#define AU1300_NAND_INT (AU1300_FIRST_INT + 62)
693#define AU1300_DDMA_INT (AU1300_FIRST_INT + 75)
694#define AU1300_MMU_INT (AU1300_FIRST_INT + 76)
695#define AU1300_MPU_INT (AU1300_FIRST_INT + 77)
696#define AU1300_GPU_INT (AU1300_FIRST_INT + 78)
697#define AU1300_UDMA_INT (AU1300_FIRST_INT + 79)
698#define AU1300_TOY_INT (AU1300_FIRST_INT + 80)
699#define AU1300_TOY_MATCH0_INT (AU1300_FIRST_INT + 81)
700#define AU1300_TOY_MATCH1_INT (AU1300_FIRST_INT + 82)
701#define AU1300_TOY_MATCH2_INT (AU1300_FIRST_INT + 83)
702#define AU1300_RTC_INT (AU1300_FIRST_INT + 84)
703#define AU1300_RTC_MATCH0_INT (AU1300_FIRST_INT + 85)
704#define AU1300_RTC_MATCH1_INT (AU1300_FIRST_INT + 86)
705#define AU1300_RTC_MATCH2_INT (AU1300_FIRST_INT + 87)
706#define AU1300_UART0_INT (AU1300_FIRST_INT + 88)
707#define AU1300_SD0_INT (AU1300_FIRST_INT + 89)
708#define AU1300_USB_INT (AU1300_FIRST_INT + 90)
709#define AU1300_LCD_INT (AU1300_FIRST_INT + 91)
710#define AU1300_BSA_INT (AU1300_FIRST_INT + 92)
711#define AU1300_MPE_INT (AU1300_FIRST_INT + 93)
712#define AU1300_ITE_INT (AU1300_FIRST_INT + 94)
713#define AU1300_AES_INT (AU1300_FIRST_INT + 95)
714#define AU1300_CIM_INT (AU1300_FIRST_INT + 96)
715
716/**********************************************************************/
717
718/*
719 * Physical base addresses for integrated peripherals
720 * 0..au1000 1..au1500 2..au1100 3..au1550 4..au1200 5..au1300
721 */
722
723#define AU1000_AC97_PHYS_ADDR 0x10000000 /* 012 */
724#define AU1300_ROM_PHYS_ADDR 0x10000000 /* 5 */
725#define AU1300_OTP_PHYS_ADDR 0x10002000 /* 5 */
726#define AU1300_VSS_PHYS_ADDR 0x10003000 /* 5 */
727#define AU1300_UART0_PHYS_ADDR 0x10100000 /* 5 */
728#define AU1300_UART1_PHYS_ADDR 0x10101000 /* 5 */
729#define AU1300_UART2_PHYS_ADDR 0x10102000 /* 5 */
730#define AU1300_UART3_PHYS_ADDR 0x10103000 /* 5 */
731#define AU1000_USB_OHCI_PHYS_ADDR 0x10100000 /* 012 */
732#define AU1000_USB_UDC_PHYS_ADDR 0x10200000 /* 0123 */
733#define AU1300_GPIC_PHYS_ADDR 0x10200000 /* 5 */
734#define AU1000_IRDA_PHYS_ADDR 0x10300000 /* 02 */
735#define AU1200_AES_PHYS_ADDR 0x10300000 /* 45 */
736#define AU1000_IC0_PHYS_ADDR 0x10400000 /* 01234 */
737#define AU1300_GPU_PHYS_ADDR 0x10500000 /* 5 */
738#define AU1000_MAC0_PHYS_ADDR 0x10500000 /* 023 */
739#define AU1000_MAC1_PHYS_ADDR 0x10510000 /* 023 */
740#define AU1000_MACEN_PHYS_ADDR 0x10520000 /* 023 */
741#define AU1100_SD0_PHYS_ADDR 0x10600000 /* 245 */
742#define AU1300_SD1_PHYS_ADDR 0x10601000 /* 5 */
743#define AU1300_SD2_PHYS_ADDR 0x10602000 /* 5 */
744#define AU1100_SD1_PHYS_ADDR 0x10680000 /* 24 */
745#define AU1300_SYS_PHYS_ADDR 0x10900000 /* 5 */
746#define AU1550_PSC2_PHYS_ADDR 0x10A00000 /* 3 */
747#define AU1550_PSC3_PHYS_ADDR 0x10B00000 /* 3 */
748#define AU1300_PSC0_PHYS_ADDR 0x10A00000 /* 5 */
749#define AU1300_PSC1_PHYS_ADDR 0x10A01000 /* 5 */
750#define AU1300_PSC2_PHYS_ADDR 0x10A02000 /* 5 */
751#define AU1300_PSC3_PHYS_ADDR 0x10A03000 /* 5 */
752#define AU1000_I2S_PHYS_ADDR 0x11000000 /* 02 */
753#define AU1500_MAC0_PHYS_ADDR 0x11500000 /* 1 */
754#define AU1500_MAC1_PHYS_ADDR 0x11510000 /* 1 */
755#define AU1500_MACEN_PHYS_ADDR 0x11520000 /* 1 */
756#define AU1000_UART0_PHYS_ADDR 0x11100000 /* 01234 */
757#define AU1200_SWCNT_PHYS_ADDR 0x1110010C /* 4 */
758#define AU1000_UART1_PHYS_ADDR 0x11200000 /* 0234 */
759#define AU1000_UART2_PHYS_ADDR 0x11300000 /* 0 */
760#define AU1000_UART3_PHYS_ADDR 0x11400000 /* 0123 */
761#define AU1000_SSI0_PHYS_ADDR 0x11600000 /* 02 */
762#define AU1000_SSI1_PHYS_ADDR 0x11680000 /* 02 */
763#define AU1500_GPIO2_PHYS_ADDR 0x11700000 /* 1234 */
764#define AU1000_IC1_PHYS_ADDR 0x11800000 /* 01234 */
765#define AU1000_SYS_PHYS_ADDR 0x11900000 /* 012345 */
766#define AU1550_PSC0_PHYS_ADDR 0x11A00000 /* 34 */
767#define AU1550_PSC1_PHYS_ADDR 0x11B00000 /* 34 */
768#define AU1000_MEM_PHYS_ADDR 0x14000000 /* 01234 */
769#define AU1000_STATIC_MEM_PHYS_ADDR 0x14001000 /* 01234 */
770#define AU1300_UDMA_PHYS_ADDR 0x14001800 /* 5 */
771#define AU1000_DMA_PHYS_ADDR 0x14002000 /* 012 */
772#define AU1550_DBDMA_PHYS_ADDR 0x14002000 /* 345 */
773#define AU1550_DBDMA_CONF_PHYS_ADDR 0x14003000 /* 345 */
774#define AU1000_MACDMA0_PHYS_ADDR 0x14004000 /* 0123 */
775#define AU1000_MACDMA1_PHYS_ADDR 0x14004200 /* 0123 */
776#define AU1200_CIM_PHYS_ADDR 0x14004000 /* 45 */
777#define AU1500_PCI_PHYS_ADDR 0x14005000 /* 13 */
778#define AU1550_PE_PHYS_ADDR 0x14008000 /* 3 */
779#define AU1200_MAEBE_PHYS_ADDR 0x14010000 /* 4 */
780#define AU1200_MAEFE_PHYS_ADDR 0x14012000 /* 4 */
781#define AU1300_MAEITE_PHYS_ADDR 0x14010000 /* 5 */
782#define AU1300_MAEMPE_PHYS_ADDR 0x14014000 /* 5 */
783#define AU1550_USB_OHCI_PHYS_ADDR 0x14020000 /* 3 */
784#define AU1200_USB_CTL_PHYS_ADDR 0x14020000 /* 4 */
785#define AU1200_USB_OTG_PHYS_ADDR 0x14020020 /* 4 */
786#define AU1200_USB_OHCI_PHYS_ADDR 0x14020100 /* 4 */
787#define AU1200_USB_EHCI_PHYS_ADDR 0x14020200 /* 4 */
788#define AU1200_USB_UDC_PHYS_ADDR 0x14022000 /* 4 */
789#define AU1300_USB_EHCI_PHYS_ADDR 0x14020000 /* 5 */
790#define AU1300_USB_OHCI0_PHYS_ADDR 0x14020400 /* 5 */
791#define AU1300_USB_OHCI1_PHYS_ADDR 0x14020800 /* 5 */
792#define AU1300_USB_CTL_PHYS_ADDR 0x14021000 /* 5 */
793#define AU1300_USB_OTG_PHYS_ADDR 0x14022000 /* 5 */
794#define AU1300_MAEBSA_PHYS_ADDR 0x14030000 /* 5 */
795#define AU1100_LCD_PHYS_ADDR 0x15000000 /* 2 */
796#define AU1200_LCD_PHYS_ADDR 0x15000000 /* 45 */
797#define AU1500_PCI_MEM_PHYS_ADDR 0x400000000ULL /* 13 */
798#define AU1500_PCI_IO_PHYS_ADDR 0x500000000ULL /* 13 */
799#define AU1500_PCI_CONFIG0_PHYS_ADDR 0x600000000ULL /* 13 */
800#define AU1500_PCI_CONFIG1_PHYS_ADDR 0x680000000ULL /* 13 */
801#define AU1000_PCMCIA_IO_PHYS_ADDR 0xF00000000ULL /* 012345 */
802#define AU1000_PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL /* 012345 */
803#define AU1000_PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL /* 012345 */
804
805/**********************************************************************/
806
807
808/*
809 * Au1300 GPIO+INT controller (GPIC) register offsets and bits
810 * Registers are 128bits (0x10 bytes), divided into 4 "banks".
811 */
812#define AU1300_GPIC_PINVAL 0x0000
813#define AU1300_GPIC_PINVALCLR 0x0010
814#define AU1300_GPIC_IPEND 0x0020
815#define AU1300_GPIC_PRIENC 0x0030
816#define AU1300_GPIC_IEN 0x0040 /* int_mask in manual */
817#define AU1300_GPIC_IDIS 0x0050 /* int_maskclr in manual */
818#define AU1300_GPIC_DMASEL 0x0060
819#define AU1300_GPIC_DEVSEL 0x0080
820#define AU1300_GPIC_DEVCLR 0x0090
821#define AU1300_GPIC_RSTVAL 0x00a0
822/* pin configuration space. one 32bit register for up to 128 IRQs */
823#define AU1300_GPIC_PINCFG 0x1000
824
825#define GPIC_GPIO_TO_BIT(gpio) \
826 (1 << ((gpio) & 0x1f))
827
828#define GPIC_GPIO_BANKOFF(gpio) \
829 (((gpio) >> 5) * 4)
830
831/* Pin Control bits: who owns the pin, what does it do */
832#define GPIC_CFG_PC_GPIN 0
833#define GPIC_CFG_PC_DEV 1
834#define GPIC_CFG_PC_GPOLOW 2
835#define GPIC_CFG_PC_GPOHIGH 3
836#define GPIC_CFG_PC_MASK 3
837
838/* assign pin to MIPS IRQ line */
839#define GPIC_CFG_IL_SET(x) (((x) & 3) << 2)
840#define GPIC_CFG_IL_MASK (3 << 2)
841
842/* pin interrupt type setup */
843#define GPIC_CFG_IC_OFF (0 << 4)
844#define GPIC_CFG_IC_LEVEL_LOW (1 << 4)
845#define GPIC_CFG_IC_LEVEL_HIGH (2 << 4)
846#define GPIC_CFG_IC_EDGE_FALL (5 << 4)
847#define GPIC_CFG_IC_EDGE_RISE (6 << 4)
848#define GPIC_CFG_IC_EDGE_BOTH (7 << 4)
849#define GPIC_CFG_IC_MASK (7 << 4)
850
851/* allow interrupt to wake cpu from 'wait' */
852#define GPIC_CFG_IDLEWAKE (1 << 7)
853
854/***********************************************************************/
855
856/* Au1000 SDRAM memory controller register offsets */
857#define AU1000_MEM_SDMODE0 0x0000
858#define AU1000_MEM_SDMODE1 0x0004
859#define AU1000_MEM_SDMODE2 0x0008
860#define AU1000_MEM_SDADDR0 0x000C
861#define AU1000_MEM_SDADDR1 0x0010
862#define AU1000_MEM_SDADDR2 0x0014
863#define AU1000_MEM_SDREFCFG 0x0018
864#define AU1000_MEM_SDPRECMD 0x001C
865#define AU1000_MEM_SDAUTOREF 0x0020
866#define AU1000_MEM_SDWRMD0 0x0024
867#define AU1000_MEM_SDWRMD1 0x0028
868#define AU1000_MEM_SDWRMD2 0x002C
869#define AU1000_MEM_SDSLEEP 0x0030
870#define AU1000_MEM_SDSMCKE 0x0034
871
872/* MEM_SDMODE register content definitions */
873#define MEM_SDMODE_F (1 << 22)
874#define MEM_SDMODE_SR (1 << 21)
875#define MEM_SDMODE_BS (1 << 20)
876#define MEM_SDMODE_RS (3 << 18)
877#define MEM_SDMODE_CS (7 << 15)
878#define MEM_SDMODE_TRAS (15 << 11)
879#define MEM_SDMODE_TMRD (3 << 9)
880#define MEM_SDMODE_TWR (3 << 7)
881#define MEM_SDMODE_TRP (3 << 5)
882#define MEM_SDMODE_TRCD (3 << 3)
883#define MEM_SDMODE_TCL (7 << 0)
884
885#define MEM_SDMODE_BS_2Bank (0 << 20)
886#define MEM_SDMODE_BS_4Bank (1 << 20)
887#define MEM_SDMODE_RS_11Row (0 << 18)
888#define MEM_SDMODE_RS_12Row (1 << 18)
889#define MEM_SDMODE_RS_13Row (2 << 18)
890#define MEM_SDMODE_RS_N(N) ((N) << 18)
891#define MEM_SDMODE_CS_7Col (0 << 15)
892#define MEM_SDMODE_CS_8Col (1 << 15)
893#define MEM_SDMODE_CS_9Col (2 << 15)
894#define MEM_SDMODE_CS_10Col (3 << 15)
895#define MEM_SDMODE_CS_11Col (4 << 15)
896#define MEM_SDMODE_CS_N(N) ((N) << 15)
897#define MEM_SDMODE_TRAS_N(N) ((N) << 11)
898#define MEM_SDMODE_TMRD_N(N) ((N) << 9)
899#define MEM_SDMODE_TWR_N(N) ((N) << 7)
900#define MEM_SDMODE_TRP_N(N) ((N) << 5)
901#define MEM_SDMODE_TRCD_N(N) ((N) << 3)
902#define MEM_SDMODE_TCL_N(N) ((N) << 0)
903
904/* MEM_SDADDR register contents definitions */
905#define MEM_SDADDR_E (1 << 20)
906#define MEM_SDADDR_CSBA (0x03FF << 10)
907#define MEM_SDADDR_CSMASK (0x03FF << 0)
908#define MEM_SDADDR_CSBA_N(N) ((N) & (0x03FF << 22) >> 12)
909#define MEM_SDADDR_CSMASK_N(N) ((N)&(0x03FF << 22) >> 22)
910
911/* MEM_SDREFCFG register content definitions */
912#define MEM_SDREFCFG_TRC (15 << 28)
913#define MEM_SDREFCFG_TRPM (3 << 26)
914#define MEM_SDREFCFG_E (1 << 25)
915#define MEM_SDREFCFG_RE (0x1ffffff << 0)
916#define MEM_SDREFCFG_TRC_N(N) ((N) << MEM_SDREFCFG_TRC)
917#define MEM_SDREFCFG_TRPM_N(N) ((N) << MEM_SDREFCFG_TRPM)
918#define MEM_SDREFCFG_REF_N(N) (N)
919
920/* Au1550 SDRAM Register Offsets */
921#define AU1550_MEM_SDMODE0 0x0800
922#define AU1550_MEM_SDMODE1 0x0808
923#define AU1550_MEM_SDMODE2 0x0810
924#define AU1550_MEM_SDADDR0 0x0820
925#define AU1550_MEM_SDADDR1 0x0828
926#define AU1550_MEM_SDADDR2 0x0830
927#define AU1550_MEM_SDCONFIGA 0x0840
928#define AU1550_MEM_SDCONFIGB 0x0848
929#define AU1550_MEM_SDSTAT 0x0850
930#define AU1550_MEM_SDERRADDR 0x0858
931#define AU1550_MEM_SDSTRIDE0 0x0860
932#define AU1550_MEM_SDSTRIDE1 0x0868
933#define AU1550_MEM_SDSTRIDE2 0x0870
934#define AU1550_MEM_SDWRMD0 0x0880
935#define AU1550_MEM_SDWRMD1 0x0888
936#define AU1550_MEM_SDWRMD2 0x0890
937#define AU1550_MEM_SDPRECMD 0x08C0
938#define AU1550_MEM_SDAUTOREF 0x08C8
939#define AU1550_MEM_SDSREF 0x08D0
940#define AU1550_MEM_SDSLEEP MEM_SDSREF
941
942/* Static Bus Controller */
943#define MEM_STCFG0 0xB4001000
944#define MEM_STTIME0 0xB4001004
945#define MEM_STADDR0 0xB4001008
946
947#define MEM_STCFG1 0xB4001010
948#define MEM_STTIME1 0xB4001014
949#define MEM_STADDR1 0xB4001018
950
951#define MEM_STCFG2 0xB4001020
952#define MEM_STTIME2 0xB4001024
953#define MEM_STADDR2 0xB4001028
954
955#define MEM_STCFG3 0xB4001030
956#define MEM_STTIME3 0xB4001034
957#define MEM_STADDR3 0xB4001038
958
959#define MEM_STNDCTL 0xB4001100
960#define MEM_STSTAT 0xB4001104
961
962#define MEM_STNAND_CMD 0x0
963#define MEM_STNAND_ADDR 0x4
964#define MEM_STNAND_DATA 0x20
965
966
967/* Programmable Counters 0 and 1 */
968#define SYS_BASE 0xB1900000
969#define SYS_COUNTER_CNTRL (SYS_BASE + 0x14)
970# define SYS_CNTRL_E1S (1 << 23)
971# define SYS_CNTRL_T1S (1 << 20)
972# define SYS_CNTRL_M21 (1 << 19)
973# define SYS_CNTRL_M11 (1 << 18)
974# define SYS_CNTRL_M01 (1 << 17)
975# define SYS_CNTRL_C1S (1 << 16)
976# define SYS_CNTRL_BP (1 << 14)
977# define SYS_CNTRL_EN1 (1 << 13)
978# define SYS_CNTRL_BT1 (1 << 12)
979# define SYS_CNTRL_EN0 (1 << 11)
980# define SYS_CNTRL_BT0 (1 << 10)
981# define SYS_CNTRL_E0 (1 << 8)
982# define SYS_CNTRL_E0S (1 << 7)
983# define SYS_CNTRL_32S (1 << 5)
984# define SYS_CNTRL_T0S (1 << 4)
985# define SYS_CNTRL_M20 (1 << 3)
986# define SYS_CNTRL_M10 (1 << 2)
987# define SYS_CNTRL_M00 (1 << 1)
988# define SYS_CNTRL_C0S (1 << 0)
989
990/* Programmable Counter 0 Registers */
991#define SYS_TOYTRIM (SYS_BASE + 0)
992#define SYS_TOYWRITE (SYS_BASE + 4)
993#define SYS_TOYMATCH0 (SYS_BASE + 8)
994#define SYS_TOYMATCH1 (SYS_BASE + 0xC)
995#define SYS_TOYMATCH2 (SYS_BASE + 0x10)
996#define SYS_TOYREAD (SYS_BASE + 0x40)
997
998/* Programmable Counter 1 Registers */
999#define SYS_RTCTRIM (SYS_BASE + 0x44)
1000#define SYS_RTCWRITE (SYS_BASE + 0x48)
1001#define SYS_RTCMATCH0 (SYS_BASE + 0x4C)
1002#define SYS_RTCMATCH1 (SYS_BASE + 0x50)
1003#define SYS_RTCMATCH2 (SYS_BASE + 0x54)
1004#define SYS_RTCREAD (SYS_BASE + 0x58)
1005
1006/* I2S Controller */
1007#define I2S_DATA 0xB1000000
1008# define I2S_DATA_MASK 0xffffff
1009#define I2S_CONFIG 0xB1000004
1010# define I2S_CONFIG_XU (1 << 25)
1011# define I2S_CONFIG_XO (1 << 24)
1012# define I2S_CONFIG_RU (1 << 23)
1013# define I2S_CONFIG_RO (1 << 22)
1014# define I2S_CONFIG_TR (1 << 21)
1015# define I2S_CONFIG_TE (1 << 20)
1016# define I2S_CONFIG_TF (1 << 19)
1017# define I2S_CONFIG_RR (1 << 18)
1018# define I2S_CONFIG_RE (1 << 17)
1019# define I2S_CONFIG_RF (1 << 16)
1020# define I2S_CONFIG_PD (1 << 11)
1021# define I2S_CONFIG_LB (1 << 10)
1022# define I2S_CONFIG_IC (1 << 9)
1023# define I2S_CONFIG_FM_BIT 7
1024# define I2S_CONFIG_FM_MASK (0x3 << I2S_CONFIG_FM_BIT)
1025# define I2S_CONFIG_FM_I2S (0x0 << I2S_CONFIG_FM_BIT)
1026# define I2S_CONFIG_FM_LJ (0x1 << I2S_CONFIG_FM_BIT)
1027# define I2S_CONFIG_FM_RJ (0x2 << I2S_CONFIG_FM_BIT)
1028# define I2S_CONFIG_TN (1 << 6)
1029# define I2S_CONFIG_RN (1 << 5)
1030# define I2S_CONFIG_SZ_BIT 0
1031# define I2S_CONFIG_SZ_MASK (0x1F << I2S_CONFIG_SZ_BIT)
1032
1033#define I2S_CONTROL 0xB1000008
1034# define I2S_CONTROL_D (1 << 1)
1035# define I2S_CONTROL_CE (1 << 0)
1036
1037
1038/* Ethernet Controllers */
1039
1040/* 4 byte offsets from AU1000_ETH_BASE */
1041#define MAC_CONTROL 0x0
1042# define MAC_RX_ENABLE (1 << 2)
1043# define MAC_TX_ENABLE (1 << 3)
1044# define MAC_DEF_CHECK (1 << 5)
1045# define MAC_SET_BL(X) (((X) & 0x3) << 6)
1046# define MAC_AUTO_PAD (1 << 8)
1047# define MAC_DISABLE_RETRY (1 << 10)
1048# define MAC_DISABLE_BCAST (1 << 11)
1049# define MAC_LATE_COL (1 << 12)
1050# define MAC_HASH_MODE (1 << 13)
1051# define MAC_HASH_ONLY (1 << 15)
1052# define MAC_PASS_ALL (1 << 16)
1053# define MAC_INVERSE_FILTER (1 << 17)
1054# define MAC_PROMISCUOUS (1 << 18)
1055# define MAC_PASS_ALL_MULTI (1 << 19)
1056# define MAC_FULL_DUPLEX (1 << 20)
1057# define MAC_NORMAL_MODE 0
1058# define MAC_INT_LOOPBACK (1 << 21)
1059# define MAC_EXT_LOOPBACK (1 << 22)
1060# define MAC_DISABLE_RX_OWN (1 << 23)
1061# define MAC_BIG_ENDIAN (1 << 30)
1062# define MAC_RX_ALL (1 << 31)
1063#define MAC_ADDRESS_HIGH 0x4
1064#define MAC_ADDRESS_LOW 0x8
1065#define MAC_MCAST_HIGH 0xC
1066#define MAC_MCAST_LOW 0x10
1067#define MAC_MII_CNTRL 0x14
1068# define MAC_MII_BUSY (1 << 0)
1069# define MAC_MII_READ 0
1070# define MAC_MII_WRITE (1 << 1)
1071# define MAC_SET_MII_SELECT_REG(X) (((X) & 0x1f) << 6)
1072# define MAC_SET_MII_SELECT_PHY(X) (((X) & 0x1f) << 11)
1073#define MAC_MII_DATA 0x18
1074#define MAC_FLOW_CNTRL 0x1C
1075# define MAC_FLOW_CNTRL_BUSY (1 << 0)
1076# define MAC_FLOW_CNTRL_ENABLE (1 << 1)
1077# define MAC_PASS_CONTROL (1 << 2)
1078# define MAC_SET_PAUSE(X) (((X) & 0xffff) << 16)
1079#define MAC_VLAN1_TAG 0x20
1080#define MAC_VLAN2_TAG 0x24
1081
1082/* Ethernet Controller Enable */
1083
1084# define MAC_EN_CLOCK_ENABLE (1 << 0)
1085# define MAC_EN_RESET0 (1 << 1)
1086# define MAC_EN_TOSS (0 << 2)
1087# define MAC_EN_CACHEABLE (1 << 3)
1088# define MAC_EN_RESET1 (1 << 4)
1089# define MAC_EN_RESET2 (1 << 5)
1090# define MAC_DMA_RESET (1 << 6)
1091
1092/* Ethernet Controller DMA Channels */
1093
1094#define MAC0_TX_DMA_ADDR 0xB4004000
1095#define MAC1_TX_DMA_ADDR 0xB4004200
1096/* offsets from MAC_TX_RING_ADDR address */
1097#define MAC_TX_BUFF0_STATUS 0x0
1098# define TX_FRAME_ABORTED (1 << 0)
1099# define TX_JAB_TIMEOUT (1 << 1)
1100# define TX_NO_CARRIER (1 << 2)
1101# define TX_LOSS_CARRIER (1 << 3)
1102# define TX_EXC_DEF (1 << 4)
1103# define TX_LATE_COLL_ABORT (1 << 5)
1104# define TX_EXC_COLL (1 << 6)
1105# define TX_UNDERRUN (1 << 7)
1106# define TX_DEFERRED (1 << 8)
1107# define TX_LATE_COLL (1 << 9)
1108# define TX_COLL_CNT_MASK (0xF << 10)
1109# define TX_PKT_RETRY (1 << 31)
1110#define MAC_TX_BUFF0_ADDR 0x4
1111# define TX_DMA_ENABLE (1 << 0)
1112# define TX_T_DONE (1 << 1)
1113# define TX_GET_DMA_BUFFER(X) (((X) >> 2) & 0x3)
1114#define MAC_TX_BUFF0_LEN 0x8
1115#define MAC_TX_BUFF1_STATUS 0x10
1116#define MAC_TX_BUFF1_ADDR 0x14
1117#define MAC_TX_BUFF1_LEN 0x18
1118#define MAC_TX_BUFF2_STATUS 0x20
1119#define MAC_TX_BUFF2_ADDR 0x24
1120#define MAC_TX_BUFF2_LEN 0x28
1121#define MAC_TX_BUFF3_STATUS 0x30
1122#define MAC_TX_BUFF3_ADDR 0x34
1123#define MAC_TX_BUFF3_LEN 0x38
1124
1125#define MAC0_RX_DMA_ADDR 0xB4004100
1126#define MAC1_RX_DMA_ADDR 0xB4004300
1127/* offsets from MAC_RX_RING_ADDR */
1128#define MAC_RX_BUFF0_STATUS 0x0
1129# define RX_FRAME_LEN_MASK 0x3fff
1130# define RX_WDOG_TIMER (1 << 14)
1131# define RX_RUNT (1 << 15)
1132# define RX_OVERLEN (1 << 16)
1133# define RX_COLL (1 << 17)
1134# define RX_ETHER (1 << 18)
1135# define RX_MII_ERROR (1 << 19)
1136# define RX_DRIBBLING (1 << 20)
1137# define RX_CRC_ERROR (1 << 21)
1138# define RX_VLAN1 (1 << 22)
1139# define RX_VLAN2 (1 << 23)
1140# define RX_LEN_ERROR (1 << 24)
1141# define RX_CNTRL_FRAME (1 << 25)
1142# define RX_U_CNTRL_FRAME (1 << 26)
1143# define RX_MCAST_FRAME (1 << 27)
1144# define RX_BCAST_FRAME (1 << 28)
1145# define RX_FILTER_FAIL (1 << 29)
1146# define RX_PACKET_FILTER (1 << 30)
1147# define RX_MISSED_FRAME (1 << 31)
1148
1149# define RX_ERROR (RX_WDOG_TIMER | RX_RUNT | RX_OVERLEN | \
1150 RX_COLL | RX_MII_ERROR | RX_CRC_ERROR | \
1151 RX_LEN_ERROR | RX_U_CNTRL_FRAME | RX_MISSED_FRAME)
1152#define MAC_RX_BUFF0_ADDR 0x4
1153# define RX_DMA_ENABLE (1 << 0)
1154# define RX_T_DONE (1 << 1)
1155# define RX_GET_DMA_BUFFER(X) (((X) >> 2) & 0x3)
1156# define RX_SET_BUFF_ADDR(X) ((X) & 0xffffffc0)
1157#define MAC_RX_BUFF1_STATUS 0x10
1158#define MAC_RX_BUFF1_ADDR 0x14
1159#define MAC_RX_BUFF2_STATUS 0x20
1160#define MAC_RX_BUFF2_ADDR 0x24
1161#define MAC_RX_BUFF3_STATUS 0x30
1162#define MAC_RX_BUFF3_ADDR 0x34
1163
1164/* SSIO */
1165#define SSI0_STATUS 0xB1600000
1166# define SSI_STATUS_BF (1 << 4)
1167# define SSI_STATUS_OF (1 << 3)
1168# define SSI_STATUS_UF (1 << 2)
1169# define SSI_STATUS_D (1 << 1)
1170# define SSI_STATUS_B (1 << 0)
1171#define SSI0_INT 0xB1600004
1172# define SSI_INT_OI (1 << 3)
1173# define SSI_INT_UI (1 << 2)
1174# define SSI_INT_DI (1 << 1)
1175#define SSI0_INT_ENABLE 0xB1600008
1176# define SSI_INTE_OIE (1 << 3)
1177# define SSI_INTE_UIE (1 << 2)
1178# define SSI_INTE_DIE (1 << 1)
1179#define SSI0_CONFIG 0xB1600020
1180# define SSI_CONFIG_AO (1 << 24)
1181# define SSI_CONFIG_DO (1 << 23)
1182# define SSI_CONFIG_ALEN_BIT 20
1183# define SSI_CONFIG_ALEN_MASK (0x7 << 20)
1184# define SSI_CONFIG_DLEN_BIT 16
1185# define SSI_CONFIG_DLEN_MASK (0x7 << 16)
1186# define SSI_CONFIG_DD (1 << 11)
1187# define SSI_CONFIG_AD (1 << 10)
1188# define SSI_CONFIG_BM_BIT 8
1189# define SSI_CONFIG_BM_MASK (0x3 << 8)
1190# define SSI_CONFIG_CE (1 << 7)
1191# define SSI_CONFIG_DP (1 << 6)
1192# define SSI_CONFIG_DL (1 << 5)
1193# define SSI_CONFIG_EP (1 << 4)
1194#define SSI0_ADATA 0xB1600024
1195# define SSI_AD_D (1 << 24)
1196# define SSI_AD_ADDR_BIT 16
1197# define SSI_AD_ADDR_MASK (0xff << 16)
1198# define SSI_AD_DATA_BIT 0
1199# define SSI_AD_DATA_MASK (0xfff << 0)
1200#define SSI0_CLKDIV 0xB1600028
1201#define SSI0_CONTROL 0xB1600100
1202# define SSI_CONTROL_CD (1 << 1)
1203# define SSI_CONTROL_E (1 << 0)
1204
1205/* SSI1 */
1206#define SSI1_STATUS 0xB1680000
1207#define SSI1_INT 0xB1680004
1208#define SSI1_INT_ENABLE 0xB1680008
1209#define SSI1_CONFIG 0xB1680020
1210#define SSI1_ADATA 0xB1680024
1211#define SSI1_CLKDIV 0xB1680028
1212#define SSI1_ENABLE 0xB1680100
1213
1214/*
1215 * Register content definitions
1216 */
1217#define SSI_STATUS_BF (1 << 4)
1218#define SSI_STATUS_OF (1 << 3)
1219#define SSI_STATUS_UF (1 << 2)
1220#define SSI_STATUS_D (1 << 1)
1221#define SSI_STATUS_B (1 << 0)
1222
1223/* SSI_INT */
1224#define SSI_INT_OI (1 << 3)
1225#define SSI_INT_UI (1 << 2)
1226#define SSI_INT_DI (1 << 1)
1227
1228/* SSI_INTEN */
1229#define SSI_INTEN_OIE (1 << 3)
1230#define SSI_INTEN_UIE (1 << 2)
1231#define SSI_INTEN_DIE (1 << 1)
1232
1233#define SSI_CONFIG_AO (1 << 24)
1234#define SSI_CONFIG_DO (1 << 23)
1235#define SSI_CONFIG_ALEN (7 << 20)
1236#define SSI_CONFIG_DLEN (15 << 16)
1237#define SSI_CONFIG_DD (1 << 11)
1238#define SSI_CONFIG_AD (1 << 10)
1239#define SSI_CONFIG_BM (3 << 8)
1240#define SSI_CONFIG_CE (1 << 7)
1241#define SSI_CONFIG_DP (1 << 6)
1242#define SSI_CONFIG_DL (1 << 5)
1243#define SSI_CONFIG_EP (1 << 4)
1244#define SSI_CONFIG_ALEN_N(N) ((N-1) << 20)
1245#define SSI_CONFIG_DLEN_N(N) ((N-1) << 16)
1246#define SSI_CONFIG_BM_HI (0 << 8)
1247#define SSI_CONFIG_BM_LO (1 << 8)
1248#define SSI_CONFIG_BM_CY (2 << 8)
1249
1250#define SSI_ADATA_D (1 << 24)
1251#define SSI_ADATA_ADDR (0xFF << 16)
1252#define SSI_ADATA_DATA 0x0FFF
1253#define SSI_ADATA_ADDR_N(N) (N << 16)
1254
1255#define SSI_ENABLE_CD (1 << 1)
1256#define SSI_ENABLE_E (1 << 0)
1257
1258
1259/*
1260 * The IrDA peripheral has an IRFIRSEL pin, but on the DB/PB boards it's not
1261 * used to select FIR/SIR mode on the transceiver but as a GPIO. Instead a
1262 * CPLD has to be told about the mode.
1263 */
1264#define AU1000_IRDA_PHY_MODE_OFF 0
1265#define AU1000_IRDA_PHY_MODE_SIR 1
1266#define AU1000_IRDA_PHY_MODE_FIR 2
1267
1268struct au1k_irda_platform_data {
1269 void(*set_phy_mode)(int mode);
1270};
1271
1272
1273/* GPIO */
1274#define SYS_PINFUNC 0xB190002C
1275# define SYS_PF_USB (1 << 15) /* 2nd USB device/host */
1276# define SYS_PF_U3 (1 << 14) /* GPIO23/U3TXD */
1277# define SYS_PF_U2 (1 << 13) /* GPIO22/U2TXD */
1278# define SYS_PF_U1 (1 << 12) /* GPIO21/U1TXD */
1279# define SYS_PF_SRC (1 << 11) /* GPIO6/SROMCKE */
1280# define SYS_PF_CK5 (1 << 10) /* GPIO3/CLK5 */
1281# define SYS_PF_CK4 (1 << 9) /* GPIO2/CLK4 */
1282# define SYS_PF_IRF (1 << 8) /* GPIO15/IRFIRSEL */
1283# define SYS_PF_UR3 (1 << 7) /* GPIO[14:9]/UART3 */
1284# define SYS_PF_I2D (1 << 6) /* GPIO8/I2SDI */
1285# define SYS_PF_I2S (1 << 5) /* I2S/GPIO[29:31] */
1286# define SYS_PF_NI2 (1 << 4) /* NI2/GPIO[24:28] */
1287# define SYS_PF_U0 (1 << 3) /* U0TXD/GPIO20 */
1288# define SYS_PF_RD (1 << 2) /* IRTXD/GPIO19 */
1289# define SYS_PF_A97 (1 << 1) /* AC97/SSL1 */
1290# define SYS_PF_S0 (1 << 0) /* SSI_0/GPIO[16:18] */
1291
1292/* Au1100 only */
1293# define SYS_PF_PC (1 << 18) /* PCMCIA/GPIO[207:204] */
1294# define SYS_PF_LCD (1 << 17) /* extern lcd/GPIO[203:200] */
1295# define SYS_PF_CS (1 << 16) /* EXTCLK0/32KHz to gpio2 */
1296# define SYS_PF_EX0 (1 << 9) /* GPIO2/clock */
1297
1298/* Au1550 only. Redefines lots of pins */
1299# define SYS_PF_PSC2_MASK (7 << 17)
1300# define SYS_PF_PSC2_AC97 0
1301# define SYS_PF_PSC2_SPI 0
1302# define SYS_PF_PSC2_I2S (1 << 17)
1303# define SYS_PF_PSC2_SMBUS (3 << 17)
1304# define SYS_PF_PSC2_GPIO (7 << 17)
1305# define SYS_PF_PSC3_MASK (7 << 20)
1306# define SYS_PF_PSC3_AC97 0
1307# define SYS_PF_PSC3_SPI 0
1308# define SYS_PF_PSC3_I2S (1 << 20)
1309# define SYS_PF_PSC3_SMBUS (3 << 20)
1310# define SYS_PF_PSC3_GPIO (7 << 20)
1311# define SYS_PF_PSC1_S1 (1 << 1)
1312# define SYS_PF_MUST_BE_SET ((1 << 5) | (1 << 2))
1313
1314/* Au1200 only */
1315#define SYS_PINFUNC_DMA (1 << 31)
1316#define SYS_PINFUNC_S0A (1 << 30)
1317#define SYS_PINFUNC_S1A (1 << 29)
1318#define SYS_PINFUNC_LP0 (1 << 28)
1319#define SYS_PINFUNC_LP1 (1 << 27)
1320#define SYS_PINFUNC_LD16 (1 << 26)
1321#define SYS_PINFUNC_LD8 (1 << 25)
1322#define SYS_PINFUNC_LD1 (1 << 24)
1323#define SYS_PINFUNC_LD0 (1 << 23)
1324#define SYS_PINFUNC_P1A (3 << 21)
1325#define SYS_PINFUNC_P1B (1 << 20)
1326#define SYS_PINFUNC_FS3 (1 << 19)
1327#define SYS_PINFUNC_P0A (3 << 17)
1328#define SYS_PINFUNC_CS (1 << 16)
1329#define SYS_PINFUNC_CIM (1 << 15)
1330#define SYS_PINFUNC_P1C (1 << 14)
1331#define SYS_PINFUNC_U1T (1 << 12)
1332#define SYS_PINFUNC_U1R (1 << 11)
1333#define SYS_PINFUNC_EX1 (1 << 10)
1334#define SYS_PINFUNC_EX0 (1 << 9)
1335#define SYS_PINFUNC_U0R (1 << 8)
1336#define SYS_PINFUNC_MC (1 << 7)
1337#define SYS_PINFUNC_S0B (1 << 6)
1338#define SYS_PINFUNC_S0C (1 << 5)
1339#define SYS_PINFUNC_P0B (1 << 4)
1340#define SYS_PINFUNC_U0T (1 << 3)
1341#define SYS_PINFUNC_S1B (1 << 2)
1342
1343/* Power Management */
1344#define SYS_SCRATCH0 0xB1900018
1345#define SYS_SCRATCH1 0xB190001C
1346#define SYS_WAKEMSK 0xB1900034
1347#define SYS_ENDIAN 0xB1900038
1348#define SYS_POWERCTRL 0xB190003C
1349#define SYS_WAKESRC 0xB190005C
1350#define SYS_SLPPWR 0xB1900078
1351#define SYS_SLEEP 0xB190007C
1352
1353#define SYS_WAKEMSK_D2 (1 << 9)
1354#define SYS_WAKEMSK_M2 (1 << 8)
1355#define SYS_WAKEMSK_GPIO(x) (1 << (x))
1356
1357/* Clock Controller */
1358#define SYS_FREQCTRL0 0xB1900020
1359# define SYS_FC_FRDIV2_BIT 22
1360# define SYS_FC_FRDIV2_MASK (0xff << SYS_FC_FRDIV2_BIT)
1361# define SYS_FC_FE2 (1 << 21)
1362# define SYS_FC_FS2 (1 << 20)
1363# define SYS_FC_FRDIV1_BIT 12
1364# define SYS_FC_FRDIV1_MASK (0xff << SYS_FC_FRDIV1_BIT)
1365# define SYS_FC_FE1 (1 << 11)
1366# define SYS_FC_FS1 (1 << 10)
1367# define SYS_FC_FRDIV0_BIT 2
1368# define SYS_FC_FRDIV0_MASK (0xff << SYS_FC_FRDIV0_BIT)
1369# define SYS_FC_FE0 (1 << 1)
1370# define SYS_FC_FS0 (1 << 0)
1371#define SYS_FREQCTRL1 0xB1900024
1372# define SYS_FC_FRDIV5_BIT 22
1373# define SYS_FC_FRDIV5_MASK (0xff << SYS_FC_FRDIV5_BIT)
1374# define SYS_FC_FE5 (1 << 21)
1375# define SYS_FC_FS5 (1 << 20)
1376# define SYS_FC_FRDIV4_BIT 12
1377# define SYS_FC_FRDIV4_MASK (0xff << SYS_FC_FRDIV4_BIT)
1378# define SYS_FC_FE4 (1 << 11)
1379# define SYS_FC_FS4 (1 << 10)
1380# define SYS_FC_FRDIV3_BIT 2
1381# define SYS_FC_FRDIV3_MASK (0xff << SYS_FC_FRDIV3_BIT)
1382# define SYS_FC_FE3 (1 << 1)
1383# define SYS_FC_FS3 (1 << 0)
1384#define SYS_CLKSRC 0xB1900028
1385# define SYS_CS_ME1_BIT 27
1386# define SYS_CS_ME1_MASK (0x7 << SYS_CS_ME1_BIT)
1387# define SYS_CS_DE1 (1 << 26)
1388# define SYS_CS_CE1 (1 << 25)
1389# define SYS_CS_ME0_BIT 22
1390# define SYS_CS_ME0_MASK (0x7 << SYS_CS_ME0_BIT)
1391# define SYS_CS_DE0 (1 << 21)
1392# define SYS_CS_CE0 (1 << 20)
1393# define SYS_CS_MI2_BIT 17
1394# define SYS_CS_MI2_MASK (0x7 << SYS_CS_MI2_BIT)
1395# define SYS_CS_DI2 (1 << 16)
1396# define SYS_CS_CI2 (1 << 15)
1397
1398# define SYS_CS_ML_BIT 7
1399# define SYS_CS_ML_MASK (0x7 << SYS_CS_ML_BIT)
1400# define SYS_CS_DL (1 << 6)
1401# define SYS_CS_CL (1 << 5)
1402
1403# define SYS_CS_MUH_BIT 12
1404# define SYS_CS_MUH_MASK (0x7 << SYS_CS_MUH_BIT)
1405# define SYS_CS_DUH (1 << 11)
1406# define SYS_CS_CUH (1 << 10)
1407# define SYS_CS_MUD_BIT 7
1408# define SYS_CS_MUD_MASK (0x7 << SYS_CS_MUD_BIT)
1409# define SYS_CS_DUD (1 << 6)
1410# define SYS_CS_CUD (1 << 5)
1411
1412# define SYS_CS_MIR_BIT 2
1413# define SYS_CS_MIR_MASK (0x7 << SYS_CS_MIR_BIT)
1414# define SYS_CS_DIR (1 << 1)
1415# define SYS_CS_CIR (1 << 0)
1416
1417# define SYS_CS_MUX_AUX 0x1
1418# define SYS_CS_MUX_FQ0 0x2
1419# define SYS_CS_MUX_FQ1 0x3
1420# define SYS_CS_MUX_FQ2 0x4
1421# define SYS_CS_MUX_FQ3 0x5
1422# define SYS_CS_MUX_FQ4 0x6
1423# define SYS_CS_MUX_FQ5 0x7
1424#define SYS_CPUPLL 0xB1900060
1425#define SYS_AUXPLL 0xB1900064
1426
1427/* AC97 Controller */
1428#define AC97C_CONFIG 0xB0000000
1429# define AC97C_RECV_SLOTS_BIT 13
1430# define AC97C_RECV_SLOTS_MASK (0x3ff << AC97C_RECV_SLOTS_BIT)
1431# define AC97C_XMIT_SLOTS_BIT 3
1432# define AC97C_XMIT_SLOTS_MASK (0x3ff << AC97C_XMIT_SLOTS_BIT)
1433# define AC97C_SG (1 << 2)
1434# define AC97C_SYNC (1 << 1)
1435# define AC97C_RESET (1 << 0)
1436#define AC97C_STATUS 0xB0000004
1437# define AC97C_XU (1 << 11)
1438# define AC97C_XO (1 << 10)
1439# define AC97C_RU (1 << 9)
1440# define AC97C_RO (1 << 8)
1441# define AC97C_READY (1 << 7)
1442# define AC97C_CP (1 << 6)
1443# define AC97C_TR (1 << 5)
1444# define AC97C_TE (1 << 4)
1445# define AC97C_TF (1 << 3)
1446# define AC97C_RR (1 << 2)
1447# define AC97C_RE (1 << 1)
1448# define AC97C_RF (1 << 0)
1449#define AC97C_DATA 0xB0000008
1450#define AC97C_CMD 0xB000000C
1451# define AC97C_WD_BIT 16
1452# define AC97C_READ (1 << 7)
1453# define AC97C_INDEX_MASK 0x7f
1454#define AC97C_CNTRL 0xB0000010
1455# define AC97C_RS (1 << 1)
1456# define AC97C_CE (1 << 0)
1457
1458
1459/* The PCI chip selects are outside the 32bit space, and since we can't
1460 * just program the 36bit addresses into BARs, we have to take a chunk
1461 * out of the 32bit space and reserve it for PCI. When these addresses
1462 * are ioremap()ed, they'll be fixed up to the real 36bit address before
1463 * being passed to the real ioremap function.
1464 */
1465#define ALCHEMY_PCI_MEMWIN_START (AU1500_PCI_MEM_PHYS_ADDR >> 4)
1466#define ALCHEMY_PCI_MEMWIN_END (ALCHEMY_PCI_MEMWIN_START + 0x0FFFFFFF)
1467
1468/* for PCI IO it's simpler because we get to do the ioremap ourselves and then
1469 * adjust the device's resources.
1470 */
1471#define ALCHEMY_PCI_IOWIN_START 0x00001000
1472#define ALCHEMY_PCI_IOWIN_END 0x0000FFFF
1473
1474#ifdef CONFIG_PCI
1475
1476#define IOPORT_RESOURCE_START 0x00001000 /* skip legacy probing */
1477#define IOPORT_RESOURCE_END 0xffffffff
1478#define IOMEM_RESOURCE_START 0x10000000
1479#define IOMEM_RESOURCE_END 0xfffffffffULL
1480
1481#else
1482
1483/* Don't allow any legacy ports probing */
1484#define IOPORT_RESOURCE_START 0x10000000
1485#define IOPORT_RESOURCE_END 0xffffffff
1486#define IOMEM_RESOURCE_START 0x10000000
1487#define IOMEM_RESOURCE_END 0xfffffffffULL
1488
1489#endif
1490
1491/* PCI controller block register offsets */
1492#define PCI_REG_CMEM 0x0000
1493#define PCI_REG_CONFIG 0x0004
1494#define PCI_REG_B2BMASK_CCH 0x0008
1495#define PCI_REG_B2BBASE0_VID 0x000C
1496#define PCI_REG_B2BBASE1_SID 0x0010
1497#define PCI_REG_MWMASK_DEV 0x0014
1498#define PCI_REG_MWBASE_REV_CCL 0x0018
1499#define PCI_REG_ERR_ADDR 0x001C
1500#define PCI_REG_SPEC_INTACK 0x0020
1501#define PCI_REG_ID 0x0100
1502#define PCI_REG_STATCMD 0x0104
1503#define PCI_REG_CLASSREV 0x0108
1504#define PCI_REG_PARAM 0x010C
1505#define PCI_REG_MBAR 0x0110
1506#define PCI_REG_TIMEOUT 0x0140
1507
1508/* PCI controller block register bits */
1509#define PCI_CMEM_E (1 << 28) /* enable cacheable memory */
1510#define PCI_CMEM_CMBASE(x) (((x) & 0x3fff) << 14)
1511#define PCI_CMEM_CMMASK(x) ((x) & 0x3fff)
1512#define PCI_CONFIG_ERD (1 << 27) /* pci error during R/W */
1513#define PCI_CONFIG_ET (1 << 26) /* error in target mode */
1514#define PCI_CONFIG_EF (1 << 25) /* fatal error */
1515#define PCI_CONFIG_EP (1 << 24) /* parity error */
1516#define PCI_CONFIG_EM (1 << 23) /* multiple errors */
1517#define PCI_CONFIG_BM (1 << 22) /* bad master error */
1518#define PCI_CONFIG_PD (1 << 20) /* PCI Disable */
1519#define PCI_CONFIG_BME (1 << 19) /* Byte Mask Enable for reads */
1520#define PCI_CONFIG_NC (1 << 16) /* mark mem access non-coherent */
1521#define PCI_CONFIG_IA (1 << 15) /* INTA# enabled (target mode) */
1522#define PCI_CONFIG_IP (1 << 13) /* int on PCI_PERR# */
1523#define PCI_CONFIG_IS (1 << 12) /* int on PCI_SERR# */
1524#define PCI_CONFIG_IMM (1 << 11) /* int on master abort */
1525#define PCI_CONFIG_ITM (1 << 10) /* int on target abort (as master) */
1526#define PCI_CONFIG_ITT (1 << 9) /* int on target abort (as target) */
1527#define PCI_CONFIG_IPB (1 << 8) /* int on PERR# in bus master acc */
1528#define PCI_CONFIG_SIC_NO (0 << 6) /* no byte mask changes */
1529#define PCI_CONFIG_SIC_BA_ADR (1 << 6) /* on byte/hw acc, invert adr bits */
1530#define PCI_CONFIG_SIC_HWA_DAT (2 << 6) /* on halfword acc, swap data */
1531#define PCI_CONFIG_SIC_ALL (3 << 6) /* swap data bytes on all accesses */
1532#define PCI_CONFIG_ST (1 << 5) /* swap data by target transactions */
1533#define PCI_CONFIG_SM (1 << 4) /* swap data from PCI ctl */
1534#define PCI_CONFIG_AEN (1 << 3) /* enable internal arbiter */
1535#define PCI_CONFIG_R2H (1 << 2) /* REQ2# to hi-prio arbiter */
1536#define PCI_CONFIG_R1H (1 << 1) /* REQ1# to hi-prio arbiter */
1537#define PCI_CONFIG_CH (1 << 0) /* PCI ctl to hi-prio arbiter */
1538#define PCI_B2BMASK_B2BMASK(x) (((x) & 0xffff) << 16)
1539#define PCI_B2BMASK_CCH(x) ((x) & 0xffff) /* 16 upper bits of class code */
1540#define PCI_B2BBASE0_VID_B0(x) (((x) & 0xffff) << 16)
1541#define PCI_B2BBASE0_VID_SV(x) ((x) & 0xffff)
1542#define PCI_B2BBASE1_SID_B1(x) (((x) & 0xffff) << 16)
1543#define PCI_B2BBASE1_SID_SI(x) ((x) & 0xffff)
1544#define PCI_MWMASKDEV_MWMASK(x) (((x) & 0xffff) << 16)
1545#define PCI_MWMASKDEV_DEVID(x) ((x) & 0xffff)
1546#define PCI_MWBASEREVCCL_BASE(x) (((x) & 0xffff) << 16)
1547#define PCI_MWBASEREVCCL_REV(x) (((x) & 0xff) << 8)
1548#define PCI_MWBASEREVCCL_CCL(x) ((x) & 0xff)
1549#define PCI_ID_DID(x) (((x) & 0xffff) << 16)
1550#define PCI_ID_VID(x) ((x) & 0xffff)
1551#define PCI_STATCMD_STATUS(x) (((x) & 0xffff) << 16)
1552#define PCI_STATCMD_CMD(x) ((x) & 0xffff)
1553#define PCI_CLASSREV_CLASS(x) (((x) & 0x00ffffff) << 8)
1554#define PCI_CLASSREV_REV(x) ((x) & 0xff)
1555#define PCI_PARAM_BIST(x) (((x) & 0xff) << 24)
1556#define PCI_PARAM_HT(x) (((x) & 0xff) << 16)
1557#define PCI_PARAM_LT(x) (((x) & 0xff) << 8)
1558#define PCI_PARAM_CLS(x) ((x) & 0xff)
1559#define PCI_TIMEOUT_RETRIES(x) (((x) & 0xff) << 8) /* max retries */
1560#define PCI_TIMEOUT_TO(x) ((x) & 0xff) /* target ready timeout */
1561
1562#endif 1211#endif
diff --git a/arch/mips/include/asm/mach-au1x00/au1000_dma.h b/arch/mips/include/asm/mach-au1x00/au1000_dma.h
index 7cedca5a305c..0a0cd4270c6f 100644
--- a/arch/mips/include/asm/mach-au1x00/au1000_dma.h
+++ b/arch/mips/include/asm/mach-au1x00/au1000_dma.h
@@ -106,7 +106,7 @@ enum {
106struct dma_chan { 106struct dma_chan {
107 int dev_id; /* this channel is allocated if >= 0, */ 107 int dev_id; /* this channel is allocated if >= 0, */
108 /* free otherwise */ 108 /* free otherwise */
109 unsigned int io; 109 void __iomem *io;
110 const char *dev_str; 110 const char *dev_str;
111 int irq; 111 int irq;
112 void *irq_dev; 112 void *irq_dev;
@@ -157,7 +157,7 @@ static inline void enable_dma_buffer0(unsigned int dmanr)
157 157
158 if (!chan) 158 if (!chan)
159 return; 159 return;
160 au_writel(DMA_BE0, chan->io + DMA_MODE_SET); 160 __raw_writel(DMA_BE0, chan->io + DMA_MODE_SET);
161} 161}
162 162
163static inline void enable_dma_buffer1(unsigned int dmanr) 163static inline void enable_dma_buffer1(unsigned int dmanr)
@@ -166,7 +166,7 @@ static inline void enable_dma_buffer1(unsigned int dmanr)
166 166
167 if (!chan) 167 if (!chan)
168 return; 168 return;
169 au_writel(DMA_BE1, chan->io + DMA_MODE_SET); 169 __raw_writel(DMA_BE1, chan->io + DMA_MODE_SET);
170} 170}
171static inline void enable_dma_buffers(unsigned int dmanr) 171static inline void enable_dma_buffers(unsigned int dmanr)
172{ 172{
@@ -174,7 +174,7 @@ static inline void enable_dma_buffers(unsigned int dmanr)
174 174
175 if (!chan) 175 if (!chan)
176 return; 176 return;
177 au_writel(DMA_BE0 | DMA_BE1, chan->io + DMA_MODE_SET); 177 __raw_writel(DMA_BE0 | DMA_BE1, chan->io + DMA_MODE_SET);
178} 178}
179 179
180static inline void start_dma(unsigned int dmanr) 180static inline void start_dma(unsigned int dmanr)
@@ -183,7 +183,7 @@ static inline void start_dma(unsigned int dmanr)
183 183
184 if (!chan) 184 if (!chan)
185 return; 185 return;
186 au_writel(DMA_GO, chan->io + DMA_MODE_SET); 186 __raw_writel(DMA_GO, chan->io + DMA_MODE_SET);
187} 187}
188 188
189#define DMA_HALT_POLL 0x5000 189#define DMA_HALT_POLL 0x5000
@@ -195,11 +195,11 @@ static inline void halt_dma(unsigned int dmanr)
195 195
196 if (!chan) 196 if (!chan)
197 return; 197 return;
198 au_writel(DMA_GO, chan->io + DMA_MODE_CLEAR); 198 __raw_writel(DMA_GO, chan->io + DMA_MODE_CLEAR);
199 199
200 /* Poll the halt bit */ 200 /* Poll the halt bit */
201 for (i = 0; i < DMA_HALT_POLL; i++) 201 for (i = 0; i < DMA_HALT_POLL; i++)
202 if (au_readl(chan->io + DMA_MODE_READ) & DMA_HALT) 202 if (__raw_readl(chan->io + DMA_MODE_READ) & DMA_HALT)
203 break; 203 break;
204 if (i == DMA_HALT_POLL) 204 if (i == DMA_HALT_POLL)
205 printk(KERN_INFO "halt_dma: HALT poll expired!\n"); 205 printk(KERN_INFO "halt_dma: HALT poll expired!\n");
@@ -215,7 +215,7 @@ static inline void disable_dma(unsigned int dmanr)
215 halt_dma(dmanr); 215 halt_dma(dmanr);
216 216
217 /* Now we can disable the buffers */ 217 /* Now we can disable the buffers */
218 au_writel(~DMA_GO, chan->io + DMA_MODE_CLEAR); 218 __raw_writel(~DMA_GO, chan->io + DMA_MODE_CLEAR);
219} 219}
220 220
221static inline int dma_halted(unsigned int dmanr) 221static inline int dma_halted(unsigned int dmanr)
@@ -224,7 +224,7 @@ static inline int dma_halted(unsigned int dmanr)
224 224
225 if (!chan) 225 if (!chan)
226 return 1; 226 return 1;
227 return (au_readl(chan->io + DMA_MODE_READ) & DMA_HALT) ? 1 : 0; 227 return (__raw_readl(chan->io + DMA_MODE_READ) & DMA_HALT) ? 1 : 0;
228} 228}
229 229
230/* Initialize a DMA channel. */ 230/* Initialize a DMA channel. */
@@ -239,14 +239,14 @@ static inline void init_dma(unsigned int dmanr)
239 disable_dma(dmanr); 239 disable_dma(dmanr);
240 240
241 /* Set device FIFO address */ 241 /* Set device FIFO address */
242 au_writel(CPHYSADDR(chan->fifo_addr), chan->io + DMA_PERIPHERAL_ADDR); 242 __raw_writel(CPHYSADDR(chan->fifo_addr), chan->io + DMA_PERIPHERAL_ADDR);
243 243
244 mode = chan->mode | (chan->dev_id << DMA_DID_BIT); 244 mode = chan->mode | (chan->dev_id << DMA_DID_BIT);
245 if (chan->irq) 245 if (chan->irq)
246 mode |= DMA_IE; 246 mode |= DMA_IE;
247 247
248 au_writel(~mode, chan->io + DMA_MODE_CLEAR); 248 __raw_writel(~mode, chan->io + DMA_MODE_CLEAR);
249 au_writel(mode, chan->io + DMA_MODE_SET); 249 __raw_writel(mode, chan->io + DMA_MODE_SET);
250} 250}
251 251
252/* 252/*
@@ -283,7 +283,7 @@ static inline int get_dma_active_buffer(unsigned int dmanr)
283 283
284 if (!chan) 284 if (!chan)
285 return -1; 285 return -1;
286 return (au_readl(chan->io + DMA_MODE_READ) & DMA_AB) ? 1 : 0; 286 return (__raw_readl(chan->io + DMA_MODE_READ) & DMA_AB) ? 1 : 0;
287} 287}
288 288
289/* 289/*
@@ -304,7 +304,7 @@ static inline void set_dma_fifo_addr(unsigned int dmanr, unsigned int a)
304 if (chan->dev_id != DMA_ID_GP04 && chan->dev_id != DMA_ID_GP05) 304 if (chan->dev_id != DMA_ID_GP04 && chan->dev_id != DMA_ID_GP05)
305 return; 305 return;
306 306
307 au_writel(CPHYSADDR(a), chan->io + DMA_PERIPHERAL_ADDR); 307 __raw_writel(CPHYSADDR(a), chan->io + DMA_PERIPHERAL_ADDR);
308} 308}
309 309
310/* 310/*
@@ -316,7 +316,7 @@ static inline void clear_dma_done0(unsigned int dmanr)
316 316
317 if (!chan) 317 if (!chan)
318 return; 318 return;
319 au_writel(DMA_D0, chan->io + DMA_MODE_CLEAR); 319 __raw_writel(DMA_D0, chan->io + DMA_MODE_CLEAR);
320} 320}
321 321
322static inline void clear_dma_done1(unsigned int dmanr) 322static inline void clear_dma_done1(unsigned int dmanr)
@@ -325,7 +325,7 @@ static inline void clear_dma_done1(unsigned int dmanr)
325 325
326 if (!chan) 326 if (!chan)
327 return; 327 return;
328 au_writel(DMA_D1, chan->io + DMA_MODE_CLEAR); 328 __raw_writel(DMA_D1, chan->io + DMA_MODE_CLEAR);
329} 329}
330 330
331/* 331/*
@@ -344,7 +344,7 @@ static inline void set_dma_addr0(unsigned int dmanr, unsigned int a)
344 344
345 if (!chan) 345 if (!chan)
346 return; 346 return;
347 au_writel(a, chan->io + DMA_BUFFER0_START); 347 __raw_writel(a, chan->io + DMA_BUFFER0_START);
348} 348}
349 349
350/* 350/*
@@ -356,7 +356,7 @@ static inline void set_dma_addr1(unsigned int dmanr, unsigned int a)
356 356
357 if (!chan) 357 if (!chan)
358 return; 358 return;
359 au_writel(a, chan->io + DMA_BUFFER1_START); 359 __raw_writel(a, chan->io + DMA_BUFFER1_START);
360} 360}
361 361
362 362
@@ -370,7 +370,7 @@ static inline void set_dma_count0(unsigned int dmanr, unsigned int count)
370 if (!chan) 370 if (!chan)
371 return; 371 return;
372 count &= DMA_COUNT_MASK; 372 count &= DMA_COUNT_MASK;
373 au_writel(count, chan->io + DMA_BUFFER0_COUNT); 373 __raw_writel(count, chan->io + DMA_BUFFER0_COUNT);
374} 374}
375 375
376/* 376/*
@@ -383,7 +383,7 @@ static inline void set_dma_count1(unsigned int dmanr, unsigned int count)
383 if (!chan) 383 if (!chan)
384 return; 384 return;
385 count &= DMA_COUNT_MASK; 385 count &= DMA_COUNT_MASK;
386 au_writel(count, chan->io + DMA_BUFFER1_COUNT); 386 __raw_writel(count, chan->io + DMA_BUFFER1_COUNT);
387} 387}
388 388
389/* 389/*
@@ -396,8 +396,8 @@ static inline void set_dma_count(unsigned int dmanr, unsigned int count)
396 if (!chan) 396 if (!chan)
397 return; 397 return;
398 count &= DMA_COUNT_MASK; 398 count &= DMA_COUNT_MASK;
399 au_writel(count, chan->io + DMA_BUFFER0_COUNT); 399 __raw_writel(count, chan->io + DMA_BUFFER0_COUNT);
400 au_writel(count, chan->io + DMA_BUFFER1_COUNT); 400 __raw_writel(count, chan->io + DMA_BUFFER1_COUNT);
401} 401}
402 402
403/* 403/*
@@ -410,7 +410,7 @@ static inline unsigned int get_dma_buffer_done(unsigned int dmanr)
410 410
411 if (!chan) 411 if (!chan)
412 return 0; 412 return 0;
413 return au_readl(chan->io + DMA_MODE_READ) & (DMA_D0 | DMA_D1); 413 return __raw_readl(chan->io + DMA_MODE_READ) & (DMA_D0 | DMA_D1);
414} 414}
415 415
416 416
@@ -437,10 +437,10 @@ static inline int get_dma_residue(unsigned int dmanr)
437 if (!chan) 437 if (!chan)
438 return 0; 438 return 0;
439 439
440 curBufCntReg = (au_readl(chan->io + DMA_MODE_READ) & DMA_AB) ? 440 curBufCntReg = (__raw_readl(chan->io + DMA_MODE_READ) & DMA_AB) ?
441 DMA_BUFFER1_COUNT : DMA_BUFFER0_COUNT; 441 DMA_BUFFER1_COUNT : DMA_BUFFER0_COUNT;
442 442
443 count = au_readl(chan->io + curBufCntReg) & DMA_COUNT_MASK; 443 count = __raw_readl(chan->io + curBufCntReg) & DMA_COUNT_MASK;
444 444
445 if ((chan->mode & DMA_DW_MASK) == DMA_DW16) 445 if ((chan->mode & DMA_DW_MASK) == DMA_DW16)
446 count <<= 1; 446 count <<= 1;
diff --git a/arch/mips/include/asm/mach-au1x00/gpio-au1000.h b/arch/mips/include/asm/mach-au1x00/gpio-au1000.h
index 796afd051c35..9785e4ebb450 100644
--- a/arch/mips/include/asm/mach-au1x00/gpio-au1000.h
+++ b/arch/mips/include/asm/mach-au1x00/gpio-au1000.h
@@ -25,20 +25,20 @@
25#define MAKE_IRQ(intc, off) (AU1000_INTC##intc##_INT_BASE + (off)) 25#define MAKE_IRQ(intc, off) (AU1000_INTC##intc##_INT_BASE + (off))
26 26
27/* GPIO1 registers within SYS_ area */ 27/* GPIO1 registers within SYS_ area */
28#define SYS_TRIOUTRD 0x100 28#define AU1000_SYS_TRIOUTRD 0x100
29#define SYS_TRIOUTCLR 0x100 29#define AU1000_SYS_TRIOUTCLR 0x100
30#define SYS_OUTPUTRD 0x108 30#define AU1000_SYS_OUTPUTRD 0x108
31#define SYS_OUTPUTSET 0x108 31#define AU1000_SYS_OUTPUTSET 0x108
32#define SYS_OUTPUTCLR 0x10C 32#define AU1000_SYS_OUTPUTCLR 0x10C
33#define SYS_PINSTATERD 0x110 33#define AU1000_SYS_PINSTATERD 0x110
34#define SYS_PININPUTEN 0x110 34#define AU1000_SYS_PININPUTEN 0x110
35 35
36/* register offsets within GPIO2 block */ 36/* register offsets within GPIO2 block */
37#define GPIO2_DIR 0x00 37#define AU1000_GPIO2_DIR 0x00
38#define GPIO2_OUTPUT 0x08 38#define AU1000_GPIO2_OUTPUT 0x08
39#define GPIO2_PINSTATE 0x0C 39#define AU1000_GPIO2_PINSTATE 0x0C
40#define GPIO2_INTENABLE 0x10 40#define AU1000_GPIO2_INTENABLE 0x10
41#define GPIO2_ENABLE 0x14 41#define AU1000_GPIO2_ENABLE 0x14
42 42
43struct gpio; 43struct gpio;
44 44
@@ -217,26 +217,21 @@ static inline int au1200_irq_to_gpio(int irq)
217 */ 217 */
218static inline void alchemy_gpio1_set_value(int gpio, int v) 218static inline void alchemy_gpio1_set_value(int gpio, int v)
219{ 219{
220 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_SYS_PHYS_ADDR);
221 unsigned long mask = 1 << (gpio - ALCHEMY_GPIO1_BASE); 220 unsigned long mask = 1 << (gpio - ALCHEMY_GPIO1_BASE);
222 unsigned long r = v ? SYS_OUTPUTSET : SYS_OUTPUTCLR; 221 unsigned long r = v ? AU1000_SYS_OUTPUTSET : AU1000_SYS_OUTPUTCLR;
223 __raw_writel(mask, base + r); 222 alchemy_wrsys(mask, r);
224 wmb();
225} 223}
226 224
227static inline int alchemy_gpio1_get_value(int gpio) 225static inline int alchemy_gpio1_get_value(int gpio)
228{ 226{
229 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_SYS_PHYS_ADDR);
230 unsigned long mask = 1 << (gpio - ALCHEMY_GPIO1_BASE); 227 unsigned long mask = 1 << (gpio - ALCHEMY_GPIO1_BASE);
231 return __raw_readl(base + SYS_PINSTATERD) & mask; 228 return alchemy_rdsys(AU1000_SYS_PINSTATERD) & mask;
232} 229}
233 230
234static inline int alchemy_gpio1_direction_input(int gpio) 231static inline int alchemy_gpio1_direction_input(int gpio)
235{ 232{
236 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_SYS_PHYS_ADDR);
237 unsigned long mask = 1 << (gpio - ALCHEMY_GPIO1_BASE); 233 unsigned long mask = 1 << (gpio - ALCHEMY_GPIO1_BASE);
238 __raw_writel(mask, base + SYS_TRIOUTCLR); 234 alchemy_wrsys(mask, AU1000_SYS_TRIOUTCLR);
239 wmb();
240 return 0; 235 return 0;
241} 236}
242 237
@@ -279,13 +274,13 @@ static inline void __alchemy_gpio2_mod_dir(int gpio, int to_out)
279{ 274{
280 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR); 275 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR);
281 unsigned long mask = 1 << (gpio - ALCHEMY_GPIO2_BASE); 276 unsigned long mask = 1 << (gpio - ALCHEMY_GPIO2_BASE);
282 unsigned long d = __raw_readl(base + GPIO2_DIR); 277 unsigned long d = __raw_readl(base + AU1000_GPIO2_DIR);
283 278
284 if (to_out) 279 if (to_out)
285 d |= mask; 280 d |= mask;
286 else 281 else
287 d &= ~mask; 282 d &= ~mask;
288 __raw_writel(d, base + GPIO2_DIR); 283 __raw_writel(d, base + AU1000_GPIO2_DIR);
289 wmb(); 284 wmb();
290} 285}
291 286
@@ -294,14 +289,15 @@ static inline void alchemy_gpio2_set_value(int gpio, int v)
294 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR); 289 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR);
295 unsigned long mask; 290 unsigned long mask;
296 mask = ((v) ? 0x00010001 : 0x00010000) << (gpio - ALCHEMY_GPIO2_BASE); 291 mask = ((v) ? 0x00010001 : 0x00010000) << (gpio - ALCHEMY_GPIO2_BASE);
297 __raw_writel(mask, base + GPIO2_OUTPUT); 292 __raw_writel(mask, base + AU1000_GPIO2_OUTPUT);
298 wmb(); 293 wmb();
299} 294}
300 295
301static inline int alchemy_gpio2_get_value(int gpio) 296static inline int alchemy_gpio2_get_value(int gpio)
302{ 297{
303 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR); 298 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR);
304 return __raw_readl(base + GPIO2_PINSTATE) & (1 << (gpio - ALCHEMY_GPIO2_BASE)); 299 return __raw_readl(base + AU1000_GPIO2_PINSTATE) &
300 (1 << (gpio - ALCHEMY_GPIO2_BASE));
305} 301}
306 302
307static inline int alchemy_gpio2_direction_input(int gpio) 303static inline int alchemy_gpio2_direction_input(int gpio)
@@ -352,12 +348,12 @@ static inline int alchemy_gpio2_to_irq(int gpio)
352static inline void __alchemy_gpio2_mod_int(int gpio2, int en) 348static inline void __alchemy_gpio2_mod_int(int gpio2, int en)
353{ 349{
354 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR); 350 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR);
355 unsigned long r = __raw_readl(base + GPIO2_INTENABLE); 351 unsigned long r = __raw_readl(base + AU1000_GPIO2_INTENABLE);
356 if (en) 352 if (en)
357 r |= 1 << gpio2; 353 r |= 1 << gpio2;
358 else 354 else
359 r &= ~(1 << gpio2); 355 r &= ~(1 << gpio2);
360 __raw_writel(r, base + GPIO2_INTENABLE); 356 __raw_writel(r, base + AU1000_GPIO2_INTENABLE);
361 wmb(); 357 wmb();
362} 358}
363 359
@@ -434,9 +430,9 @@ static inline void alchemy_gpio2_disable_int(int gpio2)
434static inline void alchemy_gpio2_enable(void) 430static inline void alchemy_gpio2_enable(void)
435{ 431{
436 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR); 432 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR);
437 __raw_writel(3, base + GPIO2_ENABLE); /* reset, clock enabled */ 433 __raw_writel(3, base + AU1000_GPIO2_ENABLE); /* reset, clock enabled */
438 wmb(); 434 wmb();
439 __raw_writel(1, base + GPIO2_ENABLE); /* clock enabled */ 435 __raw_writel(1, base + AU1000_GPIO2_ENABLE); /* clock enabled */
440 wmb(); 436 wmb();
441} 437}
442 438
@@ -448,7 +444,7 @@ static inline void alchemy_gpio2_enable(void)
448static inline void alchemy_gpio2_disable(void) 444static inline void alchemy_gpio2_disable(void)
449{ 445{
450 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR); 446 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR);
451 __raw_writel(2, base + GPIO2_ENABLE); /* reset, clock disabled */ 447 __raw_writel(2, base + AU1000_GPIO2_ENABLE); /* reset, clock disabled */
452 wmb(); 448 wmb();
453} 449}
454 450
diff --git a/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h b/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h
index bba7399a49a3..1f5643b89a91 100644
--- a/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h
+++ b/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h
@@ -18,6 +18,7 @@ enum bcm47xx_board {
18 BCM47XX_BOARD_ASUS_WL300G, 18 BCM47XX_BOARD_ASUS_WL300G,
19 BCM47XX_BOARD_ASUS_WL320GE, 19 BCM47XX_BOARD_ASUS_WL320GE,
20 BCM47XX_BOARD_ASUS_WL330GE, 20 BCM47XX_BOARD_ASUS_WL330GE,
21 BCM47XX_BOARD_ASUS_WL500G,
21 BCM47XX_BOARD_ASUS_WL500GD, 22 BCM47XX_BOARD_ASUS_WL500GD,
22 BCM47XX_BOARD_ASUS_WL500GPV1, 23 BCM47XX_BOARD_ASUS_WL500GPV1,
23 BCM47XX_BOARD_ASUS_WL500GPV2, 24 BCM47XX_BOARD_ASUS_WL500GPV2,
@@ -70,11 +71,15 @@ enum bcm47xx_board {
70 BCM47XX_BOARD_LINKSYS_WRT310NV1, 71 BCM47XX_BOARD_LINKSYS_WRT310NV1,
71 BCM47XX_BOARD_LINKSYS_WRT310NV2, 72 BCM47XX_BOARD_LINKSYS_WRT310NV2,
72 BCM47XX_BOARD_LINKSYS_WRT54G3GV2, 73 BCM47XX_BOARD_LINKSYS_WRT54G3GV2,
73 BCM47XX_BOARD_LINKSYS_WRT54G, 74 BCM47XX_BOARD_LINKSYS_WRT54G_TYPE_0101,
75 BCM47XX_BOARD_LINKSYS_WRT54G_TYPE_0467,
76 BCM47XX_BOARD_LINKSYS_WRT54G_TYPE_0708,
74 BCM47XX_BOARD_LINKSYS_WRT610NV1, 77 BCM47XX_BOARD_LINKSYS_WRT610NV1,
75 BCM47XX_BOARD_LINKSYS_WRT610NV2, 78 BCM47XX_BOARD_LINKSYS_WRT610NV2,
76 BCM47XX_BOARD_LINKSYS_WRTSL54GS, 79 BCM47XX_BOARD_LINKSYS_WRTSL54GS,
77 80
81 BCM47XX_BOARD_MICROSOFT_MN700,
82
78 BCM47XX_BOARD_MOTOROLA_WE800G, 83 BCM47XX_BOARD_MOTOROLA_WE800G,
79 BCM47XX_BOARD_MOTOROLA_WR850GP, 84 BCM47XX_BOARD_MOTOROLA_WR850GP,
80 BCM47XX_BOARD_MOTOROLA_WR850GV2V3, 85 BCM47XX_BOARD_MOTOROLA_WR850GV2V3,
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
index 3112f08f0c72..56bb19219d48 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
@@ -19,118 +19,68 @@
19#define BCM6368_CPU_ID 0x6368 19#define BCM6368_CPU_ID 0x6368
20 20
21void __init bcm63xx_cpu_init(void); 21void __init bcm63xx_cpu_init(void);
22u16 __bcm63xx_get_cpu_id(void);
23u8 bcm63xx_get_cpu_rev(void); 22u8 bcm63xx_get_cpu_rev(void);
24unsigned int bcm63xx_get_cpu_freq(void); 23unsigned int bcm63xx_get_cpu_freq(void);
25 24
25static inline u16 __pure __bcm63xx_get_cpu_id(const u16 cpu_id)
26{
27 switch (cpu_id) {
26#ifdef CONFIG_BCM63XX_CPU_3368 28#ifdef CONFIG_BCM63XX_CPU_3368
27# ifdef bcm63xx_get_cpu_id 29 case BCM3368_CPU_ID:
28# undef bcm63xx_get_cpu_id
29# define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
30# define BCMCPU_RUNTIME_DETECT
31# else
32# define bcm63xx_get_cpu_id() BCM3368_CPU_ID
33# endif
34# define BCMCPU_IS_3368() (bcm63xx_get_cpu_id() == BCM3368_CPU_ID)
35#else
36# define BCMCPU_IS_3368() (0)
37#endif 30#endif
38 31
39#ifdef CONFIG_BCM63XX_CPU_6328 32#ifdef CONFIG_BCM63XX_CPU_6328
40# ifdef bcm63xx_get_cpu_id 33 case BCM6328_CPU_ID:
41# undef bcm63xx_get_cpu_id
42# define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
43# define BCMCPU_RUNTIME_DETECT
44# else
45# define bcm63xx_get_cpu_id() BCM6328_CPU_ID
46# endif
47# define BCMCPU_IS_6328() (bcm63xx_get_cpu_id() == BCM6328_CPU_ID)
48#else
49# define BCMCPU_IS_6328() (0)
50#endif 34#endif
51 35
52#ifdef CONFIG_BCM63XX_CPU_6338 36#ifdef CONFIG_BCM63XX_CPU_6338
53# ifdef bcm63xx_get_cpu_id 37 case BCM6338_CPU_ID:
54# undef bcm63xx_get_cpu_id
55# define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
56# define BCMCPU_RUNTIME_DETECT
57# else
58# define bcm63xx_get_cpu_id() BCM6338_CPU_ID
59# endif
60# define BCMCPU_IS_6338() (bcm63xx_get_cpu_id() == BCM6338_CPU_ID)
61#else
62# define BCMCPU_IS_6338() (0)
63#endif 38#endif
64 39
65#ifdef CONFIG_BCM63XX_CPU_6345 40#ifdef CONFIG_BCM63XX_CPU_6345
66# ifdef bcm63xx_get_cpu_id 41 case BCM6345_CPU_ID:
67# undef bcm63xx_get_cpu_id
68# define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
69# define BCMCPU_RUNTIME_DETECT
70# else
71# define bcm63xx_get_cpu_id() BCM6345_CPU_ID
72# endif
73# define BCMCPU_IS_6345() (bcm63xx_get_cpu_id() == BCM6345_CPU_ID)
74#else
75# define BCMCPU_IS_6345() (0)
76#endif 42#endif
77 43
78#ifdef CONFIG_BCM63XX_CPU_6348 44#ifdef CONFIG_BCM63XX_CPU_6348
79# ifdef bcm63xx_get_cpu_id 45 case BCM6348_CPU_ID:
80# undef bcm63xx_get_cpu_id
81# define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
82# define BCMCPU_RUNTIME_DETECT
83# else
84# define bcm63xx_get_cpu_id() BCM6348_CPU_ID
85# endif
86# define BCMCPU_IS_6348() (bcm63xx_get_cpu_id() == BCM6348_CPU_ID)
87#else
88# define BCMCPU_IS_6348() (0)
89#endif 46#endif
90 47
91#ifdef CONFIG_BCM63XX_CPU_6358 48#ifdef CONFIG_BCM63XX_CPU_6358
92# ifdef bcm63xx_get_cpu_id 49 case BCM6358_CPU_ID:
93# undef bcm63xx_get_cpu_id
94# define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
95# define BCMCPU_RUNTIME_DETECT
96# else
97# define bcm63xx_get_cpu_id() BCM6358_CPU_ID
98# endif
99# define BCMCPU_IS_6358() (bcm63xx_get_cpu_id() == BCM6358_CPU_ID)
100#else
101# define BCMCPU_IS_6358() (0)
102#endif 50#endif
103 51
104#ifdef CONFIG_BCM63XX_CPU_6362 52#ifdef CONFIG_BCM63XX_CPU_6362
105# ifdef bcm63xx_get_cpu_id 53 case BCM6362_CPU_ID:
106# undef bcm63xx_get_cpu_id
107# define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
108# define BCMCPU_RUNTIME_DETECT
109# else
110# define bcm63xx_get_cpu_id() BCM6362_CPU_ID
111# endif
112# define BCMCPU_IS_6362() (bcm63xx_get_cpu_id() == BCM6362_CPU_ID)
113#else
114# define BCMCPU_IS_6362() (0)
115#endif 54#endif
116 55
117
118#ifdef CONFIG_BCM63XX_CPU_6368 56#ifdef CONFIG_BCM63XX_CPU_6368
119# ifdef bcm63xx_get_cpu_id 57 case BCM6368_CPU_ID:
120# undef bcm63xx_get_cpu_id
121# define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
122# define BCMCPU_RUNTIME_DETECT
123# else
124# define bcm63xx_get_cpu_id() BCM6368_CPU_ID
125# endif
126# define BCMCPU_IS_6368() (bcm63xx_get_cpu_id() == BCM6368_CPU_ID)
127#else
128# define BCMCPU_IS_6368() (0)
129#endif 58#endif
59 break;
60 default:
61 unreachable();
62 }
130 63
131#ifndef bcm63xx_get_cpu_id 64 return cpu_id;
132#error "No CPU support configured" 65}
133#endif 66
67extern u16 bcm63xx_cpu_id;
68
69static inline u16 __pure bcm63xx_get_cpu_id(void)
70{
71 const u16 cpu_id = bcm63xx_cpu_id;
72
73 return __bcm63xx_get_cpu_id(cpu_id);
74}
75
76#define BCMCPU_IS_3368() (bcm63xx_get_cpu_id() == BCM3368_CPU_ID)
77#define BCMCPU_IS_6328() (bcm63xx_get_cpu_id() == BCM6328_CPU_ID)
78#define BCMCPU_IS_6338() (bcm63xx_get_cpu_id() == BCM6338_CPU_ID)
79#define BCMCPU_IS_6345() (bcm63xx_get_cpu_id() == BCM6345_CPU_ID)
80#define BCMCPU_IS_6348() (bcm63xx_get_cpu_id() == BCM6348_CPU_ID)
81#define BCMCPU_IS_6358() (bcm63xx_get_cpu_id() == BCM6358_CPU_ID)
82#define BCMCPU_IS_6362() (bcm63xx_get_cpu_id() == BCM6362_CPU_ID)
83#define BCMCPU_IS_6368() (bcm63xx_get_cpu_id() == BCM6368_CPU_ID)
134 84
135/* 85/*
136 * While registers sets are (mostly) the same across 63xx CPU, base 86 * While registers sets are (mostly) the same across 63xx CPU, base
@@ -598,55 +548,6 @@ enum bcm63xx_regs_set {
598 548
599extern const unsigned long *bcm63xx_regs_base; 549extern const unsigned long *bcm63xx_regs_base;
600 550
601#define __GEN_RSET_BASE(__cpu, __rset) \
602 case RSET_## __rset : \
603 return BCM_## __cpu ##_## __rset ##_BASE;
604
605#define __GEN_RSET(__cpu) \
606 switch (set) { \
607 __GEN_RSET_BASE(__cpu, DSL_LMEM) \
608 __GEN_RSET_BASE(__cpu, PERF) \
609 __GEN_RSET_BASE(__cpu, TIMER) \
610 __GEN_RSET_BASE(__cpu, WDT) \
611 __GEN_RSET_BASE(__cpu, UART0) \
612 __GEN_RSET_BASE(__cpu, UART1) \
613 __GEN_RSET_BASE(__cpu, GPIO) \
614 __GEN_RSET_BASE(__cpu, SPI) \
615 __GEN_RSET_BASE(__cpu, HSSPI) \
616 __GEN_RSET_BASE(__cpu, UDC0) \
617 __GEN_RSET_BASE(__cpu, OHCI0) \
618 __GEN_RSET_BASE(__cpu, OHCI_PRIV) \
619 __GEN_RSET_BASE(__cpu, USBH_PRIV) \
620 __GEN_RSET_BASE(__cpu, USBD) \
621 __GEN_RSET_BASE(__cpu, USBDMA) \
622 __GEN_RSET_BASE(__cpu, MPI) \
623 __GEN_RSET_BASE(__cpu, PCMCIA) \
624 __GEN_RSET_BASE(__cpu, PCIE) \
625 __GEN_RSET_BASE(__cpu, DSL) \
626 __GEN_RSET_BASE(__cpu, ENET0) \
627 __GEN_RSET_BASE(__cpu, ENET1) \
628 __GEN_RSET_BASE(__cpu, ENETDMA) \
629 __GEN_RSET_BASE(__cpu, ENETDMAC) \
630 __GEN_RSET_BASE(__cpu, ENETDMAS) \
631 __GEN_RSET_BASE(__cpu, ENETSW) \
632 __GEN_RSET_BASE(__cpu, EHCI0) \
633 __GEN_RSET_BASE(__cpu, SDRAM) \
634 __GEN_RSET_BASE(__cpu, MEMC) \
635 __GEN_RSET_BASE(__cpu, DDR) \
636 __GEN_RSET_BASE(__cpu, M2M) \
637 __GEN_RSET_BASE(__cpu, ATM) \
638 __GEN_RSET_BASE(__cpu, XTM) \
639 __GEN_RSET_BASE(__cpu, XTMDMA) \
640 __GEN_RSET_BASE(__cpu, XTMDMAC) \
641 __GEN_RSET_BASE(__cpu, XTMDMAS) \
642 __GEN_RSET_BASE(__cpu, PCM) \
643 __GEN_RSET_BASE(__cpu, PCMDMA) \
644 __GEN_RSET_BASE(__cpu, PCMDMAC) \
645 __GEN_RSET_BASE(__cpu, PCMDMAS) \
646 __GEN_RSET_BASE(__cpu, RNG) \
647 __GEN_RSET_BASE(__cpu, MISC) \
648 }
649
650#define __GEN_CPU_REGS_TABLE(__cpu) \ 551#define __GEN_CPU_REGS_TABLE(__cpu) \
651 [RSET_DSL_LMEM] = BCM_## __cpu ##_DSL_LMEM_BASE, \ 552 [RSET_DSL_LMEM] = BCM_## __cpu ##_DSL_LMEM_BASE, \
652 [RSET_PERF] = BCM_## __cpu ##_PERF_BASE, \ 553 [RSET_PERF] = BCM_## __cpu ##_PERF_BASE, \
@@ -693,36 +594,7 @@ extern const unsigned long *bcm63xx_regs_base;
693 594
694static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set) 595static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
695{ 596{
696#ifdef BCMCPU_RUNTIME_DETECT
697 return bcm63xx_regs_base[set]; 597 return bcm63xx_regs_base[set];
698#else
699#ifdef CONFIG_BCM63XX_CPU_3368
700 __GEN_RSET(3368)
701#endif
702#ifdef CONFIG_BCM63XX_CPU_6328
703 __GEN_RSET(6328)
704#endif
705#ifdef CONFIG_BCM63XX_CPU_6338
706 __GEN_RSET(6338)
707#endif
708#ifdef CONFIG_BCM63XX_CPU_6345
709 __GEN_RSET(6345)
710#endif
711#ifdef CONFIG_BCM63XX_CPU_6348
712 __GEN_RSET(6348)
713#endif
714#ifdef CONFIG_BCM63XX_CPU_6358
715 __GEN_RSET(6358)
716#endif
717#ifdef CONFIG_BCM63XX_CPU_6362
718 __GEN_RSET(6362)
719#endif
720#ifdef CONFIG_BCM63XX_CPU_6368
721 __GEN_RSET(6368)
722#endif
723#endif
724 /* unreached */
725 return 0;
726} 598}
727 599
728/* 600/*
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h
index 753953e86242..466fc85899f4 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h
@@ -112,55 +112,9 @@ enum bcm63xx_regs_enetdmac {
112 112
113static inline unsigned long bcm63xx_enetdmacreg(enum bcm63xx_regs_enetdmac reg) 113static inline unsigned long bcm63xx_enetdmacreg(enum bcm63xx_regs_enetdmac reg)
114{ 114{
115#ifdef BCMCPU_RUNTIME_DETECT
116 extern const unsigned long *bcm63xx_regs_enetdmac; 115 extern const unsigned long *bcm63xx_regs_enetdmac;
117 116
118 return bcm63xx_regs_enetdmac[reg]; 117 return bcm63xx_regs_enetdmac[reg];
119#else
120#ifdef CONFIG_BCM63XX_CPU_6345
121 switch (reg) {
122 case ENETDMAC_CHANCFG:
123 return ENETDMA_6345_CHANCFG_REG;
124 case ENETDMAC_IR:
125 return ENETDMA_6345_IR_REG;
126 case ENETDMAC_IRMASK:
127 return ENETDMA_6345_IRMASK_REG;
128 case ENETDMAC_MAXBURST:
129 return ENETDMA_6345_MAXBURST_REG;
130 case ENETDMAC_BUFALLOC:
131 return ENETDMA_6345_BUFALLOC_REG;
132 case ENETDMAC_RSTART:
133 return ENETDMA_6345_RSTART_REG;
134 case ENETDMAC_FC:
135 return ENETDMA_6345_FC_REG;
136 case ENETDMAC_LEN:
137 return ENETDMA_6345_LEN_REG;
138 }
139#endif
140#if defined(CONFIG_BCM63XX_CPU_6328) || \
141 defined(CONFIG_BCM63XX_CPU_6338) || \
142 defined(CONFIG_BCM63XX_CPU_6348) || \
143 defined(CONFIG_BCM63XX_CPU_6358) || \
144 defined(CONFIG_BCM63XX_CPU_6362) || \
145 defined(CONFIG_BCM63XX_CPU_6368)
146 switch (reg) {
147 case ENETDMAC_CHANCFG:
148 return ENETDMAC_CHANCFG_REG;
149 case ENETDMAC_IR:
150 return ENETDMAC_IR_REG;
151 case ENETDMAC_IRMASK:
152 return ENETDMAC_IRMASK_REG;
153 case ENETDMAC_MAXBURST:
154 return ENETDMAC_MAXBURST_REG;
155 case ENETDMAC_BUFALLOC:
156 case ENETDMAC_RSTART:
157 case ENETDMAC_FC:
158 case ENETDMAC_LEN:
159 return 0;
160 }
161#endif
162#endif
163 return 0;
164} 118}
165 119
166 120
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h
index c426cabc620a..25737655d141 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h
@@ -30,26 +30,6 @@ enum bcm63xx_regs_spi {
30 SPI_RX_DATA, 30 SPI_RX_DATA,
31}; 31};
32 32
33#define __GEN_SPI_RSET_BASE(__cpu, __rset) \
34 case SPI_## __rset: \
35 return SPI_## __cpu ##_## __rset;
36
37#define __GEN_SPI_RSET(__cpu) \
38 switch (reg) { \
39 __GEN_SPI_RSET_BASE(__cpu, CMD) \
40 __GEN_SPI_RSET_BASE(__cpu, INT_STATUS) \
41 __GEN_SPI_RSET_BASE(__cpu, INT_MASK_ST) \
42 __GEN_SPI_RSET_BASE(__cpu, INT_MASK) \
43 __GEN_SPI_RSET_BASE(__cpu, ST) \
44 __GEN_SPI_RSET_BASE(__cpu, CLK_CFG) \
45 __GEN_SPI_RSET_BASE(__cpu, FILL_BYTE) \
46 __GEN_SPI_RSET_BASE(__cpu, MSG_TAIL) \
47 __GEN_SPI_RSET_BASE(__cpu, RX_TAIL) \
48 __GEN_SPI_RSET_BASE(__cpu, MSG_CTL) \
49 __GEN_SPI_RSET_BASE(__cpu, MSG_DATA) \
50 __GEN_SPI_RSET_BASE(__cpu, RX_DATA) \
51 }
52
53#define __GEN_SPI_REGS_TABLE(__cpu) \ 33#define __GEN_SPI_REGS_TABLE(__cpu) \
54 [SPI_CMD] = SPI_## __cpu ##_CMD, \ 34 [SPI_CMD] = SPI_## __cpu ##_CMD, \
55 [SPI_INT_STATUS] = SPI_## __cpu ##_INT_STATUS, \ 35 [SPI_INT_STATUS] = SPI_## __cpu ##_INT_STATUS, \
@@ -66,20 +46,9 @@ enum bcm63xx_regs_spi {
66 46
67static inline unsigned long bcm63xx_spireg(enum bcm63xx_regs_spi reg) 47static inline unsigned long bcm63xx_spireg(enum bcm63xx_regs_spi reg)
68{ 48{
69#ifdef BCMCPU_RUNTIME_DETECT
70 extern const unsigned long *bcm63xx_regs_spi; 49 extern const unsigned long *bcm63xx_regs_spi;
71 50
72 return bcm63xx_regs_spi[reg]; 51 return bcm63xx_regs_spi[reg];
73#else
74#if defined(CONFIG_BCM63XX_CPU_6338) || defined(CONFIG_BCM63XX_CPU_6348)
75 __GEN_SPI_RSET(6348)
76#endif
77#if defined(CONFIG_BCM63XX_CPU_6358) || defined(CONFIG_BCM63XX_CPU_6362) || \
78 defined(CONFIG_BCM63XX_CPU_6368)
79 __GEN_SPI_RSET(6358)
80#endif
81#endif
82 return 0;
83} 52}
84 53
85#endif /* BCM63XX_DEV_SPI_H */ 54#endif /* BCM63XX_DEV_SPI_H */
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
index ab427f8814e6..4794067cb5a7 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
@@ -215,23 +215,23 @@
215 215
216/* Interrupt Mask register */ 216/* Interrupt Mask register */
217#define PERF_IRQMASK_3368_REG 0xc 217#define PERF_IRQMASK_3368_REG 0xc
218#define PERF_IRQMASK_6328_REG 0x20 218#define PERF_IRQMASK_6328_REG(x) (0x20 + (x) * 0x10)
219#define PERF_IRQMASK_6338_REG 0xc 219#define PERF_IRQMASK_6338_REG 0xc
220#define PERF_IRQMASK_6345_REG 0xc 220#define PERF_IRQMASK_6345_REG 0xc
221#define PERF_IRQMASK_6348_REG 0xc 221#define PERF_IRQMASK_6348_REG 0xc
222#define PERF_IRQMASK_6358_REG 0xc 222#define PERF_IRQMASK_6358_REG(x) (0xc + (x) * 0x2c)
223#define PERF_IRQMASK_6362_REG 0x20 223#define PERF_IRQMASK_6362_REG(x) (0x20 + (x) * 0x10)
224#define PERF_IRQMASK_6368_REG 0x20 224#define PERF_IRQMASK_6368_REG(x) (0x20 + (x) * 0x10)
225 225
226/* Interrupt Status register */ 226/* Interrupt Status register */
227#define PERF_IRQSTAT_3368_REG 0x10 227#define PERF_IRQSTAT_3368_REG 0x10
228#define PERF_IRQSTAT_6328_REG 0x28 228#define PERF_IRQSTAT_6328_REG(x) (0x28 + (x) * 0x10)
229#define PERF_IRQSTAT_6338_REG 0x10 229#define PERF_IRQSTAT_6338_REG 0x10
230#define PERF_IRQSTAT_6345_REG 0x10 230#define PERF_IRQSTAT_6345_REG 0x10
231#define PERF_IRQSTAT_6348_REG 0x10 231#define PERF_IRQSTAT_6348_REG 0x10
232#define PERF_IRQSTAT_6358_REG 0x10 232#define PERF_IRQSTAT_6358_REG(x) (0x10 + (x) * 0x2c)
233#define PERF_IRQSTAT_6362_REG 0x28 233#define PERF_IRQSTAT_6362_REG(x) (0x28 + (x) * 0x10)
234#define PERF_IRQSTAT_6368_REG 0x28 234#define PERF_IRQSTAT_6368_REG(x) (0x28 + (x) * 0x10)
235 235
236/* External Interrupt Configuration register */ 236/* External Interrupt Configuration register */
237#define PERF_EXTIRQ_CFG_REG_3368 0x14 237#define PERF_EXTIRQ_CFG_REG_3368 0x14
diff --git a/arch/mips/include/asm/mach-bcm63xx/cpu-feature-overrides.h b/arch/mips/include/asm/mach-bcm63xx/cpu-feature-overrides.h
index e9c408e8ff4c..bc1167dbd4e3 100644
--- a/arch/mips/include/asm/mach-bcm63xx/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-bcm63xx/cpu-feature-overrides.h
@@ -24,7 +24,7 @@
24#define cpu_has_smartmips 0 24#define cpu_has_smartmips 0
25#define cpu_has_vtag_icache 0 25#define cpu_has_vtag_icache 0
26 26
27#if !defined(BCMCPU_RUNTIME_DETECT) && (defined(CONFIG_BCM63XX_CPU_6348) || defined(CONFIG_BCM63XX_CPU_6345) || defined(CONFIG_BCM63XX_CPU_6338)) 27#if !defined(CONFIG_SYS_HAS_CPU_BMIPS4350)
28#define cpu_has_dc_aliases 0 28#define cpu_has_dc_aliases 0
29#endif 29#endif
30 30
diff --git a/arch/mips/include/asm/mach-loongson/boot_param.h b/arch/mips/include/asm/mach-loongson/boot_param.h
index 829a7ec185fb..3388fc53599e 100644
--- a/arch/mips/include/asm/mach-loongson/boot_param.h
+++ b/arch/mips/include/asm/mach-loongson/boot_param.h
@@ -146,6 +146,9 @@ struct boot_params {
146 146
147struct loongson_system_configuration { 147struct loongson_system_configuration {
148 u32 nr_cpus; 148 u32 nr_cpus;
149 u32 nr_nodes;
150 int cores_per_node;
151 int cores_per_package;
149 enum loongson_cpu_type cputype; 152 enum loongson_cpu_type cputype;
150 u64 ht_control_base; 153 u64 ht_control_base;
151 u64 pci_mem_start_addr; 154 u64 pci_mem_start_addr;
@@ -160,4 +163,5 @@ struct loongson_system_configuration {
160 163
161extern struct efi_memory_map_loongson *loongson_memmap; 164extern struct efi_memory_map_loongson *loongson_memmap;
162extern struct loongson_system_configuration loongson_sysconf; 165extern struct loongson_system_configuration loongson_sysconf;
166extern int cpuhotplug_workaround;
163#endif 167#endif
diff --git a/arch/mips/include/asm/mach-loongson/kernel-entry-init.h b/arch/mips/include/asm/mach-loongson/kernel-entry-init.h
new file mode 100644
index 000000000000..df5fca8eeb80
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson/kernel-entry-init.h
@@ -0,0 +1,52 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2005 Embedded Alley Solutions, Inc
7 * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
8 * Copyright (C) 2009 Jiajie Chen (chenjiajie@cse.buaa.edu.cn)
9 * Copyright (C) 2012 Huacai Chen (chenhc@lemote.com)
10 */
11#ifndef __ASM_MACH_LOONGSON_KERNEL_ENTRY_H
12#define __ASM_MACH_LOONGSON_KERNEL_ENTRY_H
13
14/*
15 * Override macros used in arch/mips/kernel/head.S.
16 */
17 .macro kernel_entry_setup
18#ifdef CONFIG_CPU_LOONGSON3
19 .set push
20 .set mips64
21 /* Set LPA on LOONGSON3 config3 */
22 mfc0 t0, $16, 3
23 or t0, (0x1 << 7)
24 mtc0 t0, $16, 3
25 /* Set ELPA on LOONGSON3 pagegrain */
26 li t0, (0x1 << 29)
27 mtc0 t0, $5, 1
28 _ehb
29 .set pop
30#endif
31 .endm
32
33/*
34 * Do SMP slave processor setup.
35 */
36 .macro smp_slave_setup
37#ifdef CONFIG_CPU_LOONGSON3
38 .set push
39 .set mips64
40 /* Set LPA on LOONGSON3 config3 */
41 mfc0 t0, $16, 3
42 or t0, (0x1 << 7)
43 mtc0 t0, $16, 3
44 /* Set ELPA on LOONGSON3 pagegrain */
45 li t0, (0x1 << 29)
46 mtc0 t0, $5, 1
47 _ehb
48 .set pop
49#endif
50 .endm
51
52#endif /* __ASM_MACH_LOONGSON_KERNEL_ENTRY_H */
diff --git a/arch/mips/include/asm/mach-loongson/loongson.h b/arch/mips/include/asm/mach-loongson/loongson.h
index f3fd1eb8e3dd..92bf76c21441 100644
--- a/arch/mips/include/asm/mach-loongson/loongson.h
+++ b/arch/mips/include/asm/mach-loongson/loongson.h
@@ -249,8 +249,15 @@ static inline void do_perfcnt_IRQ(void)
249#define LOONGSON_PXARB_CFG LOONGSON_REG(LOONGSON_REGBASE + 0x68) 249#define LOONGSON_PXARB_CFG LOONGSON_REG(LOONGSON_REGBASE + 0x68)
250#define LOONGSON_PXARB_STATUS LOONGSON_REG(LOONGSON_REGBASE + 0x6c) 250#define LOONGSON_PXARB_STATUS LOONGSON_REG(LOONGSON_REGBASE + 0x6c)
251 251
252/* Chip Config */ 252#define MAX_PACKAGES 4
253#define LOONGSON_CHIPCFG0 LOONGSON_REG(LOONGSON_REGBASE + 0x80) 253
254/* Chip Config registor of each physical cpu package, PRid >= Loongson-2F */
255extern u64 loongson_chipcfg[MAX_PACKAGES];
256#define LOONGSON_CHIPCFG(id) (*(volatile u32 *)(loongson_chipcfg[id]))
257
258/* Freq Control register of each physical cpu package, PRid >= Loongson-3B */
259extern u64 loongson_freqctrl[MAX_PACKAGES];
260#define LOONGSON_FREQCTRL(id) (*(volatile u32 *)(loongson_freqctrl[id]))
254 261
255/* pcimap */ 262/* pcimap */
256 263
diff --git a/arch/mips/include/asm/mach-loongson/machine.h b/arch/mips/include/asm/mach-loongson/machine.h
index 1b1f592fa2be..228e37847a36 100644
--- a/arch/mips/include/asm/mach-loongson/machine.h
+++ b/arch/mips/include/asm/mach-loongson/machine.h
@@ -24,10 +24,10 @@
24 24
25#endif 25#endif
26 26
27#ifdef CONFIG_LEMOTE_MACH3A 27#ifdef CONFIG_LOONGSON_MACH3X
28 28
29#define LOONGSON_MACHTYPE MACH_LEMOTE_A1101 29#define LOONGSON_MACHTYPE MACH_LEMOTE_A1101
30 30
31#endif /* CONFIG_LEMOTE_MACH3A */ 31#endif /* CONFIG_LOONGSON_MACH3X */
32 32
33#endif /* __ASM_MACH_LOONGSON_MACHINE_H */ 33#endif /* __ASM_MACH_LOONGSON_MACHINE_H */
diff --git a/arch/mips/include/asm/mach-loongson/mmzone.h b/arch/mips/include/asm/mach-loongson/mmzone.h
new file mode 100644
index 000000000000..37c08a27b4f0
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson/mmzone.h
@@ -0,0 +1,53 @@
1/*
2 * Copyright (C) 2010 Loongson Inc. & Lemote Inc. &
3 * Insititute of Computing Technology
4 * Author: Xiang Gao, gaoxiang@ict.ac.cn
5 * Huacai Chen, chenhc@lemote.com
6 * Xiaofu Meng, Shuangshuang Zhang
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13#ifndef _ASM_MACH_MMZONE_H
14#define _ASM_MACH_MMZONE_H
15
16#include <boot_param.h>
17#define NODE_ADDRSPACE_SHIFT 44
18#define NODE0_ADDRSPACE_OFFSET 0x000000000000UL
19#define NODE1_ADDRSPACE_OFFSET 0x100000000000UL
20#define NODE2_ADDRSPACE_OFFSET 0x200000000000UL
21#define NODE3_ADDRSPACE_OFFSET 0x300000000000UL
22
23#define pa_to_nid(addr) (((addr) & 0xf00000000000) >> NODE_ADDRSPACE_SHIFT)
24
25#define LEVELS_PER_SLICE 128
26
27struct slice_data {
28 unsigned long irq_enable_mask[2];
29 int level_to_irq[LEVELS_PER_SLICE];
30};
31
32struct hub_data {
33 cpumask_t h_cpus;
34 unsigned long slice_map;
35 unsigned long irq_alloc_mask[2];
36 struct slice_data slice[2];
37};
38
39struct node_data {
40 struct pglist_data pglist;
41 struct hub_data hub;
42 cpumask_t cpumask;
43};
44
45extern struct node_data *__node_data[];
46
47#define NODE_DATA(n) (&__node_data[(n)]->pglist)
48#define hub_data(n) (&__node_data[(n)]->hub)
49
50extern void setup_zero_pages(void);
51extern void __init prom_init_numa_memory(void);
52
53#endif /* _ASM_MACH_MMZONE_H */
diff --git a/arch/mips/include/asm/mach-loongson/topology.h b/arch/mips/include/asm/mach-loongson/topology.h
new file mode 100644
index 000000000000..5598ba77d2ef
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson/topology.h
@@ -0,0 +1,23 @@
1#ifndef _ASM_MACH_TOPOLOGY_H
2#define _ASM_MACH_TOPOLOGY_H
3
4#ifdef CONFIG_NUMA
5
6#define cpu_to_node(cpu) ((cpu) >> 2)
7#define parent_node(node) (node)
8#define cpumask_of_node(node) (&__node_data[(node)]->cpumask)
9
10struct pci_bus;
11extern int pcibus_to_node(struct pci_bus *);
12
13#define cpumask_of_pcibus(bus) (cpu_online_mask)
14
15extern unsigned char __node_distances[MAX_NUMNODES][MAX_NUMNODES];
16
17#define node_distance(from, to) (__node_distances[(from)][(to)])
18
19#endif
20
21#include <asm-generic/topology.h>
22
23#endif /* _ASM_MACH_TOPOLOGY_H */
diff --git a/arch/mips/include/asm/mach-malta/irq.h b/arch/mips/include/asm/mach-malta/irq.h
index 47cfe64efbb0..f2c13d211abb 100644
--- a/arch/mips/include/asm/mach-malta/irq.h
+++ b/arch/mips/include/asm/mach-malta/irq.h
@@ -2,6 +2,7 @@
2#define __ASM_MACH_MIPS_IRQ_H 2#define __ASM_MACH_MIPS_IRQ_H
3 3
4 4
5#define GIC_NUM_INTRS (24 + NR_CPUS * 2)
5#define NR_IRQS 256 6#define NR_IRQS 256
6 7
7#include_next <irq.h> 8#include_next <irq.h>
diff --git a/arch/mips/include/asm/mach-sead3/irq.h b/arch/mips/include/asm/mach-sead3/irq.h
index 5d154cfbcf4c..d8106f75b9af 100644
--- a/arch/mips/include/asm/mach-sead3/irq.h
+++ b/arch/mips/include/asm/mach-sead3/irq.h
@@ -1,6 +1,7 @@
1#ifndef __ASM_MACH_MIPS_IRQ_H 1#ifndef __ASM_MACH_MIPS_IRQ_H
2#define __ASM_MACH_MIPS_IRQ_H 2#define __ASM_MACH_MIPS_IRQ_H
3 3
4#define GIC_NUM_INTRS (24 + NR_CPUS * 2)
4#define NR_IRQS 256 5#define NR_IRQS 256
5 6
6 7
diff --git a/arch/mips/include/asm/mips-boards/bonito64.h b/arch/mips/include/asm/mips-boards/bonito64.h
index b2048d1bcc1c..5368891d424b 100644
--- a/arch/mips/include/asm/mips-boards/bonito64.h
+++ b/arch/mips/include/asm/mips-boards/bonito64.h
@@ -414,7 +414,6 @@ extern unsigned long _pcictrl_bonito_pcicfg;
414 414
415 415
416#define BONITO_PCIMEMBASECFG_ADDRMASK(WIN, CFG) ((((CFG) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK) >> BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT) << BONITO_PCIMEMBASECFG_ASHIFT) 416#define BONITO_PCIMEMBASECFG_ADDRMASK(WIN, CFG) ((((CFG) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK) >> BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT) << BONITO_PCIMEMBASECFG_ASHIFT)
417#define BONITO_PCIMEMBASECFG_ADDRMASK(WIN, CFG) ((((CFG) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK) >> BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT) << BONITO_PCIMEMBASECFG_ASHIFT)
418#define BONITO_PCIMEMBASECFG_ADDRTRANS(WIN, CFG) ((((CFG) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS) >> BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS_SHIFT) << BONITO_PCIMEMBASECFG_ASHIFT) 417#define BONITO_PCIMEMBASECFG_ADDRTRANS(WIN, CFG) ((((CFG) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS) >> BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS_SHIFT) << BONITO_PCIMEMBASECFG_ASHIFT)
419 418
420#define BONITO_PCITOPHYS(WIN, ADDR, CFG) ( \ 419#define BONITO_PCITOPHYS(WIN, ADDR, CFG) ( \
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 98e9754a4b6b..cf3b580c3df6 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -265,6 +265,7 @@
265#define PG_XIE (_ULCAST_(1) << 30) 265#define PG_XIE (_ULCAST_(1) << 30)
266#define PG_ELPA (_ULCAST_(1) << 29) 266#define PG_ELPA (_ULCAST_(1) << 29)
267#define PG_ESP (_ULCAST_(1) << 28) 267#define PG_ESP (_ULCAST_(1) << 28)
268#define PG_IEC (_ULCAST_(1) << 27)
268 269
269/* 270/*
270 * R4x00 interrupt enable / cause bits 271 * R4x00 interrupt enable / cause bits
@@ -630,7 +631,6 @@
630#define MIPS_CONF4_MMUSIZEEXT_SHIFT (0) 631#define MIPS_CONF4_MMUSIZEEXT_SHIFT (0)
631#define MIPS_CONF4_MMUSIZEEXT (_ULCAST_(255) << 0) 632#define MIPS_CONF4_MMUSIZEEXT (_ULCAST_(255) << 0)
632#define MIPS_CONF4_FTLBSETS_SHIFT (0) 633#define MIPS_CONF4_FTLBSETS_SHIFT (0)
633#define MIPS_CONF4_FTLBSETS_SHIFT (0)
634#define MIPS_CONF4_FTLBSETS (_ULCAST_(15) << MIPS_CONF4_FTLBSETS_SHIFT) 634#define MIPS_CONF4_FTLBSETS (_ULCAST_(15) << MIPS_CONF4_FTLBSETS_SHIFT)
635#define MIPS_CONF4_FTLBWAYS_SHIFT (4) 635#define MIPS_CONF4_FTLBWAYS_SHIFT (4)
636#define MIPS_CONF4_FTLBWAYS (_ULCAST_(15) << MIPS_CONF4_FTLBWAYS_SHIFT) 636#define MIPS_CONF4_FTLBWAYS (_ULCAST_(15) << MIPS_CONF4_FTLBWAYS_SHIFT)
@@ -652,6 +652,7 @@
652 652
653#define MIPS_CONF5_NF (_ULCAST_(1) << 0) 653#define MIPS_CONF5_NF (_ULCAST_(1) << 0)
654#define MIPS_CONF5_UFR (_ULCAST_(1) << 2) 654#define MIPS_CONF5_UFR (_ULCAST_(1) << 2)
655#define MIPS_CONF5_MRP (_ULCAST_(1) << 3)
655#define MIPS_CONF5_MSAEN (_ULCAST_(1) << 27) 656#define MIPS_CONF5_MSAEN (_ULCAST_(1) << 27)
656#define MIPS_CONF5_EVA (_ULCAST_(1) << 28) 657#define MIPS_CONF5_EVA (_ULCAST_(1) << 28)
657#define MIPS_CONF5_CV (_ULCAST_(1) << 29) 658#define MIPS_CONF5_CV (_ULCAST_(1) << 29)
@@ -668,6 +669,12 @@
668#define MIPS_CONF7_IAR (_ULCAST_(1) << 10) 669#define MIPS_CONF7_IAR (_ULCAST_(1) << 10)
669#define MIPS_CONF7_AR (_ULCAST_(1) << 16) 670#define MIPS_CONF7_AR (_ULCAST_(1) << 16)
670 671
672/* MAAR bit definitions */
673#define MIPS_MAAR_ADDR ((BIT_ULL(BITS_PER_LONG - 12) - 1) << 12)
674#define MIPS_MAAR_ADDR_SHIFT 12
675#define MIPS_MAAR_S (_ULCAST_(1) << 1)
676#define MIPS_MAAR_V (_ULCAST_(1) << 0)
677
671/* EntryHI bit definition */ 678/* EntryHI bit definition */
672#define MIPS_ENTRYHI_EHINV (_ULCAST_(1) << 10) 679#define MIPS_ENTRYHI_EHINV (_ULCAST_(1) << 10)
673 680
@@ -706,6 +713,37 @@
706#define MIPS_SEGCFG_MK _ULCAST_(1) 713#define MIPS_SEGCFG_MK _ULCAST_(1)
707#define MIPS_SEGCFG_UK _ULCAST_(0) 714#define MIPS_SEGCFG_UK _ULCAST_(0)
708 715
716#define MIPS_PWFIELD_GDI_SHIFT 24
717#define MIPS_PWFIELD_GDI_MASK 0x3f000000
718#define MIPS_PWFIELD_UDI_SHIFT 18
719#define MIPS_PWFIELD_UDI_MASK 0x00fc0000
720#define MIPS_PWFIELD_MDI_SHIFT 12
721#define MIPS_PWFIELD_MDI_MASK 0x0003f000
722#define MIPS_PWFIELD_PTI_SHIFT 6
723#define MIPS_PWFIELD_PTI_MASK 0x00000fc0
724#define MIPS_PWFIELD_PTEI_SHIFT 0
725#define MIPS_PWFIELD_PTEI_MASK 0x0000003f
726
727#define MIPS_PWSIZE_GDW_SHIFT 24
728#define MIPS_PWSIZE_GDW_MASK 0x3f000000
729#define MIPS_PWSIZE_UDW_SHIFT 18
730#define MIPS_PWSIZE_UDW_MASK 0x00fc0000
731#define MIPS_PWSIZE_MDW_SHIFT 12
732#define MIPS_PWSIZE_MDW_MASK 0x0003f000
733#define MIPS_PWSIZE_PTW_SHIFT 6
734#define MIPS_PWSIZE_PTW_MASK 0x00000fc0
735#define MIPS_PWSIZE_PTEW_SHIFT 0
736#define MIPS_PWSIZE_PTEW_MASK 0x0000003f
737
738#define MIPS_PWCTL_PWEN_SHIFT 31
739#define MIPS_PWCTL_PWEN_MASK 0x80000000
740#define MIPS_PWCTL_DPH_SHIFT 7
741#define MIPS_PWCTL_DPH_MASK 0x00000080
742#define MIPS_PWCTL_HUGEPG_SHIFT 6
743#define MIPS_PWCTL_HUGEPG_MASK 0x00000060
744#define MIPS_PWCTL_PSN_SHIFT 0
745#define MIPS_PWCTL_PSN_MASK 0x0000003f
746
709#ifndef __ASSEMBLY__ 747#ifndef __ASSEMBLY__
710 748
711/* 749/*
@@ -1044,6 +1082,11 @@ do { \
1044#define write_c0_config6(val) __write_32bit_c0_register($16, 6, val) 1082#define write_c0_config6(val) __write_32bit_c0_register($16, 6, val)
1045#define write_c0_config7(val) __write_32bit_c0_register($16, 7, val) 1083#define write_c0_config7(val) __write_32bit_c0_register($16, 7, val)
1046 1084
1085#define read_c0_maar() __read_ulong_c0_register($17, 1)
1086#define write_c0_maar(val) __write_ulong_c0_register($17, 1, val)
1087#define read_c0_maari() __read_32bit_c0_register($17, 2)
1088#define write_c0_maari(val) __write_32bit_c0_register($17, 2, val)
1089
1047/* 1090/*
1048 * The WatchLo register. There may be up to 8 of them. 1091 * The WatchLo register. There may be up to 8 of them.
1049 */ 1092 */
@@ -1201,6 +1244,19 @@ do { \
1201#define read_c0_segctl2() __read_32bit_c0_register($5, 4) 1244#define read_c0_segctl2() __read_32bit_c0_register($5, 4)
1202#define write_c0_segctl2(val) __write_32bit_c0_register($5, 4, val) 1245#define write_c0_segctl2(val) __write_32bit_c0_register($5, 4, val)
1203 1246
1247/* Hardware Page Table Walker */
1248#define read_c0_pwbase() __read_ulong_c0_register($5, 5)
1249#define write_c0_pwbase(val) __write_ulong_c0_register($5, 5, val)
1250
1251#define read_c0_pwfield() __read_ulong_c0_register($5, 6)
1252#define write_c0_pwfield(val) __write_ulong_c0_register($5, 6, val)
1253
1254#define read_c0_pwsize() __read_ulong_c0_register($5, 7)
1255#define write_c0_pwsize(val) __write_ulong_c0_register($5, 7, val)
1256
1257#define read_c0_pwctl() __read_32bit_c0_register($6, 6)
1258#define write_c0_pwctl(val) __write_32bit_c0_register($6, 6, val)
1259
1204/* Cavium OCTEON (cnMIPS) */ 1260/* Cavium OCTEON (cnMIPS) */
1205#define read_c0_cvmcount() __read_ulong_c0_register($9, 6) 1261#define read_c0_cvmcount() __read_ulong_c0_register($9, 6)
1206#define write_c0_cvmcount(val) __write_ulong_c0_register($9, 6, val) 1262#define write_c0_cvmcount(val) __write_ulong_c0_register($9, 6, val)
diff --git a/arch/mips/include/asm/mmu_context.h b/arch/mips/include/asm/mmu_context.h
index 2e373da5f8e9..2f82568a3ee4 100644
--- a/arch/mips/include/asm/mmu_context.h
+++ b/arch/mips/include/asm/mmu_context.h
@@ -20,10 +20,20 @@
20#include <asm/tlbflush.h> 20#include <asm/tlbflush.h>
21#include <asm-generic/mm_hooks.h> 21#include <asm-generic/mm_hooks.h>
22 22
23#define htw_set_pwbase(pgd) \
24do { \
25 if (cpu_has_htw) { \
26 write_c0_pwbase(pgd); \
27 back_to_back_c0_hazard(); \
28 htw_reset(); \
29 } \
30} while (0)
31
23#define TLBMISS_HANDLER_SETUP_PGD(pgd) \ 32#define TLBMISS_HANDLER_SETUP_PGD(pgd) \
24do { \ 33do { \
25 extern void tlbmiss_handler_setup_pgd(unsigned long); \ 34 extern void tlbmiss_handler_setup_pgd(unsigned long); \
26 tlbmiss_handler_setup_pgd((unsigned long)(pgd)); \ 35 tlbmiss_handler_setup_pgd((unsigned long)(pgd)); \
36 htw_set_pwbase((unsigned long)pgd); \
27} while (0) 37} while (0)
28 38
29#ifdef CONFIG_MIPS_PGD_C0_CONTEXT 39#ifdef CONFIG_MIPS_PGD_C0_CONTEXT
diff --git a/arch/mips/include/asm/msa.h b/arch/mips/include/asm/msa.h
index 538f6d482db8..af5638b12c75 100644
--- a/arch/mips/include/asm/msa.h
+++ b/arch/mips/include/asm/msa.h
@@ -12,8 +12,11 @@
12 12
13#include <asm/mipsregs.h> 13#include <asm/mipsregs.h>
14 14
15#ifndef __ASSEMBLY__
16
15extern void _save_msa(struct task_struct *); 17extern void _save_msa(struct task_struct *);
16extern void _restore_msa(struct task_struct *); 18extern void _restore_msa(struct task_struct *);
19extern void _init_msa_upper(void);
17 20
18static inline void enable_msa(void) 21static inline void enable_msa(void)
19{ 22{
@@ -112,10 +115,10 @@ static inline unsigned int read_msa_##name(void) \
112 " .set push\n" \ 115 " .set push\n" \
113 " .set noat\n" \ 116 " .set noat\n" \
114 " .insn\n" \ 117 " .insn\n" \
115 " .word #CFC_MSA_INSN | (" #cs " << 11)\n" \ 118 " .word %1 | (" #cs " << 11)\n" \
116 " move %0, $1\n" \ 119 " move %0, $1\n" \
117 " .set pop\n" \ 120 " .set pop\n" \
118 : "=r"(reg)); \ 121 : "=r"(reg) : "i"(CFC_MSA_INSN)); \
119 return reg; \ 122 return reg; \
120} \ 123} \
121 \ 124 \
@@ -126,22 +129,13 @@ static inline void write_msa_##name(unsigned int val) \
126 " .set noat\n" \ 129 " .set noat\n" \
127 " move $1, %0\n" \ 130 " move $1, %0\n" \
128 " .insn\n" \ 131 " .insn\n" \
129 " .word #CTC_MSA_INSN | (" #cs " << 6)\n" \ 132 " .word %1 | (" #cs " << 6)\n" \
130 " .set pop\n" \ 133 " .set pop\n" \
131 : : "r"(val)); \ 134 : : "r"(val), "i"(CTC_MSA_INSN)); \
132} 135}
133 136
134#endif /* !TOOLCHAIN_SUPPORTS_MSA */ 137#endif /* !TOOLCHAIN_SUPPORTS_MSA */
135 138
136#define MSA_IR 0
137#define MSA_CSR 1
138#define MSA_ACCESS 2
139#define MSA_SAVE 3
140#define MSA_MODIFY 4
141#define MSA_REQUEST 5
142#define MSA_MAP 6
143#define MSA_UNMAP 7
144
145__BUILD_MSA_CTL_REG(ir, 0) 139__BUILD_MSA_CTL_REG(ir, 0)
146__BUILD_MSA_CTL_REG(csr, 1) 140__BUILD_MSA_CTL_REG(csr, 1)
147__BUILD_MSA_CTL_REG(access, 2) 141__BUILD_MSA_CTL_REG(access, 2)
@@ -151,6 +145,17 @@ __BUILD_MSA_CTL_REG(request, 5)
151__BUILD_MSA_CTL_REG(map, 6) 145__BUILD_MSA_CTL_REG(map, 6)
152__BUILD_MSA_CTL_REG(unmap, 7) 146__BUILD_MSA_CTL_REG(unmap, 7)
153 147
148#endif /* !__ASSEMBLY__ */
149
150#define MSA_IR 0
151#define MSA_CSR 1
152#define MSA_ACCESS 2
153#define MSA_SAVE 3
154#define MSA_MODIFY 4
155#define MSA_REQUEST 5
156#define MSA_MAP 6
157#define MSA_UNMAP 7
158
154/* MSA Implementation Register (MSAIR) */ 159/* MSA Implementation Register (MSAIR) */
155#define MSA_IR_REVB 0 160#define MSA_IR_REVB 0
156#define MSA_IR_REVF (_ULCAST_(0xff) << MSA_IR_REVB) 161#define MSA_IR_REVF (_ULCAST_(0xff) << MSA_IR_REVB)
diff --git a/arch/mips/include/asm/octeon/cvmx-bootinfo.h b/arch/mips/include/asm/octeon/cvmx-bootinfo.h
index 7b7818d1e4d5..2298199a287e 100644
--- a/arch/mips/include/asm/octeon/cvmx-bootinfo.h
+++ b/arch/mips/include/asm/octeon/cvmx-bootinfo.h
@@ -228,6 +228,7 @@ enum cvmx_board_types_enum {
228 */ 228 */
229 CVMX_BOARD_TYPE_CUST_PRIVATE_MIN = 20001, 229 CVMX_BOARD_TYPE_CUST_PRIVATE_MIN = 20001,
230 CVMX_BOARD_TYPE_UBNT_E100 = 20002, 230 CVMX_BOARD_TYPE_UBNT_E100 = 20002,
231 CVMX_BOARD_TYPE_CUST_DSR1000N = 20006,
231 CVMX_BOARD_TYPE_CUST_PRIVATE_MAX = 30000, 232 CVMX_BOARD_TYPE_CUST_PRIVATE_MAX = 30000,
232 233
233 /* The remaining range is reserved for future use. */ 234 /* The remaining range is reserved for future use. */
@@ -327,6 +328,7 @@ static inline const char *cvmx_board_type_to_string(enum
327 /* Customer private range */ 328 /* Customer private range */
328 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_PRIVATE_MIN) 329 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_PRIVATE_MIN)
329 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_UBNT_E100) 330 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_UBNT_E100)
331 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_DSR1000N)
330 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_PRIVATE_MAX) 332 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_PRIVATE_MAX)
331 } 333 }
332 return "Unsupported Board"; 334 return "Unsupported Board";
diff --git a/arch/mips/include/asm/pgtable-32.h b/arch/mips/include/asm/pgtable-32.h
index b4204c179b97..cd7d6064bcbe 100644
--- a/arch/mips/include/asm/pgtable-32.h
+++ b/arch/mips/include/asm/pgtable-32.h
@@ -18,6 +18,18 @@
18 18
19#include <asm-generic/pgtable-nopmd.h> 19#include <asm-generic/pgtable-nopmd.h>
20 20
21extern int temp_tlb_entry __cpuinitdata;
22
23/*
24 * - add_temporary_entry() add a temporary TLB entry. We use TLB entries
25 * starting at the top and working down. This is for populating the
26 * TLB before trap_init() puts the TLB miss handler in place. It
27 * should be used only for entries matching the actual page tables,
28 * to prevent inconsistencies.
29 */
30extern int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1,
31 unsigned long entryhi, unsigned long pagemask);
32
21/* 33/*
22 * Basically we have the same two-level (which is the logical three level 34 * Basically we have the same two-level (which is the logical three level
23 * Linux page table layout folded) page tables as the i386. Some day 35 * Linux page table layout folded) page tables as the i386. Some day
diff --git a/arch/mips/include/asm/pgtable.h b/arch/mips/include/asm/pgtable.h
index 539ddd148bbb..027c74db13f9 100644
--- a/arch/mips/include/asm/pgtable.h
+++ b/arch/mips/include/asm/pgtable.h
@@ -97,6 +97,31 @@ extern void paging_init(void);
97 97
98#define pmd_page_vaddr(pmd) pmd_val(pmd) 98#define pmd_page_vaddr(pmd) pmd_val(pmd)
99 99
100#define htw_stop() \
101do { \
102 if (cpu_has_htw) \
103 write_c0_pwctl(read_c0_pwctl() & \
104 ~(1 << MIPS_PWCTL_PWEN_SHIFT)); \
105} while(0)
106
107#define htw_start() \
108do { \
109 if (cpu_has_htw) \
110 write_c0_pwctl(read_c0_pwctl() | \
111 (1 << MIPS_PWCTL_PWEN_SHIFT)); \
112} while(0)
113
114
115#define htw_reset() \
116do { \
117 if (cpu_has_htw) { \
118 htw_stop(); \
119 back_to_back_c0_hazard(); \
120 htw_start(); \
121 back_to_back_c0_hazard(); \
122 } \
123} while(0)
124
100#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) 125#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
101 126
102#define pte_none(pte) (!(((pte).pte_low | (pte).pte_high) & ~_PAGE_GLOBAL)) 127#define pte_none(pte) (!(((pte).pte_low | (pte).pte_high) & ~_PAGE_GLOBAL))
@@ -131,6 +156,7 @@ static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *pt
131 null.pte_low = null.pte_high = _PAGE_GLOBAL; 156 null.pte_low = null.pte_high = _PAGE_GLOBAL;
132 157
133 set_pte_at(mm, addr, ptep, null); 158 set_pte_at(mm, addr, ptep, null);
159 htw_reset();
134} 160}
135#else 161#else
136 162
@@ -168,6 +194,7 @@ static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *pt
168 else 194 else
169#endif 195#endif
170 set_pte_at(mm, addr, ptep, __pte(0)); 196 set_pte_at(mm, addr, ptep, __pte(0));
197 htw_reset();
171} 198}
172#endif 199#endif
173 200
diff --git a/arch/mips/include/asm/processor.h b/arch/mips/include/asm/processor.h
index d5098bc554f4..05f08438a7c4 100644
--- a/arch/mips/include/asm/processor.h
+++ b/arch/mips/include/asm/processor.h
@@ -238,7 +238,13 @@ typedef struct {
238 unsigned long seg; 238 unsigned long seg;
239} mm_segment_t; 239} mm_segment_t;
240 240
241#define ARCH_MIN_TASKALIGN 8 241#ifdef CONFIG_CPU_HAS_MSA
242# define ARCH_MIN_TASKALIGN 16
243# define FPU_ALIGN __aligned(16)
244#else
245# define ARCH_MIN_TASKALIGN 8
246# define FPU_ALIGN
247#endif
242 248
243struct mips_abi; 249struct mips_abi;
244 250
@@ -255,7 +261,7 @@ struct thread_struct {
255 unsigned long cp0_status; 261 unsigned long cp0_status;
256 262
257 /* Saved fpu/fpu emulator stuff. */ 263 /* Saved fpu/fpu emulator stuff. */
258 struct mips_fpu_struct fpu; 264 struct mips_fpu_struct fpu FPU_ALIGN;
259#ifdef CONFIG_MIPS_MT_FPAFF 265#ifdef CONFIG_MIPS_MT_FPAFF
260 /* Emulated instruction count */ 266 /* Emulated instruction count */
261 unsigned long emulated_fp; 267 unsigned long emulated_fp;
diff --git a/arch/mips/include/asm/ptrace.h b/arch/mips/include/asm/ptrace.h
index 7e6e682aece3..fc783f843bdc 100644
--- a/arch/mips/include/asm/ptrace.h
+++ b/arch/mips/include/asm/ptrace.h
@@ -23,7 +23,7 @@
23struct pt_regs { 23struct pt_regs {
24#ifdef CONFIG_32BIT 24#ifdef CONFIG_32BIT
25 /* Pad bytes for argument save space on the stack. */ 25 /* Pad bytes for argument save space on the stack. */
26 unsigned long pad0[6]; 26 unsigned long pad0[8];
27#endif 27#endif
28 28
29 /* Saved main processor registers. */ 29 /* Saved main processor registers. */
@@ -47,8 +47,10 @@ struct pt_regs {
47 47
48struct task_struct; 48struct task_struct;
49 49
50extern int ptrace_getregs(struct task_struct *child, __s64 __user *data); 50extern int ptrace_getregs(struct task_struct *child,
51extern int ptrace_setregs(struct task_struct *child, __s64 __user *data); 51 struct user_pt_regs __user *data);
52extern int ptrace_setregs(struct task_struct *child,
53 struct user_pt_regs __user *data);
52 54
53extern int ptrace_getfpregs(struct task_struct *child, __u32 __user *data); 55extern int ptrace_getfpregs(struct task_struct *child, __u32 __user *data);
54extern int ptrace_setfpregs(struct task_struct *child, __u32 __user *data); 56extern int ptrace_setfpregs(struct task_struct *child, __u32 __user *data);
diff --git a/arch/mips/include/asm/reg.h b/arch/mips/include/asm/reg.h
index 910e71a12466..84dc7e2e27a8 100644
--- a/arch/mips/include/asm/reg.h
+++ b/arch/mips/include/asm/reg.h
@@ -1,128 +1 @@
1/* #include <uapi/asm/reg.h>
2 * Various register offset definitions for debuggers, core file
3 * examiners and whatnot.
4 *
5 * This file is subject to the terms and conditions of the GNU General Public
6 * License. See the file "COPYING" in the main directory of this archive
7 * for more details.
8 *
9 * Copyright (C) 1995, 1999 Ralf Baechle
10 * Copyright (C) 1995, 1999 Silicon Graphics
11 */
12#ifndef __ASM_MIPS_REG_H
13#define __ASM_MIPS_REG_H
14
15
16#if defined(CONFIG_32BIT) || defined(WANT_COMPAT_REG_H)
17
18#define EF_R0 6
19#define EF_R1 7
20#define EF_R2 8
21#define EF_R3 9
22#define EF_R4 10
23#define EF_R5 11
24#define EF_R6 12
25#define EF_R7 13
26#define EF_R8 14
27#define EF_R9 15
28#define EF_R10 16
29#define EF_R11 17
30#define EF_R12 18
31#define EF_R13 19
32#define EF_R14 20
33#define EF_R15 21
34#define EF_R16 22
35#define EF_R17 23
36#define EF_R18 24
37#define EF_R19 25
38#define EF_R20 26
39#define EF_R21 27
40#define EF_R22 28
41#define EF_R23 29
42#define EF_R24 30
43#define EF_R25 31
44
45/*
46 * k0/k1 unsaved
47 */
48#define EF_R26 32
49#define EF_R27 33
50
51#define EF_R28 34
52#define EF_R29 35
53#define EF_R30 36
54#define EF_R31 37
55
56/*
57 * Saved special registers
58 */
59#define EF_LO 38
60#define EF_HI 39
61
62#define EF_CP0_EPC 40
63#define EF_CP0_BADVADDR 41
64#define EF_CP0_STATUS 42
65#define EF_CP0_CAUSE 43
66#define EF_UNUSED0 44
67
68#define EF_SIZE 180
69
70#endif
71
72#if defined(CONFIG_64BIT) && !defined(WANT_COMPAT_REG_H)
73
74#define EF_R0 0
75#define EF_R1 1
76#define EF_R2 2
77#define EF_R3 3
78#define EF_R4 4
79#define EF_R5 5
80#define EF_R6 6
81#define EF_R7 7
82#define EF_R8 8
83#define EF_R9 9
84#define EF_R10 10
85#define EF_R11 11
86#define EF_R12 12
87#define EF_R13 13
88#define EF_R14 14
89#define EF_R15 15
90#define EF_R16 16
91#define EF_R17 17
92#define EF_R18 18
93#define EF_R19 19
94#define EF_R20 20
95#define EF_R21 21
96#define EF_R22 22
97#define EF_R23 23
98#define EF_R24 24
99#define EF_R25 25
100
101/*
102 * k0/k1 unsaved
103 */
104#define EF_R26 26
105#define EF_R27 27
106
107
108#define EF_R28 28
109#define EF_R29 29
110#define EF_R30 30
111#define EF_R31 31
112
113/*
114 * Saved special registers
115 */
116#define EF_LO 32
117#define EF_HI 33
118
119#define EF_CP0_EPC 34
120#define EF_CP0_BADVADDR 35
121#define EF_CP0_STATUS 36
122#define EF_CP0_CAUSE 37
123
124#define EF_SIZE 304 /* size in bytes */
125
126#endif /* CONFIG_64BIT */
127
128#endif /* __ASM_MIPS_REG_H */
diff --git a/arch/mips/include/asm/smp-cps.h b/arch/mips/include/asm/smp-cps.h
index a06a08a9afc6..326c16ebd589 100644
--- a/arch/mips/include/asm/smp-cps.h
+++ b/arch/mips/include/asm/smp-cps.h
@@ -31,11 +31,19 @@ extern void mips_cps_core_init(void);
31 31
32extern struct vpe_boot_config *mips_cps_boot_vpes(void); 32extern struct vpe_boot_config *mips_cps_boot_vpes(void);
33 33
34extern bool mips_cps_smp_in_use(void);
35
36extern void mips_cps_pm_save(void); 34extern void mips_cps_pm_save(void);
37extern void mips_cps_pm_restore(void); 35extern void mips_cps_pm_restore(void);
38 36
37#ifdef CONFIG_MIPS_CPS
38
39extern bool mips_cps_smp_in_use(void);
40
41#else /* !CONFIG_MIPS_CPS */
42
43static inline bool mips_cps_smp_in_use(void) { return false; }
44
45#endif /* !CONFIG_MIPS_CPS */
46
39#else /* __ASSEMBLY__ */ 47#else /* __ASSEMBLY__ */
40 48
41.extern mips_cps_bootcfg; 49.extern mips_cps_bootcfg;
diff --git a/arch/mips/include/asm/smp.h b/arch/mips/include/asm/smp.h
index b037334fca22..1e0f20a9cdda 100644
--- a/arch/mips/include/asm/smp.h
+++ b/arch/mips/include/asm/smp.h
@@ -22,6 +22,7 @@
22 22
23extern int smp_num_siblings; 23extern int smp_num_siblings;
24extern cpumask_t cpu_sibling_map[]; 24extern cpumask_t cpu_sibling_map[];
25extern cpumask_t cpu_core_map[];
25 26
26#define raw_smp_processor_id() (current_thread_info()->cpu) 27#define raw_smp_processor_id() (current_thread_info()->cpu)
27 28
@@ -36,6 +37,11 @@ extern int __cpu_logical_map[NR_CPUS];
36 37
37#define NO_PROC_ID (-1) 38#define NO_PROC_ID (-1)
38 39
40#define topology_physical_package_id(cpu) (cpu_data[cpu].package)
41#define topology_core_id(cpu) (cpu_data[cpu].core)
42#define topology_core_cpumask(cpu) (&cpu_core_map[cpu])
43#define topology_thread_cpumask(cpu) (&cpu_sibling_map[cpu])
44
39#define SMP_RESCHEDULE_YOURSELF 0x1 /* XXX braindead */ 45#define SMP_RESCHEDULE_YOURSELF 0x1 /* XXX braindead */
40#define SMP_CALL_FUNCTION 0x2 46#define SMP_CALL_FUNCTION 0x2
41/* Octeon - Tell another core to flush its icache */ 47/* Octeon - Tell another core to flush its icache */
diff --git a/arch/mips/include/asm/sparsemem.h b/arch/mips/include/asm/sparsemem.h
index d2da53c2c2f8..b1071c1e54f5 100644
--- a/arch/mips/include/asm/sparsemem.h
+++ b/arch/mips/include/asm/sparsemem.h
@@ -11,7 +11,7 @@
11#else 11#else
12# define SECTION_SIZE_BITS 28 12# define SECTION_SIZE_BITS 28
13#endif 13#endif
14#define MAX_PHYSMEM_BITS 35 14#define MAX_PHYSMEM_BITS 48
15 15
16#endif /* CONFIG_SPARSEMEM */ 16#endif /* CONFIG_SPARSEMEM */
17#endif /* _MIPS_SPARSEMEM_H */ 17#endif /* _MIPS_SPARSEMEM_H */
diff --git a/arch/mips/include/asm/user.h b/arch/mips/include/asm/user.h
deleted file mode 100644
index 6bad61b0a53a..000000000000
--- a/arch/mips/include/asm/user.h
+++ /dev/null
@@ -1,58 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994, 1995, 1996, 1999 by Ralf Baechle
7 */
8#ifndef _ASM_USER_H
9#define _ASM_USER_H
10
11#include <asm/page.h>
12#include <asm/reg.h>
13
14/*
15 * Core file format: The core file is written in such a way that gdb
16 * can understand it and provide useful information to the user (under
17 * linux we use the `trad-core' bfd, NOT the irix-core). The file
18 * contents are as follows:
19 *
20 * upage: 1 page consisting of a user struct that tells gdb
21 * what is present in the file. Directly after this is a
22 * copy of the task_struct, which is currently not used by gdb,
23 * but it may come in handy at some point. All of the registers
24 * are stored as part of the upage. The upage should always be
25 * only one page long.
26 * data: The data segment follows next. We use current->end_text to
27 * current->brk to pick up all of the user variables, plus any memory
28 * that may have been sbrk'ed. No attempt is made to determine if a
29 * page is demand-zero or if a page is totally unused, we just cover
30 * the entire range. All of the addresses are rounded in such a way
31 * that an integral number of pages is written.
32 * stack: We need the stack information in order to get a meaningful
33 * backtrace. We need to write the data from usp to
34 * current->start_stack, so we round each of these in order to be able
35 * to write an integer number of pages.
36 */
37struct user {
38 unsigned long regs[EF_SIZE / /* integer and fp regs */
39 sizeof(unsigned long) + 64];
40 size_t u_tsize; /* text size (pages) */
41 size_t u_dsize; /* data size (pages) */
42 size_t u_ssize; /* stack size (pages) */
43 unsigned long start_code; /* text starting address */
44 unsigned long start_data; /* data starting address */
45 unsigned long start_stack; /* stack starting address */
46 long int signal; /* signal causing core dump */
47 unsigned long u_ar0; /* help gdb find registers */
48 unsigned long magic; /* identifies a core file */
49 char u_comm[32]; /* user command name */
50};
51
52#define NBPG PAGE_SIZE
53#define UPAGES 1
54#define HOST_TEXT_START_ADDR (u.start_code)
55#define HOST_DATA_START_ADDR (u.start_data)
56#define HOST_STACK_END_ADDR (u.start_stack + u.u_ssize * NBPG)
57
58#endif /* _ASM_USER_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-15 07:05:30 -0500