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-rw-r--r--arch/mips/include/asm/cpu-features.h33
1 files changed, 32 insertions, 1 deletions
diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
index a324751b02ff..49c7a29a1f9e 100644
--- a/arch/mips/include/asm/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
@@ -238,8 +238,39 @@
238/* MIPSR2 and MIPSR6 have a lot of similarities */ 238/* MIPSR2 and MIPSR6 have a lot of similarities */
239#define cpu_has_mips_r2_r6 (cpu_has_mips_r2 | cpu_has_mips_r6) 239#define cpu_has_mips_r2_r6 (cpu_has_mips_r2 | cpu_has_mips_r6)
240 240
241/*
242 * cpu_has_mips_r2_exec_hazard - return if IHB is required on current processor
243 *
244 * Returns non-zero value if the current processor implementation requires
245 * an IHB instruction to deal with an instruction hazard as per MIPS R2
246 * architecture specification, zero otherwise.
247 */
241#ifndef cpu_has_mips_r2_exec_hazard 248#ifndef cpu_has_mips_r2_exec_hazard
242#define cpu_has_mips_r2_exec_hazard (cpu_has_mips_r2 | cpu_has_mips_r6) 249#define cpu_has_mips_r2_exec_hazard \
250({ \
251 int __res; \
252 \
253 switch (current_cpu_type()) { \
254 case CPU_M14KC: \
255 case CPU_74K: \
256 case CPU_1074K: \
257 case CPU_PROAPTIV: \
258 case CPU_P5600: \
259 case CPU_M5150: \
260 case CPU_QEMU_GENERIC: \
261 case CPU_CAVIUM_OCTEON: \
262 case CPU_CAVIUM_OCTEON_PLUS: \
263 case CPU_CAVIUM_OCTEON2: \
264 case CPU_CAVIUM_OCTEON3: \
265 __res = 0; \
266 break; \
267 \
268 default: \
269 __res = 1; \
270 } \
271 \
272 __res; \
273})
243#endif 274#endif
244 275
245/* 276/*