aboutsummaryrefslogtreecommitdiffstats
path: root/arch/mips/include/asm
diff options
context:
space:
mode:
Diffstat (limited to 'arch/mips/include/asm')
-rw-r--r--arch/mips/include/asm/cpu-features.h8
-rw-r--r--arch/mips/include/asm/delay.h2
-rw-r--r--arch/mips/include/asm/hugetlb.h114
-rw-r--r--arch/mips/include/asm/ioctl.h85
-rw-r--r--arch/mips/include/asm/mach-au1x00/au1000_gpio.h56
-rw-r--r--arch/mips/include/asm/mach-au1x00/gpio-au1000.h604
-rw-r--r--arch/mips/include/asm/mach-au1x00/gpio.h35
-rw-r--r--arch/mips/include/asm/mach-bcm47xx/gpio.h3
-rw-r--r--arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h2
-rw-r--r--arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h6
-rw-r--r--arch/mips/include/asm/mach-generic/dma-coherence.h6
-rw-r--r--arch/mips/include/asm/mach-ip27/dma-coherence.h6
-rw-r--r--arch/mips/include/asm/mach-ip32/dma-coherence.h6
-rw-r--r--arch/mips/include/asm/mach-jazz/dma-coherence.h6
-rw-r--r--arch/mips/include/asm/mach-lemote/dma-coherence.h6
-rw-r--r--arch/mips/include/asm/mach-rc32434/cpu-feature-overrides.h5
-rw-r--r--arch/mips/include/asm/mipsregs.h16
-rw-r--r--arch/mips/include/asm/octeon/cvmx-bootinfo.h13
-rw-r--r--arch/mips/include/asm/octeon/cvmx-bootmem.h85
-rw-r--r--arch/mips/include/asm/octeon/cvmx-helper-errata.h33
-rw-r--r--arch/mips/include/asm/octeon/cvmx-helper-jtag.h43
-rw-r--r--arch/mips/include/asm/octeon/cvmx-npei-defs.h2560
-rw-r--r--arch/mips/include/asm/octeon/cvmx-npi-defs.h1735
-rw-r--r--arch/mips/include/asm/octeon/cvmx-pci-defs.h1645
-rw-r--r--arch/mips/include/asm/octeon/cvmx-pcieep-defs.h1365
-rw-r--r--arch/mips/include/asm/octeon/cvmx-pciercx-defs.h1397
-rw-r--r--arch/mips/include/asm/octeon/cvmx-pescx-defs.h410
-rw-r--r--arch/mips/include/asm/octeon/cvmx-pexp-defs.h229
-rw-r--r--arch/mips/include/asm/octeon/cvmx.h12
-rw-r--r--arch/mips/include/asm/octeon/octeon-feature.h27
-rw-r--r--arch/mips/include/asm/octeon/octeon.h2
-rw-r--r--arch/mips/include/asm/page.h5
-rw-r--r--arch/mips/include/asm/pci.h13
-rw-r--r--arch/mips/include/asm/pgtable-bits.h1
-rw-r--r--arch/mips/include/asm/pgtable.h10
-rw-r--r--arch/mips/include/asm/r4kcache.h1
-rw-r--r--arch/mips/include/asm/suspend.h9
-rw-r--r--arch/mips/include/asm/txx9/dmac.h51
-rw-r--r--arch/mips/include/asm/txx9/generic.h6
-rw-r--r--arch/mips/include/asm/txx9/tx4927.h4
-rw-r--r--arch/mips/include/asm/txx9/tx4938.h3
-rw-r--r--arch/mips/include/asm/txx9/tx4939.h6
42 files changed, 10437 insertions, 194 deletions
diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
index c0047f861337..8ab1d12ba7f4 100644
--- a/arch/mips/include/asm/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
@@ -147,6 +147,10 @@
147#define cpu_has_mips_r (cpu_has_mips32r1 | cpu_has_mips32r2 | \ 147#define cpu_has_mips_r (cpu_has_mips32r1 | cpu_has_mips32r2 | \
148 cpu_has_mips64r1 | cpu_has_mips64r2) 148 cpu_has_mips64r1 | cpu_has_mips64r2)
149 149
150#ifndef cpu_has_mips_r2_exec_hazard
151#define cpu_has_mips_r2_exec_hazard cpu_has_mips_r2
152#endif
153
150/* 154/*
151 * MIPS32, MIPS64, VR5500, IDT32332, IDT32334 and maybe a few other 155 * MIPS32, MIPS64, VR5500, IDT32332, IDT32334 and maybe a few other
152 * pre-MIPS32/MIPS53 processors have CLO, CLZ. For 64-bit kernels 156 * pre-MIPS32/MIPS53 processors have CLO, CLZ. For 64-bit kernels
@@ -230,4 +234,8 @@
230#define cpu_scache_line_size() cpu_data[0].scache.linesz 234#define cpu_scache_line_size() cpu_data[0].scache.linesz
231#endif 235#endif
232 236
237#ifndef cpu_hwrena_impl_bits
238#define cpu_hwrena_impl_bits 0
239#endif
240
233#endif /* __ASM_CPU_FEATURES_H */ 241#endif /* __ASM_CPU_FEATURES_H */
diff --git a/arch/mips/include/asm/delay.h b/arch/mips/include/asm/delay.h
index a07e51b2be13..d2d8949be6b7 100644
--- a/arch/mips/include/asm/delay.h
+++ b/arch/mips/include/asm/delay.h
@@ -15,7 +15,7 @@ extern void __delay(unsigned int loops);
15extern void __ndelay(unsigned int ns); 15extern void __ndelay(unsigned int ns);
16extern void __udelay(unsigned int us); 16extern void __udelay(unsigned int us);
17 17
18#define ndelay(ns) __udelay(ns) 18#define ndelay(ns) __ndelay(ns)
19#define udelay(us) __udelay(us) 19#define udelay(us) __udelay(us)
20 20
21/* make sure "usecs *= ..." in udelay do not overflow. */ 21/* make sure "usecs *= ..." in udelay do not overflow. */
diff --git a/arch/mips/include/asm/hugetlb.h b/arch/mips/include/asm/hugetlb.h
new file mode 100644
index 000000000000..f5e856015329
--- /dev/null
+++ b/arch/mips/include/asm/hugetlb.h
@@ -0,0 +1,114 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2008, 2009 Cavium Networks, Inc.
7 */
8
9#ifndef __ASM_HUGETLB_H
10#define __ASM_HUGETLB_H
11
12#include <asm/page.h>
13
14
15static inline int is_hugepage_only_range(struct mm_struct *mm,
16 unsigned long addr,
17 unsigned long len)
18{
19 return 0;
20}
21
22static inline int prepare_hugepage_range(struct file *file,
23 unsigned long addr,
24 unsigned long len)
25{
26 unsigned long task_size = STACK_TOP;
27 struct hstate *h = hstate_file(file);
28
29 if (len & ~huge_page_mask(h))
30 return -EINVAL;
31 if (addr & ~huge_page_mask(h))
32 return -EINVAL;
33 if (len > task_size)
34 return -ENOMEM;
35 if (task_size - len < addr)
36 return -EINVAL;
37 return 0;
38}
39
40static inline void hugetlb_prefault_arch_hook(struct mm_struct *mm)
41{
42}
43
44static inline void hugetlb_free_pgd_range(struct mmu_gather *tlb,
45 unsigned long addr,
46 unsigned long end,
47 unsigned long floor,
48 unsigned long ceiling)
49{
50 free_pgd_range(tlb, addr, end, floor, ceiling);
51}
52
53static inline void set_huge_pte_at(struct mm_struct *mm, unsigned long addr,
54 pte_t *ptep, pte_t pte)
55{
56 set_pte_at(mm, addr, ptep, pte);
57}
58
59static inline pte_t huge_ptep_get_and_clear(struct mm_struct *mm,
60 unsigned long addr, pte_t *ptep)
61{
62 pte_t clear;
63 pte_t pte = *ptep;
64
65 pte_val(clear) = (unsigned long)invalid_pte_table;
66 set_pte_at(mm, addr, ptep, clear);
67 return pte;
68}
69
70static inline void huge_ptep_clear_flush(struct vm_area_struct *vma,
71 unsigned long addr, pte_t *ptep)
72{
73}
74
75static inline int huge_pte_none(pte_t pte)
76{
77 unsigned long val = pte_val(pte) & ~_PAGE_GLOBAL;
78 return !val || (val == (unsigned long)invalid_pte_table);
79}
80
81static inline pte_t huge_pte_wrprotect(pte_t pte)
82{
83 return pte_wrprotect(pte);
84}
85
86static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
87 unsigned long addr, pte_t *ptep)
88{
89 ptep_set_wrprotect(mm, addr, ptep);
90}
91
92static inline int huge_ptep_set_access_flags(struct vm_area_struct *vma,
93 unsigned long addr,
94 pte_t *ptep, pte_t pte,
95 int dirty)
96{
97 return ptep_set_access_flags(vma, addr, ptep, pte, dirty);
98}
99
100static inline pte_t huge_ptep_get(pte_t *ptep)
101{
102 return *ptep;
103}
104
105static inline int arch_prepare_hugepage(struct page *page)
106{
107 return 0;
108}
109
110static inline void arch_release_hugepage(struct page *page)
111{
112}
113
114#endif /* __ASM_HUGETLB_H */
diff --git a/arch/mips/include/asm/ioctl.h b/arch/mips/include/asm/ioctl.h
index 916163401b2c..c515a1a4c47c 100644
--- a/arch/mips/include/asm/ioctl.h
+++ b/arch/mips/include/asm/ioctl.h
@@ -3,40 +3,16 @@
3 * License. See the file "COPYING" in the main directory of this archive 3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details. 4 * for more details.
5 * 5 *
6 * Copyright (C) 1995, 96, 99, 2001 Ralf Baechle 6 * Copyright (C) 1995, 96, 99, 2001 Ralf Baechle <ralf@linux-mips.org>
7 * Copyright (C) 2009 Wind River Systems
8 * Written by Ralf Baechle <ralf@linux-mips.org>
7 */ 9 */
8#ifndef _ASM_IOCTL_H 10#ifndef __ASM_IOCTL_H
9#define _ASM_IOCTL_H 11#define __ASM_IOCTL_H
10 12
11/*
12 * The original linux ioctl numbering scheme was just a general
13 * "anything goes" setup, where more or less random numbers were
14 * assigned. Sorry, I was clueless when I started out on this.
15 *
16 * On the alpha, we'll try to clean it up a bit, using a more sane
17 * ioctl numbering, and also trying to be compatible with OSF/1 in
18 * the process. I'd like to clean it up for the i386 as well, but
19 * it's so painful recognizing both the new and the old numbers..
20 *
21 * The same applies for for the MIPS ABI; in fact even the macros
22 * from Linux/Alpha fit almost perfectly.
23 */
24
25#define _IOC_NRBITS 8
26#define _IOC_TYPEBITS 8
27#define _IOC_SIZEBITS 13 13#define _IOC_SIZEBITS 13
28#define _IOC_DIRBITS 3 14#define _IOC_DIRBITS 3
29 15
30#define _IOC_NRMASK ((1 << _IOC_NRBITS)-1)
31#define _IOC_TYPEMASK ((1 << _IOC_TYPEBITS)-1)
32#define _IOC_SIZEMASK ((1 << _IOC_SIZEBITS)-1)
33#define _IOC_DIRMASK ((1 << _IOC_DIRBITS)-1)
34
35#define _IOC_NRSHIFT 0
36#define _IOC_TYPESHIFT (_IOC_NRSHIFT+_IOC_NRBITS)
37#define _IOC_SIZESHIFT (_IOC_TYPESHIFT+_IOC_TYPEBITS)
38#define _IOC_DIRSHIFT (_IOC_SIZESHIFT+_IOC_SIZEBITS)
39
40/* 16/*
41 * Direction bits _IOC_NONE could be 0, but OSF/1 gives it a bit. 17 * Direction bits _IOC_NONE could be 0, but OSF/1 gives it a bit.
42 * And this turns out useful to catch old ioctl numbers in header 18 * And this turns out useful to catch old ioctl numbers in header
@@ -46,53 +22,6 @@
46#define _IOC_READ 2U 22#define _IOC_READ 2U
47#define _IOC_WRITE 4U 23#define _IOC_WRITE 4U
48 24
49/* 25#include <asm-generic/ioctl.h>
50 * The following are included for compatibility
51 */
52#define _IOC_VOID 0x20000000
53#define _IOC_OUT 0x40000000
54#define _IOC_IN 0x80000000
55#define _IOC_INOUT (IOC_IN|IOC_OUT)
56
57#define _IOC(dir, type, nr, size) \
58 (((dir) << _IOC_DIRSHIFT) | \
59 ((type) << _IOC_TYPESHIFT) | \
60 ((nr) << _IOC_NRSHIFT) | \
61 ((size) << _IOC_SIZESHIFT))
62
63#ifdef __KERNEL__
64/* provoke compile error for invalid uses of size argument */
65extern unsigned int __invalid_size_argument_for_IOC;
66#define _IOC_TYPECHECK(t) \
67 ((sizeof(t) == sizeof(t[1]) && \
68 sizeof(t) < (1 << _IOC_SIZEBITS)) ? \
69 sizeof(t) : __invalid_size_argument_for_IOC)
70#else
71#define _IOC_TYPECHECK(t) (sizeof(t))
72#endif
73
74/* used to create numbers */
75#define _IO(type, nr) _IOC(_IOC_NONE, (type), (nr), 0)
76#define _IOR(type, nr, size) _IOC(_IOC_READ, (type), (nr), (_IOC_TYPECHECK(size)))
77#define _IOW(type, nr, size) _IOC(_IOC_WRITE, (type), (nr), (_IOC_TYPECHECK(size)))
78#define _IOWR(type, nr, size) _IOC(_IOC_READ|_IOC_WRITE, (type), (nr), (_IOC_TYPECHECK(size)))
79#define _IOR_BAD(type, nr, size) _IOC(_IOC_READ, (type), (nr), sizeof(size))
80#define _IOW_BAD(type, nr, size) _IOC(_IOC_WRITE, (type), (nr), sizeof(size))
81#define _IOWR_BAD(type, nr, size) _IOC(_IOC_READ|_IOC_WRITE, (type), (nr), sizeof(size))
82
83
84/* used to decode them.. */
85#define _IOC_DIR(nr) (((nr) >> _IOC_DIRSHIFT) & _IOC_DIRMASK)
86#define _IOC_TYPE(nr) (((nr) >> _IOC_TYPESHIFT) & _IOC_TYPEMASK)
87#define _IOC_NR(nr) (((nr) >> _IOC_NRSHIFT) & _IOC_NRMASK)
88#define _IOC_SIZE(nr) (((nr) >> _IOC_SIZESHIFT) & _IOC_SIZEMASK)
89
90/* ...and for the drivers/sound files... */
91
92#define IOC_IN (_IOC_WRITE << _IOC_DIRSHIFT)
93#define IOC_OUT (_IOC_READ << _IOC_DIRSHIFT)
94#define IOC_INOUT ((_IOC_WRITE|_IOC_READ) << _IOC_DIRSHIFT)
95#define IOCSIZE_MASK (_IOC_SIZEMASK << _IOC_SIZESHIFT)
96#define IOCSIZE_SHIFT (_IOC_SIZESHIFT)
97 26
98#endif /* _ASM_IOCTL_H */ 27#endif /* __ASM_IOCTL_H */
diff --git a/arch/mips/include/asm/mach-au1x00/au1000_gpio.h b/arch/mips/include/asm/mach-au1x00/au1000_gpio.h
deleted file mode 100644
index d8c96fda5549..000000000000
--- a/arch/mips/include/asm/mach-au1x00/au1000_gpio.h
+++ /dev/null
@@ -1,56 +0,0 @@
1/*
2 * FILE NAME au1000_gpio.h
3 *
4 * BRIEF MODULE DESCRIPTION
5 * API to Alchemy Au1xx0 GPIO device.
6 *
7 * Author: MontaVista Software, Inc. <source@mvista.com>
8 * Steve Longerbeam
9 *
10 * Copyright 2001, 2008 MontaVista Software Inc.
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 *
17 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
18 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
20 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
23 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
24 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * You should have received a copy of the GNU General Public License along
29 * with this program; if not, write to the Free Software Foundation, Inc.,
30 * 675 Mass Ave, Cambridge, MA 02139, USA.
31 */
32
33#ifndef __AU1000_GPIO_H
34#define __AU1000_GPIO_H
35
36#include <linux/ioctl.h>
37
38#define AU1000GPIO_IOC_MAGIC 'A'
39
40#define AU1000GPIO_IN _IOR(AU1000GPIO_IOC_MAGIC, 0, int)
41#define AU1000GPIO_SET _IOW(AU1000GPIO_IOC_MAGIC, 1, int)
42#define AU1000GPIO_CLEAR _IOW(AU1000GPIO_IOC_MAGIC, 2, int)
43#define AU1000GPIO_OUT _IOW(AU1000GPIO_IOC_MAGIC, 3, int)
44#define AU1000GPIO_TRISTATE _IOW(AU1000GPIO_IOC_MAGIC, 4, int)
45#define AU1000GPIO_AVAIL_MASK _IOR(AU1000GPIO_IOC_MAGIC, 5, int)
46
47#ifdef __KERNEL__
48extern u32 get_au1000_avail_gpio_mask(void);
49extern int au1000gpio_tristate(u32 data);
50extern int au1000gpio_in(u32 *data);
51extern int au1000gpio_set(u32 data);
52extern int au1000gpio_clear(u32 data);
53extern int au1000gpio_out(u32 data);
54#endif
55
56#endif
diff --git a/arch/mips/include/asm/mach-au1x00/gpio-au1000.h b/arch/mips/include/asm/mach-au1x00/gpio-au1000.h
new file mode 100644
index 000000000000..127d4ed9f073
--- /dev/null
+++ b/arch/mips/include/asm/mach-au1x00/gpio-au1000.h
@@ -0,0 +1,604 @@
1/*
2 * GPIO functions for Au1000, Au1500, Au1100, Au1550, Au1200
3 *
4 * Copyright (c) 2009 Manuel Lauss.
5 *
6 * Licensed under the terms outlined in the file COPYING.
7 */
8
9#ifndef _ALCHEMY_GPIO_AU1000_H_
10#define _ALCHEMY_GPIO_AU1000_H_
11
12#include <asm/mach-au1x00/au1000.h>
13
14/* The default GPIO numberspace as documented in the Alchemy manuals.
15 * GPIO0-31 from GPIO1 block, GPIO200-215 from GPIO2 block.
16 */
17#define ALCHEMY_GPIO1_BASE 0
18#define ALCHEMY_GPIO2_BASE 200
19
20#define ALCHEMY_GPIO1_NUM 32
21#define ALCHEMY_GPIO2_NUM 16
22#define ALCHEMY_GPIO1_MAX (ALCHEMY_GPIO1_BASE + ALCHEMY_GPIO1_NUM - 1)
23#define ALCHEMY_GPIO2_MAX (ALCHEMY_GPIO2_BASE + ALCHEMY_GPIO2_NUM - 1)
24
25#define MAKE_IRQ(intc, off) (AU1000_INTC##intc##_INT_BASE + (off))
26
27
28static inline int au1000_gpio1_to_irq(int gpio)
29{
30 return MAKE_IRQ(1, gpio - ALCHEMY_GPIO1_BASE);
31}
32
33static inline int au1000_gpio2_to_irq(int gpio)
34{
35 return -ENXIO;
36}
37
38#ifdef CONFIG_SOC_AU1000
39static inline int au1000_irq_to_gpio(int irq)
40{
41 if ((irq >= AU1000_GPIO_0) && (irq <= AU1000_GPIO_31))
42 return ALCHEMY_GPIO1_BASE + (irq - AU1000_GPIO_0) + 0;
43
44 return -ENXIO;
45}
46#endif
47
48static inline int au1500_gpio1_to_irq(int gpio)
49{
50 gpio -= ALCHEMY_GPIO1_BASE;
51
52 switch (gpio) {
53 case 0 ... 15:
54 case 20:
55 case 23 ... 28: return MAKE_IRQ(1, gpio);
56 }
57
58 return -ENXIO;
59}
60
61static inline int au1500_gpio2_to_irq(int gpio)
62{
63 gpio -= ALCHEMY_GPIO2_BASE;
64
65 switch (gpio) {
66 case 0 ... 3: return MAKE_IRQ(1, 16 + gpio - 0);
67 case 4 ... 5: return MAKE_IRQ(1, 21 + gpio - 4);
68 case 6 ... 7: return MAKE_IRQ(1, 29 + gpio - 6);
69 }
70
71 return -ENXIO;
72}
73
74#ifdef CONFIG_SOC_AU1500
75static inline int au1500_irq_to_gpio(int irq)
76{
77 switch (irq) {
78 case AU1000_GPIO_0 ... AU1000_GPIO_15:
79 case AU1500_GPIO_20:
80 case AU1500_GPIO_23 ... AU1500_GPIO_28:
81 return ALCHEMY_GPIO1_BASE + (irq - AU1000_GPIO_0) + 0;
82 case AU1500_GPIO_200 ... AU1500_GPIO_203:
83 return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO_200) + 0;
84 case AU1500_GPIO_204 ... AU1500_GPIO_205:
85 return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO_204) + 4;
86 case AU1500_GPIO_206 ... AU1500_GPIO_207:
87 return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO_206) + 6;
88 case AU1500_GPIO_208_215:
89 return ALCHEMY_GPIO2_BASE + 8;
90 }
91
92 return -ENXIO;
93}
94#endif
95
96static inline int au1100_gpio1_to_irq(int gpio)
97{
98 return MAKE_IRQ(1, gpio - ALCHEMY_GPIO1_BASE);
99}
100
101static inline int au1100_gpio2_to_irq(int gpio)
102{
103 gpio -= ALCHEMY_GPIO2_BASE;
104
105 if ((gpio >= 8) && (gpio <= 15))
106 return MAKE_IRQ(0, 29); /* shared GPIO208_215 */
107}
108
109#ifdef CONFIG_SOC_AU1100
110static inline int au1100_irq_to_gpio(int irq)
111{
112 switch (irq) {
113 case AU1000_GPIO_0 ... AU1000_GPIO_31:
114 return ALCHEMY_GPIO1_BASE + (irq - AU1000_GPIO_0) + 0;
115 case AU1100_GPIO_208_215:
116 return ALCHEMY_GPIO2_BASE + 8;
117 }
118
119 return -ENXIO;
120}
121#endif
122
123static inline int au1550_gpio1_to_irq(int gpio)
124{
125 gpio -= ALCHEMY_GPIO1_BASE;
126
127 switch (gpio) {
128 case 0 ... 15:
129 case 20 ... 28: return MAKE_IRQ(1, gpio);
130 case 16 ... 17: return MAKE_IRQ(1, 18 + gpio - 16);
131 }
132
133 return -ENXIO;
134}
135
136static inline int au1550_gpio2_to_irq(int gpio)
137{
138 gpio -= ALCHEMY_GPIO2_BASE;
139
140 switch (gpio) {
141 case 0: return MAKE_IRQ(1, 16);
142 case 1 ... 5: return MAKE_IRQ(1, 17); /* shared GPIO201_205 */
143 case 6 ... 7: return MAKE_IRQ(1, 29 + gpio - 6);
144 case 8 ... 15: return MAKE_IRQ(1, 31); /* shared GPIO208_215 */
145 }
146
147 return -ENXIO;
148}
149
150#ifdef CONFIG_SOC_AU1550
151static inline int au1550_irq_to_gpio(int irq)
152{
153 switch (irq) {
154 case AU1000_GPIO_0 ... AU1000_GPIO_15:
155 return ALCHEMY_GPIO1_BASE + (irq - AU1000_GPIO_0) + 0;
156 case AU1550_GPIO_200:
157 case AU1500_GPIO_201_205:
158 return ALCHEMY_GPIO2_BASE + (irq - AU1550_GPIO_200) + 0;
159 case AU1500_GPIO_16 ... AU1500_GPIO_28:
160 return ALCHEMY_GPIO1_BASE + (irq - AU1500_GPIO_16) + 16;
161 case AU1500_GPIO_206 ... AU1500_GPIO_208_218:
162 return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO_206) + 6;
163 }
164
165 return -ENXIO;
166}
167#endif
168
169static inline int au1200_gpio1_to_irq(int gpio)
170{
171 return MAKE_IRQ(1, gpio - ALCHEMY_GPIO1_BASE);
172}
173
174static inline int au1200_gpio2_to_irq(int gpio)
175{
176 gpio -= ALCHEMY_GPIO2_BASE;
177
178 switch (gpio) {
179 case 0 ... 2: return MAKE_IRQ(0, 5 + gpio - 0);
180 case 3: return MAKE_IRQ(0, 22);
181 case 4 ... 7: return MAKE_IRQ(0, 24 + gpio - 4);
182 case 8 ... 15: return MAKE_IRQ(0, 28); /* shared GPIO208_215 */
183 }
184
185 return -ENXIO;
186}
187
188#ifdef CONFIG_SOC_AU1200
189static inline int au1200_irq_to_gpio(int irq)
190{
191 switch (irq) {
192 case AU1000_GPIO_0 ... AU1000_GPIO_31:
193 return ALCHEMY_GPIO1_BASE + (irq - AU1000_GPIO_0) + 0;
194 case AU1200_GPIO_200 ... AU1200_GPIO_202:
195 return ALCHEMY_GPIO2_BASE + (irq - AU1200_GPIO_200) + 0;
196 case AU1200_GPIO_203:
197 return ALCHEMY_GPIO2_BASE + 3;
198 case AU1200_GPIO_204 ... AU1200_GPIO_208_215:
199 return ALCHEMY_GPIO2_BASE + (irq - AU1200_GPIO_204) + 4;
200 }
201
202 return -ENXIO;
203}
204#endif
205
206/*
207 * GPIO1 block macros for common linux gpio functions.
208 */
209static inline void alchemy_gpio1_set_value(int gpio, int v)
210{
211 unsigned long mask = 1 << (gpio - ALCHEMY_GPIO1_BASE);
212 unsigned long r = v ? SYS_OUTPUTSET : SYS_OUTPUTCLR;
213 au_writel(mask, r);
214 au_sync();
215}
216
217static inline int alchemy_gpio1_get_value(int gpio)
218{
219 unsigned long mask = 1 << (gpio - ALCHEMY_GPIO1_BASE);
220 return au_readl(SYS_PINSTATERD) & mask;
221}
222
223static inline int alchemy_gpio1_direction_input(int gpio)
224{
225 unsigned long mask = 1 << (gpio - ALCHEMY_GPIO1_BASE);
226 au_writel(mask, SYS_TRIOUTCLR);
227 au_sync();
228 return 0;
229}
230
231static inline int alchemy_gpio1_direction_output(int gpio, int v)
232{
233 /* hardware switches to "output" mode when one of the two
234 * "set_value" registers is accessed.
235 */
236 alchemy_gpio1_set_value(gpio, v);
237 return 0;
238}
239
240static inline int alchemy_gpio1_is_valid(int gpio)
241{
242 return ((gpio >= ALCHEMY_GPIO1_BASE) && (gpio <= ALCHEMY_GPIO1_MAX));
243}
244
245static inline int alchemy_gpio1_to_irq(int gpio)
246{
247#if defined(CONFIG_SOC_AU1000)
248 return au1000_gpio1_to_irq(gpio);
249#elif defined(CONFIG_SOC_AU1100)
250 return au1100_gpio1_to_irq(gpio);
251#elif defined(CONFIG_SOC_AU1500)
252 return au1500_gpio1_to_irq(gpio);
253#elif defined(CONFIG_SOC_AU1550)
254 return au1550_gpio1_to_irq(gpio);
255#elif defined(CONFIG_SOC_AU1200)
256 return au1200_gpio1_to_irq(gpio);
257#else
258 return -ENXIO;
259#endif
260}
261
262/*
263 * GPIO2 block macros for common linux GPIO functions. The 'gpio'
264 * parameter must be in range of ALCHEMY_GPIO2_BASE..ALCHEMY_GPIO2_MAX.
265 */
266static inline void __alchemy_gpio2_mod_dir(int gpio, int to_out)
267{
268 unsigned long mask = 1 << (gpio - ALCHEMY_GPIO2_BASE);
269 unsigned long d = au_readl(GPIO2_DIR);
270 if (to_out)
271 d |= mask;
272 else
273 d &= ~mask;
274 au_writel(d, GPIO2_DIR);
275 au_sync();
276}
277
278static inline void alchemy_gpio2_set_value(int gpio, int v)
279{
280 unsigned long mask;
281 mask = ((v) ? 0x00010001 : 0x00010000) << (gpio - ALCHEMY_GPIO2_BASE);
282 au_writel(mask, GPIO2_OUTPUT);
283 au_sync();
284}
285
286static inline int alchemy_gpio2_get_value(int gpio)
287{
288 return au_readl(GPIO2_PINSTATE) & (1 << (gpio - ALCHEMY_GPIO2_BASE));
289}
290
291static inline int alchemy_gpio2_direction_input(int gpio)
292{
293 unsigned long flags;
294 local_irq_save(flags);
295 __alchemy_gpio2_mod_dir(gpio, 0);
296 local_irq_restore(flags);
297 return 0;
298}
299
300static inline int alchemy_gpio2_direction_output(int gpio, int v)
301{
302 unsigned long flags;
303 alchemy_gpio2_set_value(gpio, v);
304 local_irq_save(flags);
305 __alchemy_gpio2_mod_dir(gpio, 1);
306 local_irq_restore(flags);
307 return 0;
308}
309
310static inline int alchemy_gpio2_is_valid(int gpio)
311{
312 return ((gpio >= ALCHEMY_GPIO2_BASE) && (gpio <= ALCHEMY_GPIO2_MAX));
313}
314
315static inline int alchemy_gpio2_to_irq(int gpio)
316{
317#if defined(CONFIG_SOC_AU1000)
318 return au1000_gpio2_to_irq(gpio);
319#elif defined(CONFIG_SOC_AU1100)
320 return au1100_gpio2_to_irq(gpio);
321#elif defined(CONFIG_SOC_AU1500)
322 return au1500_gpio2_to_irq(gpio);
323#elif defined(CONFIG_SOC_AU1550)
324 return au1550_gpio2_to_irq(gpio);
325#elif defined(CONFIG_SOC_AU1200)
326 return au1200_gpio2_to_irq(gpio);
327#else
328 return -ENXIO;
329#endif
330}
331
332/**********************************************************************/
333
334/* On Au1000, Au1500 and Au1100 GPIOs won't work as inputs before
335 * SYS_PININPUTEN is written to at least once. On Au1550/Au1200 this
336 * register enables use of GPIOs as wake source.
337 */
338static inline void alchemy_gpio1_input_enable(void)
339{
340 au_writel(0, SYS_PININPUTEN); /* the write op is key */
341 au_sync();
342}
343
344/* GPIO2 shared interrupts and control */
345
346static inline void __alchemy_gpio2_mod_int(int gpio2, int en)
347{
348 unsigned long r = au_readl(GPIO2_INTENABLE);
349 if (en)
350 r |= 1 << gpio2;
351 else
352 r &= ~(1 << gpio2);
353 au_writel(r, GPIO2_INTENABLE);
354 au_sync();
355}
356
357/**
358 * alchemy_gpio2_enable_int - Enable a GPIO2 pins' shared irq contribution.
359 * @gpio2: The GPIO2 pin to activate (200...215).
360 *
361 * GPIO208-215 have one shared interrupt line to the INTC. They are
362 * and'ed with a per-pin enable bit and finally or'ed together to form
363 * a single irq request (useful for active-high sources).
364 * With this function, a pins' individual contribution to the int request
365 * can be enabled. As with all other GPIO-based interrupts, the INTC
366 * must be programmed to accept the GPIO208_215 interrupt as well.
367 *
368 * NOTE: Calling this macro is only necessary for GPIO208-215; all other
369 * GPIO2-based interrupts have their own request to the INTC. Please
370 * consult your Alchemy databook for more information!
371 *
372 * NOTE: On the Au1550, GPIOs 201-205 also have a shared interrupt request
373 * line to the INTC, GPIO201_205. This function can be used for those
374 * as well.
375 *
376 * NOTE: 'gpio2' parameter must be in range of the GPIO2 numberspace
377 * (200-215 by default). No sanity checks are made,
378 */
379static inline void alchemy_gpio2_enable_int(int gpio2)
380{
381 unsigned long flags;
382
383 gpio2 -= ALCHEMY_GPIO2_BASE;
384
385#if defined(CONFIG_SOC_AU1100) || defined(CONFIG_SOC_AU1500)
386 /* Au1100/Au1500 have GPIO208-215 enable bits at 0..7 */
387 gpio2 -= 8;
388#endif
389 local_irq_save(flags);
390 __alchemy_gpio2_mod_int(gpio2, 1);
391 local_irq_restore(flags);
392}
393
394/**
395 * alchemy_gpio2_disable_int - Disable a GPIO2 pins' shared irq contribution.
396 * @gpio2: The GPIO2 pin to activate (200...215).
397 *
398 * see function alchemy_gpio2_enable_int() for more information.
399 */
400static inline void alchemy_gpio2_disable_int(int gpio2)
401{
402 unsigned long flags;
403
404 gpio2 -= ALCHEMY_GPIO2_BASE;
405
406#if defined(CONFIG_SOC_AU1100) || defined(CONFIG_SOC_AU1500)
407 /* Au1100/Au1500 have GPIO208-215 enable bits at 0..7 */
408 gpio2 -= 8;
409#endif
410 local_irq_save(flags);
411 __alchemy_gpio2_mod_int(gpio2, 0);
412 local_irq_restore(flags);
413}
414
415/**
416 * alchemy_gpio2_enable - Activate GPIO2 block.
417 *
418 * The GPIO2 block must be enabled excplicitly to work. On systems
419 * where this isn't done by the bootloader, this macro can be used.
420 */
421static inline void alchemy_gpio2_enable(void)
422{
423 au_writel(3, GPIO2_ENABLE); /* reset, clock enabled */
424 au_sync();
425 au_writel(1, GPIO2_ENABLE); /* clock enabled */
426 au_sync();
427}
428
429/**
430 * alchemy_gpio2_disable - disable GPIO2 block.
431 *
432 * Disable and put GPIO2 block in low-power mode.
433 */
434static inline void alchemy_gpio2_disable(void)
435{
436 au_writel(2, GPIO2_ENABLE); /* reset, clock disabled */
437 au_sync();
438}
439
440/**********************************************************************/
441
442/* wrappers for on-chip gpios; can be used before gpio chips have been
443 * registered with gpiolib.
444 */
445static inline int alchemy_gpio_direction_input(int gpio)
446{
447 return (gpio >= ALCHEMY_GPIO2_BASE) ?
448 alchemy_gpio2_direction_input(gpio) :
449 alchemy_gpio1_direction_input(gpio);
450}
451
452static inline int alchemy_gpio_direction_output(int gpio, int v)
453{
454 return (gpio >= ALCHEMY_GPIO2_BASE) ?
455 alchemy_gpio2_direction_output(gpio, v) :
456 alchemy_gpio1_direction_output(gpio, v);
457}
458
459static inline int alchemy_gpio_get_value(int gpio)
460{
461 return (gpio >= ALCHEMY_GPIO2_BASE) ?
462 alchemy_gpio2_get_value(gpio) :
463 alchemy_gpio1_get_value(gpio);
464}
465
466static inline void alchemy_gpio_set_value(int gpio, int v)
467{
468 if (gpio >= ALCHEMY_GPIO2_BASE)
469 alchemy_gpio2_set_value(gpio, v);
470 else
471 alchemy_gpio1_set_value(gpio, v);
472}
473
474static inline int alchemy_gpio_is_valid(int gpio)
475{
476 return (gpio >= ALCHEMY_GPIO2_BASE) ?
477 alchemy_gpio2_is_valid(gpio) :
478 alchemy_gpio1_is_valid(gpio);
479}
480
481static inline int alchemy_gpio_cansleep(int gpio)
482{
483 return 0; /* Alchemy never gets tired */
484}
485
486static inline int alchemy_gpio_to_irq(int gpio)
487{
488 return (gpio >= ALCHEMY_GPIO2_BASE) ?
489 alchemy_gpio2_to_irq(gpio) :
490 alchemy_gpio1_to_irq(gpio);
491}
492
493static inline int alchemy_irq_to_gpio(int irq)
494{
495#if defined(CONFIG_SOC_AU1000)
496 return au1000_irq_to_gpio(irq);
497#elif defined(CONFIG_SOC_AU1100)
498 return au1100_irq_to_gpio(irq);
499#elif defined(CONFIG_SOC_AU1500)
500 return au1500_irq_to_gpio(irq);
501#elif defined(CONFIG_SOC_AU1550)
502 return au1550_irq_to_gpio(irq);
503#elif defined(CONFIG_SOC_AU1200)
504 return au1200_irq_to_gpio(irq);
505#else
506 return -ENXIO;
507#endif
508}
509
510/**********************************************************************/
511
512/* Linux gpio framework integration.
513 *
514 * 4 use cases of Au1000-Au1200 GPIOS:
515 *(1) GPIOLIB=y, ALCHEMY_GPIO_INDIRECT=y:
516 * Board must register gpiochips.
517 *(2) GPIOLIB=y, ALCHEMY_GPIO_INDIRECT=n:
518 * 2 (1 for Au1000) gpio_chips are registered.
519 *
520 *(3) GPIOLIB=n, ALCHEMY_GPIO_INDIRECT=y:
521 * the boards' gpio.h must provide the linux gpio wrapper functions,
522 *
523 *(4) GPIOLIB=n, ALCHEMY_GPIO_INDIRECT=n:
524 * inlinable gpio functions are provided which enable access to the
525 * Au1000 gpios only by using the numbers straight out of the data-
526 * sheets.
527
528 * Cases 1 and 3 are intended for boards which want to provide their own
529 * GPIO namespace and -operations (i.e. for example you have 8 GPIOs
530 * which are in part provided by spare Au1000 GPIO pins and in part by
531 * an external FPGA but you still want them to be accssible in linux
532 * as gpio0-7. The board can of course use the alchemy_gpioX_* functions
533 * as required).
534 */
535
536#ifndef CONFIG_GPIOLIB
537
538
539#ifndef CONFIG_ALCHEMY_GPIO_INDIRECT /* case (4) */
540
541static inline int gpio_direction_input(int gpio)
542{
543 return alchemy_gpio_direction_input(gpio);
544}
545
546static inline int gpio_direction_output(int gpio, int v)
547{
548 return alchemy_gpio_direction_output(gpio, v);
549}
550
551static inline int gpio_get_value(int gpio)
552{
553 return alchemy_gpio_get_value(gpio);
554}
555
556static inline void gpio_set_value(int gpio, int v)
557{
558 alchemy_gpio_set_value(gpio, v);
559}
560
561static inline int gpio_is_valid(int gpio)
562{
563 return alchemy_gpio_is_valid(gpio);
564}
565
566static inline int gpio_cansleep(int gpio)
567{
568 return alchemy_gpio_cansleep(gpio);
569}
570
571static inline int gpio_to_irq(int gpio)
572{
573 return alchemy_gpio_to_irq(gpio);
574}
575
576static inline int irq_to_gpio(int irq)
577{
578 return alchemy_irq_to_gpio(irq);
579}
580
581#endif /* !CONFIG_ALCHEMY_GPIO_INDIRECT */
582
583
584#else /* CONFIG GPIOLIB */
585
586
587 /* using gpiolib to provide up to 2 gpio_chips for on-chip gpios */
588#ifndef CONFIG_ALCHEMY_GPIO_INDIRECT /* case (2) */
589
590/* get everything through gpiolib */
591#define gpio_to_irq __gpio_to_irq
592#define gpio_get_value __gpio_get_value
593#define gpio_set_value __gpio_set_value
594#define gpio_cansleep __gpio_cansleep
595#define irq_to_gpio alchemy_irq_to_gpio
596
597#include <asm-generic/gpio.h>
598
599#endif /* !CONFIG_ALCHEMY_GPIO_INDIRECT */
600
601
602#endif /* !CONFIG_GPIOLIB */
603
604#endif /* _ALCHEMY_GPIO_AU1000_H_ */
diff --git a/arch/mips/include/asm/mach-au1x00/gpio.h b/arch/mips/include/asm/mach-au1x00/gpio.h
index 34d9b7279024..f9b7d41c659a 100644
--- a/arch/mips/include/asm/mach-au1x00/gpio.h
+++ b/arch/mips/include/asm/mach-au1x00/gpio.h
@@ -1,33 +1,10 @@
1#ifndef _AU1XXX_GPIO_H_ 1#ifndef _ALCHEMY_GPIO_H_
2#define _AU1XXX_GPIO_H_ 2#define _ALCHEMY_GPIO_H_
3 3
4#include <linux/types.h> 4#if defined(CONFIG_ALCHEMY_GPIO_AU1000)
5 5
6#define AU1XXX_GPIO_BASE 200 6#include <asm/mach-au1x00/gpio-au1000.h>
7 7
8/* GPIO bank 1 offsets */ 8#endif
9#define AU1000_GPIO1_TRI_OUT 0x0100
10#define AU1000_GPIO1_OUT 0x0108
11#define AU1000_GPIO1_ST 0x0110
12#define AU1000_GPIO1_CLR 0x010C
13 9
14/* GPIO bank 2 offsets */ 10#endif /* _ALCHEMY_GPIO_H_ */
15#define AU1000_GPIO2_DIR 0x00
16#define AU1000_GPIO2_RSVD 0x04
17#define AU1000_GPIO2_OUT 0x08
18#define AU1000_GPIO2_ST 0x0C
19#define AU1000_GPIO2_INT 0x10
20#define AU1000_GPIO2_EN 0x14
21
22#define GPIO2_OUT_EN_MASK 0x00010000
23
24#define gpio_to_irq(gpio) NULL
25
26#define gpio_get_value __gpio_get_value
27#define gpio_set_value __gpio_set_value
28
29#define gpio_cansleep __gpio_cansleep
30
31#include <asm-generic/gpio.h>
32
33#endif /* _AU1XXX_GPIO_H_ */
diff --git a/arch/mips/include/asm/mach-bcm47xx/gpio.h b/arch/mips/include/asm/mach-bcm47xx/gpio.h
index 1784fde2e28f..98504142124e 100644
--- a/arch/mips/include/asm/mach-bcm47xx/gpio.h
+++ b/arch/mips/include/asm/mach-bcm47xx/gpio.h
@@ -37,6 +37,9 @@ static inline int gpio_direction_input(unsigned gpio)
37 37
38static inline int gpio_direction_output(unsigned gpio, int value) 38static inline int gpio_direction_output(unsigned gpio, int value)
39{ 39{
40 /* first set the gpio out value */
41 ssb_gpio_out(&ssb_bcm47xx, 1 << gpio, value ? 1 << gpio : 0);
42 /* then set the gpio mode */
40 ssb_gpio_outen(&ssb_bcm47xx, 1 << gpio, 1 << gpio); 43 ssb_gpio_outen(&ssb_bcm47xx, 1 << gpio, 1 << gpio);
41 return 0; 44 return 0;
42} 45}
diff --git a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
index 04ce6e6569da..3d830756b13a 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
@@ -47,11 +47,13 @@
47#define cpu_has_mips32r2 0 47#define cpu_has_mips32r2 0
48#define cpu_has_mips64r1 0 48#define cpu_has_mips64r1 0
49#define cpu_has_mips64r2 1 49#define cpu_has_mips64r2 1
50#define cpu_has_mips_r2_exec_hazard 0
50#define cpu_has_dsp 0 51#define cpu_has_dsp 0
51#define cpu_has_mipsmt 0 52#define cpu_has_mipsmt 0
52#define cpu_has_userlocal 0 53#define cpu_has_userlocal 0
53#define cpu_has_vint 0 54#define cpu_has_vint 0
54#define cpu_has_veic 0 55#define cpu_has_veic 0
56#define cpu_hwrena_impl_bits 0xc0000000
55#define ARCH_HAS_READ_CURRENT_TIMER 1 57#define ARCH_HAS_READ_CURRENT_TIMER 1
56#define ARCH_HAS_IRQ_PER_CPU 1 58#define ARCH_HAS_IRQ_PER_CPU 1
57#define ARCH_HAS_SPINLOCK_PREFETCH 1 59#define ARCH_HAS_SPINLOCK_PREFETCH 1
diff --git a/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h b/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h
index f30fce92aabb..17d579471ec4 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h
@@ -30,12 +30,14 @@ static inline dma_addr_t plat_map_dma_mem_page(struct device *dev,
30 return octeon_map_dma_mem(dev, page_address(page), PAGE_SIZE); 30 return octeon_map_dma_mem(dev, page_address(page), PAGE_SIZE);
31} 31}
32 32
33static inline unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr) 33static inline unsigned long plat_dma_addr_to_phys(struct device *dev,
34 dma_addr_t dma_addr)
34{ 35{
35 return dma_addr; 36 return dma_addr;
36} 37}
37 38
38static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr) 39static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr,
40 size_t size, enum dma_data_direction direction)
39{ 41{
40 octeon_unmap_dma_mem(dev, dma_addr); 42 octeon_unmap_dma_mem(dev, dma_addr);
41} 43}
diff --git a/arch/mips/include/asm/mach-generic/dma-coherence.h b/arch/mips/include/asm/mach-generic/dma-coherence.h
index 36c611b6c597..8da98073e952 100644
--- a/arch/mips/include/asm/mach-generic/dma-coherence.h
+++ b/arch/mips/include/asm/mach-generic/dma-coherence.h
@@ -23,12 +23,14 @@ static inline dma_addr_t plat_map_dma_mem_page(struct device *dev,
23 return page_to_phys(page); 23 return page_to_phys(page);
24} 24}
25 25
26static inline unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr) 26static inline unsigned long plat_dma_addr_to_phys(struct device *dev,
27 dma_addr_t dma_addr)
27{ 28{
28 return dma_addr; 29 return dma_addr;
29} 30}
30 31
31static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr) 32static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr,
33 size_t size, enum dma_data_direction direction)
32{ 34{
33} 35}
34 36
diff --git a/arch/mips/include/asm/mach-ip27/dma-coherence.h b/arch/mips/include/asm/mach-ip27/dma-coherence.h
index 4c21bfca10c3..d3d04018a858 100644
--- a/arch/mips/include/asm/mach-ip27/dma-coherence.h
+++ b/arch/mips/include/asm/mach-ip27/dma-coherence.h
@@ -33,12 +33,14 @@ static dma_addr_t plat_map_dma_mem_page(struct device *dev, struct page *page)
33 return pa; 33 return pa;
34} 34}
35 35
36static unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr) 36static unsigned long plat_dma_addr_to_phys(struct device *dev,
37 dma_addr_t dma_addr)
37{ 38{
38 return dma_addr & ~(0xffUL << 56); 39 return dma_addr & ~(0xffUL << 56);
39} 40}
40 41
41static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr) 42static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr,
43 size_t size, enum dma_data_direction direction)
42{ 44{
43} 45}
44 46
diff --git a/arch/mips/include/asm/mach-ip32/dma-coherence.h b/arch/mips/include/asm/mach-ip32/dma-coherence.h
index 7ae40f4b1c80..37855955b313 100644
--- a/arch/mips/include/asm/mach-ip32/dma-coherence.h
+++ b/arch/mips/include/asm/mach-ip32/dma-coherence.h
@@ -50,7 +50,8 @@ static dma_addr_t plat_map_dma_mem_page(struct device *dev, struct page *page)
50} 50}
51 51
52/* This is almost certainly wrong but it's what dma-ip32.c used to use */ 52/* This is almost certainly wrong but it's what dma-ip32.c used to use */
53static unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr) 53static unsigned long plat_dma_addr_to_phys(struct device *dev,
54 dma_addr_t dma_addr)
54{ 55{
55 unsigned long addr = dma_addr & RAM_OFFSET_MASK; 56 unsigned long addr = dma_addr & RAM_OFFSET_MASK;
56 57
@@ -60,7 +61,8 @@ static unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr)
60 return addr; 61 return addr;
61} 62}
62 63
63static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr) 64static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr,
65 size_t size, enum dma_data_direction direction)
64{ 66{
65} 67}
66 68
diff --git a/arch/mips/include/asm/mach-jazz/dma-coherence.h b/arch/mips/include/asm/mach-jazz/dma-coherence.h
index 1c7cd27efa7b..f93aee59454a 100644
--- a/arch/mips/include/asm/mach-jazz/dma-coherence.h
+++ b/arch/mips/include/asm/mach-jazz/dma-coherence.h
@@ -22,12 +22,14 @@ static dma_addr_t plat_map_dma_mem_page(struct device *dev, struct page *page)
22 return vdma_alloc(page_to_phys(page), PAGE_SIZE); 22 return vdma_alloc(page_to_phys(page), PAGE_SIZE);
23} 23}
24 24
25static unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr) 25static unsigned long plat_dma_addr_to_phys(struct device *dev,
26 dma_addr_t dma_addr)
26{ 27{
27 return vdma_log2phys(dma_addr); 28 return vdma_log2phys(dma_addr);
28} 29}
29 30
30static void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr) 31static void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr,
32 size_t size, enum dma_data_direction direction)
31{ 33{
32 vdma_free(dma_addr); 34 vdma_free(dma_addr);
33} 35}
diff --git a/arch/mips/include/asm/mach-lemote/dma-coherence.h b/arch/mips/include/asm/mach-lemote/dma-coherence.h
index 38fad7dfe7da..c8de5e750777 100644
--- a/arch/mips/include/asm/mach-lemote/dma-coherence.h
+++ b/arch/mips/include/asm/mach-lemote/dma-coherence.h
@@ -25,12 +25,14 @@ static inline dma_addr_t plat_map_dma_mem_page(struct device *dev,
25 return page_to_phys(page) | 0x80000000; 25 return page_to_phys(page) | 0x80000000;
26} 26}
27 27
28static inline unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr) 28static inline unsigned long plat_dma_addr_to_phys(struct device *dev,
29 dma_addr_t dma_addr)
29{ 30{
30 return dma_addr & 0x7fffffff; 31 return dma_addr & 0x7fffffff;
31} 32}
32 33
33static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr) 34static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr,
35 size_t size, enum dma_data_direction direction)
34{ 36{
35} 37}
36 38
diff --git a/arch/mips/include/asm/mach-rc32434/cpu-feature-overrides.h b/arch/mips/include/asm/mach-rc32434/cpu-feature-overrides.h
index f3bc7efa2608..c3e4d3a4c95d 100644
--- a/arch/mips/include/asm/mach-rc32434/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-rc32434/cpu-feature-overrides.h
@@ -53,11 +53,6 @@
53#define cpu_has_smartmips 0 53#define cpu_has_smartmips 0
54 54
55#define cpu_has_vtag_icache 0 55#define cpu_has_vtag_icache 0
56/* #define cpu_has_dc_aliases ? */
57/* #define cpu_has_ic_fills_f_dc ? */
58/* #define cpu_has_pindexed_dcache ? */
59
60/* #define cpu_icache_snoops_remote_store ? */
61 56
62#define cpu_has_mips32r1 1 57#define cpu_has_mips32r1 1
63#define cpu_has_mips32r2 0 58#define cpu_has_mips32r2 0
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 32ef8bec5c85..a581d60cbcc2 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -220,6 +220,22 @@
220#error Bad page size configuration! 220#error Bad page size configuration!
221#endif 221#endif
222 222
223/*
224 * Default huge tlb size for a given kernel configuration
225 */
226#ifdef CONFIG_PAGE_SIZE_4KB
227#define PM_HUGE_MASK PM_1M
228#elif defined(CONFIG_PAGE_SIZE_8KB)
229#define PM_HUGE_MASK PM_4M
230#elif defined(CONFIG_PAGE_SIZE_16KB)
231#define PM_HUGE_MASK PM_16M
232#elif defined(CONFIG_PAGE_SIZE_32KB)
233#define PM_HUGE_MASK PM_64M
234#elif defined(CONFIG_PAGE_SIZE_64KB)
235#define PM_HUGE_MASK PM_256M
236#elif defined(CONFIG_HUGETLB_PAGE)
237#error Bad page size configuration for hugetlbfs!
238#endif
223 239
224/* 240/*
225 * Values used for computation of new tlb entries 241 * Values used for computation of new tlb entries
diff --git a/arch/mips/include/asm/octeon/cvmx-bootinfo.h b/arch/mips/include/asm/octeon/cvmx-bootinfo.h
index 692989acd8a9..f3c23a43f845 100644
--- a/arch/mips/include/asm/octeon/cvmx-bootinfo.h
+++ b/arch/mips/include/asm/octeon/cvmx-bootinfo.h
@@ -157,6 +157,13 @@ enum cvmx_board_types_enum {
157 CVMX_BOARD_TYPE_NIC_XLE_4G = 21, 157 CVMX_BOARD_TYPE_NIC_XLE_4G = 21,
158 CVMX_BOARD_TYPE_EBT5600 = 22, 158 CVMX_BOARD_TYPE_EBT5600 = 22,
159 CVMX_BOARD_TYPE_EBH5201 = 23, 159 CVMX_BOARD_TYPE_EBH5201 = 23,
160 CVMX_BOARD_TYPE_EBT5200 = 24,
161 CVMX_BOARD_TYPE_CB5600 = 25,
162 CVMX_BOARD_TYPE_CB5601 = 26,
163 CVMX_BOARD_TYPE_CB5200 = 27,
164 /* Special 'generic' board type, supports many boards */
165 CVMX_BOARD_TYPE_GENERIC = 28,
166 CVMX_BOARD_TYPE_EBH5610 = 29,
160 CVMX_BOARD_TYPE_MAX, 167 CVMX_BOARD_TYPE_MAX,
161 168
162 /* 169 /*
@@ -228,6 +235,12 @@ static inline const char *cvmx_board_type_to_string(enum
228 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIC_XLE_4G) 235 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIC_XLE_4G)
229 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBT5600) 236 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBT5600)
230 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBH5201) 237 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBH5201)
238 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBT5200)
239 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CB5600)
240 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CB5601)
241 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CB5200)
242 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_GENERIC)
243 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBH5610)
231 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_MAX) 244 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_MAX)
232 245
233 /* Customer boards listed here */ 246 /* Customer boards listed here */
diff --git a/arch/mips/include/asm/octeon/cvmx-bootmem.h b/arch/mips/include/asm/octeon/cvmx-bootmem.h
index 1cbe4b55889d..8e708bdb43f7 100644
--- a/arch/mips/include/asm/octeon/cvmx-bootmem.h
+++ b/arch/mips/include/asm/octeon/cvmx-bootmem.h
@@ -183,6 +183,64 @@ extern void *cvmx_bootmem_alloc_range(uint64_t size, uint64_t alignment,
183 * Returns 0 on failure, 183 * Returns 0 on failure,
184 * !0 on success 184 * !0 on success
185 */ 185 */
186
187
188/**
189 * Allocate a block of memory from the free list that was passed
190 * to the application by the bootloader, and assign it a name in the
191 * global named block table. (part of the cvmx_bootmem_descriptor_t structure)
192 * Named blocks can later be freed.
193 *
194 * @size: Size in bytes of block to allocate
195 * @alignment: Alignment required - must be power of 2
196 * @name: name of block - must be less than CVMX_BOOTMEM_NAME_LEN bytes
197 *
198 * Returns a pointer to block of memory, NULL on error
199 */
200extern void *cvmx_bootmem_alloc_named(uint64_t size, uint64_t alignment,
201 char *name);
202
203
204
205/**
206 * Allocate a block of memory from the free list that was passed
207 * to the application by the bootloader, and assign it a name in the
208 * global named block table. (part of the cvmx_bootmem_descriptor_t structure)
209 * Named blocks can later be freed.
210 *
211 * @size: Size in bytes of block to allocate
212 * @address: Physical address to allocate memory at. If this
213 * memory is not available, the allocation fails.
214 * @name: name of block - must be less than CVMX_BOOTMEM_NAME_LEN
215 * bytes
216 *
217 * Returns a pointer to block of memory, NULL on error
218 */
219extern void *cvmx_bootmem_alloc_named_address(uint64_t size, uint64_t address,
220 char *name);
221
222
223
224/**
225 * Allocate a block of memory from a specific range of the free list
226 * that was passed to the application by the bootloader, and assign it
227 * a name in the global named block table. (part of the
228 * cvmx_bootmem_descriptor_t structure) Named blocks can later be
229 * freed. If request cannot be satisfied within the address range
230 * specified, NULL is returned
231 *
232 * @size: Size in bytes of block to allocate
233 * @min_addr: minimum address of range
234 * @max_addr: maximum address of range
235 * @align: Alignment of memory to be allocated. (must be a power of 2)
236 * @name: name of block - must be less than CVMX_BOOTMEM_NAME_LEN bytes
237 *
238 * Returns a pointer to block of memory, NULL on error
239 */
240extern void *cvmx_bootmem_alloc_named_range(uint64_t size, uint64_t min_addr,
241 uint64_t max_addr, uint64_t align,
242 char *name);
243
186extern int cvmx_bootmem_free_named(char *name); 244extern int cvmx_bootmem_free_named(char *name);
187 245
188/** 246/**
@@ -224,6 +282,33 @@ int64_t cvmx_bootmem_phy_alloc(uint64_t req_size, uint64_t address_min,
224 uint32_t flags); 282 uint32_t flags);
225 283
226/** 284/**
285 * Allocates a named block of physical memory from the free list, at
286 * (optional) requested address and alignment.
287 *
288 * @param size size of region to allocate. All requests are rounded
289 * up to be a multiple CVMX_BOOTMEM_ALIGNMENT_SIZE
290 * bytes size
291 * @param min_addr Minimum address that block can occupy.
292 * @param max_addr Specifies the maximum address_min (inclusive) that
293 * the allocation can use.
294 * @param alignment Requested alignment of the block. If this
295 * alignment cannot be met, the allocation fails.
296 * This must be a power of 2. (Note: Alignment of
297 * CVMX_BOOTMEM_ALIGNMENT_SIZE bytes is required, and
298 * internally enforced. Requested alignments of less
299 * than CVMX_BOOTMEM_ALIGNMENT_SIZE are set to
300 * CVMX_BOOTMEM_ALIGNMENT_SIZE.)
301 * @param name name to assign to named block
302 * @param flags Flags to control options for the allocation.
303 *
304 * @return physical address of block allocated, or -1 on failure
305 */
306int64_t cvmx_bootmem_phy_named_block_alloc(uint64_t size, uint64_t min_addr,
307 uint64_t max_addr,
308 uint64_t alignment,
309 char *name, uint32_t flags);
310
311/**
227 * Finds a named memory block by name. 312 * Finds a named memory block by name.
228 * Also used for finding an unused entry in the named block table. 313 * Also used for finding an unused entry in the named block table.
229 * 314 *
diff --git a/arch/mips/include/asm/octeon/cvmx-helper-errata.h b/arch/mips/include/asm/octeon/cvmx-helper-errata.h
new file mode 100644
index 000000000000..5fc99189ff58
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-helper-errata.h
@@ -0,0 +1,33 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_HELPER_ERRATA_H__
29#define __CVMX_HELPER_ERRATA_H__
30
31extern void __cvmx_helper_errata_qlm_disable_2nd_order_cdr(int qlm);
32
33#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-helper-jtag.h b/arch/mips/include/asm/octeon/cvmx-helper-jtag.h
new file mode 100644
index 000000000000..29f016ddb895
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-helper-jtag.h
@@ -0,0 +1,43 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28/**
29 * @file
30 *
31 * Helper utilities for qlm_jtag.
32 *
33 */
34
35#ifndef __CVMX_HELPER_JTAG_H__
36#define __CVMX_HELPER_JTAG_H__
37
38extern void cvmx_helper_qlm_jtag_init(void);
39extern uint32_t cvmx_helper_qlm_jtag_shift(int qlm, int bits, uint32_t data);
40extern void cvmx_helper_qlm_jtag_shift_zeros(int qlm, int bits);
41extern void cvmx_helper_qlm_jtag_update(int qlm);
42
43#endif /* __CVMX_HELPER_JTAG_H__ */
diff --git a/arch/mips/include/asm/octeon/cvmx-npei-defs.h b/arch/mips/include/asm/octeon/cvmx-npei-defs.h
new file mode 100644
index 000000000000..4b347bb8ce80
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-npei-defs.h
@@ -0,0 +1,2560 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_NPEI_DEFS_H__
29#define __CVMX_NPEI_DEFS_H__
30
31#define CVMX_NPEI_BAR1_INDEXX(offset) \
32 (0x0000000000000000ull + (((offset) & 31) * 16))
33#define CVMX_NPEI_BIST_STATUS \
34 (0x0000000000000580ull)
35#define CVMX_NPEI_BIST_STATUS2 \
36 (0x0000000000000680ull)
37#define CVMX_NPEI_CTL_PORT0 \
38 (0x0000000000000250ull)
39#define CVMX_NPEI_CTL_PORT1 \
40 (0x0000000000000260ull)
41#define CVMX_NPEI_CTL_STATUS \
42 (0x0000000000000570ull)
43#define CVMX_NPEI_CTL_STATUS2 \
44 (0x0000000000003C00ull)
45#define CVMX_NPEI_DATA_OUT_CNT \
46 (0x00000000000005F0ull)
47#define CVMX_NPEI_DBG_DATA \
48 (0x0000000000000510ull)
49#define CVMX_NPEI_DBG_SELECT \
50 (0x0000000000000500ull)
51#define CVMX_NPEI_DMA0_INT_LEVEL \
52 (0x00000000000005C0ull)
53#define CVMX_NPEI_DMA1_INT_LEVEL \
54 (0x00000000000005D0ull)
55#define CVMX_NPEI_DMAX_COUNTS(offset) \
56 (0x0000000000000450ull + (((offset) & 7) * 16))
57#define CVMX_NPEI_DMAX_DBELL(offset) \
58 (0x00000000000003B0ull + (((offset) & 7) * 16))
59#define CVMX_NPEI_DMAX_IBUFF_SADDR(offset) \
60 (0x0000000000000400ull + (((offset) & 7) * 16))
61#define CVMX_NPEI_DMAX_NADDR(offset) \
62 (0x00000000000004A0ull + (((offset) & 7) * 16))
63#define CVMX_NPEI_DMA_CNTS \
64 (0x00000000000005E0ull)
65#define CVMX_NPEI_DMA_CONTROL \
66 (0x00000000000003A0ull)
67#define CVMX_NPEI_INT_A_ENB \
68 (0x0000000000000560ull)
69#define CVMX_NPEI_INT_A_ENB2 \
70 (0x0000000000003CE0ull)
71#define CVMX_NPEI_INT_A_SUM \
72 (0x0000000000000550ull)
73#define CVMX_NPEI_INT_ENB \
74 (0x0000000000000540ull)
75#define CVMX_NPEI_INT_ENB2 \
76 (0x0000000000003CD0ull)
77#define CVMX_NPEI_INT_INFO \
78 (0x0000000000000590ull)
79#define CVMX_NPEI_INT_SUM \
80 (0x0000000000000530ull)
81#define CVMX_NPEI_INT_SUM2 \
82 (0x0000000000003CC0ull)
83#define CVMX_NPEI_LAST_WIN_RDATA0 \
84 (0x0000000000000600ull)
85#define CVMX_NPEI_LAST_WIN_RDATA1 \
86 (0x0000000000000610ull)
87#define CVMX_NPEI_MEM_ACCESS_CTL \
88 (0x00000000000004F0ull)
89#define CVMX_NPEI_MEM_ACCESS_SUBIDX(offset) \
90 (0x0000000000000340ull + (((offset) & 31) * 16) - 16 * 12)
91#define CVMX_NPEI_MSI_ENB0 \
92 (0x0000000000003C50ull)
93#define CVMX_NPEI_MSI_ENB1 \
94 (0x0000000000003C60ull)
95#define CVMX_NPEI_MSI_ENB2 \
96 (0x0000000000003C70ull)
97#define CVMX_NPEI_MSI_ENB3 \
98 (0x0000000000003C80ull)
99#define CVMX_NPEI_MSI_RCV0 \
100 (0x0000000000003C10ull)
101#define CVMX_NPEI_MSI_RCV1 \
102 (0x0000000000003C20ull)
103#define CVMX_NPEI_MSI_RCV2 \
104 (0x0000000000003C30ull)
105#define CVMX_NPEI_MSI_RCV3 \
106 (0x0000000000003C40ull)
107#define CVMX_NPEI_MSI_RD_MAP \
108 (0x0000000000003CA0ull)
109#define CVMX_NPEI_MSI_W1C_ENB0 \
110 (0x0000000000003CF0ull)
111#define CVMX_NPEI_MSI_W1C_ENB1 \
112 (0x0000000000003D00ull)
113#define CVMX_NPEI_MSI_W1C_ENB2 \
114 (0x0000000000003D10ull)
115#define CVMX_NPEI_MSI_W1C_ENB3 \
116 (0x0000000000003D20ull)
117#define CVMX_NPEI_MSI_W1S_ENB0 \
118 (0x0000000000003D30ull)
119#define CVMX_NPEI_MSI_W1S_ENB1 \
120 (0x0000000000003D40ull)
121#define CVMX_NPEI_MSI_W1S_ENB2 \
122 (0x0000000000003D50ull)
123#define CVMX_NPEI_MSI_W1S_ENB3 \
124 (0x0000000000003D60ull)
125#define CVMX_NPEI_MSI_WR_MAP \
126 (0x0000000000003C90ull)
127#define CVMX_NPEI_PCIE_CREDIT_CNT \
128 (0x0000000000003D70ull)
129#define CVMX_NPEI_PCIE_MSI_RCV \
130 (0x0000000000003CB0ull)
131#define CVMX_NPEI_PCIE_MSI_RCV_B1 \
132 (0x0000000000000650ull)
133#define CVMX_NPEI_PCIE_MSI_RCV_B2 \
134 (0x0000000000000660ull)
135#define CVMX_NPEI_PCIE_MSI_RCV_B3 \
136 (0x0000000000000670ull)
137#define CVMX_NPEI_PKTX_CNTS(offset) \
138 (0x0000000000002400ull + (((offset) & 31) * 16))
139#define CVMX_NPEI_PKTX_INSTR_BADDR(offset) \
140 (0x0000000000002800ull + (((offset) & 31) * 16))
141#define CVMX_NPEI_PKTX_INSTR_BAOFF_DBELL(offset) \
142 (0x0000000000002C00ull + (((offset) & 31) * 16))
143#define CVMX_NPEI_PKTX_INSTR_FIFO_RSIZE(offset) \
144 (0x0000000000003000ull + (((offset) & 31) * 16))
145#define CVMX_NPEI_PKTX_INSTR_HEADER(offset) \
146 (0x0000000000003400ull + (((offset) & 31) * 16))
147#define CVMX_NPEI_PKTX_IN_BP(offset) \
148 (0x0000000000003800ull + (((offset) & 31) * 16))
149#define CVMX_NPEI_PKTX_SLIST_BADDR(offset) \
150 (0x0000000000001400ull + (((offset) & 31) * 16))
151#define CVMX_NPEI_PKTX_SLIST_BAOFF_DBELL(offset) \
152 (0x0000000000001800ull + (((offset) & 31) * 16))
153#define CVMX_NPEI_PKTX_SLIST_FIFO_RSIZE(offset) \
154 (0x0000000000001C00ull + (((offset) & 31) * 16))
155#define CVMX_NPEI_PKT_CNT_INT \
156 (0x0000000000001110ull)
157#define CVMX_NPEI_PKT_CNT_INT_ENB \
158 (0x0000000000001130ull)
159#define CVMX_NPEI_PKT_DATA_OUT_ES \
160 (0x00000000000010B0ull)
161#define CVMX_NPEI_PKT_DATA_OUT_NS \
162 (0x00000000000010A0ull)
163#define CVMX_NPEI_PKT_DATA_OUT_ROR \
164 (0x0000000000001090ull)
165#define CVMX_NPEI_PKT_DPADDR \
166 (0x0000000000001080ull)
167#define CVMX_NPEI_PKT_INPUT_CONTROL \
168 (0x0000000000001150ull)
169#define CVMX_NPEI_PKT_INSTR_ENB \
170 (0x0000000000001000ull)
171#define CVMX_NPEI_PKT_INSTR_RD_SIZE \
172 (0x0000000000001190ull)
173#define CVMX_NPEI_PKT_INSTR_SIZE \
174 (0x0000000000001020ull)
175#define CVMX_NPEI_PKT_INT_LEVELS \
176 (0x0000000000001100ull)
177#define CVMX_NPEI_PKT_IN_BP \
178 (0x00000000000006B0ull)
179#define CVMX_NPEI_PKT_IN_DONEX_CNTS(offset) \
180 (0x0000000000002000ull + (((offset) & 31) * 16))
181#define CVMX_NPEI_PKT_IN_INSTR_COUNTS \
182 (0x00000000000006A0ull)
183#define CVMX_NPEI_PKT_IN_PCIE_PORT \
184 (0x00000000000011A0ull)
185#define CVMX_NPEI_PKT_IPTR \
186 (0x0000000000001070ull)
187#define CVMX_NPEI_PKT_OUTPUT_WMARK \
188 (0x0000000000001160ull)
189#define CVMX_NPEI_PKT_OUT_BMODE \
190 (0x00000000000010D0ull)
191#define CVMX_NPEI_PKT_OUT_ENB \
192 (0x0000000000001010ull)
193#define CVMX_NPEI_PKT_PCIE_PORT \
194 (0x00000000000010E0ull)
195#define CVMX_NPEI_PKT_PORT_IN_RST \
196 (0x0000000000000690ull)
197#define CVMX_NPEI_PKT_SLIST_ES \
198 (0x0000000000001050ull)
199#define CVMX_NPEI_PKT_SLIST_ID_SIZE \
200 (0x0000000000001180ull)
201#define CVMX_NPEI_PKT_SLIST_NS \
202 (0x0000000000001040ull)
203#define CVMX_NPEI_PKT_SLIST_ROR \
204 (0x0000000000001030ull)
205#define CVMX_NPEI_PKT_TIME_INT \
206 (0x0000000000001120ull)
207#define CVMX_NPEI_PKT_TIME_INT_ENB \
208 (0x0000000000001140ull)
209#define CVMX_NPEI_RSL_INT_BLOCKS \
210 (0x0000000000000520ull)
211#define CVMX_NPEI_SCRATCH_1 \
212 (0x0000000000000270ull)
213#define CVMX_NPEI_STATE1 \
214 (0x0000000000000620ull)
215#define CVMX_NPEI_STATE2 \
216 (0x0000000000000630ull)
217#define CVMX_NPEI_STATE3 \
218 (0x0000000000000640ull)
219#define CVMX_NPEI_WINDOW_CTL \
220 (0x0000000000000380ull)
221#define CVMX_NPEI_WIN_RD_ADDR \
222 (0x0000000000000210ull)
223#define CVMX_NPEI_WIN_RD_DATA \
224 (0x0000000000000240ull)
225#define CVMX_NPEI_WIN_WR_ADDR \
226 (0x0000000000000200ull)
227#define CVMX_NPEI_WIN_WR_DATA \
228 (0x0000000000000220ull)
229#define CVMX_NPEI_WIN_WR_MASK \
230 (0x0000000000000230ull)
231
232union cvmx_npei_bar1_indexx {
233 uint32_t u32;
234 struct cvmx_npei_bar1_indexx_s {
235 uint32_t reserved_18_31:14;
236 uint32_t addr_idx:14;
237 uint32_t ca:1;
238 uint32_t end_swp:2;
239 uint32_t addr_v:1;
240 } s;
241 struct cvmx_npei_bar1_indexx_s cn52xx;
242 struct cvmx_npei_bar1_indexx_s cn52xxp1;
243 struct cvmx_npei_bar1_indexx_s cn56xx;
244 struct cvmx_npei_bar1_indexx_s cn56xxp1;
245};
246
247union cvmx_npei_bist_status {
248 uint64_t u64;
249 struct cvmx_npei_bist_status_s {
250 uint64_t pkt_rdf:1;
251 uint64_t pkt_pmem:1;
252 uint64_t pkt_p1:1;
253 uint64_t reserved_60_60:1;
254 uint64_t pcr_gim:1;
255 uint64_t pkt_pif:1;
256 uint64_t pcsr_int:1;
257 uint64_t pcsr_im:1;
258 uint64_t pcsr_cnt:1;
259 uint64_t pcsr_id:1;
260 uint64_t pcsr_sl:1;
261 uint64_t reserved_50_52:3;
262 uint64_t pkt_ind:1;
263 uint64_t pkt_slm:1;
264 uint64_t reserved_36_47:12;
265 uint64_t d0_pst:1;
266 uint64_t d1_pst:1;
267 uint64_t d2_pst:1;
268 uint64_t d3_pst:1;
269 uint64_t reserved_31_31:1;
270 uint64_t n2p0_c:1;
271 uint64_t n2p0_o:1;
272 uint64_t n2p1_c:1;
273 uint64_t n2p1_o:1;
274 uint64_t cpl_p0:1;
275 uint64_t cpl_p1:1;
276 uint64_t p2n1_po:1;
277 uint64_t p2n1_no:1;
278 uint64_t p2n1_co:1;
279 uint64_t p2n0_po:1;
280 uint64_t p2n0_no:1;
281 uint64_t p2n0_co:1;
282 uint64_t p2n0_c0:1;
283 uint64_t p2n0_c1:1;
284 uint64_t p2n0_n:1;
285 uint64_t p2n0_p0:1;
286 uint64_t p2n0_p1:1;
287 uint64_t p2n1_c0:1;
288 uint64_t p2n1_c1:1;
289 uint64_t p2n1_n:1;
290 uint64_t p2n1_p0:1;
291 uint64_t p2n1_p1:1;
292 uint64_t csm0:1;
293 uint64_t csm1:1;
294 uint64_t dif0:1;
295 uint64_t dif1:1;
296 uint64_t dif2:1;
297 uint64_t dif3:1;
298 uint64_t reserved_2_2:1;
299 uint64_t msi:1;
300 uint64_t ncb_cmd:1;
301 } s;
302 struct cvmx_npei_bist_status_cn52xx {
303 uint64_t pkt_rdf:1;
304 uint64_t pkt_pmem:1;
305 uint64_t pkt_p1:1;
306 uint64_t reserved_60_60:1;
307 uint64_t pcr_gim:1;
308 uint64_t pkt_pif:1;
309 uint64_t pcsr_int:1;
310 uint64_t pcsr_im:1;
311 uint64_t pcsr_cnt:1;
312 uint64_t pcsr_id:1;
313 uint64_t pcsr_sl:1;
314 uint64_t pkt_imem:1;
315 uint64_t pkt_pfm:1;
316 uint64_t pkt_pof:1;
317 uint64_t reserved_48_49:2;
318 uint64_t pkt_pop0:1;
319 uint64_t pkt_pop1:1;
320 uint64_t d0_mem:1;
321 uint64_t d1_mem:1;
322 uint64_t d2_mem:1;
323 uint64_t d3_mem:1;
324 uint64_t d4_mem:1;
325 uint64_t ds_mem:1;
326 uint64_t reserved_36_39:4;
327 uint64_t d0_pst:1;
328 uint64_t d1_pst:1;
329 uint64_t d2_pst:1;
330 uint64_t d3_pst:1;
331 uint64_t d4_pst:1;
332 uint64_t n2p0_c:1;
333 uint64_t n2p0_o:1;
334 uint64_t n2p1_c:1;
335 uint64_t n2p1_o:1;
336 uint64_t cpl_p0:1;
337 uint64_t cpl_p1:1;
338 uint64_t p2n1_po:1;
339 uint64_t p2n1_no:1;
340 uint64_t p2n1_co:1;
341 uint64_t p2n0_po:1;
342 uint64_t p2n0_no:1;
343 uint64_t p2n0_co:1;
344 uint64_t p2n0_c0:1;
345 uint64_t p2n0_c1:1;
346 uint64_t p2n0_n:1;
347 uint64_t p2n0_p0:1;
348 uint64_t p2n0_p1:1;
349 uint64_t p2n1_c0:1;
350 uint64_t p2n1_c1:1;
351 uint64_t p2n1_n:1;
352 uint64_t p2n1_p0:1;
353 uint64_t p2n1_p1:1;
354 uint64_t csm0:1;
355 uint64_t csm1:1;
356 uint64_t dif0:1;
357 uint64_t dif1:1;
358 uint64_t dif2:1;
359 uint64_t dif3:1;
360 uint64_t dif4:1;
361 uint64_t msi:1;
362 uint64_t ncb_cmd:1;
363 } cn52xx;
364 struct cvmx_npei_bist_status_cn52xxp1 {
365 uint64_t reserved_46_63:18;
366 uint64_t d0_mem0:1;
367 uint64_t d1_mem1:1;
368 uint64_t d2_mem2:1;
369 uint64_t d3_mem3:1;
370 uint64_t dr0_mem:1;
371 uint64_t d0_mem:1;
372 uint64_t d1_mem:1;
373 uint64_t d2_mem:1;
374 uint64_t d3_mem:1;
375 uint64_t dr1_mem:1;
376 uint64_t d0_pst:1;
377 uint64_t d1_pst:1;
378 uint64_t d2_pst:1;
379 uint64_t d3_pst:1;
380 uint64_t dr2_mem:1;
381 uint64_t n2p0_c:1;
382 uint64_t n2p0_o:1;
383 uint64_t n2p1_c:1;
384 uint64_t n2p1_o:1;
385 uint64_t cpl_p0:1;
386 uint64_t cpl_p1:1;
387 uint64_t p2n1_po:1;
388 uint64_t p2n1_no:1;
389 uint64_t p2n1_co:1;
390 uint64_t p2n0_po:1;
391 uint64_t p2n0_no:1;
392 uint64_t p2n0_co:1;
393 uint64_t p2n0_c0:1;
394 uint64_t p2n0_c1:1;
395 uint64_t p2n0_n:1;
396 uint64_t p2n0_p0:1;
397 uint64_t p2n0_p1:1;
398 uint64_t p2n1_c0:1;
399 uint64_t p2n1_c1:1;
400 uint64_t p2n1_n:1;
401 uint64_t p2n1_p0:1;
402 uint64_t p2n1_p1:1;
403 uint64_t csm0:1;
404 uint64_t csm1:1;
405 uint64_t dif0:1;
406 uint64_t dif1:1;
407 uint64_t dif2:1;
408 uint64_t dif3:1;
409 uint64_t dr3_mem:1;
410 uint64_t msi:1;
411 uint64_t ncb_cmd:1;
412 } cn52xxp1;
413 struct cvmx_npei_bist_status_cn56xx {
414 uint64_t pkt_rdf:1;
415 uint64_t reserved_60_62:3;
416 uint64_t pcr_gim:1;
417 uint64_t pkt_pif:1;
418 uint64_t pcsr_int:1;
419 uint64_t pcsr_im:1;
420 uint64_t pcsr_cnt:1;
421 uint64_t pcsr_id:1;
422 uint64_t pcsr_sl:1;
423 uint64_t pkt_imem:1;
424 uint64_t pkt_pfm:1;
425 uint64_t pkt_pof:1;
426 uint64_t reserved_48_49:2;
427 uint64_t pkt_pop0:1;
428 uint64_t pkt_pop1:1;
429 uint64_t d0_mem:1;
430 uint64_t d1_mem:1;
431 uint64_t d2_mem:1;
432 uint64_t d3_mem:1;
433 uint64_t d4_mem:1;
434 uint64_t ds_mem:1;
435 uint64_t reserved_36_39:4;
436 uint64_t d0_pst:1;
437 uint64_t d1_pst:1;
438 uint64_t d2_pst:1;
439 uint64_t d3_pst:1;
440 uint64_t d4_pst:1;
441 uint64_t n2p0_c:1;
442 uint64_t n2p0_o:1;
443 uint64_t n2p1_c:1;
444 uint64_t n2p1_o:1;
445 uint64_t cpl_p0:1;
446 uint64_t cpl_p1:1;
447 uint64_t p2n1_po:1;
448 uint64_t p2n1_no:1;
449 uint64_t p2n1_co:1;
450 uint64_t p2n0_po:1;
451 uint64_t p2n0_no:1;
452 uint64_t p2n0_co:1;
453 uint64_t p2n0_c0:1;
454 uint64_t p2n0_c1:1;
455 uint64_t p2n0_n:1;
456 uint64_t p2n0_p0:1;
457 uint64_t p2n0_p1:1;
458 uint64_t p2n1_c0:1;
459 uint64_t p2n1_c1:1;
460 uint64_t p2n1_n:1;
461 uint64_t p2n1_p0:1;
462 uint64_t p2n1_p1:1;
463 uint64_t csm0:1;
464 uint64_t csm1:1;
465 uint64_t dif0:1;
466 uint64_t dif1:1;
467 uint64_t dif2:1;
468 uint64_t dif3:1;
469 uint64_t dif4:1;
470 uint64_t msi:1;
471 uint64_t ncb_cmd:1;
472 } cn56xx;
473 struct cvmx_npei_bist_status_cn56xxp1 {
474 uint64_t reserved_58_63:6;
475 uint64_t pcsr_int:1;
476 uint64_t pcsr_im:1;
477 uint64_t pcsr_cnt:1;
478 uint64_t pcsr_id:1;
479 uint64_t pcsr_sl:1;
480 uint64_t pkt_pout:1;
481 uint64_t pkt_imem:1;
482 uint64_t pkt_cntm:1;
483 uint64_t pkt_ind:1;
484 uint64_t pkt_slm:1;
485 uint64_t pkt_odf:1;
486 uint64_t pkt_oif:1;
487 uint64_t pkt_out:1;
488 uint64_t pkt_i0:1;
489 uint64_t pkt_i1:1;
490 uint64_t pkt_s0:1;
491 uint64_t pkt_s1:1;
492 uint64_t d0_mem:1;
493 uint64_t d1_mem:1;
494 uint64_t d2_mem:1;
495 uint64_t d3_mem:1;
496 uint64_t d4_mem:1;
497 uint64_t d0_pst:1;
498 uint64_t d1_pst:1;
499 uint64_t d2_pst:1;
500 uint64_t d3_pst:1;
501 uint64_t d4_pst:1;
502 uint64_t n2p0_c:1;
503 uint64_t n2p0_o:1;
504 uint64_t n2p1_c:1;
505 uint64_t n2p1_o:1;
506 uint64_t cpl_p0:1;
507 uint64_t cpl_p1:1;
508 uint64_t p2n1_po:1;
509 uint64_t p2n1_no:1;
510 uint64_t p2n1_co:1;
511 uint64_t p2n0_po:1;
512 uint64_t p2n0_no:1;
513 uint64_t p2n0_co:1;
514 uint64_t p2n0_c0:1;
515 uint64_t p2n0_c1:1;
516 uint64_t p2n0_n:1;
517 uint64_t p2n0_p0:1;
518 uint64_t p2n0_p1:1;
519 uint64_t p2n1_c0:1;
520 uint64_t p2n1_c1:1;
521 uint64_t p2n1_n:1;
522 uint64_t p2n1_p0:1;
523 uint64_t p2n1_p1:1;
524 uint64_t csm0:1;
525 uint64_t csm1:1;
526 uint64_t dif0:1;
527 uint64_t dif1:1;
528 uint64_t dif2:1;
529 uint64_t dif3:1;
530 uint64_t dif4:1;
531 uint64_t msi:1;
532 uint64_t ncb_cmd:1;
533 } cn56xxp1;
534};
535
536union cvmx_npei_bist_status2 {
537 uint64_t u64;
538 struct cvmx_npei_bist_status2_s {
539 uint64_t reserved_5_63:59;
540 uint64_t psc_p0:1;
541 uint64_t psc_p1:1;
542 uint64_t pkt_gd:1;
543 uint64_t pkt_gl:1;
544 uint64_t pkt_blk:1;
545 } s;
546 struct cvmx_npei_bist_status2_s cn52xx;
547 struct cvmx_npei_bist_status2_s cn56xx;
548};
549
550union cvmx_npei_ctl_port0 {
551 uint64_t u64;
552 struct cvmx_npei_ctl_port0_s {
553 uint64_t reserved_21_63:43;
554 uint64_t waitl_com:1;
555 uint64_t intd:1;
556 uint64_t intc:1;
557 uint64_t intb:1;
558 uint64_t inta:1;
559 uint64_t intd_map:2;
560 uint64_t intc_map:2;
561 uint64_t intb_map:2;
562 uint64_t inta_map:2;
563 uint64_t ctlp_ro:1;
564 uint64_t reserved_6_6:1;
565 uint64_t ptlp_ro:1;
566 uint64_t bar2_enb:1;
567 uint64_t bar2_esx:2;
568 uint64_t bar2_cax:1;
569 uint64_t wait_com:1;
570 } s;
571 struct cvmx_npei_ctl_port0_s cn52xx;
572 struct cvmx_npei_ctl_port0_s cn52xxp1;
573 struct cvmx_npei_ctl_port0_s cn56xx;
574 struct cvmx_npei_ctl_port0_s cn56xxp1;
575};
576
577union cvmx_npei_ctl_port1 {
578 uint64_t u64;
579 struct cvmx_npei_ctl_port1_s {
580 uint64_t reserved_21_63:43;
581 uint64_t waitl_com:1;
582 uint64_t intd:1;
583 uint64_t intc:1;
584 uint64_t intb:1;
585 uint64_t inta:1;
586 uint64_t intd_map:2;
587 uint64_t intc_map:2;
588 uint64_t intb_map:2;
589 uint64_t inta_map:2;
590 uint64_t ctlp_ro:1;
591 uint64_t reserved_6_6:1;
592 uint64_t ptlp_ro:1;
593 uint64_t bar2_enb:1;
594 uint64_t bar2_esx:2;
595 uint64_t bar2_cax:1;
596 uint64_t wait_com:1;
597 } s;
598 struct cvmx_npei_ctl_port1_s cn52xx;
599 struct cvmx_npei_ctl_port1_s cn52xxp1;
600 struct cvmx_npei_ctl_port1_s cn56xx;
601 struct cvmx_npei_ctl_port1_s cn56xxp1;
602};
603
604union cvmx_npei_ctl_status {
605 uint64_t u64;
606 struct cvmx_npei_ctl_status_s {
607 uint64_t reserved_44_63:20;
608 uint64_t p1_ntags:6;
609 uint64_t p0_ntags:6;
610 uint64_t cfg_rtry:16;
611 uint64_t ring_en:1;
612 uint64_t lnk_rst:1;
613 uint64_t arb:1;
614 uint64_t pkt_bp:4;
615 uint64_t host_mode:1;
616 uint64_t chip_rev:8;
617 } s;
618 struct cvmx_npei_ctl_status_s cn52xx;
619 struct cvmx_npei_ctl_status_cn52xxp1 {
620 uint64_t reserved_44_63:20;
621 uint64_t p1_ntags:6;
622 uint64_t p0_ntags:6;
623 uint64_t cfg_rtry:16;
624 uint64_t reserved_15_15:1;
625 uint64_t lnk_rst:1;
626 uint64_t arb:1;
627 uint64_t reserved_9_12:4;
628 uint64_t host_mode:1;
629 uint64_t chip_rev:8;
630 } cn52xxp1;
631 struct cvmx_npei_ctl_status_s cn56xx;
632 struct cvmx_npei_ctl_status_cn56xxp1 {
633 uint64_t reserved_16_63:48;
634 uint64_t ring_en:1;
635 uint64_t lnk_rst:1;
636 uint64_t arb:1;
637 uint64_t pkt_bp:4;
638 uint64_t host_mode:1;
639 uint64_t chip_rev:8;
640 } cn56xxp1;
641};
642
643union cvmx_npei_ctl_status2 {
644 uint64_t u64;
645 struct cvmx_npei_ctl_status2_s {
646 uint64_t reserved_16_63:48;
647 uint64_t mps:1;
648 uint64_t mrrs:3;
649 uint64_t c1_w_flt:1;
650 uint64_t c0_w_flt:1;
651 uint64_t c1_b1_s:3;
652 uint64_t c0_b1_s:3;
653 uint64_t c1_wi_d:1;
654 uint64_t c1_b0_d:1;
655 uint64_t c0_wi_d:1;
656 uint64_t c0_b0_d:1;
657 } s;
658 struct cvmx_npei_ctl_status2_s cn52xx;
659 struct cvmx_npei_ctl_status2_s cn52xxp1;
660 struct cvmx_npei_ctl_status2_s cn56xx;
661 struct cvmx_npei_ctl_status2_s cn56xxp1;
662};
663
664union cvmx_npei_data_out_cnt {
665 uint64_t u64;
666 struct cvmx_npei_data_out_cnt_s {
667 uint64_t reserved_44_63:20;
668 uint64_t p1_ucnt:16;
669 uint64_t p1_fcnt:6;
670 uint64_t p0_ucnt:16;
671 uint64_t p0_fcnt:6;
672 } s;
673 struct cvmx_npei_data_out_cnt_s cn52xx;
674 struct cvmx_npei_data_out_cnt_s cn52xxp1;
675 struct cvmx_npei_data_out_cnt_s cn56xx;
676 struct cvmx_npei_data_out_cnt_s cn56xxp1;
677};
678
679union cvmx_npei_dbg_data {
680 uint64_t u64;
681 struct cvmx_npei_dbg_data_s {
682 uint64_t reserved_28_63:36;
683 uint64_t qlm0_rev_lanes:1;
684 uint64_t reserved_25_26:2;
685 uint64_t qlm1_spd:2;
686 uint64_t c_mul:5;
687 uint64_t dsel_ext:1;
688 uint64_t data:17;
689 } s;
690 struct cvmx_npei_dbg_data_cn52xx {
691 uint64_t reserved_29_63:35;
692 uint64_t qlm0_link_width:1;
693 uint64_t qlm0_rev_lanes:1;
694 uint64_t qlm1_mode:2;
695 uint64_t qlm1_spd:2;
696 uint64_t c_mul:5;
697 uint64_t dsel_ext:1;
698 uint64_t data:17;
699 } cn52xx;
700 struct cvmx_npei_dbg_data_cn52xx cn52xxp1;
701 struct cvmx_npei_dbg_data_cn56xx {
702 uint64_t reserved_29_63:35;
703 uint64_t qlm2_rev_lanes:1;
704 uint64_t qlm0_rev_lanes:1;
705 uint64_t qlm3_spd:2;
706 uint64_t qlm1_spd:2;
707 uint64_t c_mul:5;
708 uint64_t dsel_ext:1;
709 uint64_t data:17;
710 } cn56xx;
711 struct cvmx_npei_dbg_data_cn56xx cn56xxp1;
712};
713
714union cvmx_npei_dbg_select {
715 uint64_t u64;
716 struct cvmx_npei_dbg_select_s {
717 uint64_t reserved_16_63:48;
718 uint64_t dbg_sel:16;
719 } s;
720 struct cvmx_npei_dbg_select_s cn52xx;
721 struct cvmx_npei_dbg_select_s cn52xxp1;
722 struct cvmx_npei_dbg_select_s cn56xx;
723 struct cvmx_npei_dbg_select_s cn56xxp1;
724};
725
726union cvmx_npei_dmax_counts {
727 uint64_t u64;
728 struct cvmx_npei_dmax_counts_s {
729 uint64_t reserved_39_63:25;
730 uint64_t fcnt:7;
731 uint64_t dbell:32;
732 } s;
733 struct cvmx_npei_dmax_counts_s cn52xx;
734 struct cvmx_npei_dmax_counts_s cn52xxp1;
735 struct cvmx_npei_dmax_counts_s cn56xx;
736 struct cvmx_npei_dmax_counts_s cn56xxp1;
737};
738
739union cvmx_npei_dmax_dbell {
740 uint32_t u32;
741 struct cvmx_npei_dmax_dbell_s {
742 uint32_t reserved_16_31:16;
743 uint32_t dbell:16;
744 } s;
745 struct cvmx_npei_dmax_dbell_s cn52xx;
746 struct cvmx_npei_dmax_dbell_s cn52xxp1;
747 struct cvmx_npei_dmax_dbell_s cn56xx;
748 struct cvmx_npei_dmax_dbell_s cn56xxp1;
749};
750
751union cvmx_npei_dmax_ibuff_saddr {
752 uint64_t u64;
753 struct cvmx_npei_dmax_ibuff_saddr_s {
754 uint64_t reserved_37_63:27;
755 uint64_t idle:1;
756 uint64_t saddr:29;
757 uint64_t reserved_0_6:7;
758 } s;
759 struct cvmx_npei_dmax_ibuff_saddr_cn52xx {
760 uint64_t reserved_36_63:28;
761 uint64_t saddr:29;
762 uint64_t reserved_0_6:7;
763 } cn52xx;
764 struct cvmx_npei_dmax_ibuff_saddr_cn52xx cn52xxp1;
765 struct cvmx_npei_dmax_ibuff_saddr_s cn56xx;
766 struct cvmx_npei_dmax_ibuff_saddr_cn52xx cn56xxp1;
767};
768
769union cvmx_npei_dmax_naddr {
770 uint64_t u64;
771 struct cvmx_npei_dmax_naddr_s {
772 uint64_t reserved_36_63:28;
773 uint64_t addr:36;
774 } s;
775 struct cvmx_npei_dmax_naddr_s cn52xx;
776 struct cvmx_npei_dmax_naddr_s cn52xxp1;
777 struct cvmx_npei_dmax_naddr_s cn56xx;
778 struct cvmx_npei_dmax_naddr_s cn56xxp1;
779};
780
781union cvmx_npei_dma0_int_level {
782 uint64_t u64;
783 struct cvmx_npei_dma0_int_level_s {
784 uint64_t time:32;
785 uint64_t cnt:32;
786 } s;
787 struct cvmx_npei_dma0_int_level_s cn52xx;
788 struct cvmx_npei_dma0_int_level_s cn52xxp1;
789 struct cvmx_npei_dma0_int_level_s cn56xx;
790 struct cvmx_npei_dma0_int_level_s cn56xxp1;
791};
792
793union cvmx_npei_dma1_int_level {
794 uint64_t u64;
795 struct cvmx_npei_dma1_int_level_s {
796 uint64_t time:32;
797 uint64_t cnt:32;
798 } s;
799 struct cvmx_npei_dma1_int_level_s cn52xx;
800 struct cvmx_npei_dma1_int_level_s cn52xxp1;
801 struct cvmx_npei_dma1_int_level_s cn56xx;
802 struct cvmx_npei_dma1_int_level_s cn56xxp1;
803};
804
805union cvmx_npei_dma_cnts {
806 uint64_t u64;
807 struct cvmx_npei_dma_cnts_s {
808 uint64_t dma1:32;
809 uint64_t dma0:32;
810 } s;
811 struct cvmx_npei_dma_cnts_s cn52xx;
812 struct cvmx_npei_dma_cnts_s cn52xxp1;
813 struct cvmx_npei_dma_cnts_s cn56xx;
814 struct cvmx_npei_dma_cnts_s cn56xxp1;
815};
816
817union cvmx_npei_dma_control {
818 uint64_t u64;
819 struct cvmx_npei_dma_control_s {
820 uint64_t reserved_39_63:25;
821 uint64_t dma4_enb:1;
822 uint64_t dma3_enb:1;
823 uint64_t dma2_enb:1;
824 uint64_t dma1_enb:1;
825 uint64_t dma0_enb:1;
826 uint64_t b0_lend:1;
827 uint64_t dwb_denb:1;
828 uint64_t dwb_ichk:9;
829 uint64_t fpa_que:3;
830 uint64_t o_add1:1;
831 uint64_t o_ro:1;
832 uint64_t o_ns:1;
833 uint64_t o_es:2;
834 uint64_t o_mode:1;
835 uint64_t csize:14;
836 } s;
837 struct cvmx_npei_dma_control_s cn52xx;
838 struct cvmx_npei_dma_control_cn52xxp1 {
839 uint64_t reserved_38_63:26;
840 uint64_t dma3_enb:1;
841 uint64_t dma2_enb:1;
842 uint64_t dma1_enb:1;
843 uint64_t dma0_enb:1;
844 uint64_t b0_lend:1;
845 uint64_t dwb_denb:1;
846 uint64_t dwb_ichk:9;
847 uint64_t fpa_que:3;
848 uint64_t o_add1:1;
849 uint64_t o_ro:1;
850 uint64_t o_ns:1;
851 uint64_t o_es:2;
852 uint64_t o_mode:1;
853 uint64_t csize:14;
854 } cn52xxp1;
855 struct cvmx_npei_dma_control_s cn56xx;
856 struct cvmx_npei_dma_control_s cn56xxp1;
857};
858
859union cvmx_npei_int_a_enb {
860 uint64_t u64;
861 struct cvmx_npei_int_a_enb_s {
862 uint64_t reserved_10_63:54;
863 uint64_t pout_err:1;
864 uint64_t pin_bp:1;
865 uint64_t p1_rdlk:1;
866 uint64_t p0_rdlk:1;
867 uint64_t pgl_err:1;
868 uint64_t pdi_err:1;
869 uint64_t pop_err:1;
870 uint64_t pins_err:1;
871 uint64_t dma1_cpl:1;
872 uint64_t dma0_cpl:1;
873 } s;
874 struct cvmx_npei_int_a_enb_cn52xx {
875 uint64_t reserved_8_63:56;
876 uint64_t p1_rdlk:1;
877 uint64_t p0_rdlk:1;
878 uint64_t pgl_err:1;
879 uint64_t pdi_err:1;
880 uint64_t pop_err:1;
881 uint64_t pins_err:1;
882 uint64_t dma1_cpl:1;
883 uint64_t dma0_cpl:1;
884 } cn52xx;
885 struct cvmx_npei_int_a_enb_cn52xxp1 {
886 uint64_t reserved_2_63:62;
887 uint64_t dma1_cpl:1;
888 uint64_t dma0_cpl:1;
889 } cn52xxp1;
890 struct cvmx_npei_int_a_enb_s cn56xx;
891};
892
893union cvmx_npei_int_a_enb2 {
894 uint64_t u64;
895 struct cvmx_npei_int_a_enb2_s {
896 uint64_t reserved_10_63:54;
897 uint64_t pout_err:1;
898 uint64_t pin_bp:1;
899 uint64_t p1_rdlk:1;
900 uint64_t p0_rdlk:1;
901 uint64_t pgl_err:1;
902 uint64_t pdi_err:1;
903 uint64_t pop_err:1;
904 uint64_t pins_err:1;
905 uint64_t dma1_cpl:1;
906 uint64_t dma0_cpl:1;
907 } s;
908 struct cvmx_npei_int_a_enb2_cn52xx {
909 uint64_t reserved_8_63:56;
910 uint64_t p1_rdlk:1;
911 uint64_t p0_rdlk:1;
912 uint64_t pgl_err:1;
913 uint64_t pdi_err:1;
914 uint64_t pop_err:1;
915 uint64_t pins_err:1;
916 uint64_t reserved_0_1:2;
917 } cn52xx;
918 struct cvmx_npei_int_a_enb2_cn52xxp1 {
919 uint64_t reserved_2_63:62;
920 uint64_t dma1_cpl:1;
921 uint64_t dma0_cpl:1;
922 } cn52xxp1;
923 struct cvmx_npei_int_a_enb2_s cn56xx;
924};
925
926union cvmx_npei_int_a_sum {
927 uint64_t u64;
928 struct cvmx_npei_int_a_sum_s {
929 uint64_t reserved_10_63:54;
930 uint64_t pout_err:1;
931 uint64_t pin_bp:1;
932 uint64_t p1_rdlk:1;
933 uint64_t p0_rdlk:1;
934 uint64_t pgl_err:1;
935 uint64_t pdi_err:1;
936 uint64_t pop_err:1;
937 uint64_t pins_err:1;
938 uint64_t dma1_cpl:1;
939 uint64_t dma0_cpl:1;
940 } s;
941 struct cvmx_npei_int_a_sum_cn52xx {
942 uint64_t reserved_8_63:56;
943 uint64_t p1_rdlk:1;
944 uint64_t p0_rdlk:1;
945 uint64_t pgl_err:1;
946 uint64_t pdi_err:1;
947 uint64_t pop_err:1;
948 uint64_t pins_err:1;
949 uint64_t dma1_cpl:1;
950 uint64_t dma0_cpl:1;
951 } cn52xx;
952 struct cvmx_npei_int_a_sum_cn52xxp1 {
953 uint64_t reserved_2_63:62;
954 uint64_t dma1_cpl:1;
955 uint64_t dma0_cpl:1;
956 } cn52xxp1;
957 struct cvmx_npei_int_a_sum_s cn56xx;
958};
959
960union cvmx_npei_int_enb {
961 uint64_t u64;
962 struct cvmx_npei_int_enb_s {
963 uint64_t mio_inta:1;
964 uint64_t reserved_62_62:1;
965 uint64_t int_a:1;
966 uint64_t c1_ldwn:1;
967 uint64_t c0_ldwn:1;
968 uint64_t c1_exc:1;
969 uint64_t c0_exc:1;
970 uint64_t c1_up_wf:1;
971 uint64_t c0_up_wf:1;
972 uint64_t c1_un_wf:1;
973 uint64_t c0_un_wf:1;
974 uint64_t c1_un_bx:1;
975 uint64_t c1_un_wi:1;
976 uint64_t c1_un_b2:1;
977 uint64_t c1_un_b1:1;
978 uint64_t c1_un_b0:1;
979 uint64_t c1_up_bx:1;
980 uint64_t c1_up_wi:1;
981 uint64_t c1_up_b2:1;
982 uint64_t c1_up_b1:1;
983 uint64_t c1_up_b0:1;
984 uint64_t c0_un_bx:1;
985 uint64_t c0_un_wi:1;
986 uint64_t c0_un_b2:1;
987 uint64_t c0_un_b1:1;
988 uint64_t c0_un_b0:1;
989 uint64_t c0_up_bx:1;
990 uint64_t c0_up_wi:1;
991 uint64_t c0_up_b2:1;
992 uint64_t c0_up_b1:1;
993 uint64_t c0_up_b0:1;
994 uint64_t c1_hpint:1;
995 uint64_t c1_pmei:1;
996 uint64_t c1_wake:1;
997 uint64_t crs1_dr:1;
998 uint64_t c1_se:1;
999 uint64_t crs1_er:1;
1000 uint64_t c1_aeri:1;
1001 uint64_t c0_hpint:1;
1002 uint64_t c0_pmei:1;
1003 uint64_t c0_wake:1;
1004 uint64_t crs0_dr:1;
1005 uint64_t c0_se:1;
1006 uint64_t crs0_er:1;
1007 uint64_t c0_aeri:1;
1008 uint64_t ptime:1;
1009 uint64_t pcnt:1;
1010 uint64_t pidbof:1;
1011 uint64_t psldbof:1;
1012 uint64_t dtime1:1;
1013 uint64_t dtime0:1;
1014 uint64_t dcnt1:1;
1015 uint64_t dcnt0:1;
1016 uint64_t dma1fi:1;
1017 uint64_t dma0fi:1;
1018 uint64_t dma4dbo:1;
1019 uint64_t dma3dbo:1;
1020 uint64_t dma2dbo:1;
1021 uint64_t dma1dbo:1;
1022 uint64_t dma0dbo:1;
1023 uint64_t iob2big:1;
1024 uint64_t bar0_to:1;
1025 uint64_t rml_wto:1;
1026 uint64_t rml_rto:1;
1027 } s;
1028 struct cvmx_npei_int_enb_s cn52xx;
1029 struct cvmx_npei_int_enb_cn52xxp1 {
1030 uint64_t mio_inta:1;
1031 uint64_t reserved_62_62:1;
1032 uint64_t int_a:1;
1033 uint64_t c1_ldwn:1;
1034 uint64_t c0_ldwn:1;
1035 uint64_t c1_exc:1;
1036 uint64_t c0_exc:1;
1037 uint64_t c1_up_wf:1;
1038 uint64_t c0_up_wf:1;
1039 uint64_t c1_un_wf:1;
1040 uint64_t c0_un_wf:1;
1041 uint64_t c1_un_bx:1;
1042 uint64_t c1_un_wi:1;
1043 uint64_t c1_un_b2:1;
1044 uint64_t c1_un_b1:1;
1045 uint64_t c1_un_b0:1;
1046 uint64_t c1_up_bx:1;
1047 uint64_t c1_up_wi:1;
1048 uint64_t c1_up_b2:1;
1049 uint64_t c1_up_b1:1;
1050 uint64_t c1_up_b0:1;
1051 uint64_t c0_un_bx:1;
1052 uint64_t c0_un_wi:1;
1053 uint64_t c0_un_b2:1;
1054 uint64_t c0_un_b1:1;
1055 uint64_t c0_un_b0:1;
1056 uint64_t c0_up_bx:1;
1057 uint64_t c0_up_wi:1;
1058 uint64_t c0_up_b2:1;
1059 uint64_t c0_up_b1:1;
1060 uint64_t c0_up_b0:1;
1061 uint64_t c1_hpint:1;
1062 uint64_t c1_pmei:1;
1063 uint64_t c1_wake:1;
1064 uint64_t crs1_dr:1;
1065 uint64_t c1_se:1;
1066 uint64_t crs1_er:1;
1067 uint64_t c1_aeri:1;
1068 uint64_t c0_hpint:1;
1069 uint64_t c0_pmei:1;
1070 uint64_t c0_wake:1;
1071 uint64_t crs0_dr:1;
1072 uint64_t c0_se:1;
1073 uint64_t crs0_er:1;
1074 uint64_t c0_aeri:1;
1075 uint64_t ptime:1;
1076 uint64_t pcnt:1;
1077 uint64_t pidbof:1;
1078 uint64_t psldbof:1;
1079 uint64_t dtime1:1;
1080 uint64_t dtime0:1;
1081 uint64_t dcnt1:1;
1082 uint64_t dcnt0:1;
1083 uint64_t dma1fi:1;
1084 uint64_t dma0fi:1;
1085 uint64_t reserved_8_8:1;
1086 uint64_t dma3dbo:1;
1087 uint64_t dma2dbo:1;
1088 uint64_t dma1dbo:1;
1089 uint64_t dma0dbo:1;
1090 uint64_t iob2big:1;
1091 uint64_t bar0_to:1;
1092 uint64_t rml_wto:1;
1093 uint64_t rml_rto:1;
1094 } cn52xxp1;
1095 struct cvmx_npei_int_enb_s cn56xx;
1096 struct cvmx_npei_int_enb_cn56xxp1 {
1097 uint64_t mio_inta:1;
1098 uint64_t reserved_61_62:2;
1099 uint64_t c1_ldwn:1;
1100 uint64_t c0_ldwn:1;
1101 uint64_t c1_exc:1;
1102 uint64_t c0_exc:1;
1103 uint64_t c1_up_wf:1;
1104 uint64_t c0_up_wf:1;
1105 uint64_t c1_un_wf:1;
1106 uint64_t c0_un_wf:1;
1107 uint64_t c1_un_bx:1;
1108 uint64_t c1_un_wi:1;
1109 uint64_t c1_un_b2:1;
1110 uint64_t c1_un_b1:1;
1111 uint64_t c1_un_b0:1;
1112 uint64_t c1_up_bx:1;
1113 uint64_t c1_up_wi:1;
1114 uint64_t c1_up_b2:1;
1115 uint64_t c1_up_b1:1;
1116 uint64_t c1_up_b0:1;
1117 uint64_t c0_un_bx:1;
1118 uint64_t c0_un_wi:1;
1119 uint64_t c0_un_b2:1;
1120 uint64_t c0_un_b1:1;
1121 uint64_t c0_un_b0:1;
1122 uint64_t c0_up_bx:1;
1123 uint64_t c0_up_wi:1;
1124 uint64_t c0_up_b2:1;
1125 uint64_t c0_up_b1:1;
1126 uint64_t c0_up_b0:1;
1127 uint64_t c1_hpint:1;
1128 uint64_t c1_pmei:1;
1129 uint64_t c1_wake:1;
1130 uint64_t reserved_29_29:1;
1131 uint64_t c1_se:1;
1132 uint64_t reserved_27_27:1;
1133 uint64_t c1_aeri:1;
1134 uint64_t c0_hpint:1;
1135 uint64_t c0_pmei:1;
1136 uint64_t c0_wake:1;
1137 uint64_t reserved_22_22:1;
1138 uint64_t c0_se:1;
1139 uint64_t reserved_20_20:1;
1140 uint64_t c0_aeri:1;
1141 uint64_t ptime:1;
1142 uint64_t pcnt:1;
1143 uint64_t pidbof:1;
1144 uint64_t psldbof:1;
1145 uint64_t dtime1:1;
1146 uint64_t dtime0:1;
1147 uint64_t dcnt1:1;
1148 uint64_t dcnt0:1;
1149 uint64_t dma1fi:1;
1150 uint64_t dma0fi:1;
1151 uint64_t dma4dbo:1;
1152 uint64_t dma3dbo:1;
1153 uint64_t dma2dbo:1;
1154 uint64_t dma1dbo:1;
1155 uint64_t dma0dbo:1;
1156 uint64_t iob2big:1;
1157 uint64_t bar0_to:1;
1158 uint64_t rml_wto:1;
1159 uint64_t rml_rto:1;
1160 } cn56xxp1;
1161};
1162
1163union cvmx_npei_int_enb2 {
1164 uint64_t u64;
1165 struct cvmx_npei_int_enb2_s {
1166 uint64_t reserved_62_63:2;
1167 uint64_t int_a:1;
1168 uint64_t c1_ldwn:1;
1169 uint64_t c0_ldwn:1;
1170 uint64_t c1_exc:1;
1171 uint64_t c0_exc:1;
1172 uint64_t c1_up_wf:1;
1173 uint64_t c0_up_wf:1;
1174 uint64_t c1_un_wf:1;
1175 uint64_t c0_un_wf:1;
1176 uint64_t c1_un_bx:1;
1177 uint64_t c1_un_wi:1;
1178 uint64_t c1_un_b2:1;
1179 uint64_t c1_un_b1:1;
1180 uint64_t c1_un_b0:1;
1181 uint64_t c1_up_bx:1;
1182 uint64_t c1_up_wi:1;
1183 uint64_t c1_up_b2:1;
1184 uint64_t c1_up_b1:1;
1185 uint64_t c1_up_b0:1;
1186 uint64_t c0_un_bx:1;
1187 uint64_t c0_un_wi:1;
1188 uint64_t c0_un_b2:1;
1189 uint64_t c0_un_b1:1;
1190 uint64_t c0_un_b0:1;
1191 uint64_t c0_up_bx:1;
1192 uint64_t c0_up_wi:1;
1193 uint64_t c0_up_b2:1;
1194 uint64_t c0_up_b1:1;
1195 uint64_t c0_up_b0:1;
1196 uint64_t c1_hpint:1;
1197 uint64_t c1_pmei:1;
1198 uint64_t c1_wake:1;
1199 uint64_t crs1_dr:1;
1200 uint64_t c1_se:1;
1201 uint64_t crs1_er:1;
1202 uint64_t c1_aeri:1;
1203 uint64_t c0_hpint:1;
1204 uint64_t c0_pmei:1;
1205 uint64_t c0_wake:1;
1206 uint64_t crs0_dr:1;
1207 uint64_t c0_se:1;
1208 uint64_t crs0_er:1;
1209 uint64_t c0_aeri:1;
1210 uint64_t ptime:1;
1211 uint64_t pcnt:1;
1212 uint64_t pidbof:1;
1213 uint64_t psldbof:1;
1214 uint64_t dtime1:1;
1215 uint64_t dtime0:1;
1216 uint64_t dcnt1:1;
1217 uint64_t dcnt0:1;
1218 uint64_t dma1fi:1;
1219 uint64_t dma0fi:1;
1220 uint64_t dma4dbo:1;
1221 uint64_t dma3dbo:1;
1222 uint64_t dma2dbo:1;
1223 uint64_t dma1dbo:1;
1224 uint64_t dma0dbo:1;
1225 uint64_t iob2big:1;
1226 uint64_t bar0_to:1;
1227 uint64_t rml_wto:1;
1228 uint64_t rml_rto:1;
1229 } s;
1230 struct cvmx_npei_int_enb2_s cn52xx;
1231 struct cvmx_npei_int_enb2_cn52xxp1 {
1232 uint64_t reserved_62_63:2;
1233 uint64_t int_a:1;
1234 uint64_t c1_ldwn:1;
1235 uint64_t c0_ldwn:1;
1236 uint64_t c1_exc:1;
1237 uint64_t c0_exc:1;
1238 uint64_t c1_up_wf:1;
1239 uint64_t c0_up_wf:1;
1240 uint64_t c1_un_wf:1;
1241 uint64_t c0_un_wf:1;
1242 uint64_t c1_un_bx:1;
1243 uint64_t c1_un_wi:1;
1244 uint64_t c1_un_b2:1;
1245 uint64_t c1_un_b1:1;
1246 uint64_t c1_un_b0:1;
1247 uint64_t c1_up_bx:1;
1248 uint64_t c1_up_wi:1;
1249 uint64_t c1_up_b2:1;
1250 uint64_t c1_up_b1:1;
1251 uint64_t c1_up_b0:1;
1252 uint64_t c0_un_bx:1;
1253 uint64_t c0_un_wi:1;
1254 uint64_t c0_un_b2:1;
1255 uint64_t c0_un_b1:1;
1256 uint64_t c0_un_b0:1;
1257 uint64_t c0_up_bx:1;
1258 uint64_t c0_up_wi:1;
1259 uint64_t c0_up_b2:1;
1260 uint64_t c0_up_b1:1;
1261 uint64_t c0_up_b0:1;
1262 uint64_t c1_hpint:1;
1263 uint64_t c1_pmei:1;
1264 uint64_t c1_wake:1;
1265 uint64_t crs1_dr:1;
1266 uint64_t c1_se:1;
1267 uint64_t crs1_er:1;
1268 uint64_t c1_aeri:1;
1269 uint64_t c0_hpint:1;
1270 uint64_t c0_pmei:1;
1271 uint64_t c0_wake:1;
1272 uint64_t crs0_dr:1;
1273 uint64_t c0_se:1;
1274 uint64_t crs0_er:1;
1275 uint64_t c0_aeri:1;
1276 uint64_t ptime:1;
1277 uint64_t pcnt:1;
1278 uint64_t pidbof:1;
1279 uint64_t psldbof:1;
1280 uint64_t dtime1:1;
1281 uint64_t dtime0:1;
1282 uint64_t dcnt1:1;
1283 uint64_t dcnt0:1;
1284 uint64_t dma1fi:1;
1285 uint64_t dma0fi:1;
1286 uint64_t reserved_8_8:1;
1287 uint64_t dma3dbo:1;
1288 uint64_t dma2dbo:1;
1289 uint64_t dma1dbo:1;
1290 uint64_t dma0dbo:1;
1291 uint64_t iob2big:1;
1292 uint64_t bar0_to:1;
1293 uint64_t rml_wto:1;
1294 uint64_t rml_rto:1;
1295 } cn52xxp1;
1296 struct cvmx_npei_int_enb2_s cn56xx;
1297 struct cvmx_npei_int_enb2_cn56xxp1 {
1298 uint64_t reserved_61_63:3;
1299 uint64_t c1_ldwn:1;
1300 uint64_t c0_ldwn:1;
1301 uint64_t c1_exc:1;
1302 uint64_t c0_exc:1;
1303 uint64_t c1_up_wf:1;
1304 uint64_t c0_up_wf:1;
1305 uint64_t c1_un_wf:1;
1306 uint64_t c0_un_wf:1;
1307 uint64_t c1_un_bx:1;
1308 uint64_t c1_un_wi:1;
1309 uint64_t c1_un_b2:1;
1310 uint64_t c1_un_b1:1;
1311 uint64_t c1_un_b0:1;
1312 uint64_t c1_up_bx:1;
1313 uint64_t c1_up_wi:1;
1314 uint64_t c1_up_b2:1;
1315 uint64_t c1_up_b1:1;
1316 uint64_t c1_up_b0:1;
1317 uint64_t c0_un_bx:1;
1318 uint64_t c0_un_wi:1;
1319 uint64_t c0_un_b2:1;
1320 uint64_t c0_un_b1:1;
1321 uint64_t c0_un_b0:1;
1322 uint64_t c0_up_bx:1;
1323 uint64_t c0_up_wi:1;
1324 uint64_t c0_up_b2:1;
1325 uint64_t c0_up_b1:1;
1326 uint64_t c0_up_b0:1;
1327 uint64_t c1_hpint:1;
1328 uint64_t c1_pmei:1;
1329 uint64_t c1_wake:1;
1330 uint64_t reserved_29_29:1;
1331 uint64_t c1_se:1;
1332 uint64_t reserved_27_27:1;
1333 uint64_t c1_aeri:1;
1334 uint64_t c0_hpint:1;
1335 uint64_t c0_pmei:1;
1336 uint64_t c0_wake:1;
1337 uint64_t reserved_22_22:1;
1338 uint64_t c0_se:1;
1339 uint64_t reserved_20_20:1;
1340 uint64_t c0_aeri:1;
1341 uint64_t ptime:1;
1342 uint64_t pcnt:1;
1343 uint64_t pidbof:1;
1344 uint64_t psldbof:1;
1345 uint64_t dtime1:1;
1346 uint64_t dtime0:1;
1347 uint64_t dcnt1:1;
1348 uint64_t dcnt0:1;
1349 uint64_t dma1fi:1;
1350 uint64_t dma0fi:1;
1351 uint64_t dma4dbo:1;
1352 uint64_t dma3dbo:1;
1353 uint64_t dma2dbo:1;
1354 uint64_t dma1dbo:1;
1355 uint64_t dma0dbo:1;
1356 uint64_t iob2big:1;
1357 uint64_t bar0_to:1;
1358 uint64_t rml_wto:1;
1359 uint64_t rml_rto:1;
1360 } cn56xxp1;
1361};
1362
1363union cvmx_npei_int_info {
1364 uint64_t u64;
1365 struct cvmx_npei_int_info_s {
1366 uint64_t reserved_12_63:52;
1367 uint64_t pidbof:6;
1368 uint64_t psldbof:6;
1369 } s;
1370 struct cvmx_npei_int_info_s cn52xx;
1371 struct cvmx_npei_int_info_s cn56xx;
1372 struct cvmx_npei_int_info_s cn56xxp1;
1373};
1374
1375union cvmx_npei_int_sum {
1376 uint64_t u64;
1377 struct cvmx_npei_int_sum_s {
1378 uint64_t mio_inta:1;
1379 uint64_t reserved_62_62:1;
1380 uint64_t int_a:1;
1381 uint64_t c1_ldwn:1;
1382 uint64_t c0_ldwn:1;
1383 uint64_t c1_exc:1;
1384 uint64_t c0_exc:1;
1385 uint64_t c1_up_wf:1;
1386 uint64_t c0_up_wf:1;
1387 uint64_t c1_un_wf:1;
1388 uint64_t c0_un_wf:1;
1389 uint64_t c1_un_bx:1;
1390 uint64_t c1_un_wi:1;
1391 uint64_t c1_un_b2:1;
1392 uint64_t c1_un_b1:1;
1393 uint64_t c1_un_b0:1;
1394 uint64_t c1_up_bx:1;
1395 uint64_t c1_up_wi:1;
1396 uint64_t c1_up_b2:1;
1397 uint64_t c1_up_b1:1;
1398 uint64_t c1_up_b0:1;
1399 uint64_t c0_un_bx:1;
1400 uint64_t c0_un_wi:1;
1401 uint64_t c0_un_b2:1;
1402 uint64_t c0_un_b1:1;
1403 uint64_t c0_un_b0:1;
1404 uint64_t c0_up_bx:1;
1405 uint64_t c0_up_wi:1;
1406 uint64_t c0_up_b2:1;
1407 uint64_t c0_up_b1:1;
1408 uint64_t c0_up_b0:1;
1409 uint64_t c1_hpint:1;
1410 uint64_t c1_pmei:1;
1411 uint64_t c1_wake:1;
1412 uint64_t crs1_dr:1;
1413 uint64_t c1_se:1;
1414 uint64_t crs1_er:1;
1415 uint64_t c1_aeri:1;
1416 uint64_t c0_hpint:1;
1417 uint64_t c0_pmei:1;
1418 uint64_t c0_wake:1;
1419 uint64_t crs0_dr:1;
1420 uint64_t c0_se:1;
1421 uint64_t crs0_er:1;
1422 uint64_t c0_aeri:1;
1423 uint64_t ptime:1;
1424 uint64_t pcnt:1;
1425 uint64_t pidbof:1;
1426 uint64_t psldbof:1;
1427 uint64_t dtime1:1;
1428 uint64_t dtime0:1;
1429 uint64_t dcnt1:1;
1430 uint64_t dcnt0:1;
1431 uint64_t dma1fi:1;
1432 uint64_t dma0fi:1;
1433 uint64_t dma4dbo:1;
1434 uint64_t dma3dbo:1;
1435 uint64_t dma2dbo:1;
1436 uint64_t dma1dbo:1;
1437 uint64_t dma0dbo:1;
1438 uint64_t iob2big:1;
1439 uint64_t bar0_to:1;
1440 uint64_t rml_wto:1;
1441 uint64_t rml_rto:1;
1442 } s;
1443 struct cvmx_npei_int_sum_s cn52xx;
1444 struct cvmx_npei_int_sum_cn52xxp1 {
1445 uint64_t mio_inta:1;
1446 uint64_t reserved_62_62:1;
1447 uint64_t int_a:1;
1448 uint64_t c1_ldwn:1;
1449 uint64_t c0_ldwn:1;
1450 uint64_t c1_exc:1;
1451 uint64_t c0_exc:1;
1452 uint64_t c1_up_wf:1;
1453 uint64_t c0_up_wf:1;
1454 uint64_t c1_un_wf:1;
1455 uint64_t c0_un_wf:1;
1456 uint64_t c1_un_bx:1;
1457 uint64_t c1_un_wi:1;
1458 uint64_t c1_un_b2:1;
1459 uint64_t c1_un_b1:1;
1460 uint64_t c1_un_b0:1;
1461 uint64_t c1_up_bx:1;
1462 uint64_t c1_up_wi:1;
1463 uint64_t c1_up_b2:1;
1464 uint64_t c1_up_b1:1;
1465 uint64_t c1_up_b0:1;
1466 uint64_t c0_un_bx:1;
1467 uint64_t c0_un_wi:1;
1468 uint64_t c0_un_b2:1;
1469 uint64_t c0_un_b1:1;
1470 uint64_t c0_un_b0:1;
1471 uint64_t c0_up_bx:1;
1472 uint64_t c0_up_wi:1;
1473 uint64_t c0_up_b2:1;
1474 uint64_t c0_up_b1:1;
1475 uint64_t c0_up_b0:1;
1476 uint64_t c1_hpint:1;
1477 uint64_t c1_pmei:1;
1478 uint64_t c1_wake:1;
1479 uint64_t crs1_dr:1;
1480 uint64_t c1_se:1;
1481 uint64_t crs1_er:1;
1482 uint64_t c1_aeri:1;
1483 uint64_t c0_hpint:1;
1484 uint64_t c0_pmei:1;
1485 uint64_t c0_wake:1;
1486 uint64_t crs0_dr:1;
1487 uint64_t c0_se:1;
1488 uint64_t crs0_er:1;
1489 uint64_t c0_aeri:1;
1490 uint64_t reserved_15_18:4;
1491 uint64_t dtime1:1;
1492 uint64_t dtime0:1;
1493 uint64_t dcnt1:1;
1494 uint64_t dcnt0:1;
1495 uint64_t dma1fi:1;
1496 uint64_t dma0fi:1;
1497 uint64_t reserved_8_8:1;
1498 uint64_t dma3dbo:1;
1499 uint64_t dma2dbo:1;
1500 uint64_t dma1dbo:1;
1501 uint64_t dma0dbo:1;
1502 uint64_t iob2big:1;
1503 uint64_t bar0_to:1;
1504 uint64_t rml_wto:1;
1505 uint64_t rml_rto:1;
1506 } cn52xxp1;
1507 struct cvmx_npei_int_sum_s cn56xx;
1508 struct cvmx_npei_int_sum_cn56xxp1 {
1509 uint64_t mio_inta:1;
1510 uint64_t reserved_61_62:2;
1511 uint64_t c1_ldwn:1;
1512 uint64_t c0_ldwn:1;
1513 uint64_t c1_exc:1;
1514 uint64_t c0_exc:1;
1515 uint64_t c1_up_wf:1;
1516 uint64_t c0_up_wf:1;
1517 uint64_t c1_un_wf:1;
1518 uint64_t c0_un_wf:1;
1519 uint64_t c1_un_bx:1;
1520 uint64_t c1_un_wi:1;
1521 uint64_t c1_un_b2:1;
1522 uint64_t c1_un_b1:1;
1523 uint64_t c1_un_b0:1;
1524 uint64_t c1_up_bx:1;
1525 uint64_t c1_up_wi:1;
1526 uint64_t c1_up_b2:1;
1527 uint64_t c1_up_b1:1;
1528 uint64_t c1_up_b0:1;
1529 uint64_t c0_un_bx:1;
1530 uint64_t c0_un_wi:1;
1531 uint64_t c0_un_b2:1;
1532 uint64_t c0_un_b1:1;
1533 uint64_t c0_un_b0:1;
1534 uint64_t c0_up_bx:1;
1535 uint64_t c0_up_wi:1;
1536 uint64_t c0_up_b2:1;
1537 uint64_t c0_up_b1:1;
1538 uint64_t c0_up_b0:1;
1539 uint64_t c1_hpint:1;
1540 uint64_t c1_pmei:1;
1541 uint64_t c1_wake:1;
1542 uint64_t reserved_29_29:1;
1543 uint64_t c1_se:1;
1544 uint64_t reserved_27_27:1;
1545 uint64_t c1_aeri:1;
1546 uint64_t c0_hpint:1;
1547 uint64_t c0_pmei:1;
1548 uint64_t c0_wake:1;
1549 uint64_t reserved_22_22:1;
1550 uint64_t c0_se:1;
1551 uint64_t reserved_20_20:1;
1552 uint64_t c0_aeri:1;
1553 uint64_t ptime:1;
1554 uint64_t pcnt:1;
1555 uint64_t pidbof:1;
1556 uint64_t psldbof:1;
1557 uint64_t dtime1:1;
1558 uint64_t dtime0:1;
1559 uint64_t dcnt1:1;
1560 uint64_t dcnt0:1;
1561 uint64_t dma1fi:1;
1562 uint64_t dma0fi:1;
1563 uint64_t dma4dbo:1;
1564 uint64_t dma3dbo:1;
1565 uint64_t dma2dbo:1;
1566 uint64_t dma1dbo:1;
1567 uint64_t dma0dbo:1;
1568 uint64_t iob2big:1;
1569 uint64_t bar0_to:1;
1570 uint64_t rml_wto:1;
1571 uint64_t rml_rto:1;
1572 } cn56xxp1;
1573};
1574
1575union cvmx_npei_int_sum2 {
1576 uint64_t u64;
1577 struct cvmx_npei_int_sum2_s {
1578 uint64_t mio_inta:1;
1579 uint64_t reserved_62_62:1;
1580 uint64_t int_a:1;
1581 uint64_t c1_ldwn:1;
1582 uint64_t c0_ldwn:1;
1583 uint64_t c1_exc:1;
1584 uint64_t c0_exc:1;
1585 uint64_t c1_up_wf:1;
1586 uint64_t c0_up_wf:1;
1587 uint64_t c1_un_wf:1;
1588 uint64_t c0_un_wf:1;
1589 uint64_t c1_un_bx:1;
1590 uint64_t c1_un_wi:1;
1591 uint64_t c1_un_b2:1;
1592 uint64_t c1_un_b1:1;
1593 uint64_t c1_un_b0:1;
1594 uint64_t c1_up_bx:1;
1595 uint64_t c1_up_wi:1;
1596 uint64_t c1_up_b2:1;
1597 uint64_t c1_up_b1:1;
1598 uint64_t c1_up_b0:1;
1599 uint64_t c0_un_bx:1;
1600 uint64_t c0_un_wi:1;
1601 uint64_t c0_un_b2:1;
1602 uint64_t c0_un_b1:1;
1603 uint64_t c0_un_b0:1;
1604 uint64_t c0_up_bx:1;
1605 uint64_t c0_up_wi:1;
1606 uint64_t c0_up_b2:1;
1607 uint64_t c0_up_b1:1;
1608 uint64_t c0_up_b0:1;
1609 uint64_t c1_hpint:1;
1610 uint64_t c1_pmei:1;
1611 uint64_t c1_wake:1;
1612 uint64_t crs1_dr:1;
1613 uint64_t c1_se:1;
1614 uint64_t crs1_er:1;
1615 uint64_t c1_aeri:1;
1616 uint64_t c0_hpint:1;
1617 uint64_t c0_pmei:1;
1618 uint64_t c0_wake:1;
1619 uint64_t crs0_dr:1;
1620 uint64_t c0_se:1;
1621 uint64_t crs0_er:1;
1622 uint64_t c0_aeri:1;
1623 uint64_t reserved_15_18:4;
1624 uint64_t dtime1:1;
1625 uint64_t dtime0:1;
1626 uint64_t dcnt1:1;
1627 uint64_t dcnt0:1;
1628 uint64_t dma1fi:1;
1629 uint64_t dma0fi:1;
1630 uint64_t reserved_8_8:1;
1631 uint64_t dma3dbo:1;
1632 uint64_t dma2dbo:1;
1633 uint64_t dma1dbo:1;
1634 uint64_t dma0dbo:1;
1635 uint64_t iob2big:1;
1636 uint64_t bar0_to:1;
1637 uint64_t rml_wto:1;
1638 uint64_t rml_rto:1;
1639 } s;
1640 struct cvmx_npei_int_sum2_s cn52xx;
1641 struct cvmx_npei_int_sum2_s cn52xxp1;
1642 struct cvmx_npei_int_sum2_s cn56xx;
1643};
1644
1645union cvmx_npei_last_win_rdata0 {
1646 uint64_t u64;
1647 struct cvmx_npei_last_win_rdata0_s {
1648 uint64_t data:64;
1649 } s;
1650 struct cvmx_npei_last_win_rdata0_s cn52xx;
1651 struct cvmx_npei_last_win_rdata0_s cn52xxp1;
1652 struct cvmx_npei_last_win_rdata0_s cn56xx;
1653 struct cvmx_npei_last_win_rdata0_s cn56xxp1;
1654};
1655
1656union cvmx_npei_last_win_rdata1 {
1657 uint64_t u64;
1658 struct cvmx_npei_last_win_rdata1_s {
1659 uint64_t data:64;
1660 } s;
1661 struct cvmx_npei_last_win_rdata1_s cn52xx;
1662 struct cvmx_npei_last_win_rdata1_s cn52xxp1;
1663 struct cvmx_npei_last_win_rdata1_s cn56xx;
1664 struct cvmx_npei_last_win_rdata1_s cn56xxp1;
1665};
1666
1667union cvmx_npei_mem_access_ctl {
1668 uint64_t u64;
1669 struct cvmx_npei_mem_access_ctl_s {
1670 uint64_t reserved_14_63:50;
1671 uint64_t max_word:4;
1672 uint64_t timer:10;
1673 } s;
1674 struct cvmx_npei_mem_access_ctl_s cn52xx;
1675 struct cvmx_npei_mem_access_ctl_s cn52xxp1;
1676 struct cvmx_npei_mem_access_ctl_s cn56xx;
1677 struct cvmx_npei_mem_access_ctl_s cn56xxp1;
1678};
1679
1680union cvmx_npei_mem_access_subidx {
1681 uint64_t u64;
1682 struct cvmx_npei_mem_access_subidx_s {
1683 uint64_t reserved_42_63:22;
1684 uint64_t zero:1;
1685 uint64_t port:2;
1686 uint64_t nmerge:1;
1687 uint64_t esr:2;
1688 uint64_t esw:2;
1689 uint64_t nsr:1;
1690 uint64_t nsw:1;
1691 uint64_t ror:1;
1692 uint64_t row:1;
1693 uint64_t ba:30;
1694 } s;
1695 struct cvmx_npei_mem_access_subidx_s cn52xx;
1696 struct cvmx_npei_mem_access_subidx_s cn52xxp1;
1697 struct cvmx_npei_mem_access_subidx_s cn56xx;
1698 struct cvmx_npei_mem_access_subidx_s cn56xxp1;
1699};
1700
1701union cvmx_npei_msi_enb0 {
1702 uint64_t u64;
1703 struct cvmx_npei_msi_enb0_s {
1704 uint64_t enb:64;
1705 } s;
1706 struct cvmx_npei_msi_enb0_s cn52xx;
1707 struct cvmx_npei_msi_enb0_s cn52xxp1;
1708 struct cvmx_npei_msi_enb0_s cn56xx;
1709 struct cvmx_npei_msi_enb0_s cn56xxp1;
1710};
1711
1712union cvmx_npei_msi_enb1 {
1713 uint64_t u64;
1714 struct cvmx_npei_msi_enb1_s {
1715 uint64_t enb:64;
1716 } s;
1717 struct cvmx_npei_msi_enb1_s cn52xx;
1718 struct cvmx_npei_msi_enb1_s cn52xxp1;
1719 struct cvmx_npei_msi_enb1_s cn56xx;
1720 struct cvmx_npei_msi_enb1_s cn56xxp1;
1721};
1722
1723union cvmx_npei_msi_enb2 {
1724 uint64_t u64;
1725 struct cvmx_npei_msi_enb2_s {
1726 uint64_t enb:64;
1727 } s;
1728 struct cvmx_npei_msi_enb2_s cn52xx;
1729 struct cvmx_npei_msi_enb2_s cn52xxp1;
1730 struct cvmx_npei_msi_enb2_s cn56xx;
1731 struct cvmx_npei_msi_enb2_s cn56xxp1;
1732};
1733
1734union cvmx_npei_msi_enb3 {
1735 uint64_t u64;
1736 struct cvmx_npei_msi_enb3_s {
1737 uint64_t enb:64;
1738 } s;
1739 struct cvmx_npei_msi_enb3_s cn52xx;
1740 struct cvmx_npei_msi_enb3_s cn52xxp1;
1741 struct cvmx_npei_msi_enb3_s cn56xx;
1742 struct cvmx_npei_msi_enb3_s cn56xxp1;
1743};
1744
1745union cvmx_npei_msi_rcv0 {
1746 uint64_t u64;
1747 struct cvmx_npei_msi_rcv0_s {
1748 uint64_t intr:64;
1749 } s;
1750 struct cvmx_npei_msi_rcv0_s cn52xx;
1751 struct cvmx_npei_msi_rcv0_s cn52xxp1;
1752 struct cvmx_npei_msi_rcv0_s cn56xx;
1753 struct cvmx_npei_msi_rcv0_s cn56xxp1;
1754};
1755
1756union cvmx_npei_msi_rcv1 {
1757 uint64_t u64;
1758 struct cvmx_npei_msi_rcv1_s {
1759 uint64_t intr:64;
1760 } s;
1761 struct cvmx_npei_msi_rcv1_s cn52xx;
1762 struct cvmx_npei_msi_rcv1_s cn52xxp1;
1763 struct cvmx_npei_msi_rcv1_s cn56xx;
1764 struct cvmx_npei_msi_rcv1_s cn56xxp1;
1765};
1766
1767union cvmx_npei_msi_rcv2 {
1768 uint64_t u64;
1769 struct cvmx_npei_msi_rcv2_s {
1770 uint64_t intr:64;
1771 } s;
1772 struct cvmx_npei_msi_rcv2_s cn52xx;
1773 struct cvmx_npei_msi_rcv2_s cn52xxp1;
1774 struct cvmx_npei_msi_rcv2_s cn56xx;
1775 struct cvmx_npei_msi_rcv2_s cn56xxp1;
1776};
1777
1778union cvmx_npei_msi_rcv3 {
1779 uint64_t u64;
1780 struct cvmx_npei_msi_rcv3_s {
1781 uint64_t intr:64;
1782 } s;
1783 struct cvmx_npei_msi_rcv3_s cn52xx;
1784 struct cvmx_npei_msi_rcv3_s cn52xxp1;
1785 struct cvmx_npei_msi_rcv3_s cn56xx;
1786 struct cvmx_npei_msi_rcv3_s cn56xxp1;
1787};
1788
1789union cvmx_npei_msi_rd_map {
1790 uint64_t u64;
1791 struct cvmx_npei_msi_rd_map_s {
1792 uint64_t reserved_16_63:48;
1793 uint64_t rd_int:8;
1794 uint64_t msi_int:8;
1795 } s;
1796 struct cvmx_npei_msi_rd_map_s cn52xx;
1797 struct cvmx_npei_msi_rd_map_s cn52xxp1;
1798 struct cvmx_npei_msi_rd_map_s cn56xx;
1799 struct cvmx_npei_msi_rd_map_s cn56xxp1;
1800};
1801
1802union cvmx_npei_msi_w1c_enb0 {
1803 uint64_t u64;
1804 struct cvmx_npei_msi_w1c_enb0_s {
1805 uint64_t clr:64;
1806 } s;
1807 struct cvmx_npei_msi_w1c_enb0_s cn52xx;
1808 struct cvmx_npei_msi_w1c_enb0_s cn56xx;
1809};
1810
1811union cvmx_npei_msi_w1c_enb1 {
1812 uint64_t u64;
1813 struct cvmx_npei_msi_w1c_enb1_s {
1814 uint64_t clr:64;
1815 } s;
1816 struct cvmx_npei_msi_w1c_enb1_s cn52xx;
1817 struct cvmx_npei_msi_w1c_enb1_s cn56xx;
1818};
1819
1820union cvmx_npei_msi_w1c_enb2 {
1821 uint64_t u64;
1822 struct cvmx_npei_msi_w1c_enb2_s {
1823 uint64_t clr:64;
1824 } s;
1825 struct cvmx_npei_msi_w1c_enb2_s cn52xx;
1826 struct cvmx_npei_msi_w1c_enb2_s cn56xx;
1827};
1828
1829union cvmx_npei_msi_w1c_enb3 {
1830 uint64_t u64;
1831 struct cvmx_npei_msi_w1c_enb3_s {
1832 uint64_t clr:64;
1833 } s;
1834 struct cvmx_npei_msi_w1c_enb3_s cn52xx;
1835 struct cvmx_npei_msi_w1c_enb3_s cn56xx;
1836};
1837
1838union cvmx_npei_msi_w1s_enb0 {
1839 uint64_t u64;
1840 struct cvmx_npei_msi_w1s_enb0_s {
1841 uint64_t set:64;
1842 } s;
1843 struct cvmx_npei_msi_w1s_enb0_s cn52xx;
1844 struct cvmx_npei_msi_w1s_enb0_s cn56xx;
1845};
1846
1847union cvmx_npei_msi_w1s_enb1 {
1848 uint64_t u64;
1849 struct cvmx_npei_msi_w1s_enb1_s {
1850 uint64_t set:64;
1851 } s;
1852 struct cvmx_npei_msi_w1s_enb1_s cn52xx;
1853 struct cvmx_npei_msi_w1s_enb1_s cn56xx;
1854};
1855
1856union cvmx_npei_msi_w1s_enb2 {
1857 uint64_t u64;
1858 struct cvmx_npei_msi_w1s_enb2_s {
1859 uint64_t set:64;
1860 } s;
1861 struct cvmx_npei_msi_w1s_enb2_s cn52xx;
1862 struct cvmx_npei_msi_w1s_enb2_s cn56xx;
1863};
1864
1865union cvmx_npei_msi_w1s_enb3 {
1866 uint64_t u64;
1867 struct cvmx_npei_msi_w1s_enb3_s {
1868 uint64_t set:64;
1869 } s;
1870 struct cvmx_npei_msi_w1s_enb3_s cn52xx;
1871 struct cvmx_npei_msi_w1s_enb3_s cn56xx;
1872};
1873
1874union cvmx_npei_msi_wr_map {
1875 uint64_t u64;
1876 struct cvmx_npei_msi_wr_map_s {
1877 uint64_t reserved_16_63:48;
1878 uint64_t ciu_int:8;
1879 uint64_t msi_int:8;
1880 } s;
1881 struct cvmx_npei_msi_wr_map_s cn52xx;
1882 struct cvmx_npei_msi_wr_map_s cn52xxp1;
1883 struct cvmx_npei_msi_wr_map_s cn56xx;
1884 struct cvmx_npei_msi_wr_map_s cn56xxp1;
1885};
1886
1887union cvmx_npei_pcie_credit_cnt {
1888 uint64_t u64;
1889 struct cvmx_npei_pcie_credit_cnt_s {
1890 uint64_t reserved_48_63:16;
1891 uint64_t p1_ccnt:8;
1892 uint64_t p1_ncnt:8;
1893 uint64_t p1_pcnt:8;
1894 uint64_t p0_ccnt:8;
1895 uint64_t p0_ncnt:8;
1896 uint64_t p0_pcnt:8;
1897 } s;
1898 struct cvmx_npei_pcie_credit_cnt_s cn52xx;
1899 struct cvmx_npei_pcie_credit_cnt_s cn56xx;
1900};
1901
1902union cvmx_npei_pcie_msi_rcv {
1903 uint64_t u64;
1904 struct cvmx_npei_pcie_msi_rcv_s {
1905 uint64_t reserved_8_63:56;
1906 uint64_t intr:8;
1907 } s;
1908 struct cvmx_npei_pcie_msi_rcv_s cn52xx;
1909 struct cvmx_npei_pcie_msi_rcv_s cn52xxp1;
1910 struct cvmx_npei_pcie_msi_rcv_s cn56xx;
1911 struct cvmx_npei_pcie_msi_rcv_s cn56xxp1;
1912};
1913
1914union cvmx_npei_pcie_msi_rcv_b1 {
1915 uint64_t u64;
1916 struct cvmx_npei_pcie_msi_rcv_b1_s {
1917 uint64_t reserved_16_63:48;
1918 uint64_t intr:8;
1919 uint64_t reserved_0_7:8;
1920 } s;
1921 struct cvmx_npei_pcie_msi_rcv_b1_s cn52xx;
1922 struct cvmx_npei_pcie_msi_rcv_b1_s cn52xxp1;
1923 struct cvmx_npei_pcie_msi_rcv_b1_s cn56xx;
1924 struct cvmx_npei_pcie_msi_rcv_b1_s cn56xxp1;
1925};
1926
1927union cvmx_npei_pcie_msi_rcv_b2 {
1928 uint64_t u64;
1929 struct cvmx_npei_pcie_msi_rcv_b2_s {
1930 uint64_t reserved_24_63:40;
1931 uint64_t intr:8;
1932 uint64_t reserved_0_15:16;
1933 } s;
1934 struct cvmx_npei_pcie_msi_rcv_b2_s cn52xx;
1935 struct cvmx_npei_pcie_msi_rcv_b2_s cn52xxp1;
1936 struct cvmx_npei_pcie_msi_rcv_b2_s cn56xx;
1937 struct cvmx_npei_pcie_msi_rcv_b2_s cn56xxp1;
1938};
1939
1940union cvmx_npei_pcie_msi_rcv_b3 {
1941 uint64_t u64;
1942 struct cvmx_npei_pcie_msi_rcv_b3_s {
1943 uint64_t reserved_32_63:32;
1944 uint64_t intr:8;
1945 uint64_t reserved_0_23:24;
1946 } s;
1947 struct cvmx_npei_pcie_msi_rcv_b3_s cn52xx;
1948 struct cvmx_npei_pcie_msi_rcv_b3_s cn52xxp1;
1949 struct cvmx_npei_pcie_msi_rcv_b3_s cn56xx;
1950 struct cvmx_npei_pcie_msi_rcv_b3_s cn56xxp1;
1951};
1952
1953union cvmx_npei_pktx_cnts {
1954 uint64_t u64;
1955 struct cvmx_npei_pktx_cnts_s {
1956 uint64_t reserved_54_63:10;
1957 uint64_t timer:22;
1958 uint64_t cnt:32;
1959 } s;
1960 struct cvmx_npei_pktx_cnts_s cn52xx;
1961 struct cvmx_npei_pktx_cnts_s cn56xx;
1962 struct cvmx_npei_pktx_cnts_s cn56xxp1;
1963};
1964
1965union cvmx_npei_pktx_in_bp {
1966 uint64_t u64;
1967 struct cvmx_npei_pktx_in_bp_s {
1968 uint64_t wmark:32;
1969 uint64_t cnt:32;
1970 } s;
1971 struct cvmx_npei_pktx_in_bp_s cn52xx;
1972 struct cvmx_npei_pktx_in_bp_s cn56xx;
1973 struct cvmx_npei_pktx_in_bp_s cn56xxp1;
1974};
1975
1976union cvmx_npei_pktx_instr_baddr {
1977 uint64_t u64;
1978 struct cvmx_npei_pktx_instr_baddr_s {
1979 uint64_t addr:61;
1980 uint64_t reserved_0_2:3;
1981 } s;
1982 struct cvmx_npei_pktx_instr_baddr_s cn52xx;
1983 struct cvmx_npei_pktx_instr_baddr_s cn56xx;
1984 struct cvmx_npei_pktx_instr_baddr_s cn56xxp1;
1985};
1986
1987union cvmx_npei_pktx_instr_baoff_dbell {
1988 uint64_t u64;
1989 struct cvmx_npei_pktx_instr_baoff_dbell_s {
1990 uint64_t aoff:32;
1991 uint64_t dbell:32;
1992 } s;
1993 struct cvmx_npei_pktx_instr_baoff_dbell_s cn52xx;
1994 struct cvmx_npei_pktx_instr_baoff_dbell_s cn56xx;
1995 struct cvmx_npei_pktx_instr_baoff_dbell_s cn56xxp1;
1996};
1997
1998union cvmx_npei_pktx_instr_fifo_rsize {
1999 uint64_t u64;
2000 struct cvmx_npei_pktx_instr_fifo_rsize_s {
2001 uint64_t max:9;
2002 uint64_t rrp:9;
2003 uint64_t wrp:9;
2004 uint64_t fcnt:5;
2005 uint64_t rsize:32;
2006 } s;
2007 struct cvmx_npei_pktx_instr_fifo_rsize_s cn52xx;
2008 struct cvmx_npei_pktx_instr_fifo_rsize_s cn56xx;
2009 struct cvmx_npei_pktx_instr_fifo_rsize_s cn56xxp1;
2010};
2011
2012union cvmx_npei_pktx_instr_header {
2013 uint64_t u64;
2014 struct cvmx_npei_pktx_instr_header_s {
2015 uint64_t reserved_44_63:20;
2016 uint64_t pbp:1;
2017 uint64_t rsv_f:5;
2018 uint64_t rparmode:2;
2019 uint64_t rsv_e:1;
2020 uint64_t rskp_len:7;
2021 uint64_t rsv_d:6;
2022 uint64_t use_ihdr:1;
2023 uint64_t rsv_c:5;
2024 uint64_t par_mode:2;
2025 uint64_t rsv_b:1;
2026 uint64_t skp_len:7;
2027 uint64_t rsv_a:6;
2028 } s;
2029 struct cvmx_npei_pktx_instr_header_s cn52xx;
2030 struct cvmx_npei_pktx_instr_header_s cn56xx;
2031 struct cvmx_npei_pktx_instr_header_s cn56xxp1;
2032};
2033
2034union cvmx_npei_pktx_slist_baddr {
2035 uint64_t u64;
2036 struct cvmx_npei_pktx_slist_baddr_s {
2037 uint64_t addr:60;
2038 uint64_t reserved_0_3:4;
2039 } s;
2040 struct cvmx_npei_pktx_slist_baddr_s cn52xx;
2041 struct cvmx_npei_pktx_slist_baddr_s cn56xx;
2042 struct cvmx_npei_pktx_slist_baddr_s cn56xxp1;
2043};
2044
2045union cvmx_npei_pktx_slist_baoff_dbell {
2046 uint64_t u64;
2047 struct cvmx_npei_pktx_slist_baoff_dbell_s {
2048 uint64_t aoff:32;
2049 uint64_t dbell:32;
2050 } s;
2051 struct cvmx_npei_pktx_slist_baoff_dbell_s cn52xx;
2052 struct cvmx_npei_pktx_slist_baoff_dbell_s cn56xx;
2053 struct cvmx_npei_pktx_slist_baoff_dbell_s cn56xxp1;
2054};
2055
2056union cvmx_npei_pktx_slist_fifo_rsize {
2057 uint64_t u64;
2058 struct cvmx_npei_pktx_slist_fifo_rsize_s {
2059 uint64_t reserved_32_63:32;
2060 uint64_t rsize:32;
2061 } s;
2062 struct cvmx_npei_pktx_slist_fifo_rsize_s cn52xx;
2063 struct cvmx_npei_pktx_slist_fifo_rsize_s cn56xx;
2064 struct cvmx_npei_pktx_slist_fifo_rsize_s cn56xxp1;
2065};
2066
2067union cvmx_npei_pkt_cnt_int {
2068 uint64_t u64;
2069 struct cvmx_npei_pkt_cnt_int_s {
2070 uint64_t reserved_32_63:32;
2071 uint64_t port:32;
2072 } s;
2073 struct cvmx_npei_pkt_cnt_int_s cn52xx;
2074 struct cvmx_npei_pkt_cnt_int_s cn56xx;
2075 struct cvmx_npei_pkt_cnt_int_s cn56xxp1;
2076};
2077
2078union cvmx_npei_pkt_cnt_int_enb {
2079 uint64_t u64;
2080 struct cvmx_npei_pkt_cnt_int_enb_s {
2081 uint64_t reserved_32_63:32;
2082 uint64_t port:32;
2083 } s;
2084 struct cvmx_npei_pkt_cnt_int_enb_s cn52xx;
2085 struct cvmx_npei_pkt_cnt_int_enb_s cn56xx;
2086 struct cvmx_npei_pkt_cnt_int_enb_s cn56xxp1;
2087};
2088
2089union cvmx_npei_pkt_data_out_es {
2090 uint64_t u64;
2091 struct cvmx_npei_pkt_data_out_es_s {
2092 uint64_t es:64;
2093 } s;
2094 struct cvmx_npei_pkt_data_out_es_s cn52xx;
2095 struct cvmx_npei_pkt_data_out_es_s cn56xx;
2096 struct cvmx_npei_pkt_data_out_es_s cn56xxp1;
2097};
2098
2099union cvmx_npei_pkt_data_out_ns {
2100 uint64_t u64;
2101 struct cvmx_npei_pkt_data_out_ns_s {
2102 uint64_t reserved_32_63:32;
2103 uint64_t nsr:32;
2104 } s;
2105 struct cvmx_npei_pkt_data_out_ns_s cn52xx;
2106 struct cvmx_npei_pkt_data_out_ns_s cn56xx;
2107 struct cvmx_npei_pkt_data_out_ns_s cn56xxp1;
2108};
2109
2110union cvmx_npei_pkt_data_out_ror {
2111 uint64_t u64;
2112 struct cvmx_npei_pkt_data_out_ror_s {
2113 uint64_t reserved_32_63:32;
2114 uint64_t ror:32;
2115 } s;
2116 struct cvmx_npei_pkt_data_out_ror_s cn52xx;
2117 struct cvmx_npei_pkt_data_out_ror_s cn56xx;
2118 struct cvmx_npei_pkt_data_out_ror_s cn56xxp1;
2119};
2120
2121union cvmx_npei_pkt_dpaddr {
2122 uint64_t u64;
2123 struct cvmx_npei_pkt_dpaddr_s {
2124 uint64_t reserved_32_63:32;
2125 uint64_t dptr:32;
2126 } s;
2127 struct cvmx_npei_pkt_dpaddr_s cn52xx;
2128 struct cvmx_npei_pkt_dpaddr_s cn56xx;
2129 struct cvmx_npei_pkt_dpaddr_s cn56xxp1;
2130};
2131
2132union cvmx_npei_pkt_in_bp {
2133 uint64_t u64;
2134 struct cvmx_npei_pkt_in_bp_s {
2135 uint64_t reserved_32_63:32;
2136 uint64_t bp:32;
2137 } s;
2138 struct cvmx_npei_pkt_in_bp_s cn56xx;
2139};
2140
2141union cvmx_npei_pkt_in_donex_cnts {
2142 uint64_t u64;
2143 struct cvmx_npei_pkt_in_donex_cnts_s {
2144 uint64_t reserved_32_63:32;
2145 uint64_t cnt:32;
2146 } s;
2147 struct cvmx_npei_pkt_in_donex_cnts_s cn52xx;
2148 struct cvmx_npei_pkt_in_donex_cnts_s cn56xx;
2149 struct cvmx_npei_pkt_in_donex_cnts_s cn56xxp1;
2150};
2151
2152union cvmx_npei_pkt_in_instr_counts {
2153 uint64_t u64;
2154 struct cvmx_npei_pkt_in_instr_counts_s {
2155 uint64_t wr_cnt:32;
2156 uint64_t rd_cnt:32;
2157 } s;
2158 struct cvmx_npei_pkt_in_instr_counts_s cn52xx;
2159 struct cvmx_npei_pkt_in_instr_counts_s cn56xx;
2160};
2161
2162union cvmx_npei_pkt_in_pcie_port {
2163 uint64_t u64;
2164 struct cvmx_npei_pkt_in_pcie_port_s {
2165 uint64_t pp:64;
2166 } s;
2167 struct cvmx_npei_pkt_in_pcie_port_s cn52xx;
2168 struct cvmx_npei_pkt_in_pcie_port_s cn56xx;
2169};
2170
2171union cvmx_npei_pkt_input_control {
2172 uint64_t u64;
2173 struct cvmx_npei_pkt_input_control_s {
2174 uint64_t reserved_23_63:41;
2175 uint64_t pkt_rr:1;
2176 uint64_t pbp_dhi:13;
2177 uint64_t d_nsr:1;
2178 uint64_t d_esr:2;
2179 uint64_t d_ror:1;
2180 uint64_t use_csr:1;
2181 uint64_t nsr:1;
2182 uint64_t esr:2;
2183 uint64_t ror:1;
2184 } s;
2185 struct cvmx_npei_pkt_input_control_s cn52xx;
2186 struct cvmx_npei_pkt_input_control_s cn56xx;
2187 struct cvmx_npei_pkt_input_control_s cn56xxp1;
2188};
2189
2190union cvmx_npei_pkt_instr_enb {
2191 uint64_t u64;
2192 struct cvmx_npei_pkt_instr_enb_s {
2193 uint64_t reserved_32_63:32;
2194 uint64_t enb:32;
2195 } s;
2196 struct cvmx_npei_pkt_instr_enb_s cn52xx;
2197 struct cvmx_npei_pkt_instr_enb_s cn56xx;
2198 struct cvmx_npei_pkt_instr_enb_s cn56xxp1;
2199};
2200
2201union cvmx_npei_pkt_instr_rd_size {
2202 uint64_t u64;
2203 struct cvmx_npei_pkt_instr_rd_size_s {
2204 uint64_t rdsize:64;
2205 } s;
2206 struct cvmx_npei_pkt_instr_rd_size_s cn52xx;
2207 struct cvmx_npei_pkt_instr_rd_size_s cn56xx;
2208};
2209
2210union cvmx_npei_pkt_instr_size {
2211 uint64_t u64;
2212 struct cvmx_npei_pkt_instr_size_s {
2213 uint64_t reserved_32_63:32;
2214 uint64_t is_64b:32;
2215 } s;
2216 struct cvmx_npei_pkt_instr_size_s cn52xx;
2217 struct cvmx_npei_pkt_instr_size_s cn56xx;
2218 struct cvmx_npei_pkt_instr_size_s cn56xxp1;
2219};
2220
2221union cvmx_npei_pkt_int_levels {
2222 uint64_t u64;
2223 struct cvmx_npei_pkt_int_levels_s {
2224 uint64_t reserved_54_63:10;
2225 uint64_t time:22;
2226 uint64_t cnt:32;
2227 } s;
2228 struct cvmx_npei_pkt_int_levels_s cn52xx;
2229 struct cvmx_npei_pkt_int_levels_s cn56xx;
2230 struct cvmx_npei_pkt_int_levels_s cn56xxp1;
2231};
2232
2233union cvmx_npei_pkt_iptr {
2234 uint64_t u64;
2235 struct cvmx_npei_pkt_iptr_s {
2236 uint64_t reserved_32_63:32;
2237 uint64_t iptr:32;
2238 } s;
2239 struct cvmx_npei_pkt_iptr_s cn52xx;
2240 struct cvmx_npei_pkt_iptr_s cn56xx;
2241 struct cvmx_npei_pkt_iptr_s cn56xxp1;
2242};
2243
2244union cvmx_npei_pkt_out_bmode {
2245 uint64_t u64;
2246 struct cvmx_npei_pkt_out_bmode_s {
2247 uint64_t reserved_32_63:32;
2248 uint64_t bmode:32;
2249 } s;
2250 struct cvmx_npei_pkt_out_bmode_s cn52xx;
2251 struct cvmx_npei_pkt_out_bmode_s cn56xx;
2252 struct cvmx_npei_pkt_out_bmode_s cn56xxp1;
2253};
2254
2255union cvmx_npei_pkt_out_enb {
2256 uint64_t u64;
2257 struct cvmx_npei_pkt_out_enb_s {
2258 uint64_t reserved_32_63:32;
2259 uint64_t enb:32;
2260 } s;
2261 struct cvmx_npei_pkt_out_enb_s cn52xx;
2262 struct cvmx_npei_pkt_out_enb_s cn56xx;
2263 struct cvmx_npei_pkt_out_enb_s cn56xxp1;
2264};
2265
2266union cvmx_npei_pkt_output_wmark {
2267 uint64_t u64;
2268 struct cvmx_npei_pkt_output_wmark_s {
2269 uint64_t reserved_32_63:32;
2270 uint64_t wmark:32;
2271 } s;
2272 struct cvmx_npei_pkt_output_wmark_s cn52xx;
2273 struct cvmx_npei_pkt_output_wmark_s cn56xx;
2274};
2275
2276union cvmx_npei_pkt_pcie_port {
2277 uint64_t u64;
2278 struct cvmx_npei_pkt_pcie_port_s {
2279 uint64_t pp:64;
2280 } s;
2281 struct cvmx_npei_pkt_pcie_port_s cn52xx;
2282 struct cvmx_npei_pkt_pcie_port_s cn56xx;
2283 struct cvmx_npei_pkt_pcie_port_s cn56xxp1;
2284};
2285
2286union cvmx_npei_pkt_port_in_rst {
2287 uint64_t u64;
2288 struct cvmx_npei_pkt_port_in_rst_s {
2289 uint64_t in_rst:32;
2290 uint64_t out_rst:32;
2291 } s;
2292 struct cvmx_npei_pkt_port_in_rst_s cn52xx;
2293 struct cvmx_npei_pkt_port_in_rst_s cn56xx;
2294};
2295
2296union cvmx_npei_pkt_slist_es {
2297 uint64_t u64;
2298 struct cvmx_npei_pkt_slist_es_s {
2299 uint64_t es:64;
2300 } s;
2301 struct cvmx_npei_pkt_slist_es_s cn52xx;
2302 struct cvmx_npei_pkt_slist_es_s cn56xx;
2303 struct cvmx_npei_pkt_slist_es_s cn56xxp1;
2304};
2305
2306union cvmx_npei_pkt_slist_id_size {
2307 uint64_t u64;
2308 struct cvmx_npei_pkt_slist_id_size_s {
2309 uint64_t reserved_23_63:41;
2310 uint64_t isize:7;
2311 uint64_t bsize:16;
2312 } s;
2313 struct cvmx_npei_pkt_slist_id_size_s cn52xx;
2314 struct cvmx_npei_pkt_slist_id_size_s cn56xx;
2315 struct cvmx_npei_pkt_slist_id_size_s cn56xxp1;
2316};
2317
2318union cvmx_npei_pkt_slist_ns {
2319 uint64_t u64;
2320 struct cvmx_npei_pkt_slist_ns_s {
2321 uint64_t reserved_32_63:32;
2322 uint64_t nsr:32;
2323 } s;
2324 struct cvmx_npei_pkt_slist_ns_s cn52xx;
2325 struct cvmx_npei_pkt_slist_ns_s cn56xx;
2326 struct cvmx_npei_pkt_slist_ns_s cn56xxp1;
2327};
2328
2329union cvmx_npei_pkt_slist_ror {
2330 uint64_t u64;
2331 struct cvmx_npei_pkt_slist_ror_s {
2332 uint64_t reserved_32_63:32;
2333 uint64_t ror:32;
2334 } s;
2335 struct cvmx_npei_pkt_slist_ror_s cn52xx;
2336 struct cvmx_npei_pkt_slist_ror_s cn56xx;
2337 struct cvmx_npei_pkt_slist_ror_s cn56xxp1;
2338};
2339
2340union cvmx_npei_pkt_time_int {
2341 uint64_t u64;
2342 struct cvmx_npei_pkt_time_int_s {
2343 uint64_t reserved_32_63:32;
2344 uint64_t port:32;
2345 } s;
2346 struct cvmx_npei_pkt_time_int_s cn52xx;
2347 struct cvmx_npei_pkt_time_int_s cn56xx;
2348 struct cvmx_npei_pkt_time_int_s cn56xxp1;
2349};
2350
2351union cvmx_npei_pkt_time_int_enb {
2352 uint64_t u64;
2353 struct cvmx_npei_pkt_time_int_enb_s {
2354 uint64_t reserved_32_63:32;
2355 uint64_t port:32;
2356 } s;
2357 struct cvmx_npei_pkt_time_int_enb_s cn52xx;
2358 struct cvmx_npei_pkt_time_int_enb_s cn56xx;
2359 struct cvmx_npei_pkt_time_int_enb_s cn56xxp1;
2360};
2361
2362union cvmx_npei_rsl_int_blocks {
2363 uint64_t u64;
2364 struct cvmx_npei_rsl_int_blocks_s {
2365 uint64_t reserved_31_63:33;
2366 uint64_t iob:1;
2367 uint64_t lmc1:1;
2368 uint64_t agl:1;
2369 uint64_t reserved_24_27:4;
2370 uint64_t asxpcs1:1;
2371 uint64_t asxpcs0:1;
2372 uint64_t reserved_21_21:1;
2373 uint64_t pip:1;
2374 uint64_t reserved_18_19:2;
2375 uint64_t lmc0:1;
2376 uint64_t l2c:1;
2377 uint64_t usb1:1;
2378 uint64_t rad:1;
2379 uint64_t usb:1;
2380 uint64_t pow:1;
2381 uint64_t tim:1;
2382 uint64_t pko:1;
2383 uint64_t ipd:1;
2384 uint64_t reserved_8_8:1;
2385 uint64_t zip:1;
2386 uint64_t reserved_6_6:1;
2387 uint64_t fpa:1;
2388 uint64_t key:1;
2389 uint64_t npei:1;
2390 uint64_t gmx1:1;
2391 uint64_t gmx0:1;
2392 uint64_t mio:1;
2393 } s;
2394 struct cvmx_npei_rsl_int_blocks_s cn52xx;
2395 struct cvmx_npei_rsl_int_blocks_s cn52xxp1;
2396 struct cvmx_npei_rsl_int_blocks_cn56xx {
2397 uint64_t reserved_31_63:33;
2398 uint64_t iob:1;
2399 uint64_t lmc1:1;
2400 uint64_t agl:1;
2401 uint64_t reserved_24_27:4;
2402 uint64_t asxpcs1:1;
2403 uint64_t asxpcs0:1;
2404 uint64_t reserved_21_21:1;
2405 uint64_t pip:1;
2406 uint64_t reserved_18_19:2;
2407 uint64_t lmc0:1;
2408 uint64_t l2c:1;
2409 uint64_t reserved_15_15:1;
2410 uint64_t rad:1;
2411 uint64_t usb:1;
2412 uint64_t pow:1;
2413 uint64_t tim:1;
2414 uint64_t pko:1;
2415 uint64_t ipd:1;
2416 uint64_t reserved_8_8:1;
2417 uint64_t zip:1;
2418 uint64_t reserved_6_6:1;
2419 uint64_t fpa:1;
2420 uint64_t key:1;
2421 uint64_t npei:1;
2422 uint64_t gmx1:1;
2423 uint64_t gmx0:1;
2424 uint64_t mio:1;
2425 } cn56xx;
2426 struct cvmx_npei_rsl_int_blocks_cn56xx cn56xxp1;
2427};
2428
2429union cvmx_npei_scratch_1 {
2430 uint64_t u64;
2431 struct cvmx_npei_scratch_1_s {
2432 uint64_t data:64;
2433 } s;
2434 struct cvmx_npei_scratch_1_s cn52xx;
2435 struct cvmx_npei_scratch_1_s cn52xxp1;
2436 struct cvmx_npei_scratch_1_s cn56xx;
2437 struct cvmx_npei_scratch_1_s cn56xxp1;
2438};
2439
2440union cvmx_npei_state1 {
2441 uint64_t u64;
2442 struct cvmx_npei_state1_s {
2443 uint64_t cpl1:12;
2444 uint64_t cpl0:12;
2445 uint64_t arb:1;
2446 uint64_t csr:39;
2447 } s;
2448 struct cvmx_npei_state1_s cn52xx;
2449 struct cvmx_npei_state1_s cn52xxp1;
2450 struct cvmx_npei_state1_s cn56xx;
2451 struct cvmx_npei_state1_s cn56xxp1;
2452};
2453
2454union cvmx_npei_state2 {
2455 uint64_t u64;
2456 struct cvmx_npei_state2_s {
2457 uint64_t reserved_48_63:16;
2458 uint64_t npei:1;
2459 uint64_t rac:1;
2460 uint64_t csm1:15;
2461 uint64_t csm0:15;
2462 uint64_t nnp0:8;
2463 uint64_t nnd:8;
2464 } s;
2465 struct cvmx_npei_state2_s cn52xx;
2466 struct cvmx_npei_state2_s cn52xxp1;
2467 struct cvmx_npei_state2_s cn56xx;
2468 struct cvmx_npei_state2_s cn56xxp1;
2469};
2470
2471union cvmx_npei_state3 {
2472 uint64_t u64;
2473 struct cvmx_npei_state3_s {
2474 uint64_t reserved_56_63:8;
2475 uint64_t psm1:15;
2476 uint64_t psm0:15;
2477 uint64_t nsm1:13;
2478 uint64_t nsm0:13;
2479 } s;
2480 struct cvmx_npei_state3_s cn52xx;
2481 struct cvmx_npei_state3_s cn52xxp1;
2482 struct cvmx_npei_state3_s cn56xx;
2483 struct cvmx_npei_state3_s cn56xxp1;
2484};
2485
2486union cvmx_npei_win_rd_addr {
2487 uint64_t u64;
2488 struct cvmx_npei_win_rd_addr_s {
2489 uint64_t reserved_51_63:13;
2490 uint64_t ld_cmd:2;
2491 uint64_t iobit:1;
2492 uint64_t rd_addr:48;
2493 } s;
2494 struct cvmx_npei_win_rd_addr_s cn52xx;
2495 struct cvmx_npei_win_rd_addr_s cn52xxp1;
2496 struct cvmx_npei_win_rd_addr_s cn56xx;
2497 struct cvmx_npei_win_rd_addr_s cn56xxp1;
2498};
2499
2500union cvmx_npei_win_rd_data {
2501 uint64_t u64;
2502 struct cvmx_npei_win_rd_data_s {
2503 uint64_t rd_data:64;
2504 } s;
2505 struct cvmx_npei_win_rd_data_s cn52xx;
2506 struct cvmx_npei_win_rd_data_s cn52xxp1;
2507 struct cvmx_npei_win_rd_data_s cn56xx;
2508 struct cvmx_npei_win_rd_data_s cn56xxp1;
2509};
2510
2511union cvmx_npei_win_wr_addr {
2512 uint64_t u64;
2513 struct cvmx_npei_win_wr_addr_s {
2514 uint64_t reserved_49_63:15;
2515 uint64_t iobit:1;
2516 uint64_t wr_addr:46;
2517 uint64_t reserved_0_1:2;
2518 } s;
2519 struct cvmx_npei_win_wr_addr_s cn52xx;
2520 struct cvmx_npei_win_wr_addr_s cn52xxp1;
2521 struct cvmx_npei_win_wr_addr_s cn56xx;
2522 struct cvmx_npei_win_wr_addr_s cn56xxp1;
2523};
2524
2525union cvmx_npei_win_wr_data {
2526 uint64_t u64;
2527 struct cvmx_npei_win_wr_data_s {
2528 uint64_t wr_data:64;
2529 } s;
2530 struct cvmx_npei_win_wr_data_s cn52xx;
2531 struct cvmx_npei_win_wr_data_s cn52xxp1;
2532 struct cvmx_npei_win_wr_data_s cn56xx;
2533 struct cvmx_npei_win_wr_data_s cn56xxp1;
2534};
2535
2536union cvmx_npei_win_wr_mask {
2537 uint64_t u64;
2538 struct cvmx_npei_win_wr_mask_s {
2539 uint64_t reserved_8_63:56;
2540 uint64_t wr_mask:8;
2541 } s;
2542 struct cvmx_npei_win_wr_mask_s cn52xx;
2543 struct cvmx_npei_win_wr_mask_s cn52xxp1;
2544 struct cvmx_npei_win_wr_mask_s cn56xx;
2545 struct cvmx_npei_win_wr_mask_s cn56xxp1;
2546};
2547
2548union cvmx_npei_window_ctl {
2549 uint64_t u64;
2550 struct cvmx_npei_window_ctl_s {
2551 uint64_t reserved_32_63:32;
2552 uint64_t time:32;
2553 } s;
2554 struct cvmx_npei_window_ctl_s cn52xx;
2555 struct cvmx_npei_window_ctl_s cn52xxp1;
2556 struct cvmx_npei_window_ctl_s cn56xx;
2557 struct cvmx_npei_window_ctl_s cn56xxp1;
2558};
2559
2560#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-npi-defs.h b/arch/mips/include/asm/octeon/cvmx-npi-defs.h
new file mode 100644
index 000000000000..4e03cd8561e3
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-npi-defs.h
@@ -0,0 +1,1735 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_NPI_DEFS_H__
29#define __CVMX_NPI_DEFS_H__
30
31#define CVMX_NPI_BASE_ADDR_INPUT0 \
32 CVMX_ADD_IO_SEG(0x00011F0000000070ull)
33#define CVMX_NPI_BASE_ADDR_INPUT1 \
34 CVMX_ADD_IO_SEG(0x00011F0000000080ull)
35#define CVMX_NPI_BASE_ADDR_INPUT2 \
36 CVMX_ADD_IO_SEG(0x00011F0000000090ull)
37#define CVMX_NPI_BASE_ADDR_INPUT3 \
38 CVMX_ADD_IO_SEG(0x00011F00000000A0ull)
39#define CVMX_NPI_BASE_ADDR_INPUTX(offset) \
40 CVMX_ADD_IO_SEG(0x00011F0000000070ull + (((offset) & 3) * 16))
41#define CVMX_NPI_BASE_ADDR_OUTPUT0 \
42 CVMX_ADD_IO_SEG(0x00011F00000000B8ull)
43#define CVMX_NPI_BASE_ADDR_OUTPUT1 \
44 CVMX_ADD_IO_SEG(0x00011F00000000C0ull)
45#define CVMX_NPI_BASE_ADDR_OUTPUT2 \
46 CVMX_ADD_IO_SEG(0x00011F00000000C8ull)
47#define CVMX_NPI_BASE_ADDR_OUTPUT3 \
48 CVMX_ADD_IO_SEG(0x00011F00000000D0ull)
49#define CVMX_NPI_BASE_ADDR_OUTPUTX(offset) \
50 CVMX_ADD_IO_SEG(0x00011F00000000B8ull + (((offset) & 3) * 8))
51#define CVMX_NPI_BIST_STATUS \
52 CVMX_ADD_IO_SEG(0x00011F00000003F8ull)
53#define CVMX_NPI_BUFF_SIZE_OUTPUT0 \
54 CVMX_ADD_IO_SEG(0x00011F00000000E0ull)
55#define CVMX_NPI_BUFF_SIZE_OUTPUT1 \
56 CVMX_ADD_IO_SEG(0x00011F00000000E8ull)
57#define CVMX_NPI_BUFF_SIZE_OUTPUT2 \
58 CVMX_ADD_IO_SEG(0x00011F00000000F0ull)
59#define CVMX_NPI_BUFF_SIZE_OUTPUT3 \
60 CVMX_ADD_IO_SEG(0x00011F00000000F8ull)
61#define CVMX_NPI_BUFF_SIZE_OUTPUTX(offset) \
62 CVMX_ADD_IO_SEG(0x00011F00000000E0ull + (((offset) & 3) * 8))
63#define CVMX_NPI_COMP_CTL \
64 CVMX_ADD_IO_SEG(0x00011F0000000218ull)
65#define CVMX_NPI_CTL_STATUS \
66 CVMX_ADD_IO_SEG(0x00011F0000000010ull)
67#define CVMX_NPI_DBG_SELECT \
68 CVMX_ADD_IO_SEG(0x00011F0000000008ull)
69#define CVMX_NPI_DMA_CONTROL \
70 CVMX_ADD_IO_SEG(0x00011F0000000128ull)
71#define CVMX_NPI_DMA_HIGHP_COUNTS \
72 CVMX_ADD_IO_SEG(0x00011F0000000148ull)
73#define CVMX_NPI_DMA_HIGHP_NADDR \
74 CVMX_ADD_IO_SEG(0x00011F0000000158ull)
75#define CVMX_NPI_DMA_LOWP_COUNTS \
76 CVMX_ADD_IO_SEG(0x00011F0000000140ull)
77#define CVMX_NPI_DMA_LOWP_NADDR \
78 CVMX_ADD_IO_SEG(0x00011F0000000150ull)
79#define CVMX_NPI_HIGHP_DBELL \
80 CVMX_ADD_IO_SEG(0x00011F0000000120ull)
81#define CVMX_NPI_HIGHP_IBUFF_SADDR \
82 CVMX_ADD_IO_SEG(0x00011F0000000110ull)
83#define CVMX_NPI_INPUT_CONTROL \
84 CVMX_ADD_IO_SEG(0x00011F0000000138ull)
85#define CVMX_NPI_INT_ENB \
86 CVMX_ADD_IO_SEG(0x00011F0000000020ull)
87#define CVMX_NPI_INT_SUM \
88 CVMX_ADD_IO_SEG(0x00011F0000000018ull)
89#define CVMX_NPI_LOWP_DBELL \
90 CVMX_ADD_IO_SEG(0x00011F0000000118ull)
91#define CVMX_NPI_LOWP_IBUFF_SADDR \
92 CVMX_ADD_IO_SEG(0x00011F0000000108ull)
93#define CVMX_NPI_MEM_ACCESS_SUBID3 \
94 CVMX_ADD_IO_SEG(0x00011F0000000028ull)
95#define CVMX_NPI_MEM_ACCESS_SUBID4 \
96 CVMX_ADD_IO_SEG(0x00011F0000000030ull)
97#define CVMX_NPI_MEM_ACCESS_SUBID5 \
98 CVMX_ADD_IO_SEG(0x00011F0000000038ull)
99#define CVMX_NPI_MEM_ACCESS_SUBID6 \
100 CVMX_ADD_IO_SEG(0x00011F0000000040ull)
101#define CVMX_NPI_MEM_ACCESS_SUBIDX(offset) \
102 CVMX_ADD_IO_SEG(0x00011F0000000028ull + (((offset) & 7) * 8) - 8 * 3)
103#define CVMX_NPI_MSI_RCV \
104 (0x0000000000000190ull)
105#define CVMX_NPI_NPI_MSI_RCV \
106 CVMX_ADD_IO_SEG(0x00011F0000001190ull)
107#define CVMX_NPI_NUM_DESC_OUTPUT0 \
108 CVMX_ADD_IO_SEG(0x00011F0000000050ull)
109#define CVMX_NPI_NUM_DESC_OUTPUT1 \
110 CVMX_ADD_IO_SEG(0x00011F0000000058ull)
111#define CVMX_NPI_NUM_DESC_OUTPUT2 \
112 CVMX_ADD_IO_SEG(0x00011F0000000060ull)
113#define CVMX_NPI_NUM_DESC_OUTPUT3 \
114 CVMX_ADD_IO_SEG(0x00011F0000000068ull)
115#define CVMX_NPI_NUM_DESC_OUTPUTX(offset) \
116 CVMX_ADD_IO_SEG(0x00011F0000000050ull + (((offset) & 3) * 8))
117#define CVMX_NPI_OUTPUT_CONTROL \
118 CVMX_ADD_IO_SEG(0x00011F0000000100ull)
119#define CVMX_NPI_P0_DBPAIR_ADDR \
120 CVMX_ADD_IO_SEG(0x00011F0000000180ull)
121#define CVMX_NPI_P0_INSTR_ADDR \
122 CVMX_ADD_IO_SEG(0x00011F00000001C0ull)
123#define CVMX_NPI_P0_INSTR_CNTS \
124 CVMX_ADD_IO_SEG(0x00011F00000001A0ull)
125#define CVMX_NPI_P0_PAIR_CNTS \
126 CVMX_ADD_IO_SEG(0x00011F0000000160ull)
127#define CVMX_NPI_P1_DBPAIR_ADDR \
128 CVMX_ADD_IO_SEG(0x00011F0000000188ull)
129#define CVMX_NPI_P1_INSTR_ADDR \
130 CVMX_ADD_IO_SEG(0x00011F00000001C8ull)
131#define CVMX_NPI_P1_INSTR_CNTS \
132 CVMX_ADD_IO_SEG(0x00011F00000001A8ull)
133#define CVMX_NPI_P1_PAIR_CNTS \
134 CVMX_ADD_IO_SEG(0x00011F0000000168ull)
135#define CVMX_NPI_P2_DBPAIR_ADDR \
136 CVMX_ADD_IO_SEG(0x00011F0000000190ull)
137#define CVMX_NPI_P2_INSTR_ADDR \
138 CVMX_ADD_IO_SEG(0x00011F00000001D0ull)
139#define CVMX_NPI_P2_INSTR_CNTS \
140 CVMX_ADD_IO_SEG(0x00011F00000001B0ull)
141#define CVMX_NPI_P2_PAIR_CNTS \
142 CVMX_ADD_IO_SEG(0x00011F0000000170ull)
143#define CVMX_NPI_P3_DBPAIR_ADDR \
144 CVMX_ADD_IO_SEG(0x00011F0000000198ull)
145#define CVMX_NPI_P3_INSTR_ADDR \
146 CVMX_ADD_IO_SEG(0x00011F00000001D8ull)
147#define CVMX_NPI_P3_INSTR_CNTS \
148 CVMX_ADD_IO_SEG(0x00011F00000001B8ull)
149#define CVMX_NPI_P3_PAIR_CNTS \
150 CVMX_ADD_IO_SEG(0x00011F0000000178ull)
151#define CVMX_NPI_PCI_BAR1_INDEXX(offset) \
152 CVMX_ADD_IO_SEG(0x00011F0000001100ull + (((offset) & 31) * 4))
153#define CVMX_NPI_PCI_BIST_REG \
154 CVMX_ADD_IO_SEG(0x00011F00000011C0ull)
155#define CVMX_NPI_PCI_BURST_SIZE \
156 CVMX_ADD_IO_SEG(0x00011F00000000D8ull)
157#define CVMX_NPI_PCI_CFG00 \
158 CVMX_ADD_IO_SEG(0x00011F0000001800ull)
159#define CVMX_NPI_PCI_CFG01 \
160 CVMX_ADD_IO_SEG(0x00011F0000001804ull)
161#define CVMX_NPI_PCI_CFG02 \
162 CVMX_ADD_IO_SEG(0x00011F0000001808ull)
163#define CVMX_NPI_PCI_CFG03 \
164 CVMX_ADD_IO_SEG(0x00011F000000180Cull)
165#define CVMX_NPI_PCI_CFG04 \
166 CVMX_ADD_IO_SEG(0x00011F0000001810ull)
167#define CVMX_NPI_PCI_CFG05 \
168 CVMX_ADD_IO_SEG(0x00011F0000001814ull)
169#define CVMX_NPI_PCI_CFG06 \
170 CVMX_ADD_IO_SEG(0x00011F0000001818ull)
171#define CVMX_NPI_PCI_CFG07 \
172 CVMX_ADD_IO_SEG(0x00011F000000181Cull)
173#define CVMX_NPI_PCI_CFG08 \
174 CVMX_ADD_IO_SEG(0x00011F0000001820ull)
175#define CVMX_NPI_PCI_CFG09 \
176 CVMX_ADD_IO_SEG(0x00011F0000001824ull)
177#define CVMX_NPI_PCI_CFG10 \
178 CVMX_ADD_IO_SEG(0x00011F0000001828ull)
179#define CVMX_NPI_PCI_CFG11 \
180 CVMX_ADD_IO_SEG(0x00011F000000182Cull)
181#define CVMX_NPI_PCI_CFG12 \
182 CVMX_ADD_IO_SEG(0x00011F0000001830ull)
183#define CVMX_NPI_PCI_CFG13 \
184 CVMX_ADD_IO_SEG(0x00011F0000001834ull)
185#define CVMX_NPI_PCI_CFG15 \
186 CVMX_ADD_IO_SEG(0x00011F000000183Cull)
187#define CVMX_NPI_PCI_CFG16 \
188 CVMX_ADD_IO_SEG(0x00011F0000001840ull)
189#define CVMX_NPI_PCI_CFG17 \
190 CVMX_ADD_IO_SEG(0x00011F0000001844ull)
191#define CVMX_NPI_PCI_CFG18 \
192 CVMX_ADD_IO_SEG(0x00011F0000001848ull)
193#define CVMX_NPI_PCI_CFG19 \
194 CVMX_ADD_IO_SEG(0x00011F000000184Cull)
195#define CVMX_NPI_PCI_CFG20 \
196 CVMX_ADD_IO_SEG(0x00011F0000001850ull)
197#define CVMX_NPI_PCI_CFG21 \
198 CVMX_ADD_IO_SEG(0x00011F0000001854ull)
199#define CVMX_NPI_PCI_CFG22 \
200 CVMX_ADD_IO_SEG(0x00011F0000001858ull)
201#define CVMX_NPI_PCI_CFG56 \
202 CVMX_ADD_IO_SEG(0x00011F00000018E0ull)
203#define CVMX_NPI_PCI_CFG57 \
204 CVMX_ADD_IO_SEG(0x00011F00000018E4ull)
205#define CVMX_NPI_PCI_CFG58 \
206 CVMX_ADD_IO_SEG(0x00011F00000018E8ull)
207#define CVMX_NPI_PCI_CFG59 \
208 CVMX_ADD_IO_SEG(0x00011F00000018ECull)
209#define CVMX_NPI_PCI_CFG60 \
210 CVMX_ADD_IO_SEG(0x00011F00000018F0ull)
211#define CVMX_NPI_PCI_CFG61 \
212 CVMX_ADD_IO_SEG(0x00011F00000018F4ull)
213#define CVMX_NPI_PCI_CFG62 \
214 CVMX_ADD_IO_SEG(0x00011F00000018F8ull)
215#define CVMX_NPI_PCI_CFG63 \
216 CVMX_ADD_IO_SEG(0x00011F00000018FCull)
217#define CVMX_NPI_PCI_CNT_REG \
218 CVMX_ADD_IO_SEG(0x00011F00000011B8ull)
219#define CVMX_NPI_PCI_CTL_STATUS_2 \
220 CVMX_ADD_IO_SEG(0x00011F000000118Cull)
221#define CVMX_NPI_PCI_INT_ARB_CFG \
222 CVMX_ADD_IO_SEG(0x00011F0000000130ull)
223#define CVMX_NPI_PCI_INT_ENB2 \
224 CVMX_ADD_IO_SEG(0x00011F00000011A0ull)
225#define CVMX_NPI_PCI_INT_SUM2 \
226 CVMX_ADD_IO_SEG(0x00011F0000001198ull)
227#define CVMX_NPI_PCI_READ_CMD \
228 CVMX_ADD_IO_SEG(0x00011F0000000048ull)
229#define CVMX_NPI_PCI_READ_CMD_6 \
230 CVMX_ADD_IO_SEG(0x00011F0000001180ull)
231#define CVMX_NPI_PCI_READ_CMD_C \
232 CVMX_ADD_IO_SEG(0x00011F0000001184ull)
233#define CVMX_NPI_PCI_READ_CMD_E \
234 CVMX_ADD_IO_SEG(0x00011F0000001188ull)
235#define CVMX_NPI_PCI_SCM_REG \
236 CVMX_ADD_IO_SEG(0x00011F00000011A8ull)
237#define CVMX_NPI_PCI_TSR_REG \
238 CVMX_ADD_IO_SEG(0x00011F00000011B0ull)
239#define CVMX_NPI_PORT32_INSTR_HDR \
240 CVMX_ADD_IO_SEG(0x00011F00000001F8ull)
241#define CVMX_NPI_PORT33_INSTR_HDR \
242 CVMX_ADD_IO_SEG(0x00011F0000000200ull)
243#define CVMX_NPI_PORT34_INSTR_HDR \
244 CVMX_ADD_IO_SEG(0x00011F0000000208ull)
245#define CVMX_NPI_PORT35_INSTR_HDR \
246 CVMX_ADD_IO_SEG(0x00011F0000000210ull)
247#define CVMX_NPI_PORT_BP_CONTROL \
248 CVMX_ADD_IO_SEG(0x00011F00000001F0ull)
249#define CVMX_NPI_PX_DBPAIR_ADDR(offset) \
250 CVMX_ADD_IO_SEG(0x00011F0000000180ull + (((offset) & 3) * 8))
251#define CVMX_NPI_PX_INSTR_ADDR(offset) \
252 CVMX_ADD_IO_SEG(0x00011F00000001C0ull + (((offset) & 3) * 8))
253#define CVMX_NPI_PX_INSTR_CNTS(offset) \
254 CVMX_ADD_IO_SEG(0x00011F00000001A0ull + (((offset) & 3) * 8))
255#define CVMX_NPI_PX_PAIR_CNTS(offset) \
256 CVMX_ADD_IO_SEG(0x00011F0000000160ull + (((offset) & 3) * 8))
257#define CVMX_NPI_RSL_INT_BLOCKS \
258 CVMX_ADD_IO_SEG(0x00011F0000000000ull)
259#define CVMX_NPI_SIZE_INPUT0 \
260 CVMX_ADD_IO_SEG(0x00011F0000000078ull)
261#define CVMX_NPI_SIZE_INPUT1 \
262 CVMX_ADD_IO_SEG(0x00011F0000000088ull)
263#define CVMX_NPI_SIZE_INPUT2 \
264 CVMX_ADD_IO_SEG(0x00011F0000000098ull)
265#define CVMX_NPI_SIZE_INPUT3 \
266 CVMX_ADD_IO_SEG(0x00011F00000000A8ull)
267#define CVMX_NPI_SIZE_INPUTX(offset) \
268 CVMX_ADD_IO_SEG(0x00011F0000000078ull + (((offset) & 3) * 16))
269#define CVMX_NPI_WIN_READ_TO \
270 CVMX_ADD_IO_SEG(0x00011F00000001E0ull)
271
272union cvmx_npi_base_addr_inputx {
273 uint64_t u64;
274 struct cvmx_npi_base_addr_inputx_s {
275 uint64_t baddr:61;
276 uint64_t reserved_0_2:3;
277 } s;
278 struct cvmx_npi_base_addr_inputx_s cn30xx;
279 struct cvmx_npi_base_addr_inputx_s cn31xx;
280 struct cvmx_npi_base_addr_inputx_s cn38xx;
281 struct cvmx_npi_base_addr_inputx_s cn38xxp2;
282 struct cvmx_npi_base_addr_inputx_s cn50xx;
283 struct cvmx_npi_base_addr_inputx_s cn58xx;
284 struct cvmx_npi_base_addr_inputx_s cn58xxp1;
285};
286
287union cvmx_npi_base_addr_outputx {
288 uint64_t u64;
289 struct cvmx_npi_base_addr_outputx_s {
290 uint64_t baddr:61;
291 uint64_t reserved_0_2:3;
292 } s;
293 struct cvmx_npi_base_addr_outputx_s cn30xx;
294 struct cvmx_npi_base_addr_outputx_s cn31xx;
295 struct cvmx_npi_base_addr_outputx_s cn38xx;
296 struct cvmx_npi_base_addr_outputx_s cn38xxp2;
297 struct cvmx_npi_base_addr_outputx_s cn50xx;
298 struct cvmx_npi_base_addr_outputx_s cn58xx;
299 struct cvmx_npi_base_addr_outputx_s cn58xxp1;
300};
301
302union cvmx_npi_bist_status {
303 uint64_t u64;
304 struct cvmx_npi_bist_status_s {
305 uint64_t reserved_20_63:44;
306 uint64_t csr_bs:1;
307 uint64_t dif_bs:1;
308 uint64_t rdp_bs:1;
309 uint64_t pcnc_bs:1;
310 uint64_t pcn_bs:1;
311 uint64_t rdn_bs:1;
312 uint64_t pcac_bs:1;
313 uint64_t pcad_bs:1;
314 uint64_t rdnl_bs:1;
315 uint64_t pgf_bs:1;
316 uint64_t pig_bs:1;
317 uint64_t pof0_bs:1;
318 uint64_t pof1_bs:1;
319 uint64_t pof2_bs:1;
320 uint64_t pof3_bs:1;
321 uint64_t pos_bs:1;
322 uint64_t nus_bs:1;
323 uint64_t dob_bs:1;
324 uint64_t pdf_bs:1;
325 uint64_t dpi_bs:1;
326 } s;
327 struct cvmx_npi_bist_status_cn30xx {
328 uint64_t reserved_20_63:44;
329 uint64_t csr_bs:1;
330 uint64_t dif_bs:1;
331 uint64_t rdp_bs:1;
332 uint64_t pcnc_bs:1;
333 uint64_t pcn_bs:1;
334 uint64_t rdn_bs:1;
335 uint64_t pcac_bs:1;
336 uint64_t pcad_bs:1;
337 uint64_t rdnl_bs:1;
338 uint64_t pgf_bs:1;
339 uint64_t pig_bs:1;
340 uint64_t pof0_bs:1;
341 uint64_t reserved_5_7:3;
342 uint64_t pos_bs:1;
343 uint64_t nus_bs:1;
344 uint64_t dob_bs:1;
345 uint64_t pdf_bs:1;
346 uint64_t dpi_bs:1;
347 } cn30xx;
348 struct cvmx_npi_bist_status_s cn31xx;
349 struct cvmx_npi_bist_status_s cn38xx;
350 struct cvmx_npi_bist_status_s cn38xxp2;
351 struct cvmx_npi_bist_status_cn50xx {
352 uint64_t reserved_20_63:44;
353 uint64_t csr_bs:1;
354 uint64_t dif_bs:1;
355 uint64_t rdp_bs:1;
356 uint64_t pcnc_bs:1;
357 uint64_t pcn_bs:1;
358 uint64_t rdn_bs:1;
359 uint64_t pcac_bs:1;
360 uint64_t pcad_bs:1;
361 uint64_t rdnl_bs:1;
362 uint64_t pgf_bs:1;
363 uint64_t pig_bs:1;
364 uint64_t pof0_bs:1;
365 uint64_t pof1_bs:1;
366 uint64_t reserved_5_6:2;
367 uint64_t pos_bs:1;
368 uint64_t nus_bs:1;
369 uint64_t dob_bs:1;
370 uint64_t pdf_bs:1;
371 uint64_t dpi_bs:1;
372 } cn50xx;
373 struct cvmx_npi_bist_status_s cn58xx;
374 struct cvmx_npi_bist_status_s cn58xxp1;
375};
376
377union cvmx_npi_buff_size_outputx {
378 uint64_t u64;
379 struct cvmx_npi_buff_size_outputx_s {
380 uint64_t reserved_23_63:41;
381 uint64_t isize:7;
382 uint64_t bsize:16;
383 } s;
384 struct cvmx_npi_buff_size_outputx_s cn30xx;
385 struct cvmx_npi_buff_size_outputx_s cn31xx;
386 struct cvmx_npi_buff_size_outputx_s cn38xx;
387 struct cvmx_npi_buff_size_outputx_s cn38xxp2;
388 struct cvmx_npi_buff_size_outputx_s cn50xx;
389 struct cvmx_npi_buff_size_outputx_s cn58xx;
390 struct cvmx_npi_buff_size_outputx_s cn58xxp1;
391};
392
393union cvmx_npi_comp_ctl {
394 uint64_t u64;
395 struct cvmx_npi_comp_ctl_s {
396 uint64_t reserved_10_63:54;
397 uint64_t pctl:5;
398 uint64_t nctl:5;
399 } s;
400 struct cvmx_npi_comp_ctl_s cn50xx;
401 struct cvmx_npi_comp_ctl_s cn58xx;
402 struct cvmx_npi_comp_ctl_s cn58xxp1;
403};
404
405union cvmx_npi_ctl_status {
406 uint64_t u64;
407 struct cvmx_npi_ctl_status_s {
408 uint64_t reserved_63_63:1;
409 uint64_t chip_rev:8;
410 uint64_t dis_pniw:1;
411 uint64_t out3_enb:1;
412 uint64_t out2_enb:1;
413 uint64_t out1_enb:1;
414 uint64_t out0_enb:1;
415 uint64_t ins3_enb:1;
416 uint64_t ins2_enb:1;
417 uint64_t ins1_enb:1;
418 uint64_t ins0_enb:1;
419 uint64_t ins3_64b:1;
420 uint64_t ins2_64b:1;
421 uint64_t ins1_64b:1;
422 uint64_t ins0_64b:1;
423 uint64_t pci_wdis:1;
424 uint64_t wait_com:1;
425 uint64_t reserved_37_39:3;
426 uint64_t max_word:5;
427 uint64_t reserved_10_31:22;
428 uint64_t timer:10;
429 } s;
430 struct cvmx_npi_ctl_status_cn30xx {
431 uint64_t reserved_63_63:1;
432 uint64_t chip_rev:8;
433 uint64_t dis_pniw:1;
434 uint64_t reserved_51_53:3;
435 uint64_t out0_enb:1;
436 uint64_t reserved_47_49:3;
437 uint64_t ins0_enb:1;
438 uint64_t reserved_43_45:3;
439 uint64_t ins0_64b:1;
440 uint64_t pci_wdis:1;
441 uint64_t wait_com:1;
442 uint64_t reserved_37_39:3;
443 uint64_t max_word:5;
444 uint64_t reserved_10_31:22;
445 uint64_t timer:10;
446 } cn30xx;
447 struct cvmx_npi_ctl_status_cn31xx {
448 uint64_t reserved_63_63:1;
449 uint64_t chip_rev:8;
450 uint64_t dis_pniw:1;
451 uint64_t reserved_52_53:2;
452 uint64_t out1_enb:1;
453 uint64_t out0_enb:1;
454 uint64_t reserved_48_49:2;
455 uint64_t ins1_enb:1;
456 uint64_t ins0_enb:1;
457 uint64_t reserved_44_45:2;
458 uint64_t ins1_64b:1;
459 uint64_t ins0_64b:1;
460 uint64_t pci_wdis:1;
461 uint64_t wait_com:1;
462 uint64_t reserved_37_39:3;
463 uint64_t max_word:5;
464 uint64_t reserved_10_31:22;
465 uint64_t timer:10;
466 } cn31xx;
467 struct cvmx_npi_ctl_status_s cn38xx;
468 struct cvmx_npi_ctl_status_s cn38xxp2;
469 struct cvmx_npi_ctl_status_cn31xx cn50xx;
470 struct cvmx_npi_ctl_status_s cn58xx;
471 struct cvmx_npi_ctl_status_s cn58xxp1;
472};
473
474union cvmx_npi_dbg_select {
475 uint64_t u64;
476 struct cvmx_npi_dbg_select_s {
477 uint64_t reserved_16_63:48;
478 uint64_t dbg_sel:16;
479 } s;
480 struct cvmx_npi_dbg_select_s cn30xx;
481 struct cvmx_npi_dbg_select_s cn31xx;
482 struct cvmx_npi_dbg_select_s cn38xx;
483 struct cvmx_npi_dbg_select_s cn38xxp2;
484 struct cvmx_npi_dbg_select_s cn50xx;
485 struct cvmx_npi_dbg_select_s cn58xx;
486 struct cvmx_npi_dbg_select_s cn58xxp1;
487};
488
489union cvmx_npi_dma_control {
490 uint64_t u64;
491 struct cvmx_npi_dma_control_s {
492 uint64_t reserved_36_63:28;
493 uint64_t b0_lend:1;
494 uint64_t dwb_denb:1;
495 uint64_t dwb_ichk:9;
496 uint64_t fpa_que:3;
497 uint64_t o_add1:1;
498 uint64_t o_ro:1;
499 uint64_t o_ns:1;
500 uint64_t o_es:2;
501 uint64_t o_mode:1;
502 uint64_t hp_enb:1;
503 uint64_t lp_enb:1;
504 uint64_t csize:14;
505 } s;
506 struct cvmx_npi_dma_control_s cn30xx;
507 struct cvmx_npi_dma_control_s cn31xx;
508 struct cvmx_npi_dma_control_s cn38xx;
509 struct cvmx_npi_dma_control_s cn38xxp2;
510 struct cvmx_npi_dma_control_s cn50xx;
511 struct cvmx_npi_dma_control_s cn58xx;
512 struct cvmx_npi_dma_control_s cn58xxp1;
513};
514
515union cvmx_npi_dma_highp_counts {
516 uint64_t u64;
517 struct cvmx_npi_dma_highp_counts_s {
518 uint64_t reserved_39_63:25;
519 uint64_t fcnt:7;
520 uint64_t dbell:32;
521 } s;
522 struct cvmx_npi_dma_highp_counts_s cn30xx;
523 struct cvmx_npi_dma_highp_counts_s cn31xx;
524 struct cvmx_npi_dma_highp_counts_s cn38xx;
525 struct cvmx_npi_dma_highp_counts_s cn38xxp2;
526 struct cvmx_npi_dma_highp_counts_s cn50xx;
527 struct cvmx_npi_dma_highp_counts_s cn58xx;
528 struct cvmx_npi_dma_highp_counts_s cn58xxp1;
529};
530
531union cvmx_npi_dma_highp_naddr {
532 uint64_t u64;
533 struct cvmx_npi_dma_highp_naddr_s {
534 uint64_t reserved_40_63:24;
535 uint64_t state:4;
536 uint64_t addr:36;
537 } s;
538 struct cvmx_npi_dma_highp_naddr_s cn30xx;
539 struct cvmx_npi_dma_highp_naddr_s cn31xx;
540 struct cvmx_npi_dma_highp_naddr_s cn38xx;
541 struct cvmx_npi_dma_highp_naddr_s cn38xxp2;
542 struct cvmx_npi_dma_highp_naddr_s cn50xx;
543 struct cvmx_npi_dma_highp_naddr_s cn58xx;
544 struct cvmx_npi_dma_highp_naddr_s cn58xxp1;
545};
546
547union cvmx_npi_dma_lowp_counts {
548 uint64_t u64;
549 struct cvmx_npi_dma_lowp_counts_s {
550 uint64_t reserved_39_63:25;
551 uint64_t fcnt:7;
552 uint64_t dbell:32;
553 } s;
554 struct cvmx_npi_dma_lowp_counts_s cn30xx;
555 struct cvmx_npi_dma_lowp_counts_s cn31xx;
556 struct cvmx_npi_dma_lowp_counts_s cn38xx;
557 struct cvmx_npi_dma_lowp_counts_s cn38xxp2;
558 struct cvmx_npi_dma_lowp_counts_s cn50xx;
559 struct cvmx_npi_dma_lowp_counts_s cn58xx;
560 struct cvmx_npi_dma_lowp_counts_s cn58xxp1;
561};
562
563union cvmx_npi_dma_lowp_naddr {
564 uint64_t u64;
565 struct cvmx_npi_dma_lowp_naddr_s {
566 uint64_t reserved_40_63:24;
567 uint64_t state:4;
568 uint64_t addr:36;
569 } s;
570 struct cvmx_npi_dma_lowp_naddr_s cn30xx;
571 struct cvmx_npi_dma_lowp_naddr_s cn31xx;
572 struct cvmx_npi_dma_lowp_naddr_s cn38xx;
573 struct cvmx_npi_dma_lowp_naddr_s cn38xxp2;
574 struct cvmx_npi_dma_lowp_naddr_s cn50xx;
575 struct cvmx_npi_dma_lowp_naddr_s cn58xx;
576 struct cvmx_npi_dma_lowp_naddr_s cn58xxp1;
577};
578
579union cvmx_npi_highp_dbell {
580 uint64_t u64;
581 struct cvmx_npi_highp_dbell_s {
582 uint64_t reserved_16_63:48;
583 uint64_t dbell:16;
584 } s;
585 struct cvmx_npi_highp_dbell_s cn30xx;
586 struct cvmx_npi_highp_dbell_s cn31xx;
587 struct cvmx_npi_highp_dbell_s cn38xx;
588 struct cvmx_npi_highp_dbell_s cn38xxp2;
589 struct cvmx_npi_highp_dbell_s cn50xx;
590 struct cvmx_npi_highp_dbell_s cn58xx;
591 struct cvmx_npi_highp_dbell_s cn58xxp1;
592};
593
594union cvmx_npi_highp_ibuff_saddr {
595 uint64_t u64;
596 struct cvmx_npi_highp_ibuff_saddr_s {
597 uint64_t reserved_36_63:28;
598 uint64_t saddr:36;
599 } s;
600 struct cvmx_npi_highp_ibuff_saddr_s cn30xx;
601 struct cvmx_npi_highp_ibuff_saddr_s cn31xx;
602 struct cvmx_npi_highp_ibuff_saddr_s cn38xx;
603 struct cvmx_npi_highp_ibuff_saddr_s cn38xxp2;
604 struct cvmx_npi_highp_ibuff_saddr_s cn50xx;
605 struct cvmx_npi_highp_ibuff_saddr_s cn58xx;
606 struct cvmx_npi_highp_ibuff_saddr_s cn58xxp1;
607};
608
609union cvmx_npi_input_control {
610 uint64_t u64;
611 struct cvmx_npi_input_control_s {
612 uint64_t reserved_23_63:41;
613 uint64_t pkt_rr:1;
614 uint64_t pbp_dhi:13;
615 uint64_t d_nsr:1;
616 uint64_t d_esr:2;
617 uint64_t d_ror:1;
618 uint64_t use_csr:1;
619 uint64_t nsr:1;
620 uint64_t esr:2;
621 uint64_t ror:1;
622 } s;
623 struct cvmx_npi_input_control_cn30xx {
624 uint64_t reserved_22_63:42;
625 uint64_t pbp_dhi:13;
626 uint64_t d_nsr:1;
627 uint64_t d_esr:2;
628 uint64_t d_ror:1;
629 uint64_t use_csr:1;
630 uint64_t nsr:1;
631 uint64_t esr:2;
632 uint64_t ror:1;
633 } cn30xx;
634 struct cvmx_npi_input_control_cn30xx cn31xx;
635 struct cvmx_npi_input_control_s cn38xx;
636 struct cvmx_npi_input_control_cn30xx cn38xxp2;
637 struct cvmx_npi_input_control_s cn50xx;
638 struct cvmx_npi_input_control_s cn58xx;
639 struct cvmx_npi_input_control_s cn58xxp1;
640};
641
642union cvmx_npi_int_enb {
643 uint64_t u64;
644 struct cvmx_npi_int_enb_s {
645 uint64_t reserved_62_63:2;
646 uint64_t q1_a_f:1;
647 uint64_t q1_s_e:1;
648 uint64_t pdf_p_f:1;
649 uint64_t pdf_p_e:1;
650 uint64_t pcf_p_f:1;
651 uint64_t pcf_p_e:1;
652 uint64_t rdx_s_e:1;
653 uint64_t rwx_s_e:1;
654 uint64_t pnc_a_f:1;
655 uint64_t pnc_s_e:1;
656 uint64_t com_a_f:1;
657 uint64_t com_s_e:1;
658 uint64_t q3_a_f:1;
659 uint64_t q3_s_e:1;
660 uint64_t q2_a_f:1;
661 uint64_t q2_s_e:1;
662 uint64_t pcr_a_f:1;
663 uint64_t pcr_s_e:1;
664 uint64_t fcr_a_f:1;
665 uint64_t fcr_s_e:1;
666 uint64_t iobdma:1;
667 uint64_t p_dperr:1;
668 uint64_t win_rto:1;
669 uint64_t i3_pperr:1;
670 uint64_t i2_pperr:1;
671 uint64_t i1_pperr:1;
672 uint64_t i0_pperr:1;
673 uint64_t p3_ptout:1;
674 uint64_t p2_ptout:1;
675 uint64_t p1_ptout:1;
676 uint64_t p0_ptout:1;
677 uint64_t p3_pperr:1;
678 uint64_t p2_pperr:1;
679 uint64_t p1_pperr:1;
680 uint64_t p0_pperr:1;
681 uint64_t g3_rtout:1;
682 uint64_t g2_rtout:1;
683 uint64_t g1_rtout:1;
684 uint64_t g0_rtout:1;
685 uint64_t p3_perr:1;
686 uint64_t p2_perr:1;
687 uint64_t p1_perr:1;
688 uint64_t p0_perr:1;
689 uint64_t p3_rtout:1;
690 uint64_t p2_rtout:1;
691 uint64_t p1_rtout:1;
692 uint64_t p0_rtout:1;
693 uint64_t i3_overf:1;
694 uint64_t i2_overf:1;
695 uint64_t i1_overf:1;
696 uint64_t i0_overf:1;
697 uint64_t i3_rtout:1;
698 uint64_t i2_rtout:1;
699 uint64_t i1_rtout:1;
700 uint64_t i0_rtout:1;
701 uint64_t po3_2sml:1;
702 uint64_t po2_2sml:1;
703 uint64_t po1_2sml:1;
704 uint64_t po0_2sml:1;
705 uint64_t pci_rsl:1;
706 uint64_t rml_wto:1;
707 uint64_t rml_rto:1;
708 } s;
709 struct cvmx_npi_int_enb_cn30xx {
710 uint64_t reserved_62_63:2;
711 uint64_t q1_a_f:1;
712 uint64_t q1_s_e:1;
713 uint64_t pdf_p_f:1;
714 uint64_t pdf_p_e:1;
715 uint64_t pcf_p_f:1;
716 uint64_t pcf_p_e:1;
717 uint64_t rdx_s_e:1;
718 uint64_t rwx_s_e:1;
719 uint64_t pnc_a_f:1;
720 uint64_t pnc_s_e:1;
721 uint64_t com_a_f:1;
722 uint64_t com_s_e:1;
723 uint64_t q3_a_f:1;
724 uint64_t q3_s_e:1;
725 uint64_t q2_a_f:1;
726 uint64_t q2_s_e:1;
727 uint64_t pcr_a_f:1;
728 uint64_t pcr_s_e:1;
729 uint64_t fcr_a_f:1;
730 uint64_t fcr_s_e:1;
731 uint64_t iobdma:1;
732 uint64_t p_dperr:1;
733 uint64_t win_rto:1;
734 uint64_t reserved_36_38:3;
735 uint64_t i0_pperr:1;
736 uint64_t reserved_32_34:3;
737 uint64_t p0_ptout:1;
738 uint64_t reserved_28_30:3;
739 uint64_t p0_pperr:1;
740 uint64_t reserved_24_26:3;
741 uint64_t g0_rtout:1;
742 uint64_t reserved_20_22:3;
743 uint64_t p0_perr:1;
744 uint64_t reserved_16_18:3;
745 uint64_t p0_rtout:1;
746 uint64_t reserved_12_14:3;
747 uint64_t i0_overf:1;
748 uint64_t reserved_8_10:3;
749 uint64_t i0_rtout:1;
750 uint64_t reserved_4_6:3;
751 uint64_t po0_2sml:1;
752 uint64_t pci_rsl:1;
753 uint64_t rml_wto:1;
754 uint64_t rml_rto:1;
755 } cn30xx;
756 struct cvmx_npi_int_enb_cn31xx {
757 uint64_t reserved_62_63:2;
758 uint64_t q1_a_f:1;
759 uint64_t q1_s_e:1;
760 uint64_t pdf_p_f:1;
761 uint64_t pdf_p_e:1;
762 uint64_t pcf_p_f:1;
763 uint64_t pcf_p_e:1;
764 uint64_t rdx_s_e:1;
765 uint64_t rwx_s_e:1;
766 uint64_t pnc_a_f:1;
767 uint64_t pnc_s_e:1;
768 uint64_t com_a_f:1;
769 uint64_t com_s_e:1;
770 uint64_t q3_a_f:1;
771 uint64_t q3_s_e:1;
772 uint64_t q2_a_f:1;
773 uint64_t q2_s_e:1;
774 uint64_t pcr_a_f:1;
775 uint64_t pcr_s_e:1;
776 uint64_t fcr_a_f:1;
777 uint64_t fcr_s_e:1;
778 uint64_t iobdma:1;
779 uint64_t p_dperr:1;
780 uint64_t win_rto:1;
781 uint64_t reserved_37_38:2;
782 uint64_t i1_pperr:1;
783 uint64_t i0_pperr:1;
784 uint64_t reserved_33_34:2;
785 uint64_t p1_ptout:1;
786 uint64_t p0_ptout:1;
787 uint64_t reserved_29_30:2;
788 uint64_t p1_pperr:1;
789 uint64_t p0_pperr:1;
790 uint64_t reserved_25_26:2;
791 uint64_t g1_rtout:1;
792 uint64_t g0_rtout:1;
793 uint64_t reserved_21_22:2;
794 uint64_t p1_perr:1;
795 uint64_t p0_perr:1;
796 uint64_t reserved_17_18:2;
797 uint64_t p1_rtout:1;
798 uint64_t p0_rtout:1;
799 uint64_t reserved_13_14:2;
800 uint64_t i1_overf:1;
801 uint64_t i0_overf:1;
802 uint64_t reserved_9_10:2;
803 uint64_t i1_rtout:1;
804 uint64_t i0_rtout:1;
805 uint64_t reserved_5_6:2;
806 uint64_t po1_2sml:1;
807 uint64_t po0_2sml:1;
808 uint64_t pci_rsl:1;
809 uint64_t rml_wto:1;
810 uint64_t rml_rto:1;
811 } cn31xx;
812 struct cvmx_npi_int_enb_s cn38xx;
813 struct cvmx_npi_int_enb_cn38xxp2 {
814 uint64_t reserved_42_63:22;
815 uint64_t iobdma:1;
816 uint64_t p_dperr:1;
817 uint64_t win_rto:1;
818 uint64_t i3_pperr:1;
819 uint64_t i2_pperr:1;
820 uint64_t i1_pperr:1;
821 uint64_t i0_pperr:1;
822 uint64_t p3_ptout:1;
823 uint64_t p2_ptout:1;
824 uint64_t p1_ptout:1;
825 uint64_t p0_ptout:1;
826 uint64_t p3_pperr:1;
827 uint64_t p2_pperr:1;
828 uint64_t p1_pperr:1;
829 uint64_t p0_pperr:1;
830 uint64_t g3_rtout:1;
831 uint64_t g2_rtout:1;
832 uint64_t g1_rtout:1;
833 uint64_t g0_rtout:1;
834 uint64_t p3_perr:1;
835 uint64_t p2_perr:1;
836 uint64_t p1_perr:1;
837 uint64_t p0_perr:1;
838 uint64_t p3_rtout:1;
839 uint64_t p2_rtout:1;
840 uint64_t p1_rtout:1;
841 uint64_t p0_rtout:1;
842 uint64_t i3_overf:1;
843 uint64_t i2_overf:1;
844 uint64_t i1_overf:1;
845 uint64_t i0_overf:1;
846 uint64_t i3_rtout:1;
847 uint64_t i2_rtout:1;
848 uint64_t i1_rtout:1;
849 uint64_t i0_rtout:1;
850 uint64_t po3_2sml:1;
851 uint64_t po2_2sml:1;
852 uint64_t po1_2sml:1;
853 uint64_t po0_2sml:1;
854 uint64_t pci_rsl:1;
855 uint64_t rml_wto:1;
856 uint64_t rml_rto:1;
857 } cn38xxp2;
858 struct cvmx_npi_int_enb_cn31xx cn50xx;
859 struct cvmx_npi_int_enb_s cn58xx;
860 struct cvmx_npi_int_enb_s cn58xxp1;
861};
862
863union cvmx_npi_int_sum {
864 uint64_t u64;
865 struct cvmx_npi_int_sum_s {
866 uint64_t reserved_62_63:2;
867 uint64_t q1_a_f:1;
868 uint64_t q1_s_e:1;
869 uint64_t pdf_p_f:1;
870 uint64_t pdf_p_e:1;
871 uint64_t pcf_p_f:1;
872 uint64_t pcf_p_e:1;
873 uint64_t rdx_s_e:1;
874 uint64_t rwx_s_e:1;
875 uint64_t pnc_a_f:1;
876 uint64_t pnc_s_e:1;
877 uint64_t com_a_f:1;
878 uint64_t com_s_e:1;
879 uint64_t q3_a_f:1;
880 uint64_t q3_s_e:1;
881 uint64_t q2_a_f:1;
882 uint64_t q2_s_e:1;
883 uint64_t pcr_a_f:1;
884 uint64_t pcr_s_e:1;
885 uint64_t fcr_a_f:1;
886 uint64_t fcr_s_e:1;
887 uint64_t iobdma:1;
888 uint64_t p_dperr:1;
889 uint64_t win_rto:1;
890 uint64_t i3_pperr:1;
891 uint64_t i2_pperr:1;
892 uint64_t i1_pperr:1;
893 uint64_t i0_pperr:1;
894 uint64_t p3_ptout:1;
895 uint64_t p2_ptout:1;
896 uint64_t p1_ptout:1;
897 uint64_t p0_ptout:1;
898 uint64_t p3_pperr:1;
899 uint64_t p2_pperr:1;
900 uint64_t p1_pperr:1;
901 uint64_t p0_pperr:1;
902 uint64_t g3_rtout:1;
903 uint64_t g2_rtout:1;
904 uint64_t g1_rtout:1;
905 uint64_t g0_rtout:1;
906 uint64_t p3_perr:1;
907 uint64_t p2_perr:1;
908 uint64_t p1_perr:1;
909 uint64_t p0_perr:1;
910 uint64_t p3_rtout:1;
911 uint64_t p2_rtout:1;
912 uint64_t p1_rtout:1;
913 uint64_t p0_rtout:1;
914 uint64_t i3_overf:1;
915 uint64_t i2_overf:1;
916 uint64_t i1_overf:1;
917 uint64_t i0_overf:1;
918 uint64_t i3_rtout:1;
919 uint64_t i2_rtout:1;
920 uint64_t i1_rtout:1;
921 uint64_t i0_rtout:1;
922 uint64_t po3_2sml:1;
923 uint64_t po2_2sml:1;
924 uint64_t po1_2sml:1;
925 uint64_t po0_2sml:1;
926 uint64_t pci_rsl:1;
927 uint64_t rml_wto:1;
928 uint64_t rml_rto:1;
929 } s;
930 struct cvmx_npi_int_sum_cn30xx {
931 uint64_t reserved_62_63:2;
932 uint64_t q1_a_f:1;
933 uint64_t q1_s_e:1;
934 uint64_t pdf_p_f:1;
935 uint64_t pdf_p_e:1;
936 uint64_t pcf_p_f:1;
937 uint64_t pcf_p_e:1;
938 uint64_t rdx_s_e:1;
939 uint64_t rwx_s_e:1;
940 uint64_t pnc_a_f:1;
941 uint64_t pnc_s_e:1;
942 uint64_t com_a_f:1;
943 uint64_t com_s_e:1;
944 uint64_t q3_a_f:1;
945 uint64_t q3_s_e:1;
946 uint64_t q2_a_f:1;
947 uint64_t q2_s_e:1;
948 uint64_t pcr_a_f:1;
949 uint64_t pcr_s_e:1;
950 uint64_t fcr_a_f:1;
951 uint64_t fcr_s_e:1;
952 uint64_t iobdma:1;
953 uint64_t p_dperr:1;
954 uint64_t win_rto:1;
955 uint64_t reserved_36_38:3;
956 uint64_t i0_pperr:1;
957 uint64_t reserved_32_34:3;
958 uint64_t p0_ptout:1;
959 uint64_t reserved_28_30:3;
960 uint64_t p0_pperr:1;
961 uint64_t reserved_24_26:3;
962 uint64_t g0_rtout:1;
963 uint64_t reserved_20_22:3;
964 uint64_t p0_perr:1;
965 uint64_t reserved_16_18:3;
966 uint64_t p0_rtout:1;
967 uint64_t reserved_12_14:3;
968 uint64_t i0_overf:1;
969 uint64_t reserved_8_10:3;
970 uint64_t i0_rtout:1;
971 uint64_t reserved_4_6:3;
972 uint64_t po0_2sml:1;
973 uint64_t pci_rsl:1;
974 uint64_t rml_wto:1;
975 uint64_t rml_rto:1;
976 } cn30xx;
977 struct cvmx_npi_int_sum_cn31xx {
978 uint64_t reserved_62_63:2;
979 uint64_t q1_a_f:1;
980 uint64_t q1_s_e:1;
981 uint64_t pdf_p_f:1;
982 uint64_t pdf_p_e:1;
983 uint64_t pcf_p_f:1;
984 uint64_t pcf_p_e:1;
985 uint64_t rdx_s_e:1;
986 uint64_t rwx_s_e:1;
987 uint64_t pnc_a_f:1;
988 uint64_t pnc_s_e:1;
989 uint64_t com_a_f:1;
990 uint64_t com_s_e:1;
991 uint64_t q3_a_f:1;
992 uint64_t q3_s_e:1;
993 uint64_t q2_a_f:1;
994 uint64_t q2_s_e:1;
995 uint64_t pcr_a_f:1;
996 uint64_t pcr_s_e:1;
997 uint64_t fcr_a_f:1;
998 uint64_t fcr_s_e:1;
999 uint64_t iobdma:1;
1000 uint64_t p_dperr:1;
1001 uint64_t win_rto:1;
1002 uint64_t reserved_37_38:2;
1003 uint64_t i1_pperr:1;
1004 uint64_t i0_pperr:1;
1005 uint64_t reserved_33_34:2;
1006 uint64_t p1_ptout:1;
1007 uint64_t p0_ptout:1;
1008 uint64_t reserved_29_30:2;
1009 uint64_t p1_pperr:1;
1010 uint64_t p0_pperr:1;
1011 uint64_t reserved_25_26:2;
1012 uint64_t g1_rtout:1;
1013 uint64_t g0_rtout:1;
1014 uint64_t reserved_21_22:2;
1015 uint64_t p1_perr:1;
1016 uint64_t p0_perr:1;
1017 uint64_t reserved_17_18:2;
1018 uint64_t p1_rtout:1;
1019 uint64_t p0_rtout:1;
1020 uint64_t reserved_13_14:2;
1021 uint64_t i1_overf:1;
1022 uint64_t i0_overf:1;
1023 uint64_t reserved_9_10:2;
1024 uint64_t i1_rtout:1;
1025 uint64_t i0_rtout:1;
1026 uint64_t reserved_5_6:2;
1027 uint64_t po1_2sml:1;
1028 uint64_t po0_2sml:1;
1029 uint64_t pci_rsl:1;
1030 uint64_t rml_wto:1;
1031 uint64_t rml_rto:1;
1032 } cn31xx;
1033 struct cvmx_npi_int_sum_s cn38xx;
1034 struct cvmx_npi_int_sum_cn38xxp2 {
1035 uint64_t reserved_42_63:22;
1036 uint64_t iobdma:1;
1037 uint64_t p_dperr:1;
1038 uint64_t win_rto:1;
1039 uint64_t i3_pperr:1;
1040 uint64_t i2_pperr:1;
1041 uint64_t i1_pperr:1;
1042 uint64_t i0_pperr:1;
1043 uint64_t p3_ptout:1;
1044 uint64_t p2_ptout:1;
1045 uint64_t p1_ptout:1;
1046 uint64_t p0_ptout:1;
1047 uint64_t p3_pperr:1;
1048 uint64_t p2_pperr:1;
1049 uint64_t p1_pperr:1;
1050 uint64_t p0_pperr:1;
1051 uint64_t g3_rtout:1;
1052 uint64_t g2_rtout:1;
1053 uint64_t g1_rtout:1;
1054 uint64_t g0_rtout:1;
1055 uint64_t p3_perr:1;
1056 uint64_t p2_perr:1;
1057 uint64_t p1_perr:1;
1058 uint64_t p0_perr:1;
1059 uint64_t p3_rtout:1;
1060 uint64_t p2_rtout:1;
1061 uint64_t p1_rtout:1;
1062 uint64_t p0_rtout:1;
1063 uint64_t i3_overf:1;
1064 uint64_t i2_overf:1;
1065 uint64_t i1_overf:1;
1066 uint64_t i0_overf:1;
1067 uint64_t i3_rtout:1;
1068 uint64_t i2_rtout:1;
1069 uint64_t i1_rtout:1;
1070 uint64_t i0_rtout:1;
1071 uint64_t po3_2sml:1;
1072 uint64_t po2_2sml:1;
1073 uint64_t po1_2sml:1;
1074 uint64_t po0_2sml:1;
1075 uint64_t pci_rsl:1;
1076 uint64_t rml_wto:1;
1077 uint64_t rml_rto:1;
1078 } cn38xxp2;
1079 struct cvmx_npi_int_sum_cn31xx cn50xx;
1080 struct cvmx_npi_int_sum_s cn58xx;
1081 struct cvmx_npi_int_sum_s cn58xxp1;
1082};
1083
1084union cvmx_npi_lowp_dbell {
1085 uint64_t u64;
1086 struct cvmx_npi_lowp_dbell_s {
1087 uint64_t reserved_16_63:48;
1088 uint64_t dbell:16;
1089 } s;
1090 struct cvmx_npi_lowp_dbell_s cn30xx;
1091 struct cvmx_npi_lowp_dbell_s cn31xx;
1092 struct cvmx_npi_lowp_dbell_s cn38xx;
1093 struct cvmx_npi_lowp_dbell_s cn38xxp2;
1094 struct cvmx_npi_lowp_dbell_s cn50xx;
1095 struct cvmx_npi_lowp_dbell_s cn58xx;
1096 struct cvmx_npi_lowp_dbell_s cn58xxp1;
1097};
1098
1099union cvmx_npi_lowp_ibuff_saddr {
1100 uint64_t u64;
1101 struct cvmx_npi_lowp_ibuff_saddr_s {
1102 uint64_t reserved_36_63:28;
1103 uint64_t saddr:36;
1104 } s;
1105 struct cvmx_npi_lowp_ibuff_saddr_s cn30xx;
1106 struct cvmx_npi_lowp_ibuff_saddr_s cn31xx;
1107 struct cvmx_npi_lowp_ibuff_saddr_s cn38xx;
1108 struct cvmx_npi_lowp_ibuff_saddr_s cn38xxp2;
1109 struct cvmx_npi_lowp_ibuff_saddr_s cn50xx;
1110 struct cvmx_npi_lowp_ibuff_saddr_s cn58xx;
1111 struct cvmx_npi_lowp_ibuff_saddr_s cn58xxp1;
1112};
1113
1114union cvmx_npi_mem_access_subidx {
1115 uint64_t u64;
1116 struct cvmx_npi_mem_access_subidx_s {
1117 uint64_t reserved_38_63:26;
1118 uint64_t shortl:1;
1119 uint64_t nmerge:1;
1120 uint64_t esr:2;
1121 uint64_t esw:2;
1122 uint64_t nsr:1;
1123 uint64_t nsw:1;
1124 uint64_t ror:1;
1125 uint64_t row:1;
1126 uint64_t ba:28;
1127 } s;
1128 struct cvmx_npi_mem_access_subidx_s cn30xx;
1129 struct cvmx_npi_mem_access_subidx_cn31xx {
1130 uint64_t reserved_36_63:28;
1131 uint64_t esr:2;
1132 uint64_t esw:2;
1133 uint64_t nsr:1;
1134 uint64_t nsw:1;
1135 uint64_t ror:1;
1136 uint64_t row:1;
1137 uint64_t ba:28;
1138 } cn31xx;
1139 struct cvmx_npi_mem_access_subidx_s cn38xx;
1140 struct cvmx_npi_mem_access_subidx_cn31xx cn38xxp2;
1141 struct cvmx_npi_mem_access_subidx_s cn50xx;
1142 struct cvmx_npi_mem_access_subidx_s cn58xx;
1143 struct cvmx_npi_mem_access_subidx_s cn58xxp1;
1144};
1145
1146union cvmx_npi_msi_rcv {
1147 uint64_t u64;
1148 struct cvmx_npi_msi_rcv_s {
1149 uint64_t int_vec:64;
1150 } s;
1151 struct cvmx_npi_msi_rcv_s cn30xx;
1152 struct cvmx_npi_msi_rcv_s cn31xx;
1153 struct cvmx_npi_msi_rcv_s cn38xx;
1154 struct cvmx_npi_msi_rcv_s cn38xxp2;
1155 struct cvmx_npi_msi_rcv_s cn50xx;
1156 struct cvmx_npi_msi_rcv_s cn58xx;
1157 struct cvmx_npi_msi_rcv_s cn58xxp1;
1158};
1159
1160union cvmx_npi_num_desc_outputx {
1161 uint64_t u64;
1162 struct cvmx_npi_num_desc_outputx_s {
1163 uint64_t reserved_32_63:32;
1164 uint64_t size:32;
1165 } s;
1166 struct cvmx_npi_num_desc_outputx_s cn30xx;
1167 struct cvmx_npi_num_desc_outputx_s cn31xx;
1168 struct cvmx_npi_num_desc_outputx_s cn38xx;
1169 struct cvmx_npi_num_desc_outputx_s cn38xxp2;
1170 struct cvmx_npi_num_desc_outputx_s cn50xx;
1171 struct cvmx_npi_num_desc_outputx_s cn58xx;
1172 struct cvmx_npi_num_desc_outputx_s cn58xxp1;
1173};
1174
1175union cvmx_npi_output_control {
1176 uint64_t u64;
1177 struct cvmx_npi_output_control_s {
1178 uint64_t reserved_49_63:15;
1179 uint64_t pkt_rr:1;
1180 uint64_t p3_bmode:1;
1181 uint64_t p2_bmode:1;
1182 uint64_t p1_bmode:1;
1183 uint64_t p0_bmode:1;
1184 uint64_t o3_es:2;
1185 uint64_t o3_ns:1;
1186 uint64_t o3_ro:1;
1187 uint64_t o2_es:2;
1188 uint64_t o2_ns:1;
1189 uint64_t o2_ro:1;
1190 uint64_t o1_es:2;
1191 uint64_t o1_ns:1;
1192 uint64_t o1_ro:1;
1193 uint64_t o0_es:2;
1194 uint64_t o0_ns:1;
1195 uint64_t o0_ro:1;
1196 uint64_t o3_csrm:1;
1197 uint64_t o2_csrm:1;
1198 uint64_t o1_csrm:1;
1199 uint64_t o0_csrm:1;
1200 uint64_t reserved_20_23:4;
1201 uint64_t iptr_o3:1;
1202 uint64_t iptr_o2:1;
1203 uint64_t iptr_o1:1;
1204 uint64_t iptr_o0:1;
1205 uint64_t esr_sl3:2;
1206 uint64_t nsr_sl3:1;
1207 uint64_t ror_sl3:1;
1208 uint64_t esr_sl2:2;
1209 uint64_t nsr_sl2:1;
1210 uint64_t ror_sl2:1;
1211 uint64_t esr_sl1:2;
1212 uint64_t nsr_sl1:1;
1213 uint64_t ror_sl1:1;
1214 uint64_t esr_sl0:2;
1215 uint64_t nsr_sl0:1;
1216 uint64_t ror_sl0:1;
1217 } s;
1218 struct cvmx_npi_output_control_cn30xx {
1219 uint64_t reserved_45_63:19;
1220 uint64_t p0_bmode:1;
1221 uint64_t reserved_32_43:12;
1222 uint64_t o0_es:2;
1223 uint64_t o0_ns:1;
1224 uint64_t o0_ro:1;
1225 uint64_t reserved_25_27:3;
1226 uint64_t o0_csrm:1;
1227 uint64_t reserved_17_23:7;
1228 uint64_t iptr_o0:1;
1229 uint64_t reserved_4_15:12;
1230 uint64_t esr_sl0:2;
1231 uint64_t nsr_sl0:1;
1232 uint64_t ror_sl0:1;
1233 } cn30xx;
1234 struct cvmx_npi_output_control_cn31xx {
1235 uint64_t reserved_46_63:18;
1236 uint64_t p1_bmode:1;
1237 uint64_t p0_bmode:1;
1238 uint64_t reserved_36_43:8;
1239 uint64_t o1_es:2;
1240 uint64_t o1_ns:1;
1241 uint64_t o1_ro:1;
1242 uint64_t o0_es:2;
1243 uint64_t o0_ns:1;
1244 uint64_t o0_ro:1;
1245 uint64_t reserved_26_27:2;
1246 uint64_t o1_csrm:1;
1247 uint64_t o0_csrm:1;
1248 uint64_t reserved_18_23:6;
1249 uint64_t iptr_o1:1;
1250 uint64_t iptr_o0:1;
1251 uint64_t reserved_8_15:8;
1252 uint64_t esr_sl1:2;
1253 uint64_t nsr_sl1:1;
1254 uint64_t ror_sl1:1;
1255 uint64_t esr_sl0:2;
1256 uint64_t nsr_sl0:1;
1257 uint64_t ror_sl0:1;
1258 } cn31xx;
1259 struct cvmx_npi_output_control_s cn38xx;
1260 struct cvmx_npi_output_control_cn38xxp2 {
1261 uint64_t reserved_48_63:16;
1262 uint64_t p3_bmode:1;
1263 uint64_t p2_bmode:1;
1264 uint64_t p1_bmode:1;
1265 uint64_t p0_bmode:1;
1266 uint64_t o3_es:2;
1267 uint64_t o3_ns:1;
1268 uint64_t o3_ro:1;
1269 uint64_t o2_es:2;
1270 uint64_t o2_ns:1;
1271 uint64_t o2_ro:1;
1272 uint64_t o1_es:2;
1273 uint64_t o1_ns:1;
1274 uint64_t o1_ro:1;
1275 uint64_t o0_es:2;
1276 uint64_t o0_ns:1;
1277 uint64_t o0_ro:1;
1278 uint64_t o3_csrm:1;
1279 uint64_t o2_csrm:1;
1280 uint64_t o1_csrm:1;
1281 uint64_t o0_csrm:1;
1282 uint64_t reserved_20_23:4;
1283 uint64_t iptr_o3:1;
1284 uint64_t iptr_o2:1;
1285 uint64_t iptr_o1:1;
1286 uint64_t iptr_o0:1;
1287 uint64_t esr_sl3:2;
1288 uint64_t nsr_sl3:1;
1289 uint64_t ror_sl3:1;
1290 uint64_t esr_sl2:2;
1291 uint64_t nsr_sl2:1;
1292 uint64_t ror_sl2:1;
1293 uint64_t esr_sl1:2;
1294 uint64_t nsr_sl1:1;
1295 uint64_t ror_sl1:1;
1296 uint64_t esr_sl0:2;
1297 uint64_t nsr_sl0:1;
1298 uint64_t ror_sl0:1;
1299 } cn38xxp2;
1300 struct cvmx_npi_output_control_cn50xx {
1301 uint64_t reserved_49_63:15;
1302 uint64_t pkt_rr:1;
1303 uint64_t reserved_46_47:2;
1304 uint64_t p1_bmode:1;
1305 uint64_t p0_bmode:1;
1306 uint64_t reserved_36_43:8;
1307 uint64_t o1_es:2;
1308 uint64_t o1_ns:1;
1309 uint64_t o1_ro:1;
1310 uint64_t o0_es:2;
1311 uint64_t o0_ns:1;
1312 uint64_t o0_ro:1;
1313 uint64_t reserved_26_27:2;
1314 uint64_t o1_csrm:1;
1315 uint64_t o0_csrm:1;
1316 uint64_t reserved_18_23:6;
1317 uint64_t iptr_o1:1;
1318 uint64_t iptr_o0:1;
1319 uint64_t reserved_8_15:8;
1320 uint64_t esr_sl1:2;
1321 uint64_t nsr_sl1:1;
1322 uint64_t ror_sl1:1;
1323 uint64_t esr_sl0:2;
1324 uint64_t nsr_sl0:1;
1325 uint64_t ror_sl0:1;
1326 } cn50xx;
1327 struct cvmx_npi_output_control_s cn58xx;
1328 struct cvmx_npi_output_control_s cn58xxp1;
1329};
1330
1331union cvmx_npi_px_dbpair_addr {
1332 uint64_t u64;
1333 struct cvmx_npi_px_dbpair_addr_s {
1334 uint64_t reserved_63_63:1;
1335 uint64_t state:2;
1336 uint64_t naddr:61;
1337 } s;
1338 struct cvmx_npi_px_dbpair_addr_s cn30xx;
1339 struct cvmx_npi_px_dbpair_addr_s cn31xx;
1340 struct cvmx_npi_px_dbpair_addr_s cn38xx;
1341 struct cvmx_npi_px_dbpair_addr_s cn38xxp2;
1342 struct cvmx_npi_px_dbpair_addr_s cn50xx;
1343 struct cvmx_npi_px_dbpair_addr_s cn58xx;
1344 struct cvmx_npi_px_dbpair_addr_s cn58xxp1;
1345};
1346
1347union cvmx_npi_px_instr_addr {
1348 uint64_t u64;
1349 struct cvmx_npi_px_instr_addr_s {
1350 uint64_t state:3;
1351 uint64_t naddr:61;
1352 } s;
1353 struct cvmx_npi_px_instr_addr_s cn30xx;
1354 struct cvmx_npi_px_instr_addr_s cn31xx;
1355 struct cvmx_npi_px_instr_addr_s cn38xx;
1356 struct cvmx_npi_px_instr_addr_s cn38xxp2;
1357 struct cvmx_npi_px_instr_addr_s cn50xx;
1358 struct cvmx_npi_px_instr_addr_s cn58xx;
1359 struct cvmx_npi_px_instr_addr_s cn58xxp1;
1360};
1361
1362union cvmx_npi_px_instr_cnts {
1363 uint64_t u64;
1364 struct cvmx_npi_px_instr_cnts_s {
1365 uint64_t reserved_38_63:26;
1366 uint64_t fcnt:6;
1367 uint64_t avail:32;
1368 } s;
1369 struct cvmx_npi_px_instr_cnts_s cn30xx;
1370 struct cvmx_npi_px_instr_cnts_s cn31xx;
1371 struct cvmx_npi_px_instr_cnts_s cn38xx;
1372 struct cvmx_npi_px_instr_cnts_s cn38xxp2;
1373 struct cvmx_npi_px_instr_cnts_s cn50xx;
1374 struct cvmx_npi_px_instr_cnts_s cn58xx;
1375 struct cvmx_npi_px_instr_cnts_s cn58xxp1;
1376};
1377
1378union cvmx_npi_px_pair_cnts {
1379 uint64_t u64;
1380 struct cvmx_npi_px_pair_cnts_s {
1381 uint64_t reserved_37_63:27;
1382 uint64_t fcnt:5;
1383 uint64_t avail:32;
1384 } s;
1385 struct cvmx_npi_px_pair_cnts_s cn30xx;
1386 struct cvmx_npi_px_pair_cnts_s cn31xx;
1387 struct cvmx_npi_px_pair_cnts_s cn38xx;
1388 struct cvmx_npi_px_pair_cnts_s cn38xxp2;
1389 struct cvmx_npi_px_pair_cnts_s cn50xx;
1390 struct cvmx_npi_px_pair_cnts_s cn58xx;
1391 struct cvmx_npi_px_pair_cnts_s cn58xxp1;
1392};
1393
1394union cvmx_npi_pci_burst_size {
1395 uint64_t u64;
1396 struct cvmx_npi_pci_burst_size_s {
1397 uint64_t reserved_14_63:50;
1398 uint64_t wr_brst:7;
1399 uint64_t rd_brst:7;
1400 } s;
1401 struct cvmx_npi_pci_burst_size_s cn30xx;
1402 struct cvmx_npi_pci_burst_size_s cn31xx;
1403 struct cvmx_npi_pci_burst_size_s cn38xx;
1404 struct cvmx_npi_pci_burst_size_s cn38xxp2;
1405 struct cvmx_npi_pci_burst_size_s cn50xx;
1406 struct cvmx_npi_pci_burst_size_s cn58xx;
1407 struct cvmx_npi_pci_burst_size_s cn58xxp1;
1408};
1409
1410union cvmx_npi_pci_int_arb_cfg {
1411 uint64_t u64;
1412 struct cvmx_npi_pci_int_arb_cfg_s {
1413 uint64_t reserved_13_63:51;
1414 uint64_t hostmode:1;
1415 uint64_t pci_ovr:4;
1416 uint64_t reserved_5_7:3;
1417 uint64_t en:1;
1418 uint64_t park_mod:1;
1419 uint64_t park_dev:3;
1420 } s;
1421 struct cvmx_npi_pci_int_arb_cfg_cn30xx {
1422 uint64_t reserved_5_63:59;
1423 uint64_t en:1;
1424 uint64_t park_mod:1;
1425 uint64_t park_dev:3;
1426 } cn30xx;
1427 struct cvmx_npi_pci_int_arb_cfg_cn30xx cn31xx;
1428 struct cvmx_npi_pci_int_arb_cfg_cn30xx cn38xx;
1429 struct cvmx_npi_pci_int_arb_cfg_cn30xx cn38xxp2;
1430 struct cvmx_npi_pci_int_arb_cfg_s cn50xx;
1431 struct cvmx_npi_pci_int_arb_cfg_s cn58xx;
1432 struct cvmx_npi_pci_int_arb_cfg_s cn58xxp1;
1433};
1434
1435union cvmx_npi_pci_read_cmd {
1436 uint64_t u64;
1437 struct cvmx_npi_pci_read_cmd_s {
1438 uint64_t reserved_11_63:53;
1439 uint64_t cmd_size:11;
1440 } s;
1441 struct cvmx_npi_pci_read_cmd_s cn30xx;
1442 struct cvmx_npi_pci_read_cmd_s cn31xx;
1443 struct cvmx_npi_pci_read_cmd_s cn38xx;
1444 struct cvmx_npi_pci_read_cmd_s cn38xxp2;
1445 struct cvmx_npi_pci_read_cmd_s cn50xx;
1446 struct cvmx_npi_pci_read_cmd_s cn58xx;
1447 struct cvmx_npi_pci_read_cmd_s cn58xxp1;
1448};
1449
1450union cvmx_npi_port32_instr_hdr {
1451 uint64_t u64;
1452 struct cvmx_npi_port32_instr_hdr_s {
1453 uint64_t reserved_44_63:20;
1454 uint64_t pbp:1;
1455 uint64_t rsv_f:5;
1456 uint64_t rparmode:2;
1457 uint64_t rsv_e:1;
1458 uint64_t rskp_len:7;
1459 uint64_t rsv_d:6;
1460 uint64_t use_ihdr:1;
1461 uint64_t rsv_c:5;
1462 uint64_t par_mode:2;
1463 uint64_t rsv_b:1;
1464 uint64_t skp_len:7;
1465 uint64_t rsv_a:6;
1466 } s;
1467 struct cvmx_npi_port32_instr_hdr_s cn30xx;
1468 struct cvmx_npi_port32_instr_hdr_s cn31xx;
1469 struct cvmx_npi_port32_instr_hdr_s cn38xx;
1470 struct cvmx_npi_port32_instr_hdr_s cn38xxp2;
1471 struct cvmx_npi_port32_instr_hdr_s cn50xx;
1472 struct cvmx_npi_port32_instr_hdr_s cn58xx;
1473 struct cvmx_npi_port32_instr_hdr_s cn58xxp1;
1474};
1475
1476union cvmx_npi_port33_instr_hdr {
1477 uint64_t u64;
1478 struct cvmx_npi_port33_instr_hdr_s {
1479 uint64_t reserved_44_63:20;
1480 uint64_t pbp:1;
1481 uint64_t rsv_f:5;
1482 uint64_t rparmode:2;
1483 uint64_t rsv_e:1;
1484 uint64_t rskp_len:7;
1485 uint64_t rsv_d:6;
1486 uint64_t use_ihdr:1;
1487 uint64_t rsv_c:5;
1488 uint64_t par_mode:2;
1489 uint64_t rsv_b:1;
1490 uint64_t skp_len:7;
1491 uint64_t rsv_a:6;
1492 } s;
1493 struct cvmx_npi_port33_instr_hdr_s cn31xx;
1494 struct cvmx_npi_port33_instr_hdr_s cn38xx;
1495 struct cvmx_npi_port33_instr_hdr_s cn38xxp2;
1496 struct cvmx_npi_port33_instr_hdr_s cn50xx;
1497 struct cvmx_npi_port33_instr_hdr_s cn58xx;
1498 struct cvmx_npi_port33_instr_hdr_s cn58xxp1;
1499};
1500
1501union cvmx_npi_port34_instr_hdr {
1502 uint64_t u64;
1503 struct cvmx_npi_port34_instr_hdr_s {
1504 uint64_t reserved_44_63:20;
1505 uint64_t pbp:1;
1506 uint64_t rsv_f:5;
1507 uint64_t rparmode:2;
1508 uint64_t rsv_e:1;
1509 uint64_t rskp_len:7;
1510 uint64_t rsv_d:6;
1511 uint64_t use_ihdr:1;
1512 uint64_t rsv_c:5;
1513 uint64_t par_mode:2;
1514 uint64_t rsv_b:1;
1515 uint64_t skp_len:7;
1516 uint64_t rsv_a:6;
1517 } s;
1518 struct cvmx_npi_port34_instr_hdr_s cn38xx;
1519 struct cvmx_npi_port34_instr_hdr_s cn38xxp2;
1520 struct cvmx_npi_port34_instr_hdr_s cn58xx;
1521 struct cvmx_npi_port34_instr_hdr_s cn58xxp1;
1522};
1523
1524union cvmx_npi_port35_instr_hdr {
1525 uint64_t u64;
1526 struct cvmx_npi_port35_instr_hdr_s {
1527 uint64_t reserved_44_63:20;
1528 uint64_t pbp:1;
1529 uint64_t rsv_f:5;
1530 uint64_t rparmode:2;
1531 uint64_t rsv_e:1;
1532 uint64_t rskp_len:7;
1533 uint64_t rsv_d:6;
1534 uint64_t use_ihdr:1;
1535 uint64_t rsv_c:5;
1536 uint64_t par_mode:2;
1537 uint64_t rsv_b:1;
1538 uint64_t skp_len:7;
1539 uint64_t rsv_a:6;
1540 } s;
1541 struct cvmx_npi_port35_instr_hdr_s cn38xx;
1542 struct cvmx_npi_port35_instr_hdr_s cn38xxp2;
1543 struct cvmx_npi_port35_instr_hdr_s cn58xx;
1544 struct cvmx_npi_port35_instr_hdr_s cn58xxp1;
1545};
1546
1547union cvmx_npi_port_bp_control {
1548 uint64_t u64;
1549 struct cvmx_npi_port_bp_control_s {
1550 uint64_t reserved_8_63:56;
1551 uint64_t bp_on:4;
1552 uint64_t enb:4;
1553 } s;
1554 struct cvmx_npi_port_bp_control_s cn30xx;
1555 struct cvmx_npi_port_bp_control_s cn31xx;
1556 struct cvmx_npi_port_bp_control_s cn38xx;
1557 struct cvmx_npi_port_bp_control_s cn38xxp2;
1558 struct cvmx_npi_port_bp_control_s cn50xx;
1559 struct cvmx_npi_port_bp_control_s cn58xx;
1560 struct cvmx_npi_port_bp_control_s cn58xxp1;
1561};
1562
1563union cvmx_npi_rsl_int_blocks {
1564 uint64_t u64;
1565 struct cvmx_npi_rsl_int_blocks_s {
1566 uint64_t reserved_32_63:32;
1567 uint64_t rint_31:1;
1568 uint64_t iob:1;
1569 uint64_t reserved_28_29:2;
1570 uint64_t rint_27:1;
1571 uint64_t rint_26:1;
1572 uint64_t rint_25:1;
1573 uint64_t rint_24:1;
1574 uint64_t asx1:1;
1575 uint64_t asx0:1;
1576 uint64_t rint_21:1;
1577 uint64_t pip:1;
1578 uint64_t spx1:1;
1579 uint64_t spx0:1;
1580 uint64_t lmc:1;
1581 uint64_t l2c:1;
1582 uint64_t rint_15:1;
1583 uint64_t reserved_13_14:2;
1584 uint64_t pow:1;
1585 uint64_t tim:1;
1586 uint64_t pko:1;
1587 uint64_t ipd:1;
1588 uint64_t rint_8:1;
1589 uint64_t zip:1;
1590 uint64_t dfa:1;
1591 uint64_t fpa:1;
1592 uint64_t key:1;
1593 uint64_t npi:1;
1594 uint64_t gmx1:1;
1595 uint64_t gmx0:1;
1596 uint64_t mio:1;
1597 } s;
1598 struct cvmx_npi_rsl_int_blocks_cn30xx {
1599 uint64_t reserved_32_63:32;
1600 uint64_t rint_31:1;
1601 uint64_t iob:1;
1602 uint64_t rint_29:1;
1603 uint64_t rint_28:1;
1604 uint64_t rint_27:1;
1605 uint64_t rint_26:1;
1606 uint64_t rint_25:1;
1607 uint64_t rint_24:1;
1608 uint64_t asx1:1;
1609 uint64_t asx0:1;
1610 uint64_t rint_21:1;
1611 uint64_t pip:1;
1612 uint64_t spx1:1;
1613 uint64_t spx0:1;
1614 uint64_t lmc:1;
1615 uint64_t l2c:1;
1616 uint64_t rint_15:1;
1617 uint64_t rint_14:1;
1618 uint64_t usb:1;
1619 uint64_t pow:1;
1620 uint64_t tim:1;
1621 uint64_t pko:1;
1622 uint64_t ipd:1;
1623 uint64_t rint_8:1;
1624 uint64_t zip:1;
1625 uint64_t dfa:1;
1626 uint64_t fpa:1;
1627 uint64_t key:1;
1628 uint64_t npi:1;
1629 uint64_t gmx1:1;
1630 uint64_t gmx0:1;
1631 uint64_t mio:1;
1632 } cn30xx;
1633 struct cvmx_npi_rsl_int_blocks_cn30xx cn31xx;
1634 struct cvmx_npi_rsl_int_blocks_cn38xx {
1635 uint64_t reserved_32_63:32;
1636 uint64_t rint_31:1;
1637 uint64_t iob:1;
1638 uint64_t rint_29:1;
1639 uint64_t rint_28:1;
1640 uint64_t rint_27:1;
1641 uint64_t rint_26:1;
1642 uint64_t rint_25:1;
1643 uint64_t rint_24:1;
1644 uint64_t asx1:1;
1645 uint64_t asx0:1;
1646 uint64_t rint_21:1;
1647 uint64_t pip:1;
1648 uint64_t spx1:1;
1649 uint64_t spx0:1;
1650 uint64_t lmc:1;
1651 uint64_t l2c:1;
1652 uint64_t rint_15:1;
1653 uint64_t rint_14:1;
1654 uint64_t rint_13:1;
1655 uint64_t pow:1;
1656 uint64_t tim:1;
1657 uint64_t pko:1;
1658 uint64_t ipd:1;
1659 uint64_t rint_8:1;
1660 uint64_t zip:1;
1661 uint64_t dfa:1;
1662 uint64_t fpa:1;
1663 uint64_t key:1;
1664 uint64_t npi:1;
1665 uint64_t gmx1:1;
1666 uint64_t gmx0:1;
1667 uint64_t mio:1;
1668 } cn38xx;
1669 struct cvmx_npi_rsl_int_blocks_cn38xx cn38xxp2;
1670 struct cvmx_npi_rsl_int_blocks_cn50xx {
1671 uint64_t reserved_31_63:33;
1672 uint64_t iob:1;
1673 uint64_t lmc1:1;
1674 uint64_t agl:1;
1675 uint64_t reserved_24_27:4;
1676 uint64_t asx1:1;
1677 uint64_t asx0:1;
1678 uint64_t reserved_21_21:1;
1679 uint64_t pip:1;
1680 uint64_t spx1:1;
1681 uint64_t spx0:1;
1682 uint64_t lmc:1;
1683 uint64_t l2c:1;
1684 uint64_t reserved_15_15:1;
1685 uint64_t rad:1;
1686 uint64_t usb:1;
1687 uint64_t pow:1;
1688 uint64_t tim:1;
1689 uint64_t pko:1;
1690 uint64_t ipd:1;
1691 uint64_t reserved_8_8:1;
1692 uint64_t zip:1;
1693 uint64_t dfa:1;
1694 uint64_t fpa:1;
1695 uint64_t key:1;
1696 uint64_t npi:1;
1697 uint64_t gmx1:1;
1698 uint64_t gmx0:1;
1699 uint64_t mio:1;
1700 } cn50xx;
1701 struct cvmx_npi_rsl_int_blocks_cn38xx cn58xx;
1702 struct cvmx_npi_rsl_int_blocks_cn38xx cn58xxp1;
1703};
1704
1705union cvmx_npi_size_inputx {
1706 uint64_t u64;
1707 struct cvmx_npi_size_inputx_s {
1708 uint64_t reserved_32_63:32;
1709 uint64_t size:32;
1710 } s;
1711 struct cvmx_npi_size_inputx_s cn30xx;
1712 struct cvmx_npi_size_inputx_s cn31xx;
1713 struct cvmx_npi_size_inputx_s cn38xx;
1714 struct cvmx_npi_size_inputx_s cn38xxp2;
1715 struct cvmx_npi_size_inputx_s cn50xx;
1716 struct cvmx_npi_size_inputx_s cn58xx;
1717 struct cvmx_npi_size_inputx_s cn58xxp1;
1718};
1719
1720union cvmx_npi_win_read_to {
1721 uint64_t u64;
1722 struct cvmx_npi_win_read_to_s {
1723 uint64_t reserved_32_63:32;
1724 uint64_t time:32;
1725 } s;
1726 struct cvmx_npi_win_read_to_s cn30xx;
1727 struct cvmx_npi_win_read_to_s cn31xx;
1728 struct cvmx_npi_win_read_to_s cn38xx;
1729 struct cvmx_npi_win_read_to_s cn38xxp2;
1730 struct cvmx_npi_win_read_to_s cn50xx;
1731 struct cvmx_npi_win_read_to_s cn58xx;
1732 struct cvmx_npi_win_read_to_s cn58xxp1;
1733};
1734
1735#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-pci-defs.h b/arch/mips/include/asm/octeon/cvmx-pci-defs.h
new file mode 100644
index 000000000000..90f8d6535753
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-pci-defs.h
@@ -0,0 +1,1645 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_PCI_DEFS_H__
29#define __CVMX_PCI_DEFS_H__
30
31#define CVMX_PCI_BAR1_INDEXX(offset) \
32 (0x0000000000000100ull + (((offset) & 31) * 4))
33#define CVMX_PCI_BIST_REG \
34 (0x00000000000001C0ull)
35#define CVMX_PCI_CFG00 \
36 (0x0000000000000000ull)
37#define CVMX_PCI_CFG01 \
38 (0x0000000000000004ull)
39#define CVMX_PCI_CFG02 \
40 (0x0000000000000008ull)
41#define CVMX_PCI_CFG03 \
42 (0x000000000000000Cull)
43#define CVMX_PCI_CFG04 \
44 (0x0000000000000010ull)
45#define CVMX_PCI_CFG05 \
46 (0x0000000000000014ull)
47#define CVMX_PCI_CFG06 \
48 (0x0000000000000018ull)
49#define CVMX_PCI_CFG07 \
50 (0x000000000000001Cull)
51#define CVMX_PCI_CFG08 \
52 (0x0000000000000020ull)
53#define CVMX_PCI_CFG09 \
54 (0x0000000000000024ull)
55#define CVMX_PCI_CFG10 \
56 (0x0000000000000028ull)
57#define CVMX_PCI_CFG11 \
58 (0x000000000000002Cull)
59#define CVMX_PCI_CFG12 \
60 (0x0000000000000030ull)
61#define CVMX_PCI_CFG13 \
62 (0x0000000000000034ull)
63#define CVMX_PCI_CFG15 \
64 (0x000000000000003Cull)
65#define CVMX_PCI_CFG16 \
66 (0x0000000000000040ull)
67#define CVMX_PCI_CFG17 \
68 (0x0000000000000044ull)
69#define CVMX_PCI_CFG18 \
70 (0x0000000000000048ull)
71#define CVMX_PCI_CFG19 \
72 (0x000000000000004Cull)
73#define CVMX_PCI_CFG20 \
74 (0x0000000000000050ull)
75#define CVMX_PCI_CFG21 \
76 (0x0000000000000054ull)
77#define CVMX_PCI_CFG22 \
78 (0x0000000000000058ull)
79#define CVMX_PCI_CFG56 \
80 (0x00000000000000E0ull)
81#define CVMX_PCI_CFG57 \
82 (0x00000000000000E4ull)
83#define CVMX_PCI_CFG58 \
84 (0x00000000000000E8ull)
85#define CVMX_PCI_CFG59 \
86 (0x00000000000000ECull)
87#define CVMX_PCI_CFG60 \
88 (0x00000000000000F0ull)
89#define CVMX_PCI_CFG61 \
90 (0x00000000000000F4ull)
91#define CVMX_PCI_CFG62 \
92 (0x00000000000000F8ull)
93#define CVMX_PCI_CFG63 \
94 (0x00000000000000FCull)
95#define CVMX_PCI_CNT_REG \
96 (0x00000000000001B8ull)
97#define CVMX_PCI_CTL_STATUS_2 \
98 (0x000000000000018Cull)
99#define CVMX_PCI_DBELL_0 \
100 (0x0000000000000080ull)
101#define CVMX_PCI_DBELL_1 \
102 (0x0000000000000088ull)
103#define CVMX_PCI_DBELL_2 \
104 (0x0000000000000090ull)
105#define CVMX_PCI_DBELL_3 \
106 (0x0000000000000098ull)
107#define CVMX_PCI_DBELL_X(offset) \
108 (0x0000000000000080ull + (((offset) & 3) * 8))
109#define CVMX_PCI_DMA_CNT0 \
110 (0x00000000000000A0ull)
111#define CVMX_PCI_DMA_CNT1 \
112 (0x00000000000000A8ull)
113#define CVMX_PCI_DMA_CNTX(offset) \
114 (0x00000000000000A0ull + (((offset) & 1) * 8))
115#define CVMX_PCI_DMA_INT_LEV0 \
116 (0x00000000000000A4ull)
117#define CVMX_PCI_DMA_INT_LEV1 \
118 (0x00000000000000ACull)
119#define CVMX_PCI_DMA_INT_LEVX(offset) \
120 (0x00000000000000A4ull + (((offset) & 1) * 8))
121#define CVMX_PCI_DMA_TIME0 \
122 (0x00000000000000B0ull)
123#define CVMX_PCI_DMA_TIME1 \
124 (0x00000000000000B4ull)
125#define CVMX_PCI_DMA_TIMEX(offset) \
126 (0x00000000000000B0ull + (((offset) & 1) * 4))
127#define CVMX_PCI_INSTR_COUNT0 \
128 (0x0000000000000084ull)
129#define CVMX_PCI_INSTR_COUNT1 \
130 (0x000000000000008Cull)
131#define CVMX_PCI_INSTR_COUNT2 \
132 (0x0000000000000094ull)
133#define CVMX_PCI_INSTR_COUNT3 \
134 (0x000000000000009Cull)
135#define CVMX_PCI_INSTR_COUNTX(offset) \
136 (0x0000000000000084ull + (((offset) & 3) * 8))
137#define CVMX_PCI_INT_ENB \
138 (0x0000000000000038ull)
139#define CVMX_PCI_INT_ENB2 \
140 (0x00000000000001A0ull)
141#define CVMX_PCI_INT_SUM \
142 (0x0000000000000030ull)
143#define CVMX_PCI_INT_SUM2 \
144 (0x0000000000000198ull)
145#define CVMX_PCI_MSI_RCV \
146 (0x00000000000000F0ull)
147#define CVMX_PCI_PKTS_SENT0 \
148 (0x0000000000000040ull)
149#define CVMX_PCI_PKTS_SENT1 \
150 (0x0000000000000050ull)
151#define CVMX_PCI_PKTS_SENT2 \
152 (0x0000000000000060ull)
153#define CVMX_PCI_PKTS_SENT3 \
154 (0x0000000000000070ull)
155#define CVMX_PCI_PKTS_SENTX(offset) \
156 (0x0000000000000040ull + (((offset) & 3) * 16))
157#define CVMX_PCI_PKTS_SENT_INT_LEV0 \
158 (0x0000000000000048ull)
159#define CVMX_PCI_PKTS_SENT_INT_LEV1 \
160 (0x0000000000000058ull)
161#define CVMX_PCI_PKTS_SENT_INT_LEV2 \
162 (0x0000000000000068ull)
163#define CVMX_PCI_PKTS_SENT_INT_LEV3 \
164 (0x0000000000000078ull)
165#define CVMX_PCI_PKTS_SENT_INT_LEVX(offset) \
166 (0x0000000000000048ull + (((offset) & 3) * 16))
167#define CVMX_PCI_PKTS_SENT_TIME0 \
168 (0x000000000000004Cull)
169#define CVMX_PCI_PKTS_SENT_TIME1 \
170 (0x000000000000005Cull)
171#define CVMX_PCI_PKTS_SENT_TIME2 \
172 (0x000000000000006Cull)
173#define CVMX_PCI_PKTS_SENT_TIME3 \
174 (0x000000000000007Cull)
175#define CVMX_PCI_PKTS_SENT_TIMEX(offset) \
176 (0x000000000000004Cull + (((offset) & 3) * 16))
177#define CVMX_PCI_PKT_CREDITS0 \
178 (0x0000000000000044ull)
179#define CVMX_PCI_PKT_CREDITS1 \
180 (0x0000000000000054ull)
181#define CVMX_PCI_PKT_CREDITS2 \
182 (0x0000000000000064ull)
183#define CVMX_PCI_PKT_CREDITS3 \
184 (0x0000000000000074ull)
185#define CVMX_PCI_PKT_CREDITSX(offset) \
186 (0x0000000000000044ull + (((offset) & 3) * 16))
187#define CVMX_PCI_READ_CMD_6 \
188 (0x0000000000000180ull)
189#define CVMX_PCI_READ_CMD_C \
190 (0x0000000000000184ull)
191#define CVMX_PCI_READ_CMD_E \
192 (0x0000000000000188ull)
193#define CVMX_PCI_READ_TIMEOUT \
194 CVMX_ADD_IO_SEG(0x00011F00000000B0ull)
195#define CVMX_PCI_SCM_REG \
196 (0x00000000000001A8ull)
197#define CVMX_PCI_TSR_REG \
198 (0x00000000000001B0ull)
199#define CVMX_PCI_WIN_RD_ADDR \
200 (0x0000000000000008ull)
201#define CVMX_PCI_WIN_RD_DATA \
202 (0x0000000000000020ull)
203#define CVMX_PCI_WIN_WR_ADDR \
204 (0x0000000000000000ull)
205#define CVMX_PCI_WIN_WR_DATA \
206 (0x0000000000000010ull)
207#define CVMX_PCI_WIN_WR_MASK \
208 (0x0000000000000018ull)
209
210union cvmx_pci_bar1_indexx {
211 uint32_t u32;
212 struct cvmx_pci_bar1_indexx_s {
213 uint32_t reserved_18_31:14;
214 uint32_t addr_idx:14;
215 uint32_t ca:1;
216 uint32_t end_swp:2;
217 uint32_t addr_v:1;
218 } s;
219 struct cvmx_pci_bar1_indexx_s cn30xx;
220 struct cvmx_pci_bar1_indexx_s cn31xx;
221 struct cvmx_pci_bar1_indexx_s cn38xx;
222 struct cvmx_pci_bar1_indexx_s cn38xxp2;
223 struct cvmx_pci_bar1_indexx_s cn50xx;
224 struct cvmx_pci_bar1_indexx_s cn58xx;
225 struct cvmx_pci_bar1_indexx_s cn58xxp1;
226};
227
228union cvmx_pci_bist_reg {
229 uint64_t u64;
230 struct cvmx_pci_bist_reg_s {
231 uint64_t reserved_10_63:54;
232 uint64_t rsp_bs:1;
233 uint64_t dma0_bs:1;
234 uint64_t cmd0_bs:1;
235 uint64_t cmd_bs:1;
236 uint64_t csr2p_bs:1;
237 uint64_t csrr_bs:1;
238 uint64_t rsp2p_bs:1;
239 uint64_t csr2n_bs:1;
240 uint64_t dat2n_bs:1;
241 uint64_t dbg2n_bs:1;
242 } s;
243 struct cvmx_pci_bist_reg_s cn50xx;
244};
245
246union cvmx_pci_cfg00 {
247 uint32_t u32;
248 struct cvmx_pci_cfg00_s {
249 uint32_t devid:16;
250 uint32_t vendid:16;
251 } s;
252 struct cvmx_pci_cfg00_s cn30xx;
253 struct cvmx_pci_cfg00_s cn31xx;
254 struct cvmx_pci_cfg00_s cn38xx;
255 struct cvmx_pci_cfg00_s cn38xxp2;
256 struct cvmx_pci_cfg00_s cn50xx;
257 struct cvmx_pci_cfg00_s cn58xx;
258 struct cvmx_pci_cfg00_s cn58xxp1;
259};
260
261union cvmx_pci_cfg01 {
262 uint32_t u32;
263 struct cvmx_pci_cfg01_s {
264 uint32_t dpe:1;
265 uint32_t sse:1;
266 uint32_t rma:1;
267 uint32_t rta:1;
268 uint32_t sta:1;
269 uint32_t devt:2;
270 uint32_t mdpe:1;
271 uint32_t fbb:1;
272 uint32_t reserved_22_22:1;
273 uint32_t m66:1;
274 uint32_t cle:1;
275 uint32_t i_stat:1;
276 uint32_t reserved_11_18:8;
277 uint32_t i_dis:1;
278 uint32_t fbbe:1;
279 uint32_t see:1;
280 uint32_t ads:1;
281 uint32_t pee:1;
282 uint32_t vps:1;
283 uint32_t mwice:1;
284 uint32_t scse:1;
285 uint32_t me:1;
286 uint32_t msae:1;
287 uint32_t isae:1;
288 } s;
289 struct cvmx_pci_cfg01_s cn30xx;
290 struct cvmx_pci_cfg01_s cn31xx;
291 struct cvmx_pci_cfg01_s cn38xx;
292 struct cvmx_pci_cfg01_s cn38xxp2;
293 struct cvmx_pci_cfg01_s cn50xx;
294 struct cvmx_pci_cfg01_s cn58xx;
295 struct cvmx_pci_cfg01_s cn58xxp1;
296};
297
298union cvmx_pci_cfg02 {
299 uint32_t u32;
300 struct cvmx_pci_cfg02_s {
301 uint32_t cc:24;
302 uint32_t rid:8;
303 } s;
304 struct cvmx_pci_cfg02_s cn30xx;
305 struct cvmx_pci_cfg02_s cn31xx;
306 struct cvmx_pci_cfg02_s cn38xx;
307 struct cvmx_pci_cfg02_s cn38xxp2;
308 struct cvmx_pci_cfg02_s cn50xx;
309 struct cvmx_pci_cfg02_s cn58xx;
310 struct cvmx_pci_cfg02_s cn58xxp1;
311};
312
313union cvmx_pci_cfg03 {
314 uint32_t u32;
315 struct cvmx_pci_cfg03_s {
316 uint32_t bcap:1;
317 uint32_t brb:1;
318 uint32_t reserved_28_29:2;
319 uint32_t bcod:4;
320 uint32_t ht:8;
321 uint32_t lt:8;
322 uint32_t cls:8;
323 } s;
324 struct cvmx_pci_cfg03_s cn30xx;
325 struct cvmx_pci_cfg03_s cn31xx;
326 struct cvmx_pci_cfg03_s cn38xx;
327 struct cvmx_pci_cfg03_s cn38xxp2;
328 struct cvmx_pci_cfg03_s cn50xx;
329 struct cvmx_pci_cfg03_s cn58xx;
330 struct cvmx_pci_cfg03_s cn58xxp1;
331};
332
333union cvmx_pci_cfg04 {
334 uint32_t u32;
335 struct cvmx_pci_cfg04_s {
336 uint32_t lbase:20;
337 uint32_t lbasez:8;
338 uint32_t pf:1;
339 uint32_t typ:2;
340 uint32_t mspc:1;
341 } s;
342 struct cvmx_pci_cfg04_s cn30xx;
343 struct cvmx_pci_cfg04_s cn31xx;
344 struct cvmx_pci_cfg04_s cn38xx;
345 struct cvmx_pci_cfg04_s cn38xxp2;
346 struct cvmx_pci_cfg04_s cn50xx;
347 struct cvmx_pci_cfg04_s cn58xx;
348 struct cvmx_pci_cfg04_s cn58xxp1;
349};
350
351union cvmx_pci_cfg05 {
352 uint32_t u32;
353 struct cvmx_pci_cfg05_s {
354 uint32_t hbase:32;
355 } s;
356 struct cvmx_pci_cfg05_s cn30xx;
357 struct cvmx_pci_cfg05_s cn31xx;
358 struct cvmx_pci_cfg05_s cn38xx;
359 struct cvmx_pci_cfg05_s cn38xxp2;
360 struct cvmx_pci_cfg05_s cn50xx;
361 struct cvmx_pci_cfg05_s cn58xx;
362 struct cvmx_pci_cfg05_s cn58xxp1;
363};
364
365union cvmx_pci_cfg06 {
366 uint32_t u32;
367 struct cvmx_pci_cfg06_s {
368 uint32_t lbase:5;
369 uint32_t lbasez:23;
370 uint32_t pf:1;
371 uint32_t typ:2;
372 uint32_t mspc:1;
373 } s;
374 struct cvmx_pci_cfg06_s cn30xx;
375 struct cvmx_pci_cfg06_s cn31xx;
376 struct cvmx_pci_cfg06_s cn38xx;
377 struct cvmx_pci_cfg06_s cn38xxp2;
378 struct cvmx_pci_cfg06_s cn50xx;
379 struct cvmx_pci_cfg06_s cn58xx;
380 struct cvmx_pci_cfg06_s cn58xxp1;
381};
382
383union cvmx_pci_cfg07 {
384 uint32_t u32;
385 struct cvmx_pci_cfg07_s {
386 uint32_t hbase:32;
387 } s;
388 struct cvmx_pci_cfg07_s cn30xx;
389 struct cvmx_pci_cfg07_s cn31xx;
390 struct cvmx_pci_cfg07_s cn38xx;
391 struct cvmx_pci_cfg07_s cn38xxp2;
392 struct cvmx_pci_cfg07_s cn50xx;
393 struct cvmx_pci_cfg07_s cn58xx;
394 struct cvmx_pci_cfg07_s cn58xxp1;
395};
396
397union cvmx_pci_cfg08 {
398 uint32_t u32;
399 struct cvmx_pci_cfg08_s {
400 uint32_t lbasez:28;
401 uint32_t pf:1;
402 uint32_t typ:2;
403 uint32_t mspc:1;
404 } s;
405 struct cvmx_pci_cfg08_s cn30xx;
406 struct cvmx_pci_cfg08_s cn31xx;
407 struct cvmx_pci_cfg08_s cn38xx;
408 struct cvmx_pci_cfg08_s cn38xxp2;
409 struct cvmx_pci_cfg08_s cn50xx;
410 struct cvmx_pci_cfg08_s cn58xx;
411 struct cvmx_pci_cfg08_s cn58xxp1;
412};
413
414union cvmx_pci_cfg09 {
415 uint32_t u32;
416 struct cvmx_pci_cfg09_s {
417 uint32_t hbase:25;
418 uint32_t hbasez:7;
419 } s;
420 struct cvmx_pci_cfg09_s cn30xx;
421 struct cvmx_pci_cfg09_s cn31xx;
422 struct cvmx_pci_cfg09_s cn38xx;
423 struct cvmx_pci_cfg09_s cn38xxp2;
424 struct cvmx_pci_cfg09_s cn50xx;
425 struct cvmx_pci_cfg09_s cn58xx;
426 struct cvmx_pci_cfg09_s cn58xxp1;
427};
428
429union cvmx_pci_cfg10 {
430 uint32_t u32;
431 struct cvmx_pci_cfg10_s {
432 uint32_t cisp:32;
433 } s;
434 struct cvmx_pci_cfg10_s cn30xx;
435 struct cvmx_pci_cfg10_s cn31xx;
436 struct cvmx_pci_cfg10_s cn38xx;
437 struct cvmx_pci_cfg10_s cn38xxp2;
438 struct cvmx_pci_cfg10_s cn50xx;
439 struct cvmx_pci_cfg10_s cn58xx;
440 struct cvmx_pci_cfg10_s cn58xxp1;
441};
442
443union cvmx_pci_cfg11 {
444 uint32_t u32;
445 struct cvmx_pci_cfg11_s {
446 uint32_t ssid:16;
447 uint32_t ssvid:16;
448 } s;
449 struct cvmx_pci_cfg11_s cn30xx;
450 struct cvmx_pci_cfg11_s cn31xx;
451 struct cvmx_pci_cfg11_s cn38xx;
452 struct cvmx_pci_cfg11_s cn38xxp2;
453 struct cvmx_pci_cfg11_s cn50xx;
454 struct cvmx_pci_cfg11_s cn58xx;
455 struct cvmx_pci_cfg11_s cn58xxp1;
456};
457
458union cvmx_pci_cfg12 {
459 uint32_t u32;
460 struct cvmx_pci_cfg12_s {
461 uint32_t erbar:16;
462 uint32_t erbarz:5;
463 uint32_t reserved_1_10:10;
464 uint32_t erbar_en:1;
465 } s;
466 struct cvmx_pci_cfg12_s cn30xx;
467 struct cvmx_pci_cfg12_s cn31xx;
468 struct cvmx_pci_cfg12_s cn38xx;
469 struct cvmx_pci_cfg12_s cn38xxp2;
470 struct cvmx_pci_cfg12_s cn50xx;
471 struct cvmx_pci_cfg12_s cn58xx;
472 struct cvmx_pci_cfg12_s cn58xxp1;
473};
474
475union cvmx_pci_cfg13 {
476 uint32_t u32;
477 struct cvmx_pci_cfg13_s {
478 uint32_t reserved_8_31:24;
479 uint32_t cp:8;
480 } s;
481 struct cvmx_pci_cfg13_s cn30xx;
482 struct cvmx_pci_cfg13_s cn31xx;
483 struct cvmx_pci_cfg13_s cn38xx;
484 struct cvmx_pci_cfg13_s cn38xxp2;
485 struct cvmx_pci_cfg13_s cn50xx;
486 struct cvmx_pci_cfg13_s cn58xx;
487 struct cvmx_pci_cfg13_s cn58xxp1;
488};
489
490union cvmx_pci_cfg15 {
491 uint32_t u32;
492 struct cvmx_pci_cfg15_s {
493 uint32_t ml:8;
494 uint32_t mg:8;
495 uint32_t inta:8;
496 uint32_t il:8;
497 } s;
498 struct cvmx_pci_cfg15_s cn30xx;
499 struct cvmx_pci_cfg15_s cn31xx;
500 struct cvmx_pci_cfg15_s cn38xx;
501 struct cvmx_pci_cfg15_s cn38xxp2;
502 struct cvmx_pci_cfg15_s cn50xx;
503 struct cvmx_pci_cfg15_s cn58xx;
504 struct cvmx_pci_cfg15_s cn58xxp1;
505};
506
507union cvmx_pci_cfg16 {
508 uint32_t u32;
509 struct cvmx_pci_cfg16_s {
510 uint32_t trdnpr:1;
511 uint32_t trdard:1;
512 uint32_t rdsati:1;
513 uint32_t trdrs:1;
514 uint32_t trtae:1;
515 uint32_t twsei:1;
516 uint32_t twsen:1;
517 uint32_t twtae:1;
518 uint32_t tmae:1;
519 uint32_t tslte:3;
520 uint32_t tilt:4;
521 uint32_t pbe:12;
522 uint32_t dppmr:1;
523 uint32_t reserved_2_2:1;
524 uint32_t tswc:1;
525 uint32_t mltd:1;
526 } s;
527 struct cvmx_pci_cfg16_s cn30xx;
528 struct cvmx_pci_cfg16_s cn31xx;
529 struct cvmx_pci_cfg16_s cn38xx;
530 struct cvmx_pci_cfg16_s cn38xxp2;
531 struct cvmx_pci_cfg16_s cn50xx;
532 struct cvmx_pci_cfg16_s cn58xx;
533 struct cvmx_pci_cfg16_s cn58xxp1;
534};
535
536union cvmx_pci_cfg17 {
537 uint32_t u32;
538 struct cvmx_pci_cfg17_s {
539 uint32_t tscme:32;
540 } s;
541 struct cvmx_pci_cfg17_s cn30xx;
542 struct cvmx_pci_cfg17_s cn31xx;
543 struct cvmx_pci_cfg17_s cn38xx;
544 struct cvmx_pci_cfg17_s cn38xxp2;
545 struct cvmx_pci_cfg17_s cn50xx;
546 struct cvmx_pci_cfg17_s cn58xx;
547 struct cvmx_pci_cfg17_s cn58xxp1;
548};
549
550union cvmx_pci_cfg18 {
551 uint32_t u32;
552 struct cvmx_pci_cfg18_s {
553 uint32_t tdsrps:32;
554 } s;
555 struct cvmx_pci_cfg18_s cn30xx;
556 struct cvmx_pci_cfg18_s cn31xx;
557 struct cvmx_pci_cfg18_s cn38xx;
558 struct cvmx_pci_cfg18_s cn38xxp2;
559 struct cvmx_pci_cfg18_s cn50xx;
560 struct cvmx_pci_cfg18_s cn58xx;
561 struct cvmx_pci_cfg18_s cn58xxp1;
562};
563
564union cvmx_pci_cfg19 {
565 uint32_t u32;
566 struct cvmx_pci_cfg19_s {
567 uint32_t mrbcm:1;
568 uint32_t mrbci:1;
569 uint32_t mdwe:1;
570 uint32_t mdre:1;
571 uint32_t mdrimc:1;
572 uint32_t mdrrmc:3;
573 uint32_t tmes:8;
574 uint32_t teci:1;
575 uint32_t tmei:1;
576 uint32_t tmse:1;
577 uint32_t tmdpes:1;
578 uint32_t tmapes:1;
579 uint32_t reserved_9_10:2;
580 uint32_t tibcd:1;
581 uint32_t tibde:1;
582 uint32_t reserved_6_6:1;
583 uint32_t tidomc:1;
584 uint32_t tdomc:5;
585 } s;
586 struct cvmx_pci_cfg19_s cn30xx;
587 struct cvmx_pci_cfg19_s cn31xx;
588 struct cvmx_pci_cfg19_s cn38xx;
589 struct cvmx_pci_cfg19_s cn38xxp2;
590 struct cvmx_pci_cfg19_s cn50xx;
591 struct cvmx_pci_cfg19_s cn58xx;
592 struct cvmx_pci_cfg19_s cn58xxp1;
593};
594
595union cvmx_pci_cfg20 {
596 uint32_t u32;
597 struct cvmx_pci_cfg20_s {
598 uint32_t mdsp:32;
599 } s;
600 struct cvmx_pci_cfg20_s cn30xx;
601 struct cvmx_pci_cfg20_s cn31xx;
602 struct cvmx_pci_cfg20_s cn38xx;
603 struct cvmx_pci_cfg20_s cn38xxp2;
604 struct cvmx_pci_cfg20_s cn50xx;
605 struct cvmx_pci_cfg20_s cn58xx;
606 struct cvmx_pci_cfg20_s cn58xxp1;
607};
608
609union cvmx_pci_cfg21 {
610 uint32_t u32;
611 struct cvmx_pci_cfg21_s {
612 uint32_t scmre:32;
613 } s;
614 struct cvmx_pci_cfg21_s cn30xx;
615 struct cvmx_pci_cfg21_s cn31xx;
616 struct cvmx_pci_cfg21_s cn38xx;
617 struct cvmx_pci_cfg21_s cn38xxp2;
618 struct cvmx_pci_cfg21_s cn50xx;
619 struct cvmx_pci_cfg21_s cn58xx;
620 struct cvmx_pci_cfg21_s cn58xxp1;
621};
622
623union cvmx_pci_cfg22 {
624 uint32_t u32;
625 struct cvmx_pci_cfg22_s {
626 uint32_t mac:7;
627 uint32_t reserved_19_24:6;
628 uint32_t flush:1;
629 uint32_t mra:1;
630 uint32_t mtta:1;
631 uint32_t mrv:8;
632 uint32_t mttv:8;
633 } s;
634 struct cvmx_pci_cfg22_s cn30xx;
635 struct cvmx_pci_cfg22_s cn31xx;
636 struct cvmx_pci_cfg22_s cn38xx;
637 struct cvmx_pci_cfg22_s cn38xxp2;
638 struct cvmx_pci_cfg22_s cn50xx;
639 struct cvmx_pci_cfg22_s cn58xx;
640 struct cvmx_pci_cfg22_s cn58xxp1;
641};
642
643union cvmx_pci_cfg56 {
644 uint32_t u32;
645 struct cvmx_pci_cfg56_s {
646 uint32_t reserved_23_31:9;
647 uint32_t most:3;
648 uint32_t mmbc:2;
649 uint32_t roe:1;
650 uint32_t dpere:1;
651 uint32_t ncp:8;
652 uint32_t pxcid:8;
653 } s;
654 struct cvmx_pci_cfg56_s cn30xx;
655 struct cvmx_pci_cfg56_s cn31xx;
656 struct cvmx_pci_cfg56_s cn38xx;
657 struct cvmx_pci_cfg56_s cn38xxp2;
658 struct cvmx_pci_cfg56_s cn50xx;
659 struct cvmx_pci_cfg56_s cn58xx;
660 struct cvmx_pci_cfg56_s cn58xxp1;
661};
662
663union cvmx_pci_cfg57 {
664 uint32_t u32;
665 struct cvmx_pci_cfg57_s {
666 uint32_t reserved_30_31:2;
667 uint32_t scemr:1;
668 uint32_t mcrsd:3;
669 uint32_t mostd:3;
670 uint32_t mmrbcd:2;
671 uint32_t dc:1;
672 uint32_t usc:1;
673 uint32_t scd:1;
674 uint32_t m133:1;
675 uint32_t w64:1;
676 uint32_t bn:8;
677 uint32_t dn:5;
678 uint32_t fn:3;
679 } s;
680 struct cvmx_pci_cfg57_s cn30xx;
681 struct cvmx_pci_cfg57_s cn31xx;
682 struct cvmx_pci_cfg57_s cn38xx;
683 struct cvmx_pci_cfg57_s cn38xxp2;
684 struct cvmx_pci_cfg57_s cn50xx;
685 struct cvmx_pci_cfg57_s cn58xx;
686 struct cvmx_pci_cfg57_s cn58xxp1;
687};
688
689union cvmx_pci_cfg58 {
690 uint32_t u32;
691 struct cvmx_pci_cfg58_s {
692 uint32_t pmes:5;
693 uint32_t d2s:1;
694 uint32_t d1s:1;
695 uint32_t auxc:3;
696 uint32_t dsi:1;
697 uint32_t reserved_20_20:1;
698 uint32_t pmec:1;
699 uint32_t pcimiv:3;
700 uint32_t ncp:8;
701 uint32_t pmcid:8;
702 } s;
703 struct cvmx_pci_cfg58_s cn30xx;
704 struct cvmx_pci_cfg58_s cn31xx;
705 struct cvmx_pci_cfg58_s cn38xx;
706 struct cvmx_pci_cfg58_s cn38xxp2;
707 struct cvmx_pci_cfg58_s cn50xx;
708 struct cvmx_pci_cfg58_s cn58xx;
709 struct cvmx_pci_cfg58_s cn58xxp1;
710};
711
712union cvmx_pci_cfg59 {
713 uint32_t u32;
714 struct cvmx_pci_cfg59_s {
715 uint32_t pmdia:8;
716 uint32_t bpccen:1;
717 uint32_t bd3h:1;
718 uint32_t reserved_16_21:6;
719 uint32_t pmess:1;
720 uint32_t pmedsia:2;
721 uint32_t pmds:4;
722 uint32_t pmeens:1;
723 uint32_t reserved_2_7:6;
724 uint32_t ps:2;
725 } s;
726 struct cvmx_pci_cfg59_s cn30xx;
727 struct cvmx_pci_cfg59_s cn31xx;
728 struct cvmx_pci_cfg59_s cn38xx;
729 struct cvmx_pci_cfg59_s cn38xxp2;
730 struct cvmx_pci_cfg59_s cn50xx;
731 struct cvmx_pci_cfg59_s cn58xx;
732 struct cvmx_pci_cfg59_s cn58xxp1;
733};
734
735union cvmx_pci_cfg60 {
736 uint32_t u32;
737 struct cvmx_pci_cfg60_s {
738 uint32_t reserved_24_31:8;
739 uint32_t m64:1;
740 uint32_t mme:3;
741 uint32_t mmc:3;
742 uint32_t msien:1;
743 uint32_t ncp:8;
744 uint32_t msicid:8;
745 } s;
746 struct cvmx_pci_cfg60_s cn30xx;
747 struct cvmx_pci_cfg60_s cn31xx;
748 struct cvmx_pci_cfg60_s cn38xx;
749 struct cvmx_pci_cfg60_s cn38xxp2;
750 struct cvmx_pci_cfg60_s cn50xx;
751 struct cvmx_pci_cfg60_s cn58xx;
752 struct cvmx_pci_cfg60_s cn58xxp1;
753};
754
755union cvmx_pci_cfg61 {
756 uint32_t u32;
757 struct cvmx_pci_cfg61_s {
758 uint32_t msi31t2:30;
759 uint32_t reserved_0_1:2;
760 } s;
761 struct cvmx_pci_cfg61_s cn30xx;
762 struct cvmx_pci_cfg61_s cn31xx;
763 struct cvmx_pci_cfg61_s cn38xx;
764 struct cvmx_pci_cfg61_s cn38xxp2;
765 struct cvmx_pci_cfg61_s cn50xx;
766 struct cvmx_pci_cfg61_s cn58xx;
767 struct cvmx_pci_cfg61_s cn58xxp1;
768};
769
770union cvmx_pci_cfg62 {
771 uint32_t u32;
772 struct cvmx_pci_cfg62_s {
773 uint32_t msi:32;
774 } s;
775 struct cvmx_pci_cfg62_s cn30xx;
776 struct cvmx_pci_cfg62_s cn31xx;
777 struct cvmx_pci_cfg62_s cn38xx;
778 struct cvmx_pci_cfg62_s cn38xxp2;
779 struct cvmx_pci_cfg62_s cn50xx;
780 struct cvmx_pci_cfg62_s cn58xx;
781 struct cvmx_pci_cfg62_s cn58xxp1;
782};
783
784union cvmx_pci_cfg63 {
785 uint32_t u32;
786 struct cvmx_pci_cfg63_s {
787 uint32_t reserved_16_31:16;
788 uint32_t msimd:16;
789 } s;
790 struct cvmx_pci_cfg63_s cn30xx;
791 struct cvmx_pci_cfg63_s cn31xx;
792 struct cvmx_pci_cfg63_s cn38xx;
793 struct cvmx_pci_cfg63_s cn38xxp2;
794 struct cvmx_pci_cfg63_s cn50xx;
795 struct cvmx_pci_cfg63_s cn58xx;
796 struct cvmx_pci_cfg63_s cn58xxp1;
797};
798
799union cvmx_pci_cnt_reg {
800 uint64_t u64;
801 struct cvmx_pci_cnt_reg_s {
802 uint64_t reserved_38_63:26;
803 uint64_t hm_pcix:1;
804 uint64_t hm_speed:2;
805 uint64_t ap_pcix:1;
806 uint64_t ap_speed:2;
807 uint64_t pcicnt:32;
808 } s;
809 struct cvmx_pci_cnt_reg_s cn50xx;
810 struct cvmx_pci_cnt_reg_s cn58xx;
811 struct cvmx_pci_cnt_reg_s cn58xxp1;
812};
813
814union cvmx_pci_ctl_status_2 {
815 uint32_t u32;
816 struct cvmx_pci_ctl_status_2_s {
817 uint32_t reserved_29_31:3;
818 uint32_t bb1_hole:3;
819 uint32_t bb1_siz:1;
820 uint32_t bb_ca:1;
821 uint32_t bb_es:2;
822 uint32_t bb1:1;
823 uint32_t bb0:1;
824 uint32_t erst_n:1;
825 uint32_t bar2pres:1;
826 uint32_t scmtyp:1;
827 uint32_t scm:1;
828 uint32_t en_wfilt:1;
829 uint32_t reserved_14_14:1;
830 uint32_t ap_pcix:1;
831 uint32_t ap_64ad:1;
832 uint32_t b12_bist:1;
833 uint32_t pmo_amod:1;
834 uint32_t pmo_fpc:3;
835 uint32_t tsr_hwm:3;
836 uint32_t bar2_enb:1;
837 uint32_t bar2_esx:2;
838 uint32_t bar2_cax:1;
839 } s;
840 struct cvmx_pci_ctl_status_2_s cn30xx;
841 struct cvmx_pci_ctl_status_2_cn31xx {
842 uint32_t reserved_20_31:12;
843 uint32_t erst_n:1;
844 uint32_t bar2pres:1;
845 uint32_t scmtyp:1;
846 uint32_t scm:1;
847 uint32_t en_wfilt:1;
848 uint32_t reserved_14_14:1;
849 uint32_t ap_pcix:1;
850 uint32_t ap_64ad:1;
851 uint32_t b12_bist:1;
852 uint32_t pmo_amod:1;
853 uint32_t pmo_fpc:3;
854 uint32_t tsr_hwm:3;
855 uint32_t bar2_enb:1;
856 uint32_t bar2_esx:2;
857 uint32_t bar2_cax:1;
858 } cn31xx;
859 struct cvmx_pci_ctl_status_2_s cn38xx;
860 struct cvmx_pci_ctl_status_2_cn31xx cn38xxp2;
861 struct cvmx_pci_ctl_status_2_s cn50xx;
862 struct cvmx_pci_ctl_status_2_s cn58xx;
863 struct cvmx_pci_ctl_status_2_s cn58xxp1;
864};
865
866union cvmx_pci_dbellx {
867 uint32_t u32;
868 struct cvmx_pci_dbellx_s {
869 uint32_t reserved_16_31:16;
870 uint32_t inc_val:16;
871 } s;
872 struct cvmx_pci_dbellx_s cn30xx;
873 struct cvmx_pci_dbellx_s cn31xx;
874 struct cvmx_pci_dbellx_s cn38xx;
875 struct cvmx_pci_dbellx_s cn38xxp2;
876 struct cvmx_pci_dbellx_s cn50xx;
877 struct cvmx_pci_dbellx_s cn58xx;
878 struct cvmx_pci_dbellx_s cn58xxp1;
879};
880
881union cvmx_pci_dma_cntx {
882 uint32_t u32;
883 struct cvmx_pci_dma_cntx_s {
884 uint32_t dma_cnt:32;
885 } s;
886 struct cvmx_pci_dma_cntx_s cn30xx;
887 struct cvmx_pci_dma_cntx_s cn31xx;
888 struct cvmx_pci_dma_cntx_s cn38xx;
889 struct cvmx_pci_dma_cntx_s cn38xxp2;
890 struct cvmx_pci_dma_cntx_s cn50xx;
891 struct cvmx_pci_dma_cntx_s cn58xx;
892 struct cvmx_pci_dma_cntx_s cn58xxp1;
893};
894
895union cvmx_pci_dma_int_levx {
896 uint32_t u32;
897 struct cvmx_pci_dma_int_levx_s {
898 uint32_t pkt_cnt:32;
899 } s;
900 struct cvmx_pci_dma_int_levx_s cn30xx;
901 struct cvmx_pci_dma_int_levx_s cn31xx;
902 struct cvmx_pci_dma_int_levx_s cn38xx;
903 struct cvmx_pci_dma_int_levx_s cn38xxp2;
904 struct cvmx_pci_dma_int_levx_s cn50xx;
905 struct cvmx_pci_dma_int_levx_s cn58xx;
906 struct cvmx_pci_dma_int_levx_s cn58xxp1;
907};
908
909union cvmx_pci_dma_timex {
910 uint32_t u32;
911 struct cvmx_pci_dma_timex_s {
912 uint32_t dma_time:32;
913 } s;
914 struct cvmx_pci_dma_timex_s cn30xx;
915 struct cvmx_pci_dma_timex_s cn31xx;
916 struct cvmx_pci_dma_timex_s cn38xx;
917 struct cvmx_pci_dma_timex_s cn38xxp2;
918 struct cvmx_pci_dma_timex_s cn50xx;
919 struct cvmx_pci_dma_timex_s cn58xx;
920 struct cvmx_pci_dma_timex_s cn58xxp1;
921};
922
923union cvmx_pci_instr_countx {
924 uint32_t u32;
925 struct cvmx_pci_instr_countx_s {
926 uint32_t icnt:32;
927 } s;
928 struct cvmx_pci_instr_countx_s cn30xx;
929 struct cvmx_pci_instr_countx_s cn31xx;
930 struct cvmx_pci_instr_countx_s cn38xx;
931 struct cvmx_pci_instr_countx_s cn38xxp2;
932 struct cvmx_pci_instr_countx_s cn50xx;
933 struct cvmx_pci_instr_countx_s cn58xx;
934 struct cvmx_pci_instr_countx_s cn58xxp1;
935};
936
937union cvmx_pci_int_enb {
938 uint64_t u64;
939 struct cvmx_pci_int_enb_s {
940 uint64_t reserved_34_63:30;
941 uint64_t ill_rd:1;
942 uint64_t ill_wr:1;
943 uint64_t win_wr:1;
944 uint64_t dma1_fi:1;
945 uint64_t dma0_fi:1;
946 uint64_t idtime1:1;
947 uint64_t idtime0:1;
948 uint64_t idcnt1:1;
949 uint64_t idcnt0:1;
950 uint64_t iptime3:1;
951 uint64_t iptime2:1;
952 uint64_t iptime1:1;
953 uint64_t iptime0:1;
954 uint64_t ipcnt3:1;
955 uint64_t ipcnt2:1;
956 uint64_t ipcnt1:1;
957 uint64_t ipcnt0:1;
958 uint64_t irsl_int:1;
959 uint64_t ill_rrd:1;
960 uint64_t ill_rwr:1;
961 uint64_t idperr:1;
962 uint64_t iaperr:1;
963 uint64_t iserr:1;
964 uint64_t itsr_abt:1;
965 uint64_t imsc_msg:1;
966 uint64_t imsi_mabt:1;
967 uint64_t imsi_tabt:1;
968 uint64_t imsi_per:1;
969 uint64_t imr_tto:1;
970 uint64_t imr_abt:1;
971 uint64_t itr_abt:1;
972 uint64_t imr_wtto:1;
973 uint64_t imr_wabt:1;
974 uint64_t itr_wabt:1;
975 } s;
976 struct cvmx_pci_int_enb_cn30xx {
977 uint64_t reserved_34_63:30;
978 uint64_t ill_rd:1;
979 uint64_t ill_wr:1;
980 uint64_t win_wr:1;
981 uint64_t dma1_fi:1;
982 uint64_t dma0_fi:1;
983 uint64_t idtime1:1;
984 uint64_t idtime0:1;
985 uint64_t idcnt1:1;
986 uint64_t idcnt0:1;
987 uint64_t reserved_22_24:3;
988 uint64_t iptime0:1;
989 uint64_t reserved_18_20:3;
990 uint64_t ipcnt0:1;
991 uint64_t irsl_int:1;
992 uint64_t ill_rrd:1;
993 uint64_t ill_rwr:1;
994 uint64_t idperr:1;
995 uint64_t iaperr:1;
996 uint64_t iserr:1;
997 uint64_t itsr_abt:1;
998 uint64_t imsc_msg:1;
999 uint64_t imsi_mabt:1;
1000 uint64_t imsi_tabt:1;
1001 uint64_t imsi_per:1;
1002 uint64_t imr_tto:1;
1003 uint64_t imr_abt:1;
1004 uint64_t itr_abt:1;
1005 uint64_t imr_wtto:1;
1006 uint64_t imr_wabt:1;
1007 uint64_t itr_wabt:1;
1008 } cn30xx;
1009 struct cvmx_pci_int_enb_cn31xx {
1010 uint64_t reserved_34_63:30;
1011 uint64_t ill_rd:1;
1012 uint64_t ill_wr:1;
1013 uint64_t win_wr:1;
1014 uint64_t dma1_fi:1;
1015 uint64_t dma0_fi:1;
1016 uint64_t idtime1:1;
1017 uint64_t idtime0:1;
1018 uint64_t idcnt1:1;
1019 uint64_t idcnt0:1;
1020 uint64_t reserved_23_24:2;
1021 uint64_t iptime1:1;
1022 uint64_t iptime0:1;
1023 uint64_t reserved_19_20:2;
1024 uint64_t ipcnt1:1;
1025 uint64_t ipcnt0:1;
1026 uint64_t irsl_int:1;
1027 uint64_t ill_rrd:1;
1028 uint64_t ill_rwr:1;
1029 uint64_t idperr:1;
1030 uint64_t iaperr:1;
1031 uint64_t iserr:1;
1032 uint64_t itsr_abt:1;
1033 uint64_t imsc_msg:1;
1034 uint64_t imsi_mabt:1;
1035 uint64_t imsi_tabt:1;
1036 uint64_t imsi_per:1;
1037 uint64_t imr_tto:1;
1038 uint64_t imr_abt:1;
1039 uint64_t itr_abt:1;
1040 uint64_t imr_wtto:1;
1041 uint64_t imr_wabt:1;
1042 uint64_t itr_wabt:1;
1043 } cn31xx;
1044 struct cvmx_pci_int_enb_s cn38xx;
1045 struct cvmx_pci_int_enb_s cn38xxp2;
1046 struct cvmx_pci_int_enb_cn31xx cn50xx;
1047 struct cvmx_pci_int_enb_s cn58xx;
1048 struct cvmx_pci_int_enb_s cn58xxp1;
1049};
1050
1051union cvmx_pci_int_enb2 {
1052 uint64_t u64;
1053 struct cvmx_pci_int_enb2_s {
1054 uint64_t reserved_34_63:30;
1055 uint64_t ill_rd:1;
1056 uint64_t ill_wr:1;
1057 uint64_t win_wr:1;
1058 uint64_t dma1_fi:1;
1059 uint64_t dma0_fi:1;
1060 uint64_t rdtime1:1;
1061 uint64_t rdtime0:1;
1062 uint64_t rdcnt1:1;
1063 uint64_t rdcnt0:1;
1064 uint64_t rptime3:1;
1065 uint64_t rptime2:1;
1066 uint64_t rptime1:1;
1067 uint64_t rptime0:1;
1068 uint64_t rpcnt3:1;
1069 uint64_t rpcnt2:1;
1070 uint64_t rpcnt1:1;
1071 uint64_t rpcnt0:1;
1072 uint64_t rrsl_int:1;
1073 uint64_t ill_rrd:1;
1074 uint64_t ill_rwr:1;
1075 uint64_t rdperr:1;
1076 uint64_t raperr:1;
1077 uint64_t rserr:1;
1078 uint64_t rtsr_abt:1;
1079 uint64_t rmsc_msg:1;
1080 uint64_t rmsi_mabt:1;
1081 uint64_t rmsi_tabt:1;
1082 uint64_t rmsi_per:1;
1083 uint64_t rmr_tto:1;
1084 uint64_t rmr_abt:1;
1085 uint64_t rtr_abt:1;
1086 uint64_t rmr_wtto:1;
1087 uint64_t rmr_wabt:1;
1088 uint64_t rtr_wabt:1;
1089 } s;
1090 struct cvmx_pci_int_enb2_cn30xx {
1091 uint64_t reserved_34_63:30;
1092 uint64_t ill_rd:1;
1093 uint64_t ill_wr:1;
1094 uint64_t win_wr:1;
1095 uint64_t dma1_fi:1;
1096 uint64_t dma0_fi:1;
1097 uint64_t rdtime1:1;
1098 uint64_t rdtime0:1;
1099 uint64_t rdcnt1:1;
1100 uint64_t rdcnt0:1;
1101 uint64_t reserved_22_24:3;
1102 uint64_t rptime0:1;
1103 uint64_t reserved_18_20:3;
1104 uint64_t rpcnt0:1;
1105 uint64_t rrsl_int:1;
1106 uint64_t ill_rrd:1;
1107 uint64_t ill_rwr:1;
1108 uint64_t rdperr:1;
1109 uint64_t raperr:1;
1110 uint64_t rserr:1;
1111 uint64_t rtsr_abt:1;
1112 uint64_t rmsc_msg:1;
1113 uint64_t rmsi_mabt:1;
1114 uint64_t rmsi_tabt:1;
1115 uint64_t rmsi_per:1;
1116 uint64_t rmr_tto:1;
1117 uint64_t rmr_abt:1;
1118 uint64_t rtr_abt:1;
1119 uint64_t rmr_wtto:1;
1120 uint64_t rmr_wabt:1;
1121 uint64_t rtr_wabt:1;
1122 } cn30xx;
1123 struct cvmx_pci_int_enb2_cn31xx {
1124 uint64_t reserved_34_63:30;
1125 uint64_t ill_rd:1;
1126 uint64_t ill_wr:1;
1127 uint64_t win_wr:1;
1128 uint64_t dma1_fi:1;
1129 uint64_t dma0_fi:1;
1130 uint64_t rdtime1:1;
1131 uint64_t rdtime0:1;
1132 uint64_t rdcnt1:1;
1133 uint64_t rdcnt0:1;
1134 uint64_t reserved_23_24:2;
1135 uint64_t rptime1:1;
1136 uint64_t rptime0:1;
1137 uint64_t reserved_19_20:2;
1138 uint64_t rpcnt1:1;
1139 uint64_t rpcnt0:1;
1140 uint64_t rrsl_int:1;
1141 uint64_t ill_rrd:1;
1142 uint64_t ill_rwr:1;
1143 uint64_t rdperr:1;
1144 uint64_t raperr:1;
1145 uint64_t rserr:1;
1146 uint64_t rtsr_abt:1;
1147 uint64_t rmsc_msg:1;
1148 uint64_t rmsi_mabt:1;
1149 uint64_t rmsi_tabt:1;
1150 uint64_t rmsi_per:1;
1151 uint64_t rmr_tto:1;
1152 uint64_t rmr_abt:1;
1153 uint64_t rtr_abt:1;
1154 uint64_t rmr_wtto:1;
1155 uint64_t rmr_wabt:1;
1156 uint64_t rtr_wabt:1;
1157 } cn31xx;
1158 struct cvmx_pci_int_enb2_s cn38xx;
1159 struct cvmx_pci_int_enb2_s cn38xxp2;
1160 struct cvmx_pci_int_enb2_cn31xx cn50xx;
1161 struct cvmx_pci_int_enb2_s cn58xx;
1162 struct cvmx_pci_int_enb2_s cn58xxp1;
1163};
1164
1165union cvmx_pci_int_sum {
1166 uint64_t u64;
1167 struct cvmx_pci_int_sum_s {
1168 uint64_t reserved_34_63:30;
1169 uint64_t ill_rd:1;
1170 uint64_t ill_wr:1;
1171 uint64_t win_wr:1;
1172 uint64_t dma1_fi:1;
1173 uint64_t dma0_fi:1;
1174 uint64_t dtime1:1;
1175 uint64_t dtime0:1;
1176 uint64_t dcnt1:1;
1177 uint64_t dcnt0:1;
1178 uint64_t ptime3:1;
1179 uint64_t ptime2:1;
1180 uint64_t ptime1:1;
1181 uint64_t ptime0:1;
1182 uint64_t pcnt3:1;
1183 uint64_t pcnt2:1;
1184 uint64_t pcnt1:1;
1185 uint64_t pcnt0:1;
1186 uint64_t rsl_int:1;
1187 uint64_t ill_rrd:1;
1188 uint64_t ill_rwr:1;
1189 uint64_t dperr:1;
1190 uint64_t aperr:1;
1191 uint64_t serr:1;
1192 uint64_t tsr_abt:1;
1193 uint64_t msc_msg:1;
1194 uint64_t msi_mabt:1;
1195 uint64_t msi_tabt:1;
1196 uint64_t msi_per:1;
1197 uint64_t mr_tto:1;
1198 uint64_t mr_abt:1;
1199 uint64_t tr_abt:1;
1200 uint64_t mr_wtto:1;
1201 uint64_t mr_wabt:1;
1202 uint64_t tr_wabt:1;
1203 } s;
1204 struct cvmx_pci_int_sum_cn30xx {
1205 uint64_t reserved_34_63:30;
1206 uint64_t ill_rd:1;
1207 uint64_t ill_wr:1;
1208 uint64_t win_wr:1;
1209 uint64_t dma1_fi:1;
1210 uint64_t dma0_fi:1;
1211 uint64_t dtime1:1;
1212 uint64_t dtime0:1;
1213 uint64_t dcnt1:1;
1214 uint64_t dcnt0:1;
1215 uint64_t reserved_22_24:3;
1216 uint64_t ptime0:1;
1217 uint64_t reserved_18_20:3;
1218 uint64_t pcnt0:1;
1219 uint64_t rsl_int:1;
1220 uint64_t ill_rrd:1;
1221 uint64_t ill_rwr:1;
1222 uint64_t dperr:1;
1223 uint64_t aperr:1;
1224 uint64_t serr:1;
1225 uint64_t tsr_abt:1;
1226 uint64_t msc_msg:1;
1227 uint64_t msi_mabt:1;
1228 uint64_t msi_tabt:1;
1229 uint64_t msi_per:1;
1230 uint64_t mr_tto:1;
1231 uint64_t mr_abt:1;
1232 uint64_t tr_abt:1;
1233 uint64_t mr_wtto:1;
1234 uint64_t mr_wabt:1;
1235 uint64_t tr_wabt:1;
1236 } cn30xx;
1237 struct cvmx_pci_int_sum_cn31xx {
1238 uint64_t reserved_34_63:30;
1239 uint64_t ill_rd:1;
1240 uint64_t ill_wr:1;
1241 uint64_t win_wr:1;
1242 uint64_t dma1_fi:1;
1243 uint64_t dma0_fi:1;
1244 uint64_t dtime1:1;
1245 uint64_t dtime0:1;
1246 uint64_t dcnt1:1;
1247 uint64_t dcnt0:1;
1248 uint64_t reserved_23_24:2;
1249 uint64_t ptime1:1;
1250 uint64_t ptime0:1;
1251 uint64_t reserved_19_20:2;
1252 uint64_t pcnt1:1;
1253 uint64_t pcnt0:1;
1254 uint64_t rsl_int:1;
1255 uint64_t ill_rrd:1;
1256 uint64_t ill_rwr:1;
1257 uint64_t dperr:1;
1258 uint64_t aperr:1;
1259 uint64_t serr:1;
1260 uint64_t tsr_abt:1;
1261 uint64_t msc_msg:1;
1262 uint64_t msi_mabt:1;
1263 uint64_t msi_tabt:1;
1264 uint64_t msi_per:1;
1265 uint64_t mr_tto:1;
1266 uint64_t mr_abt:1;
1267 uint64_t tr_abt:1;
1268 uint64_t mr_wtto:1;
1269 uint64_t mr_wabt:1;
1270 uint64_t tr_wabt:1;
1271 } cn31xx;
1272 struct cvmx_pci_int_sum_s cn38xx;
1273 struct cvmx_pci_int_sum_s cn38xxp2;
1274 struct cvmx_pci_int_sum_cn31xx cn50xx;
1275 struct cvmx_pci_int_sum_s cn58xx;
1276 struct cvmx_pci_int_sum_s cn58xxp1;
1277};
1278
1279union cvmx_pci_int_sum2 {
1280 uint64_t u64;
1281 struct cvmx_pci_int_sum2_s {
1282 uint64_t reserved_34_63:30;
1283 uint64_t ill_rd:1;
1284 uint64_t ill_wr:1;
1285 uint64_t win_wr:1;
1286 uint64_t dma1_fi:1;
1287 uint64_t dma0_fi:1;
1288 uint64_t dtime1:1;
1289 uint64_t dtime0:1;
1290 uint64_t dcnt1:1;
1291 uint64_t dcnt0:1;
1292 uint64_t ptime3:1;
1293 uint64_t ptime2:1;
1294 uint64_t ptime1:1;
1295 uint64_t ptime0:1;
1296 uint64_t pcnt3:1;
1297 uint64_t pcnt2:1;
1298 uint64_t pcnt1:1;
1299 uint64_t pcnt0:1;
1300 uint64_t rsl_int:1;
1301 uint64_t ill_rrd:1;
1302 uint64_t ill_rwr:1;
1303 uint64_t dperr:1;
1304 uint64_t aperr:1;
1305 uint64_t serr:1;
1306 uint64_t tsr_abt:1;
1307 uint64_t msc_msg:1;
1308 uint64_t msi_mabt:1;
1309 uint64_t msi_tabt:1;
1310 uint64_t msi_per:1;
1311 uint64_t mr_tto:1;
1312 uint64_t mr_abt:1;
1313 uint64_t tr_abt:1;
1314 uint64_t mr_wtto:1;
1315 uint64_t mr_wabt:1;
1316 uint64_t tr_wabt:1;
1317 } s;
1318 struct cvmx_pci_int_sum2_cn30xx {
1319 uint64_t reserved_34_63:30;
1320 uint64_t ill_rd:1;
1321 uint64_t ill_wr:1;
1322 uint64_t win_wr:1;
1323 uint64_t dma1_fi:1;
1324 uint64_t dma0_fi:1;
1325 uint64_t dtime1:1;
1326 uint64_t dtime0:1;
1327 uint64_t dcnt1:1;
1328 uint64_t dcnt0:1;
1329 uint64_t reserved_22_24:3;
1330 uint64_t ptime0:1;
1331 uint64_t reserved_18_20:3;
1332 uint64_t pcnt0:1;
1333 uint64_t rsl_int:1;
1334 uint64_t ill_rrd:1;
1335 uint64_t ill_rwr:1;
1336 uint64_t dperr:1;
1337 uint64_t aperr:1;
1338 uint64_t serr:1;
1339 uint64_t tsr_abt:1;
1340 uint64_t msc_msg:1;
1341 uint64_t msi_mabt:1;
1342 uint64_t msi_tabt:1;
1343 uint64_t msi_per:1;
1344 uint64_t mr_tto:1;
1345 uint64_t mr_abt:1;
1346 uint64_t tr_abt:1;
1347 uint64_t mr_wtto:1;
1348 uint64_t mr_wabt:1;
1349 uint64_t tr_wabt:1;
1350 } cn30xx;
1351 struct cvmx_pci_int_sum2_cn31xx {
1352 uint64_t reserved_34_63:30;
1353 uint64_t ill_rd:1;
1354 uint64_t ill_wr:1;
1355 uint64_t win_wr:1;
1356 uint64_t dma1_fi:1;
1357 uint64_t dma0_fi:1;
1358 uint64_t dtime1:1;
1359 uint64_t dtime0:1;
1360 uint64_t dcnt1:1;
1361 uint64_t dcnt0:1;
1362 uint64_t reserved_23_24:2;
1363 uint64_t ptime1:1;
1364 uint64_t ptime0:1;
1365 uint64_t reserved_19_20:2;
1366 uint64_t pcnt1:1;
1367 uint64_t pcnt0:1;
1368 uint64_t rsl_int:1;
1369 uint64_t ill_rrd:1;
1370 uint64_t ill_rwr:1;
1371 uint64_t dperr:1;
1372 uint64_t aperr:1;
1373 uint64_t serr:1;
1374 uint64_t tsr_abt:1;
1375 uint64_t msc_msg:1;
1376 uint64_t msi_mabt:1;
1377 uint64_t msi_tabt:1;
1378 uint64_t msi_per:1;
1379 uint64_t mr_tto:1;
1380 uint64_t mr_abt:1;
1381 uint64_t tr_abt:1;
1382 uint64_t mr_wtto:1;
1383 uint64_t mr_wabt:1;
1384 uint64_t tr_wabt:1;
1385 } cn31xx;
1386 struct cvmx_pci_int_sum2_s cn38xx;
1387 struct cvmx_pci_int_sum2_s cn38xxp2;
1388 struct cvmx_pci_int_sum2_cn31xx cn50xx;
1389 struct cvmx_pci_int_sum2_s cn58xx;
1390 struct cvmx_pci_int_sum2_s cn58xxp1;
1391};
1392
1393union cvmx_pci_msi_rcv {
1394 uint32_t u32;
1395 struct cvmx_pci_msi_rcv_s {
1396 uint32_t reserved_6_31:26;
1397 uint32_t intr:6;
1398 } s;
1399 struct cvmx_pci_msi_rcv_s cn30xx;
1400 struct cvmx_pci_msi_rcv_s cn31xx;
1401 struct cvmx_pci_msi_rcv_s cn38xx;
1402 struct cvmx_pci_msi_rcv_s cn38xxp2;
1403 struct cvmx_pci_msi_rcv_s cn50xx;
1404 struct cvmx_pci_msi_rcv_s cn58xx;
1405 struct cvmx_pci_msi_rcv_s cn58xxp1;
1406};
1407
1408union cvmx_pci_pkt_creditsx {
1409 uint32_t u32;
1410 struct cvmx_pci_pkt_creditsx_s {
1411 uint32_t pkt_cnt:16;
1412 uint32_t ptr_cnt:16;
1413 } s;
1414 struct cvmx_pci_pkt_creditsx_s cn30xx;
1415 struct cvmx_pci_pkt_creditsx_s cn31xx;
1416 struct cvmx_pci_pkt_creditsx_s cn38xx;
1417 struct cvmx_pci_pkt_creditsx_s cn38xxp2;
1418 struct cvmx_pci_pkt_creditsx_s cn50xx;
1419 struct cvmx_pci_pkt_creditsx_s cn58xx;
1420 struct cvmx_pci_pkt_creditsx_s cn58xxp1;
1421};
1422
1423union cvmx_pci_pkts_sentx {
1424 uint32_t u32;
1425 struct cvmx_pci_pkts_sentx_s {
1426 uint32_t pkt_cnt:32;
1427 } s;
1428 struct cvmx_pci_pkts_sentx_s cn30xx;
1429 struct cvmx_pci_pkts_sentx_s cn31xx;
1430 struct cvmx_pci_pkts_sentx_s cn38xx;
1431 struct cvmx_pci_pkts_sentx_s cn38xxp2;
1432 struct cvmx_pci_pkts_sentx_s cn50xx;
1433 struct cvmx_pci_pkts_sentx_s cn58xx;
1434 struct cvmx_pci_pkts_sentx_s cn58xxp1;
1435};
1436
1437union cvmx_pci_pkts_sent_int_levx {
1438 uint32_t u32;
1439 struct cvmx_pci_pkts_sent_int_levx_s {
1440 uint32_t pkt_cnt:32;
1441 } s;
1442 struct cvmx_pci_pkts_sent_int_levx_s cn30xx;
1443 struct cvmx_pci_pkts_sent_int_levx_s cn31xx;
1444 struct cvmx_pci_pkts_sent_int_levx_s cn38xx;
1445 struct cvmx_pci_pkts_sent_int_levx_s cn38xxp2;
1446 struct cvmx_pci_pkts_sent_int_levx_s cn50xx;
1447 struct cvmx_pci_pkts_sent_int_levx_s cn58xx;
1448 struct cvmx_pci_pkts_sent_int_levx_s cn58xxp1;
1449};
1450
1451union cvmx_pci_pkts_sent_timex {
1452 uint32_t u32;
1453 struct cvmx_pci_pkts_sent_timex_s {
1454 uint32_t pkt_time:32;
1455 } s;
1456 struct cvmx_pci_pkts_sent_timex_s cn30xx;
1457 struct cvmx_pci_pkts_sent_timex_s cn31xx;
1458 struct cvmx_pci_pkts_sent_timex_s cn38xx;
1459 struct cvmx_pci_pkts_sent_timex_s cn38xxp2;
1460 struct cvmx_pci_pkts_sent_timex_s cn50xx;
1461 struct cvmx_pci_pkts_sent_timex_s cn58xx;
1462 struct cvmx_pci_pkts_sent_timex_s cn58xxp1;
1463};
1464
1465union cvmx_pci_read_cmd_6 {
1466 uint32_t u32;
1467 struct cvmx_pci_read_cmd_6_s {
1468 uint32_t reserved_9_31:23;
1469 uint32_t min_data:6;
1470 uint32_t prefetch:3;
1471 } s;
1472 struct cvmx_pci_read_cmd_6_s cn30xx;
1473 struct cvmx_pci_read_cmd_6_s cn31xx;
1474 struct cvmx_pci_read_cmd_6_s cn38xx;
1475 struct cvmx_pci_read_cmd_6_s cn38xxp2;
1476 struct cvmx_pci_read_cmd_6_s cn50xx;
1477 struct cvmx_pci_read_cmd_6_s cn58xx;
1478 struct cvmx_pci_read_cmd_6_s cn58xxp1;
1479};
1480
1481union cvmx_pci_read_cmd_c {
1482 uint32_t u32;
1483 struct cvmx_pci_read_cmd_c_s {
1484 uint32_t reserved_9_31:23;
1485 uint32_t min_data:6;
1486 uint32_t prefetch:3;
1487 } s;
1488 struct cvmx_pci_read_cmd_c_s cn30xx;
1489 struct cvmx_pci_read_cmd_c_s cn31xx;
1490 struct cvmx_pci_read_cmd_c_s cn38xx;
1491 struct cvmx_pci_read_cmd_c_s cn38xxp2;
1492 struct cvmx_pci_read_cmd_c_s cn50xx;
1493 struct cvmx_pci_read_cmd_c_s cn58xx;
1494 struct cvmx_pci_read_cmd_c_s cn58xxp1;
1495};
1496
1497union cvmx_pci_read_cmd_e {
1498 uint32_t u32;
1499 struct cvmx_pci_read_cmd_e_s {
1500 uint32_t reserved_9_31:23;
1501 uint32_t min_data:6;
1502 uint32_t prefetch:3;
1503 } s;
1504 struct cvmx_pci_read_cmd_e_s cn30xx;
1505 struct cvmx_pci_read_cmd_e_s cn31xx;
1506 struct cvmx_pci_read_cmd_e_s cn38xx;
1507 struct cvmx_pci_read_cmd_e_s cn38xxp2;
1508 struct cvmx_pci_read_cmd_e_s cn50xx;
1509 struct cvmx_pci_read_cmd_e_s cn58xx;
1510 struct cvmx_pci_read_cmd_e_s cn58xxp1;
1511};
1512
1513union cvmx_pci_read_timeout {
1514 uint64_t u64;
1515 struct cvmx_pci_read_timeout_s {
1516 uint64_t reserved_32_63:32;
1517 uint64_t enb:1;
1518 uint64_t cnt:31;
1519 } s;
1520 struct cvmx_pci_read_timeout_s cn30xx;
1521 struct cvmx_pci_read_timeout_s cn31xx;
1522 struct cvmx_pci_read_timeout_s cn38xx;
1523 struct cvmx_pci_read_timeout_s cn38xxp2;
1524 struct cvmx_pci_read_timeout_s cn50xx;
1525 struct cvmx_pci_read_timeout_s cn58xx;
1526 struct cvmx_pci_read_timeout_s cn58xxp1;
1527};
1528
1529union cvmx_pci_scm_reg {
1530 uint64_t u64;
1531 struct cvmx_pci_scm_reg_s {
1532 uint64_t reserved_32_63:32;
1533 uint64_t scm:32;
1534 } s;
1535 struct cvmx_pci_scm_reg_s cn30xx;
1536 struct cvmx_pci_scm_reg_s cn31xx;
1537 struct cvmx_pci_scm_reg_s cn38xx;
1538 struct cvmx_pci_scm_reg_s cn38xxp2;
1539 struct cvmx_pci_scm_reg_s cn50xx;
1540 struct cvmx_pci_scm_reg_s cn58xx;
1541 struct cvmx_pci_scm_reg_s cn58xxp1;
1542};
1543
1544union cvmx_pci_tsr_reg {
1545 uint64_t u64;
1546 struct cvmx_pci_tsr_reg_s {
1547 uint64_t reserved_36_63:28;
1548 uint64_t tsr:36;
1549 } s;
1550 struct cvmx_pci_tsr_reg_s cn30xx;
1551 struct cvmx_pci_tsr_reg_s cn31xx;
1552 struct cvmx_pci_tsr_reg_s cn38xx;
1553 struct cvmx_pci_tsr_reg_s cn38xxp2;
1554 struct cvmx_pci_tsr_reg_s cn50xx;
1555 struct cvmx_pci_tsr_reg_s cn58xx;
1556 struct cvmx_pci_tsr_reg_s cn58xxp1;
1557};
1558
1559union cvmx_pci_win_rd_addr {
1560 uint64_t u64;
1561 struct cvmx_pci_win_rd_addr_s {
1562 uint64_t reserved_49_63:15;
1563 uint64_t iobit:1;
1564 uint64_t reserved_0_47:48;
1565 } s;
1566 struct cvmx_pci_win_rd_addr_cn30xx {
1567 uint64_t reserved_49_63:15;
1568 uint64_t iobit:1;
1569 uint64_t rd_addr:46;
1570 uint64_t reserved_0_1:2;
1571 } cn30xx;
1572 struct cvmx_pci_win_rd_addr_cn30xx cn31xx;
1573 struct cvmx_pci_win_rd_addr_cn38xx {
1574 uint64_t reserved_49_63:15;
1575 uint64_t iobit:1;
1576 uint64_t rd_addr:45;
1577 uint64_t reserved_0_2:3;
1578 } cn38xx;
1579 struct cvmx_pci_win_rd_addr_cn38xx cn38xxp2;
1580 struct cvmx_pci_win_rd_addr_cn30xx cn50xx;
1581 struct cvmx_pci_win_rd_addr_cn38xx cn58xx;
1582 struct cvmx_pci_win_rd_addr_cn38xx cn58xxp1;
1583};
1584
1585union cvmx_pci_win_rd_data {
1586 uint64_t u64;
1587 struct cvmx_pci_win_rd_data_s {
1588 uint64_t rd_data:64;
1589 } s;
1590 struct cvmx_pci_win_rd_data_s cn30xx;
1591 struct cvmx_pci_win_rd_data_s cn31xx;
1592 struct cvmx_pci_win_rd_data_s cn38xx;
1593 struct cvmx_pci_win_rd_data_s cn38xxp2;
1594 struct cvmx_pci_win_rd_data_s cn50xx;
1595 struct cvmx_pci_win_rd_data_s cn58xx;
1596 struct cvmx_pci_win_rd_data_s cn58xxp1;
1597};
1598
1599union cvmx_pci_win_wr_addr {
1600 uint64_t u64;
1601 struct cvmx_pci_win_wr_addr_s {
1602 uint64_t reserved_49_63:15;
1603 uint64_t iobit:1;
1604 uint64_t wr_addr:45;
1605 uint64_t reserved_0_2:3;
1606 } s;
1607 struct cvmx_pci_win_wr_addr_s cn30xx;
1608 struct cvmx_pci_win_wr_addr_s cn31xx;
1609 struct cvmx_pci_win_wr_addr_s cn38xx;
1610 struct cvmx_pci_win_wr_addr_s cn38xxp2;
1611 struct cvmx_pci_win_wr_addr_s cn50xx;
1612 struct cvmx_pci_win_wr_addr_s cn58xx;
1613 struct cvmx_pci_win_wr_addr_s cn58xxp1;
1614};
1615
1616union cvmx_pci_win_wr_data {
1617 uint64_t u64;
1618 struct cvmx_pci_win_wr_data_s {
1619 uint64_t wr_data:64;
1620 } s;
1621 struct cvmx_pci_win_wr_data_s cn30xx;
1622 struct cvmx_pci_win_wr_data_s cn31xx;
1623 struct cvmx_pci_win_wr_data_s cn38xx;
1624 struct cvmx_pci_win_wr_data_s cn38xxp2;
1625 struct cvmx_pci_win_wr_data_s cn50xx;
1626 struct cvmx_pci_win_wr_data_s cn58xx;
1627 struct cvmx_pci_win_wr_data_s cn58xxp1;
1628};
1629
1630union cvmx_pci_win_wr_mask {
1631 uint64_t u64;
1632 struct cvmx_pci_win_wr_mask_s {
1633 uint64_t reserved_8_63:56;
1634 uint64_t wr_mask:8;
1635 } s;
1636 struct cvmx_pci_win_wr_mask_s cn30xx;
1637 struct cvmx_pci_win_wr_mask_s cn31xx;
1638 struct cvmx_pci_win_wr_mask_s cn38xx;
1639 struct cvmx_pci_win_wr_mask_s cn38xxp2;
1640 struct cvmx_pci_win_wr_mask_s cn50xx;
1641 struct cvmx_pci_win_wr_mask_s cn58xx;
1642 struct cvmx_pci_win_wr_mask_s cn58xxp1;
1643};
1644
1645#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-pcieep-defs.h b/arch/mips/include/asm/octeon/cvmx-pcieep-defs.h
new file mode 100644
index 000000000000..d553f8e88df6
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-pcieep-defs.h
@@ -0,0 +1,1365 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_PCIEEP_DEFS_H__
29#define __CVMX_PCIEEP_DEFS_H__
30
31#define CVMX_PCIEEP_CFG000 \
32 (0x0000000000000000ull)
33#define CVMX_PCIEEP_CFG001 \
34 (0x0000000000000004ull)
35#define CVMX_PCIEEP_CFG002 \
36 (0x0000000000000008ull)
37#define CVMX_PCIEEP_CFG003 \
38 (0x000000000000000Cull)
39#define CVMX_PCIEEP_CFG004 \
40 (0x0000000000000010ull)
41#define CVMX_PCIEEP_CFG004_MASK \
42 (0x0000000080000010ull)
43#define CVMX_PCIEEP_CFG005 \
44 (0x0000000000000014ull)
45#define CVMX_PCIEEP_CFG005_MASK \
46 (0x0000000080000014ull)
47#define CVMX_PCIEEP_CFG006 \
48 (0x0000000000000018ull)
49#define CVMX_PCIEEP_CFG006_MASK \
50 (0x0000000080000018ull)
51#define CVMX_PCIEEP_CFG007 \
52 (0x000000000000001Cull)
53#define CVMX_PCIEEP_CFG007_MASK \
54 (0x000000008000001Cull)
55#define CVMX_PCIEEP_CFG008 \
56 (0x0000000000000020ull)
57#define CVMX_PCIEEP_CFG008_MASK \
58 (0x0000000080000020ull)
59#define CVMX_PCIEEP_CFG009 \
60 (0x0000000000000024ull)
61#define CVMX_PCIEEP_CFG009_MASK \
62 (0x0000000080000024ull)
63#define CVMX_PCIEEP_CFG010 \
64 (0x0000000000000028ull)
65#define CVMX_PCIEEP_CFG011 \
66 (0x000000000000002Cull)
67#define CVMX_PCIEEP_CFG012 \
68 (0x0000000000000030ull)
69#define CVMX_PCIEEP_CFG012_MASK \
70 (0x0000000080000030ull)
71#define CVMX_PCIEEP_CFG013 \
72 (0x0000000000000034ull)
73#define CVMX_PCIEEP_CFG015 \
74 (0x000000000000003Cull)
75#define CVMX_PCIEEP_CFG016 \
76 (0x0000000000000040ull)
77#define CVMX_PCIEEP_CFG017 \
78 (0x0000000000000044ull)
79#define CVMX_PCIEEP_CFG020 \
80 (0x0000000000000050ull)
81#define CVMX_PCIEEP_CFG021 \
82 (0x0000000000000054ull)
83#define CVMX_PCIEEP_CFG022 \
84 (0x0000000000000058ull)
85#define CVMX_PCIEEP_CFG023 \
86 (0x000000000000005Cull)
87#define CVMX_PCIEEP_CFG028 \
88 (0x0000000000000070ull)
89#define CVMX_PCIEEP_CFG029 \
90 (0x0000000000000074ull)
91#define CVMX_PCIEEP_CFG030 \
92 (0x0000000000000078ull)
93#define CVMX_PCIEEP_CFG031 \
94 (0x000000000000007Cull)
95#define CVMX_PCIEEP_CFG032 \
96 (0x0000000000000080ull)
97#define CVMX_PCIEEP_CFG033 \
98 (0x0000000000000084ull)
99#define CVMX_PCIEEP_CFG034 \
100 (0x0000000000000088ull)
101#define CVMX_PCIEEP_CFG037 \
102 (0x0000000000000094ull)
103#define CVMX_PCIEEP_CFG038 \
104 (0x0000000000000098ull)
105#define CVMX_PCIEEP_CFG039 \
106 (0x000000000000009Cull)
107#define CVMX_PCIEEP_CFG040 \
108 (0x00000000000000A0ull)
109#define CVMX_PCIEEP_CFG041 \
110 (0x00000000000000A4ull)
111#define CVMX_PCIEEP_CFG042 \
112 (0x00000000000000A8ull)
113#define CVMX_PCIEEP_CFG064 \
114 (0x0000000000000100ull)
115#define CVMX_PCIEEP_CFG065 \
116 (0x0000000000000104ull)
117#define CVMX_PCIEEP_CFG066 \
118 (0x0000000000000108ull)
119#define CVMX_PCIEEP_CFG067 \
120 (0x000000000000010Cull)
121#define CVMX_PCIEEP_CFG068 \
122 (0x0000000000000110ull)
123#define CVMX_PCIEEP_CFG069 \
124 (0x0000000000000114ull)
125#define CVMX_PCIEEP_CFG070 \
126 (0x0000000000000118ull)
127#define CVMX_PCIEEP_CFG071 \
128 (0x000000000000011Cull)
129#define CVMX_PCIEEP_CFG072 \
130 (0x0000000000000120ull)
131#define CVMX_PCIEEP_CFG073 \
132 (0x0000000000000124ull)
133#define CVMX_PCIEEP_CFG074 \
134 (0x0000000000000128ull)
135#define CVMX_PCIEEP_CFG448 \
136 (0x0000000000000700ull)
137#define CVMX_PCIEEP_CFG449 \
138 (0x0000000000000704ull)
139#define CVMX_PCIEEP_CFG450 \
140 (0x0000000000000708ull)
141#define CVMX_PCIEEP_CFG451 \
142 (0x000000000000070Cull)
143#define CVMX_PCIEEP_CFG452 \
144 (0x0000000000000710ull)
145#define CVMX_PCIEEP_CFG453 \
146 (0x0000000000000714ull)
147#define CVMX_PCIEEP_CFG454 \
148 (0x0000000000000718ull)
149#define CVMX_PCIEEP_CFG455 \
150 (0x000000000000071Cull)
151#define CVMX_PCIEEP_CFG456 \
152 (0x0000000000000720ull)
153#define CVMX_PCIEEP_CFG458 \
154 (0x0000000000000728ull)
155#define CVMX_PCIEEP_CFG459 \
156 (0x000000000000072Cull)
157#define CVMX_PCIEEP_CFG460 \
158 (0x0000000000000730ull)
159#define CVMX_PCIEEP_CFG461 \
160 (0x0000000000000734ull)
161#define CVMX_PCIEEP_CFG462 \
162 (0x0000000000000738ull)
163#define CVMX_PCIEEP_CFG463 \
164 (0x000000000000073Cull)
165#define CVMX_PCIEEP_CFG464 \
166 (0x0000000000000740ull)
167#define CVMX_PCIEEP_CFG465 \
168 (0x0000000000000744ull)
169#define CVMX_PCIEEP_CFG466 \
170 (0x0000000000000748ull)
171#define CVMX_PCIEEP_CFG467 \
172 (0x000000000000074Cull)
173#define CVMX_PCIEEP_CFG468 \
174 (0x0000000000000750ull)
175#define CVMX_PCIEEP_CFG490 \
176 (0x00000000000007A8ull)
177#define CVMX_PCIEEP_CFG491 \
178 (0x00000000000007ACull)
179#define CVMX_PCIEEP_CFG492 \
180 (0x00000000000007B0ull)
181#define CVMX_PCIEEP_CFG516 \
182 (0x0000000000000810ull)
183#define CVMX_PCIEEP_CFG517 \
184 (0x0000000000000814ull)
185
186union cvmx_pcieep_cfg000 {
187 uint32_t u32;
188 struct cvmx_pcieep_cfg000_s {
189 uint32_t devid:16;
190 uint32_t vendid:16;
191 } s;
192 struct cvmx_pcieep_cfg000_s cn52xx;
193 struct cvmx_pcieep_cfg000_s cn52xxp1;
194 struct cvmx_pcieep_cfg000_s cn56xx;
195 struct cvmx_pcieep_cfg000_s cn56xxp1;
196};
197
198union cvmx_pcieep_cfg001 {
199 uint32_t u32;
200 struct cvmx_pcieep_cfg001_s {
201 uint32_t dpe:1;
202 uint32_t sse:1;
203 uint32_t rma:1;
204 uint32_t rta:1;
205 uint32_t sta:1;
206 uint32_t devt:2;
207 uint32_t mdpe:1;
208 uint32_t fbb:1;
209 uint32_t reserved_22_22:1;
210 uint32_t m66:1;
211 uint32_t cl:1;
212 uint32_t i_stat:1;
213 uint32_t reserved_11_18:8;
214 uint32_t i_dis:1;
215 uint32_t fbbe:1;
216 uint32_t see:1;
217 uint32_t ids_wcc:1;
218 uint32_t per:1;
219 uint32_t vps:1;
220 uint32_t mwice:1;
221 uint32_t scse:1;
222 uint32_t me:1;
223 uint32_t msae:1;
224 uint32_t isae:1;
225 } s;
226 struct cvmx_pcieep_cfg001_s cn52xx;
227 struct cvmx_pcieep_cfg001_s cn52xxp1;
228 struct cvmx_pcieep_cfg001_s cn56xx;
229 struct cvmx_pcieep_cfg001_s cn56xxp1;
230};
231
232union cvmx_pcieep_cfg002 {
233 uint32_t u32;
234 struct cvmx_pcieep_cfg002_s {
235 uint32_t bcc:8;
236 uint32_t sc:8;
237 uint32_t pi:8;
238 uint32_t rid:8;
239 } s;
240 struct cvmx_pcieep_cfg002_s cn52xx;
241 struct cvmx_pcieep_cfg002_s cn52xxp1;
242 struct cvmx_pcieep_cfg002_s cn56xx;
243 struct cvmx_pcieep_cfg002_s cn56xxp1;
244};
245
246union cvmx_pcieep_cfg003 {
247 uint32_t u32;
248 struct cvmx_pcieep_cfg003_s {
249 uint32_t bist:8;
250 uint32_t mfd:1;
251 uint32_t chf:7;
252 uint32_t lt:8;
253 uint32_t cls:8;
254 } s;
255 struct cvmx_pcieep_cfg003_s cn52xx;
256 struct cvmx_pcieep_cfg003_s cn52xxp1;
257 struct cvmx_pcieep_cfg003_s cn56xx;
258 struct cvmx_pcieep_cfg003_s cn56xxp1;
259};
260
261union cvmx_pcieep_cfg004 {
262 uint32_t u32;
263 struct cvmx_pcieep_cfg004_s {
264 uint32_t lbab:18;
265 uint32_t reserved_4_13:10;
266 uint32_t pf:1;
267 uint32_t typ:2;
268 uint32_t mspc:1;
269 } s;
270 struct cvmx_pcieep_cfg004_s cn52xx;
271 struct cvmx_pcieep_cfg004_s cn52xxp1;
272 struct cvmx_pcieep_cfg004_s cn56xx;
273 struct cvmx_pcieep_cfg004_s cn56xxp1;
274};
275
276union cvmx_pcieep_cfg004_mask {
277 uint32_t u32;
278 struct cvmx_pcieep_cfg004_mask_s {
279 uint32_t lmask:31;
280 uint32_t enb:1;
281 } s;
282 struct cvmx_pcieep_cfg004_mask_s cn52xx;
283 struct cvmx_pcieep_cfg004_mask_s cn52xxp1;
284 struct cvmx_pcieep_cfg004_mask_s cn56xx;
285 struct cvmx_pcieep_cfg004_mask_s cn56xxp1;
286};
287
288union cvmx_pcieep_cfg005 {
289 uint32_t u32;
290 struct cvmx_pcieep_cfg005_s {
291 uint32_t ubab:32;
292 } s;
293 struct cvmx_pcieep_cfg005_s cn52xx;
294 struct cvmx_pcieep_cfg005_s cn52xxp1;
295 struct cvmx_pcieep_cfg005_s cn56xx;
296 struct cvmx_pcieep_cfg005_s cn56xxp1;
297};
298
299union cvmx_pcieep_cfg005_mask {
300 uint32_t u32;
301 struct cvmx_pcieep_cfg005_mask_s {
302 uint32_t umask:32;
303 } s;
304 struct cvmx_pcieep_cfg005_mask_s cn52xx;
305 struct cvmx_pcieep_cfg005_mask_s cn52xxp1;
306 struct cvmx_pcieep_cfg005_mask_s cn56xx;
307 struct cvmx_pcieep_cfg005_mask_s cn56xxp1;
308};
309
310union cvmx_pcieep_cfg006 {
311 uint32_t u32;
312 struct cvmx_pcieep_cfg006_s {
313 uint32_t lbab:6;
314 uint32_t reserved_4_25:22;
315 uint32_t pf:1;
316 uint32_t typ:2;
317 uint32_t mspc:1;
318 } s;
319 struct cvmx_pcieep_cfg006_s cn52xx;
320 struct cvmx_pcieep_cfg006_s cn52xxp1;
321 struct cvmx_pcieep_cfg006_s cn56xx;
322 struct cvmx_pcieep_cfg006_s cn56xxp1;
323};
324
325union cvmx_pcieep_cfg006_mask {
326 uint32_t u32;
327 struct cvmx_pcieep_cfg006_mask_s {
328 uint32_t lmask:31;
329 uint32_t enb:1;
330 } s;
331 struct cvmx_pcieep_cfg006_mask_s cn52xx;
332 struct cvmx_pcieep_cfg006_mask_s cn52xxp1;
333 struct cvmx_pcieep_cfg006_mask_s cn56xx;
334 struct cvmx_pcieep_cfg006_mask_s cn56xxp1;
335};
336
337union cvmx_pcieep_cfg007 {
338 uint32_t u32;
339 struct cvmx_pcieep_cfg007_s {
340 uint32_t ubab:32;
341 } s;
342 struct cvmx_pcieep_cfg007_s cn52xx;
343 struct cvmx_pcieep_cfg007_s cn52xxp1;
344 struct cvmx_pcieep_cfg007_s cn56xx;
345 struct cvmx_pcieep_cfg007_s cn56xxp1;
346};
347
348union cvmx_pcieep_cfg007_mask {
349 uint32_t u32;
350 struct cvmx_pcieep_cfg007_mask_s {
351 uint32_t umask:32;
352 } s;
353 struct cvmx_pcieep_cfg007_mask_s cn52xx;
354 struct cvmx_pcieep_cfg007_mask_s cn52xxp1;
355 struct cvmx_pcieep_cfg007_mask_s cn56xx;
356 struct cvmx_pcieep_cfg007_mask_s cn56xxp1;
357};
358
359union cvmx_pcieep_cfg008 {
360 uint32_t u32;
361 struct cvmx_pcieep_cfg008_s {
362 uint32_t reserved_4_31:28;
363 uint32_t pf:1;
364 uint32_t typ:2;
365 uint32_t mspc:1;
366 } s;
367 struct cvmx_pcieep_cfg008_s cn52xx;
368 struct cvmx_pcieep_cfg008_s cn52xxp1;
369 struct cvmx_pcieep_cfg008_s cn56xx;
370 struct cvmx_pcieep_cfg008_s cn56xxp1;
371};
372
373union cvmx_pcieep_cfg008_mask {
374 uint32_t u32;
375 struct cvmx_pcieep_cfg008_mask_s {
376 uint32_t lmask:31;
377 uint32_t enb:1;
378 } s;
379 struct cvmx_pcieep_cfg008_mask_s cn52xx;
380 struct cvmx_pcieep_cfg008_mask_s cn52xxp1;
381 struct cvmx_pcieep_cfg008_mask_s cn56xx;
382 struct cvmx_pcieep_cfg008_mask_s cn56xxp1;
383};
384
385union cvmx_pcieep_cfg009 {
386 uint32_t u32;
387 struct cvmx_pcieep_cfg009_s {
388 uint32_t ubab:25;
389 uint32_t reserved_0_6:7;
390 } s;
391 struct cvmx_pcieep_cfg009_s cn52xx;
392 struct cvmx_pcieep_cfg009_s cn52xxp1;
393 struct cvmx_pcieep_cfg009_s cn56xx;
394 struct cvmx_pcieep_cfg009_s cn56xxp1;
395};
396
397union cvmx_pcieep_cfg009_mask {
398 uint32_t u32;
399 struct cvmx_pcieep_cfg009_mask_s {
400 uint32_t umask:32;
401 } s;
402 struct cvmx_pcieep_cfg009_mask_s cn52xx;
403 struct cvmx_pcieep_cfg009_mask_s cn52xxp1;
404 struct cvmx_pcieep_cfg009_mask_s cn56xx;
405 struct cvmx_pcieep_cfg009_mask_s cn56xxp1;
406};
407
408union cvmx_pcieep_cfg010 {
409 uint32_t u32;
410 struct cvmx_pcieep_cfg010_s {
411 uint32_t cisp:32;
412 } s;
413 struct cvmx_pcieep_cfg010_s cn52xx;
414 struct cvmx_pcieep_cfg010_s cn52xxp1;
415 struct cvmx_pcieep_cfg010_s cn56xx;
416 struct cvmx_pcieep_cfg010_s cn56xxp1;
417};
418
419union cvmx_pcieep_cfg011 {
420 uint32_t u32;
421 struct cvmx_pcieep_cfg011_s {
422 uint32_t ssid:16;
423 uint32_t ssvid:16;
424 } s;
425 struct cvmx_pcieep_cfg011_s cn52xx;
426 struct cvmx_pcieep_cfg011_s cn52xxp1;
427 struct cvmx_pcieep_cfg011_s cn56xx;
428 struct cvmx_pcieep_cfg011_s cn56xxp1;
429};
430
431union cvmx_pcieep_cfg012 {
432 uint32_t u32;
433 struct cvmx_pcieep_cfg012_s {
434 uint32_t eraddr:16;
435 uint32_t reserved_1_15:15;
436 uint32_t er_en:1;
437 } s;
438 struct cvmx_pcieep_cfg012_s cn52xx;
439 struct cvmx_pcieep_cfg012_s cn52xxp1;
440 struct cvmx_pcieep_cfg012_s cn56xx;
441 struct cvmx_pcieep_cfg012_s cn56xxp1;
442};
443
444union cvmx_pcieep_cfg012_mask {
445 uint32_t u32;
446 struct cvmx_pcieep_cfg012_mask_s {
447 uint32_t mask:31;
448 uint32_t enb:1;
449 } s;
450 struct cvmx_pcieep_cfg012_mask_s cn52xx;
451 struct cvmx_pcieep_cfg012_mask_s cn52xxp1;
452 struct cvmx_pcieep_cfg012_mask_s cn56xx;
453 struct cvmx_pcieep_cfg012_mask_s cn56xxp1;
454};
455
456union cvmx_pcieep_cfg013 {
457 uint32_t u32;
458 struct cvmx_pcieep_cfg013_s {
459 uint32_t reserved_8_31:24;
460 uint32_t cp:8;
461 } s;
462 struct cvmx_pcieep_cfg013_s cn52xx;
463 struct cvmx_pcieep_cfg013_s cn52xxp1;
464 struct cvmx_pcieep_cfg013_s cn56xx;
465 struct cvmx_pcieep_cfg013_s cn56xxp1;
466};
467
468union cvmx_pcieep_cfg015 {
469 uint32_t u32;
470 struct cvmx_pcieep_cfg015_s {
471 uint32_t ml:8;
472 uint32_t mg:8;
473 uint32_t inta:8;
474 uint32_t il:8;
475 } s;
476 struct cvmx_pcieep_cfg015_s cn52xx;
477 struct cvmx_pcieep_cfg015_s cn52xxp1;
478 struct cvmx_pcieep_cfg015_s cn56xx;
479 struct cvmx_pcieep_cfg015_s cn56xxp1;
480};
481
482union cvmx_pcieep_cfg016 {
483 uint32_t u32;
484 struct cvmx_pcieep_cfg016_s {
485 uint32_t pmes:5;
486 uint32_t d2s:1;
487 uint32_t d1s:1;
488 uint32_t auxc:3;
489 uint32_t dsi:1;
490 uint32_t reserved_20_20:1;
491 uint32_t pme_clock:1;
492 uint32_t pmsv:3;
493 uint32_t ncp:8;
494 uint32_t pmcid:8;
495 } s;
496 struct cvmx_pcieep_cfg016_s cn52xx;
497 struct cvmx_pcieep_cfg016_s cn52xxp1;
498 struct cvmx_pcieep_cfg016_s cn56xx;
499 struct cvmx_pcieep_cfg016_s cn56xxp1;
500};
501
502union cvmx_pcieep_cfg017 {
503 uint32_t u32;
504 struct cvmx_pcieep_cfg017_s {
505 uint32_t pmdia:8;
506 uint32_t bpccee:1;
507 uint32_t bd3h:1;
508 uint32_t reserved_16_21:6;
509 uint32_t pmess:1;
510 uint32_t pmedsia:2;
511 uint32_t pmds:4;
512 uint32_t pmeens:1;
513 uint32_t reserved_4_7:4;
514 uint32_t nsr:1;
515 uint32_t reserved_2_2:1;
516 uint32_t ps:2;
517 } s;
518 struct cvmx_pcieep_cfg017_s cn52xx;
519 struct cvmx_pcieep_cfg017_s cn52xxp1;
520 struct cvmx_pcieep_cfg017_s cn56xx;
521 struct cvmx_pcieep_cfg017_s cn56xxp1;
522};
523
524union cvmx_pcieep_cfg020 {
525 uint32_t u32;
526 struct cvmx_pcieep_cfg020_s {
527 uint32_t reserved_24_31:8;
528 uint32_t m64:1;
529 uint32_t mme:3;
530 uint32_t mmc:3;
531 uint32_t msien:1;
532 uint32_t ncp:8;
533 uint32_t msicid:8;
534 } s;
535 struct cvmx_pcieep_cfg020_s cn52xx;
536 struct cvmx_pcieep_cfg020_s cn52xxp1;
537 struct cvmx_pcieep_cfg020_s cn56xx;
538 struct cvmx_pcieep_cfg020_s cn56xxp1;
539};
540
541union cvmx_pcieep_cfg021 {
542 uint32_t u32;
543 struct cvmx_pcieep_cfg021_s {
544 uint32_t lmsi:30;
545 uint32_t reserved_0_1:2;
546 } s;
547 struct cvmx_pcieep_cfg021_s cn52xx;
548 struct cvmx_pcieep_cfg021_s cn52xxp1;
549 struct cvmx_pcieep_cfg021_s cn56xx;
550 struct cvmx_pcieep_cfg021_s cn56xxp1;
551};
552
553union cvmx_pcieep_cfg022 {
554 uint32_t u32;
555 struct cvmx_pcieep_cfg022_s {
556 uint32_t umsi:32;
557 } s;
558 struct cvmx_pcieep_cfg022_s cn52xx;
559 struct cvmx_pcieep_cfg022_s cn52xxp1;
560 struct cvmx_pcieep_cfg022_s cn56xx;
561 struct cvmx_pcieep_cfg022_s cn56xxp1;
562};
563
564union cvmx_pcieep_cfg023 {
565 uint32_t u32;
566 struct cvmx_pcieep_cfg023_s {
567 uint32_t reserved_16_31:16;
568 uint32_t msimd:16;
569 } s;
570 struct cvmx_pcieep_cfg023_s cn52xx;
571 struct cvmx_pcieep_cfg023_s cn52xxp1;
572 struct cvmx_pcieep_cfg023_s cn56xx;
573 struct cvmx_pcieep_cfg023_s cn56xxp1;
574};
575
576union cvmx_pcieep_cfg028 {
577 uint32_t u32;
578 struct cvmx_pcieep_cfg028_s {
579 uint32_t reserved_30_31:2;
580 uint32_t imn:5;
581 uint32_t si:1;
582 uint32_t dpt:4;
583 uint32_t pciecv:4;
584 uint32_t ncp:8;
585 uint32_t pcieid:8;
586 } s;
587 struct cvmx_pcieep_cfg028_s cn52xx;
588 struct cvmx_pcieep_cfg028_s cn52xxp1;
589 struct cvmx_pcieep_cfg028_s cn56xx;
590 struct cvmx_pcieep_cfg028_s cn56xxp1;
591};
592
593union cvmx_pcieep_cfg029 {
594 uint32_t u32;
595 struct cvmx_pcieep_cfg029_s {
596 uint32_t reserved_28_31:4;
597 uint32_t cspls:2;
598 uint32_t csplv:8;
599 uint32_t reserved_16_17:2;
600 uint32_t rber:1;
601 uint32_t reserved_12_14:3;
602 uint32_t el1al:3;
603 uint32_t el0al:3;
604 uint32_t etfs:1;
605 uint32_t pfs:2;
606 uint32_t mpss:3;
607 } s;
608 struct cvmx_pcieep_cfg029_s cn52xx;
609 struct cvmx_pcieep_cfg029_s cn52xxp1;
610 struct cvmx_pcieep_cfg029_s cn56xx;
611 struct cvmx_pcieep_cfg029_s cn56xxp1;
612};
613
614union cvmx_pcieep_cfg030 {
615 uint32_t u32;
616 struct cvmx_pcieep_cfg030_s {
617 uint32_t reserved_22_31:10;
618 uint32_t tp:1;
619 uint32_t ap_d:1;
620 uint32_t ur_d:1;
621 uint32_t fe_d:1;
622 uint32_t nfe_d:1;
623 uint32_t ce_d:1;
624 uint32_t reserved_15_15:1;
625 uint32_t mrrs:3;
626 uint32_t ns_en:1;
627 uint32_t ap_en:1;
628 uint32_t pf_en:1;
629 uint32_t etf_en:1;
630 uint32_t mps:3;
631 uint32_t ro_en:1;
632 uint32_t ur_en:1;
633 uint32_t fe_en:1;
634 uint32_t nfe_en:1;
635 uint32_t ce_en:1;
636 } s;
637 struct cvmx_pcieep_cfg030_s cn52xx;
638 struct cvmx_pcieep_cfg030_s cn52xxp1;
639 struct cvmx_pcieep_cfg030_s cn56xx;
640 struct cvmx_pcieep_cfg030_s cn56xxp1;
641};
642
643union cvmx_pcieep_cfg031 {
644 uint32_t u32;
645 struct cvmx_pcieep_cfg031_s {
646 uint32_t pnum:8;
647 uint32_t reserved_22_23:2;
648 uint32_t lbnc:1;
649 uint32_t dllarc:1;
650 uint32_t sderc:1;
651 uint32_t cpm:1;
652 uint32_t l1el:3;
653 uint32_t l0el:3;
654 uint32_t aslpms:2;
655 uint32_t mlw:6;
656 uint32_t mls:4;
657 } s;
658 struct cvmx_pcieep_cfg031_s cn52xx;
659 struct cvmx_pcieep_cfg031_s cn52xxp1;
660 struct cvmx_pcieep_cfg031_s cn56xx;
661 struct cvmx_pcieep_cfg031_s cn56xxp1;
662};
663
664union cvmx_pcieep_cfg032 {
665 uint32_t u32;
666 struct cvmx_pcieep_cfg032_s {
667 uint32_t reserved_30_31:2;
668 uint32_t dlla:1;
669 uint32_t scc:1;
670 uint32_t lt:1;
671 uint32_t reserved_26_26:1;
672 uint32_t nlw:6;
673 uint32_t ls:4;
674 uint32_t reserved_10_15:6;
675 uint32_t hawd:1;
676 uint32_t ecpm:1;
677 uint32_t es:1;
678 uint32_t ccc:1;
679 uint32_t rl:1;
680 uint32_t ld:1;
681 uint32_t rcb:1;
682 uint32_t reserved_2_2:1;
683 uint32_t aslpc:2;
684 } s;
685 struct cvmx_pcieep_cfg032_s cn52xx;
686 struct cvmx_pcieep_cfg032_s cn52xxp1;
687 struct cvmx_pcieep_cfg032_s cn56xx;
688 struct cvmx_pcieep_cfg032_s cn56xxp1;
689};
690
691union cvmx_pcieep_cfg033 {
692 uint32_t u32;
693 struct cvmx_pcieep_cfg033_s {
694 uint32_t ps_num:13;
695 uint32_t nccs:1;
696 uint32_t emip:1;
697 uint32_t sp_ls:2;
698 uint32_t sp_lv:8;
699 uint32_t hp_c:1;
700 uint32_t hp_s:1;
701 uint32_t pip:1;
702 uint32_t aip:1;
703 uint32_t mrlsp:1;
704 uint32_t pcp:1;
705 uint32_t abp:1;
706 } s;
707 struct cvmx_pcieep_cfg033_s cn52xx;
708 struct cvmx_pcieep_cfg033_s cn52xxp1;
709 struct cvmx_pcieep_cfg033_s cn56xx;
710 struct cvmx_pcieep_cfg033_s cn56xxp1;
711};
712
713union cvmx_pcieep_cfg034 {
714 uint32_t u32;
715 struct cvmx_pcieep_cfg034_s {
716 uint32_t reserved_25_31:7;
717 uint32_t dlls_c:1;
718 uint32_t emis:1;
719 uint32_t pds:1;
720 uint32_t mrlss:1;
721 uint32_t ccint_d:1;
722 uint32_t pd_c:1;
723 uint32_t mrls_c:1;
724 uint32_t pf_d:1;
725 uint32_t abp_d:1;
726 uint32_t reserved_13_15:3;
727 uint32_t dlls_en:1;
728 uint32_t emic:1;
729 uint32_t pcc:1;
730 uint32_t pic:2;
731 uint32_t aic:2;
732 uint32_t hpint_en:1;
733 uint32_t ccint_en:1;
734 uint32_t pd_en:1;
735 uint32_t mrls_en:1;
736 uint32_t pf_en:1;
737 uint32_t abp_en:1;
738 } s;
739 struct cvmx_pcieep_cfg034_s cn52xx;
740 struct cvmx_pcieep_cfg034_s cn52xxp1;
741 struct cvmx_pcieep_cfg034_s cn56xx;
742 struct cvmx_pcieep_cfg034_s cn56xxp1;
743};
744
745union cvmx_pcieep_cfg037 {
746 uint32_t u32;
747 struct cvmx_pcieep_cfg037_s {
748 uint32_t reserved_5_31:27;
749 uint32_t ctds:1;
750 uint32_t ctrs:4;
751 } s;
752 struct cvmx_pcieep_cfg037_s cn52xx;
753 struct cvmx_pcieep_cfg037_s cn52xxp1;
754 struct cvmx_pcieep_cfg037_s cn56xx;
755 struct cvmx_pcieep_cfg037_s cn56xxp1;
756};
757
758union cvmx_pcieep_cfg038 {
759 uint32_t u32;
760 struct cvmx_pcieep_cfg038_s {
761 uint32_t reserved_5_31:27;
762 uint32_t ctd:1;
763 uint32_t ctv:4;
764 } s;
765 struct cvmx_pcieep_cfg038_s cn52xx;
766 struct cvmx_pcieep_cfg038_s cn52xxp1;
767 struct cvmx_pcieep_cfg038_s cn56xx;
768 struct cvmx_pcieep_cfg038_s cn56xxp1;
769};
770
771union cvmx_pcieep_cfg039 {
772 uint32_t u32;
773 struct cvmx_pcieep_cfg039_s {
774 uint32_t reserved_0_31:32;
775 } s;
776 struct cvmx_pcieep_cfg039_s cn52xx;
777 struct cvmx_pcieep_cfg039_s cn52xxp1;
778 struct cvmx_pcieep_cfg039_s cn56xx;
779 struct cvmx_pcieep_cfg039_s cn56xxp1;
780};
781
782union cvmx_pcieep_cfg040 {
783 uint32_t u32;
784 struct cvmx_pcieep_cfg040_s {
785 uint32_t reserved_0_31:32;
786 } s;
787 struct cvmx_pcieep_cfg040_s cn52xx;
788 struct cvmx_pcieep_cfg040_s cn52xxp1;
789 struct cvmx_pcieep_cfg040_s cn56xx;
790 struct cvmx_pcieep_cfg040_s cn56xxp1;
791};
792
793union cvmx_pcieep_cfg041 {
794 uint32_t u32;
795 struct cvmx_pcieep_cfg041_s {
796 uint32_t reserved_0_31:32;
797 } s;
798 struct cvmx_pcieep_cfg041_s cn52xx;
799 struct cvmx_pcieep_cfg041_s cn52xxp1;
800 struct cvmx_pcieep_cfg041_s cn56xx;
801 struct cvmx_pcieep_cfg041_s cn56xxp1;
802};
803
804union cvmx_pcieep_cfg042 {
805 uint32_t u32;
806 struct cvmx_pcieep_cfg042_s {
807 uint32_t reserved_0_31:32;
808 } s;
809 struct cvmx_pcieep_cfg042_s cn52xx;
810 struct cvmx_pcieep_cfg042_s cn52xxp1;
811 struct cvmx_pcieep_cfg042_s cn56xx;
812 struct cvmx_pcieep_cfg042_s cn56xxp1;
813};
814
815union cvmx_pcieep_cfg064 {
816 uint32_t u32;
817 struct cvmx_pcieep_cfg064_s {
818 uint32_t nco:12;
819 uint32_t cv:4;
820 uint32_t pcieec:16;
821 } s;
822 struct cvmx_pcieep_cfg064_s cn52xx;
823 struct cvmx_pcieep_cfg064_s cn52xxp1;
824 struct cvmx_pcieep_cfg064_s cn56xx;
825 struct cvmx_pcieep_cfg064_s cn56xxp1;
826};
827
828union cvmx_pcieep_cfg065 {
829 uint32_t u32;
830 struct cvmx_pcieep_cfg065_s {
831 uint32_t reserved_21_31:11;
832 uint32_t ures:1;
833 uint32_t ecrces:1;
834 uint32_t mtlps:1;
835 uint32_t ros:1;
836 uint32_t ucs:1;
837 uint32_t cas:1;
838 uint32_t cts:1;
839 uint32_t fcpes:1;
840 uint32_t ptlps:1;
841 uint32_t reserved_6_11:6;
842 uint32_t sdes:1;
843 uint32_t dlpes:1;
844 uint32_t reserved_0_3:4;
845 } s;
846 struct cvmx_pcieep_cfg065_s cn52xx;
847 struct cvmx_pcieep_cfg065_s cn52xxp1;
848 struct cvmx_pcieep_cfg065_s cn56xx;
849 struct cvmx_pcieep_cfg065_s cn56xxp1;
850};
851
852union cvmx_pcieep_cfg066 {
853 uint32_t u32;
854 struct cvmx_pcieep_cfg066_s {
855 uint32_t reserved_21_31:11;
856 uint32_t urem:1;
857 uint32_t ecrcem:1;
858 uint32_t mtlpm:1;
859 uint32_t rom:1;
860 uint32_t ucm:1;
861 uint32_t cam:1;
862 uint32_t ctm:1;
863 uint32_t fcpem:1;
864 uint32_t ptlpm:1;
865 uint32_t reserved_6_11:6;
866 uint32_t sdem:1;
867 uint32_t dlpem:1;
868 uint32_t reserved_0_3:4;
869 } s;
870 struct cvmx_pcieep_cfg066_s cn52xx;
871 struct cvmx_pcieep_cfg066_s cn52xxp1;
872 struct cvmx_pcieep_cfg066_s cn56xx;
873 struct cvmx_pcieep_cfg066_s cn56xxp1;
874};
875
876union cvmx_pcieep_cfg067 {
877 uint32_t u32;
878 struct cvmx_pcieep_cfg067_s {
879 uint32_t reserved_21_31:11;
880 uint32_t ures:1;
881 uint32_t ecrces:1;
882 uint32_t mtlps:1;
883 uint32_t ros:1;
884 uint32_t ucs:1;
885 uint32_t cas:1;
886 uint32_t cts:1;
887 uint32_t fcpes:1;
888 uint32_t ptlps:1;
889 uint32_t reserved_6_11:6;
890 uint32_t sdes:1;
891 uint32_t dlpes:1;
892 uint32_t reserved_0_3:4;
893 } s;
894 struct cvmx_pcieep_cfg067_s cn52xx;
895 struct cvmx_pcieep_cfg067_s cn52xxp1;
896 struct cvmx_pcieep_cfg067_s cn56xx;
897 struct cvmx_pcieep_cfg067_s cn56xxp1;
898};
899
900union cvmx_pcieep_cfg068 {
901 uint32_t u32;
902 struct cvmx_pcieep_cfg068_s {
903 uint32_t reserved_14_31:18;
904 uint32_t anfes:1;
905 uint32_t rtts:1;
906 uint32_t reserved_9_11:3;
907 uint32_t rnrs:1;
908 uint32_t bdllps:1;
909 uint32_t btlps:1;
910 uint32_t reserved_1_5:5;
911 uint32_t res:1;
912 } s;
913 struct cvmx_pcieep_cfg068_s cn52xx;
914 struct cvmx_pcieep_cfg068_s cn52xxp1;
915 struct cvmx_pcieep_cfg068_s cn56xx;
916 struct cvmx_pcieep_cfg068_s cn56xxp1;
917};
918
919union cvmx_pcieep_cfg069 {
920 uint32_t u32;
921 struct cvmx_pcieep_cfg069_s {
922 uint32_t reserved_14_31:18;
923 uint32_t anfem:1;
924 uint32_t rttm:1;
925 uint32_t reserved_9_11:3;
926 uint32_t rnrm:1;
927 uint32_t bdllpm:1;
928 uint32_t btlpm:1;
929 uint32_t reserved_1_5:5;
930 uint32_t rem:1;
931 } s;
932 struct cvmx_pcieep_cfg069_s cn52xx;
933 struct cvmx_pcieep_cfg069_s cn52xxp1;
934 struct cvmx_pcieep_cfg069_s cn56xx;
935 struct cvmx_pcieep_cfg069_s cn56xxp1;
936};
937
938union cvmx_pcieep_cfg070 {
939 uint32_t u32;
940 struct cvmx_pcieep_cfg070_s {
941 uint32_t reserved_9_31:23;
942 uint32_t ce:1;
943 uint32_t cc:1;
944 uint32_t ge:1;
945 uint32_t gc:1;
946 uint32_t fep:5;
947 } s;
948 struct cvmx_pcieep_cfg070_s cn52xx;
949 struct cvmx_pcieep_cfg070_s cn52xxp1;
950 struct cvmx_pcieep_cfg070_s cn56xx;
951 struct cvmx_pcieep_cfg070_s cn56xxp1;
952};
953
954union cvmx_pcieep_cfg071 {
955 uint32_t u32;
956 struct cvmx_pcieep_cfg071_s {
957 uint32_t dword1:32;
958 } s;
959 struct cvmx_pcieep_cfg071_s cn52xx;
960 struct cvmx_pcieep_cfg071_s cn52xxp1;
961 struct cvmx_pcieep_cfg071_s cn56xx;
962 struct cvmx_pcieep_cfg071_s cn56xxp1;
963};
964
965union cvmx_pcieep_cfg072 {
966 uint32_t u32;
967 struct cvmx_pcieep_cfg072_s {
968 uint32_t dword2:32;
969 } s;
970 struct cvmx_pcieep_cfg072_s cn52xx;
971 struct cvmx_pcieep_cfg072_s cn52xxp1;
972 struct cvmx_pcieep_cfg072_s cn56xx;
973 struct cvmx_pcieep_cfg072_s cn56xxp1;
974};
975
976union cvmx_pcieep_cfg073 {
977 uint32_t u32;
978 struct cvmx_pcieep_cfg073_s {
979 uint32_t dword3:32;
980 } s;
981 struct cvmx_pcieep_cfg073_s cn52xx;
982 struct cvmx_pcieep_cfg073_s cn52xxp1;
983 struct cvmx_pcieep_cfg073_s cn56xx;
984 struct cvmx_pcieep_cfg073_s cn56xxp1;
985};
986
987union cvmx_pcieep_cfg074 {
988 uint32_t u32;
989 struct cvmx_pcieep_cfg074_s {
990 uint32_t dword4:32;
991 } s;
992 struct cvmx_pcieep_cfg074_s cn52xx;
993 struct cvmx_pcieep_cfg074_s cn52xxp1;
994 struct cvmx_pcieep_cfg074_s cn56xx;
995 struct cvmx_pcieep_cfg074_s cn56xxp1;
996};
997
998union cvmx_pcieep_cfg448 {
999 uint32_t u32;
1000 struct cvmx_pcieep_cfg448_s {
1001 uint32_t rtl:16;
1002 uint32_t rtltl:16;
1003 } s;
1004 struct cvmx_pcieep_cfg448_s cn52xx;
1005 struct cvmx_pcieep_cfg448_s cn52xxp1;
1006 struct cvmx_pcieep_cfg448_s cn56xx;
1007 struct cvmx_pcieep_cfg448_s cn56xxp1;
1008};
1009
1010union cvmx_pcieep_cfg449 {
1011 uint32_t u32;
1012 struct cvmx_pcieep_cfg449_s {
1013 uint32_t omr:32;
1014 } s;
1015 struct cvmx_pcieep_cfg449_s cn52xx;
1016 struct cvmx_pcieep_cfg449_s cn52xxp1;
1017 struct cvmx_pcieep_cfg449_s cn56xx;
1018 struct cvmx_pcieep_cfg449_s cn56xxp1;
1019};
1020
1021union cvmx_pcieep_cfg450 {
1022 uint32_t u32;
1023 struct cvmx_pcieep_cfg450_s {
1024 uint32_t lpec:8;
1025 uint32_t reserved_22_23:2;
1026 uint32_t link_state:6;
1027 uint32_t force_link:1;
1028 uint32_t reserved_8_14:7;
1029 uint32_t link_num:8;
1030 } s;
1031 struct cvmx_pcieep_cfg450_s cn52xx;
1032 struct cvmx_pcieep_cfg450_s cn52xxp1;
1033 struct cvmx_pcieep_cfg450_s cn56xx;
1034 struct cvmx_pcieep_cfg450_s cn56xxp1;
1035};
1036
1037union cvmx_pcieep_cfg451 {
1038 uint32_t u32;
1039 struct cvmx_pcieep_cfg451_s {
1040 uint32_t reserved_30_31:2;
1041 uint32_t l1el:3;
1042 uint32_t l0el:3;
1043 uint32_t n_fts_cc:8;
1044 uint32_t n_fts:8;
1045 uint32_t ack_freq:8;
1046 } s;
1047 struct cvmx_pcieep_cfg451_s cn52xx;
1048 struct cvmx_pcieep_cfg451_s cn52xxp1;
1049 struct cvmx_pcieep_cfg451_s cn56xx;
1050 struct cvmx_pcieep_cfg451_s cn56xxp1;
1051};
1052
1053union cvmx_pcieep_cfg452 {
1054 uint32_t u32;
1055 struct cvmx_pcieep_cfg452_s {
1056 uint32_t reserved_26_31:6;
1057 uint32_t eccrc:1;
1058 uint32_t reserved_22_24:3;
1059 uint32_t lme:6;
1060 uint32_t reserved_8_15:8;
1061 uint32_t flm:1;
1062 uint32_t reserved_6_6:1;
1063 uint32_t dllle:1;
1064 uint32_t reserved_4_4:1;
1065 uint32_t ra:1;
1066 uint32_t le:1;
1067 uint32_t sd:1;
1068 uint32_t omr:1;
1069 } s;
1070 struct cvmx_pcieep_cfg452_s cn52xx;
1071 struct cvmx_pcieep_cfg452_s cn52xxp1;
1072 struct cvmx_pcieep_cfg452_s cn56xx;
1073 struct cvmx_pcieep_cfg452_s cn56xxp1;
1074};
1075
1076union cvmx_pcieep_cfg453 {
1077 uint32_t u32;
1078 struct cvmx_pcieep_cfg453_s {
1079 uint32_t dlld:1;
1080 uint32_t reserved_26_30:5;
1081 uint32_t ack_nak:1;
1082 uint32_t fcd:1;
1083 uint32_t ilst:24;
1084 } s;
1085 struct cvmx_pcieep_cfg453_s cn52xx;
1086 struct cvmx_pcieep_cfg453_s cn52xxp1;
1087 struct cvmx_pcieep_cfg453_s cn56xx;
1088 struct cvmx_pcieep_cfg453_s cn56xxp1;
1089};
1090
1091union cvmx_pcieep_cfg454 {
1092 uint32_t u32;
1093 struct cvmx_pcieep_cfg454_s {
1094 uint32_t reserved_29_31:3;
1095 uint32_t tmfcwt:5;
1096 uint32_t tmanlt:5;
1097 uint32_t tmrt:5;
1098 uint32_t reserved_11_13:3;
1099 uint32_t nskps:3;
1100 uint32_t reserved_4_7:4;
1101 uint32_t ntss:4;
1102 } s;
1103 struct cvmx_pcieep_cfg454_s cn52xx;
1104 struct cvmx_pcieep_cfg454_s cn52xxp1;
1105 struct cvmx_pcieep_cfg454_s cn56xx;
1106 struct cvmx_pcieep_cfg454_s cn56xxp1;
1107};
1108
1109union cvmx_pcieep_cfg455 {
1110 uint32_t u32;
1111 struct cvmx_pcieep_cfg455_s {
1112 uint32_t m_cfg0_filt:1;
1113 uint32_t m_io_filt:1;
1114 uint32_t msg_ctrl:1;
1115 uint32_t m_cpl_ecrc_filt:1;
1116 uint32_t m_ecrc_filt:1;
1117 uint32_t m_cpl_len_err:1;
1118 uint32_t m_cpl_attr_err:1;
1119 uint32_t m_cpl_tc_err:1;
1120 uint32_t m_cpl_fun_err:1;
1121 uint32_t m_cpl_rid_err:1;
1122 uint32_t m_cpl_tag_err:1;
1123 uint32_t m_lk_filt:1;
1124 uint32_t m_cfg1_filt:1;
1125 uint32_t m_bar_match:1;
1126 uint32_t m_pois_filt:1;
1127 uint32_t m_fun:1;
1128 uint32_t dfcwt:1;
1129 uint32_t reserved_11_14:4;
1130 uint32_t skpiv:11;
1131 } s;
1132 struct cvmx_pcieep_cfg455_s cn52xx;
1133 struct cvmx_pcieep_cfg455_s cn52xxp1;
1134 struct cvmx_pcieep_cfg455_s cn56xx;
1135 struct cvmx_pcieep_cfg455_s cn56xxp1;
1136};
1137
1138union cvmx_pcieep_cfg456 {
1139 uint32_t u32;
1140 struct cvmx_pcieep_cfg456_s {
1141 uint32_t reserved_2_31:30;
1142 uint32_t m_vend1_drp:1;
1143 uint32_t m_vend0_drp:1;
1144 } s;
1145 struct cvmx_pcieep_cfg456_s cn52xx;
1146 struct cvmx_pcieep_cfg456_s cn52xxp1;
1147 struct cvmx_pcieep_cfg456_s cn56xx;
1148 struct cvmx_pcieep_cfg456_s cn56xxp1;
1149};
1150
1151union cvmx_pcieep_cfg458 {
1152 uint32_t u32;
1153 struct cvmx_pcieep_cfg458_s {
1154 uint32_t dbg_info_l32:32;
1155 } s;
1156 struct cvmx_pcieep_cfg458_s cn52xx;
1157 struct cvmx_pcieep_cfg458_s cn52xxp1;
1158 struct cvmx_pcieep_cfg458_s cn56xx;
1159 struct cvmx_pcieep_cfg458_s cn56xxp1;
1160};
1161
1162union cvmx_pcieep_cfg459 {
1163 uint32_t u32;
1164 struct cvmx_pcieep_cfg459_s {
1165 uint32_t dbg_info_u32:32;
1166 } s;
1167 struct cvmx_pcieep_cfg459_s cn52xx;
1168 struct cvmx_pcieep_cfg459_s cn52xxp1;
1169 struct cvmx_pcieep_cfg459_s cn56xx;
1170 struct cvmx_pcieep_cfg459_s cn56xxp1;
1171};
1172
1173union cvmx_pcieep_cfg460 {
1174 uint32_t u32;
1175 struct cvmx_pcieep_cfg460_s {
1176 uint32_t reserved_20_31:12;
1177 uint32_t tphfcc:8;
1178 uint32_t tpdfcc:12;
1179 } s;
1180 struct cvmx_pcieep_cfg460_s cn52xx;
1181 struct cvmx_pcieep_cfg460_s cn52xxp1;
1182 struct cvmx_pcieep_cfg460_s cn56xx;
1183 struct cvmx_pcieep_cfg460_s cn56xxp1;
1184};
1185
1186union cvmx_pcieep_cfg461 {
1187 uint32_t u32;
1188 struct cvmx_pcieep_cfg461_s {
1189 uint32_t reserved_20_31:12;
1190 uint32_t tchfcc:8;
1191 uint32_t tcdfcc:12;
1192 } s;
1193 struct cvmx_pcieep_cfg461_s cn52xx;
1194 struct cvmx_pcieep_cfg461_s cn52xxp1;
1195 struct cvmx_pcieep_cfg461_s cn56xx;
1196 struct cvmx_pcieep_cfg461_s cn56xxp1;
1197};
1198
1199union cvmx_pcieep_cfg462 {
1200 uint32_t u32;
1201 struct cvmx_pcieep_cfg462_s {
1202 uint32_t reserved_20_31:12;
1203 uint32_t tchfcc:8;
1204 uint32_t tcdfcc:12;
1205 } s;
1206 struct cvmx_pcieep_cfg462_s cn52xx;
1207 struct cvmx_pcieep_cfg462_s cn52xxp1;
1208 struct cvmx_pcieep_cfg462_s cn56xx;
1209 struct cvmx_pcieep_cfg462_s cn56xxp1;
1210};
1211
1212union cvmx_pcieep_cfg463 {
1213 uint32_t u32;
1214 struct cvmx_pcieep_cfg463_s {
1215 uint32_t reserved_3_31:29;
1216 uint32_t rqne:1;
1217 uint32_t trbne:1;
1218 uint32_t rtlpfccnr:1;
1219 } s;
1220 struct cvmx_pcieep_cfg463_s cn52xx;
1221 struct cvmx_pcieep_cfg463_s cn52xxp1;
1222 struct cvmx_pcieep_cfg463_s cn56xx;
1223 struct cvmx_pcieep_cfg463_s cn56xxp1;
1224};
1225
1226union cvmx_pcieep_cfg464 {
1227 uint32_t u32;
1228 struct cvmx_pcieep_cfg464_s {
1229 uint32_t wrr_vc3:8;
1230 uint32_t wrr_vc2:8;
1231 uint32_t wrr_vc1:8;
1232 uint32_t wrr_vc0:8;
1233 } s;
1234 struct cvmx_pcieep_cfg464_s cn52xx;
1235 struct cvmx_pcieep_cfg464_s cn52xxp1;
1236 struct cvmx_pcieep_cfg464_s cn56xx;
1237 struct cvmx_pcieep_cfg464_s cn56xxp1;
1238};
1239
1240union cvmx_pcieep_cfg465 {
1241 uint32_t u32;
1242 struct cvmx_pcieep_cfg465_s {
1243 uint32_t wrr_vc7:8;
1244 uint32_t wrr_vc6:8;
1245 uint32_t wrr_vc5:8;
1246 uint32_t wrr_vc4:8;
1247 } s;
1248 struct cvmx_pcieep_cfg465_s cn52xx;
1249 struct cvmx_pcieep_cfg465_s cn52xxp1;
1250 struct cvmx_pcieep_cfg465_s cn56xx;
1251 struct cvmx_pcieep_cfg465_s cn56xxp1;
1252};
1253
1254union cvmx_pcieep_cfg466 {
1255 uint32_t u32;
1256 struct cvmx_pcieep_cfg466_s {
1257 uint32_t rx_queue_order:1;
1258 uint32_t type_ordering:1;
1259 uint32_t reserved_24_29:6;
1260 uint32_t queue_mode:3;
1261 uint32_t reserved_20_20:1;
1262 uint32_t header_credits:8;
1263 uint32_t data_credits:12;
1264 } s;
1265 struct cvmx_pcieep_cfg466_s cn52xx;
1266 struct cvmx_pcieep_cfg466_s cn52xxp1;
1267 struct cvmx_pcieep_cfg466_s cn56xx;
1268 struct cvmx_pcieep_cfg466_s cn56xxp1;
1269};
1270
1271union cvmx_pcieep_cfg467 {
1272 uint32_t u32;
1273 struct cvmx_pcieep_cfg467_s {
1274 uint32_t reserved_24_31:8;
1275 uint32_t queue_mode:3;
1276 uint32_t reserved_20_20:1;
1277 uint32_t header_credits:8;
1278 uint32_t data_credits:12;
1279 } s;
1280 struct cvmx_pcieep_cfg467_s cn52xx;
1281 struct cvmx_pcieep_cfg467_s cn52xxp1;
1282 struct cvmx_pcieep_cfg467_s cn56xx;
1283 struct cvmx_pcieep_cfg467_s cn56xxp1;
1284};
1285
1286union cvmx_pcieep_cfg468 {
1287 uint32_t u32;
1288 struct cvmx_pcieep_cfg468_s {
1289 uint32_t reserved_24_31:8;
1290 uint32_t queue_mode:3;
1291 uint32_t reserved_20_20:1;
1292 uint32_t header_credits:8;
1293 uint32_t data_credits:12;
1294 } s;
1295 struct cvmx_pcieep_cfg468_s cn52xx;
1296 struct cvmx_pcieep_cfg468_s cn52xxp1;
1297 struct cvmx_pcieep_cfg468_s cn56xx;
1298 struct cvmx_pcieep_cfg468_s cn56xxp1;
1299};
1300
1301union cvmx_pcieep_cfg490 {
1302 uint32_t u32;
1303 struct cvmx_pcieep_cfg490_s {
1304 uint32_t reserved_26_31:6;
1305 uint32_t header_depth:10;
1306 uint32_t reserved_14_15:2;
1307 uint32_t data_depth:14;
1308 } s;
1309 struct cvmx_pcieep_cfg490_s cn52xx;
1310 struct cvmx_pcieep_cfg490_s cn52xxp1;
1311 struct cvmx_pcieep_cfg490_s cn56xx;
1312 struct cvmx_pcieep_cfg490_s cn56xxp1;
1313};
1314
1315union cvmx_pcieep_cfg491 {
1316 uint32_t u32;
1317 struct cvmx_pcieep_cfg491_s {
1318 uint32_t reserved_26_31:6;
1319 uint32_t header_depth:10;
1320 uint32_t reserved_14_15:2;
1321 uint32_t data_depth:14;
1322 } s;
1323 struct cvmx_pcieep_cfg491_s cn52xx;
1324 struct cvmx_pcieep_cfg491_s cn52xxp1;
1325 struct cvmx_pcieep_cfg491_s cn56xx;
1326 struct cvmx_pcieep_cfg491_s cn56xxp1;
1327};
1328
1329union cvmx_pcieep_cfg492 {
1330 uint32_t u32;
1331 struct cvmx_pcieep_cfg492_s {
1332 uint32_t reserved_26_31:6;
1333 uint32_t header_depth:10;
1334 uint32_t reserved_14_15:2;
1335 uint32_t data_depth:14;
1336 } s;
1337 struct cvmx_pcieep_cfg492_s cn52xx;
1338 struct cvmx_pcieep_cfg492_s cn52xxp1;
1339 struct cvmx_pcieep_cfg492_s cn56xx;
1340 struct cvmx_pcieep_cfg492_s cn56xxp1;
1341};
1342
1343union cvmx_pcieep_cfg516 {
1344 uint32_t u32;
1345 struct cvmx_pcieep_cfg516_s {
1346 uint32_t phy_stat:32;
1347 } s;
1348 struct cvmx_pcieep_cfg516_s cn52xx;
1349 struct cvmx_pcieep_cfg516_s cn52xxp1;
1350 struct cvmx_pcieep_cfg516_s cn56xx;
1351 struct cvmx_pcieep_cfg516_s cn56xxp1;
1352};
1353
1354union cvmx_pcieep_cfg517 {
1355 uint32_t u32;
1356 struct cvmx_pcieep_cfg517_s {
1357 uint32_t phy_ctrl:32;
1358 } s;
1359 struct cvmx_pcieep_cfg517_s cn52xx;
1360 struct cvmx_pcieep_cfg517_s cn52xxp1;
1361 struct cvmx_pcieep_cfg517_s cn56xx;
1362 struct cvmx_pcieep_cfg517_s cn56xxp1;
1363};
1364
1365#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-pciercx-defs.h b/arch/mips/include/asm/octeon/cvmx-pciercx-defs.h
new file mode 100644
index 000000000000..75574c918942
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-pciercx-defs.h
@@ -0,0 +1,1397 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_PCIERCX_DEFS_H__
29#define __CVMX_PCIERCX_DEFS_H__
30
31#define CVMX_PCIERCX_CFG000(offset) \
32 (0x0000000000000000ull + (((offset) & 1) * 0))
33#define CVMX_PCIERCX_CFG001(offset) \
34 (0x0000000000000004ull + (((offset) & 1) * 0))
35#define CVMX_PCIERCX_CFG002(offset) \
36 (0x0000000000000008ull + (((offset) & 1) * 0))
37#define CVMX_PCIERCX_CFG003(offset) \
38 (0x000000000000000Cull + (((offset) & 1) * 0))
39#define CVMX_PCIERCX_CFG004(offset) \
40 (0x0000000000000010ull + (((offset) & 1) * 0))
41#define CVMX_PCIERCX_CFG005(offset) \
42 (0x0000000000000014ull + (((offset) & 1) * 0))
43#define CVMX_PCIERCX_CFG006(offset) \
44 (0x0000000000000018ull + (((offset) & 1) * 0))
45#define CVMX_PCIERCX_CFG007(offset) \
46 (0x000000000000001Cull + (((offset) & 1) * 0))
47#define CVMX_PCIERCX_CFG008(offset) \
48 (0x0000000000000020ull + (((offset) & 1) * 0))
49#define CVMX_PCIERCX_CFG009(offset) \
50 (0x0000000000000024ull + (((offset) & 1) * 0))
51#define CVMX_PCIERCX_CFG010(offset) \
52 (0x0000000000000028ull + (((offset) & 1) * 0))
53#define CVMX_PCIERCX_CFG011(offset) \
54 (0x000000000000002Cull + (((offset) & 1) * 0))
55#define CVMX_PCIERCX_CFG012(offset) \
56 (0x0000000000000030ull + (((offset) & 1) * 0))
57#define CVMX_PCIERCX_CFG013(offset) \
58 (0x0000000000000034ull + (((offset) & 1) * 0))
59#define CVMX_PCIERCX_CFG014(offset) \
60 (0x0000000000000038ull + (((offset) & 1) * 0))
61#define CVMX_PCIERCX_CFG015(offset) \
62 (0x000000000000003Cull + (((offset) & 1) * 0))
63#define CVMX_PCIERCX_CFG016(offset) \
64 (0x0000000000000040ull + (((offset) & 1) * 0))
65#define CVMX_PCIERCX_CFG017(offset) \
66 (0x0000000000000044ull + (((offset) & 1) * 0))
67#define CVMX_PCIERCX_CFG020(offset) \
68 (0x0000000000000050ull + (((offset) & 1) * 0))
69#define CVMX_PCIERCX_CFG021(offset) \
70 (0x0000000000000054ull + (((offset) & 1) * 0))
71#define CVMX_PCIERCX_CFG022(offset) \
72 (0x0000000000000058ull + (((offset) & 1) * 0))
73#define CVMX_PCIERCX_CFG023(offset) \
74 (0x000000000000005Cull + (((offset) & 1) * 0))
75#define CVMX_PCIERCX_CFG028(offset) \
76 (0x0000000000000070ull + (((offset) & 1) * 0))
77#define CVMX_PCIERCX_CFG029(offset) \
78 (0x0000000000000074ull + (((offset) & 1) * 0))
79#define CVMX_PCIERCX_CFG030(offset) \
80 (0x0000000000000078ull + (((offset) & 1) * 0))
81#define CVMX_PCIERCX_CFG031(offset) \
82 (0x000000000000007Cull + (((offset) & 1) * 0))
83#define CVMX_PCIERCX_CFG032(offset) \
84 (0x0000000000000080ull + (((offset) & 1) * 0))
85#define CVMX_PCIERCX_CFG033(offset) \
86 (0x0000000000000084ull + (((offset) & 1) * 0))
87#define CVMX_PCIERCX_CFG034(offset) \
88 (0x0000000000000088ull + (((offset) & 1) * 0))
89#define CVMX_PCIERCX_CFG035(offset) \
90 (0x000000000000008Cull + (((offset) & 1) * 0))
91#define CVMX_PCIERCX_CFG036(offset) \
92 (0x0000000000000090ull + (((offset) & 1) * 0))
93#define CVMX_PCIERCX_CFG037(offset) \
94 (0x0000000000000094ull + (((offset) & 1) * 0))
95#define CVMX_PCIERCX_CFG038(offset) \
96 (0x0000000000000098ull + (((offset) & 1) * 0))
97#define CVMX_PCIERCX_CFG039(offset) \
98 (0x000000000000009Cull + (((offset) & 1) * 0))
99#define CVMX_PCIERCX_CFG040(offset) \
100 (0x00000000000000A0ull + (((offset) & 1) * 0))
101#define CVMX_PCIERCX_CFG041(offset) \
102 (0x00000000000000A4ull + (((offset) & 1) * 0))
103#define CVMX_PCIERCX_CFG042(offset) \
104 (0x00000000000000A8ull + (((offset) & 1) * 0))
105#define CVMX_PCIERCX_CFG064(offset) \
106 (0x0000000000000100ull + (((offset) & 1) * 0))
107#define CVMX_PCIERCX_CFG065(offset) \
108 (0x0000000000000104ull + (((offset) & 1) * 0))
109#define CVMX_PCIERCX_CFG066(offset) \
110 (0x0000000000000108ull + (((offset) & 1) * 0))
111#define CVMX_PCIERCX_CFG067(offset) \
112 (0x000000000000010Cull + (((offset) & 1) * 0))
113#define CVMX_PCIERCX_CFG068(offset) \
114 (0x0000000000000110ull + (((offset) & 1) * 0))
115#define CVMX_PCIERCX_CFG069(offset) \
116 (0x0000000000000114ull + (((offset) & 1) * 0))
117#define CVMX_PCIERCX_CFG070(offset) \
118 (0x0000000000000118ull + (((offset) & 1) * 0))
119#define CVMX_PCIERCX_CFG071(offset) \
120 (0x000000000000011Cull + (((offset) & 1) * 0))
121#define CVMX_PCIERCX_CFG072(offset) \
122 (0x0000000000000120ull + (((offset) & 1) * 0))
123#define CVMX_PCIERCX_CFG073(offset) \
124 (0x0000000000000124ull + (((offset) & 1) * 0))
125#define CVMX_PCIERCX_CFG074(offset) \
126 (0x0000000000000128ull + (((offset) & 1) * 0))
127#define CVMX_PCIERCX_CFG075(offset) \
128 (0x000000000000012Cull + (((offset) & 1) * 0))
129#define CVMX_PCIERCX_CFG076(offset) \
130 (0x0000000000000130ull + (((offset) & 1) * 0))
131#define CVMX_PCIERCX_CFG077(offset) \
132 (0x0000000000000134ull + (((offset) & 1) * 0))
133#define CVMX_PCIERCX_CFG448(offset) \
134 (0x0000000000000700ull + (((offset) & 1) * 0))
135#define CVMX_PCIERCX_CFG449(offset) \
136 (0x0000000000000704ull + (((offset) & 1) * 0))
137#define CVMX_PCIERCX_CFG450(offset) \
138 (0x0000000000000708ull + (((offset) & 1) * 0))
139#define CVMX_PCIERCX_CFG451(offset) \
140 (0x000000000000070Cull + (((offset) & 1) * 0))
141#define CVMX_PCIERCX_CFG452(offset) \
142 (0x0000000000000710ull + (((offset) & 1) * 0))
143#define CVMX_PCIERCX_CFG453(offset) \
144 (0x0000000000000714ull + (((offset) & 1) * 0))
145#define CVMX_PCIERCX_CFG454(offset) \
146 (0x0000000000000718ull + (((offset) & 1) * 0))
147#define CVMX_PCIERCX_CFG455(offset) \
148 (0x000000000000071Cull + (((offset) & 1) * 0))
149#define CVMX_PCIERCX_CFG456(offset) \
150 (0x0000000000000720ull + (((offset) & 1) * 0))
151#define CVMX_PCIERCX_CFG458(offset) \
152 (0x0000000000000728ull + (((offset) & 1) * 0))
153#define CVMX_PCIERCX_CFG459(offset) \
154 (0x000000000000072Cull + (((offset) & 1) * 0))
155#define CVMX_PCIERCX_CFG460(offset) \
156 (0x0000000000000730ull + (((offset) & 1) * 0))
157#define CVMX_PCIERCX_CFG461(offset) \
158 (0x0000000000000734ull + (((offset) & 1) * 0))
159#define CVMX_PCIERCX_CFG462(offset) \
160 (0x0000000000000738ull + (((offset) & 1) * 0))
161#define CVMX_PCIERCX_CFG463(offset) \
162 (0x000000000000073Cull + (((offset) & 1) * 0))
163#define CVMX_PCIERCX_CFG464(offset) \
164 (0x0000000000000740ull + (((offset) & 1) * 0))
165#define CVMX_PCIERCX_CFG465(offset) \
166 (0x0000000000000744ull + (((offset) & 1) * 0))
167#define CVMX_PCIERCX_CFG466(offset) \
168 (0x0000000000000748ull + (((offset) & 1) * 0))
169#define CVMX_PCIERCX_CFG467(offset) \
170 (0x000000000000074Cull + (((offset) & 1) * 0))
171#define CVMX_PCIERCX_CFG468(offset) \
172 (0x0000000000000750ull + (((offset) & 1) * 0))
173#define CVMX_PCIERCX_CFG490(offset) \
174 (0x00000000000007A8ull + (((offset) & 1) * 0))
175#define CVMX_PCIERCX_CFG491(offset) \
176 (0x00000000000007ACull + (((offset) & 1) * 0))
177#define CVMX_PCIERCX_CFG492(offset) \
178 (0x00000000000007B0ull + (((offset) & 1) * 0))
179#define CVMX_PCIERCX_CFG516(offset) \
180 (0x0000000000000810ull + (((offset) & 1) * 0))
181#define CVMX_PCIERCX_CFG517(offset) \
182 (0x0000000000000814ull + (((offset) & 1) * 0))
183
184union cvmx_pciercx_cfg000 {
185 uint32_t u32;
186 struct cvmx_pciercx_cfg000_s {
187 uint32_t devid:16;
188 uint32_t vendid:16;
189 } s;
190 struct cvmx_pciercx_cfg000_s cn52xx;
191 struct cvmx_pciercx_cfg000_s cn52xxp1;
192 struct cvmx_pciercx_cfg000_s cn56xx;
193 struct cvmx_pciercx_cfg000_s cn56xxp1;
194};
195
196union cvmx_pciercx_cfg001 {
197 uint32_t u32;
198 struct cvmx_pciercx_cfg001_s {
199 uint32_t dpe:1;
200 uint32_t sse:1;
201 uint32_t rma:1;
202 uint32_t rta:1;
203 uint32_t sta:1;
204 uint32_t devt:2;
205 uint32_t mdpe:1;
206 uint32_t fbb:1;
207 uint32_t reserved_22_22:1;
208 uint32_t m66:1;
209 uint32_t cl:1;
210 uint32_t i_stat:1;
211 uint32_t reserved_11_18:8;
212 uint32_t i_dis:1;
213 uint32_t fbbe:1;
214 uint32_t see:1;
215 uint32_t ids_wcc:1;
216 uint32_t per:1;
217 uint32_t vps:1;
218 uint32_t mwice:1;
219 uint32_t scse:1;
220 uint32_t me:1;
221 uint32_t msae:1;
222 uint32_t isae:1;
223 } s;
224 struct cvmx_pciercx_cfg001_s cn52xx;
225 struct cvmx_pciercx_cfg001_s cn52xxp1;
226 struct cvmx_pciercx_cfg001_s cn56xx;
227 struct cvmx_pciercx_cfg001_s cn56xxp1;
228};
229
230union cvmx_pciercx_cfg002 {
231 uint32_t u32;
232 struct cvmx_pciercx_cfg002_s {
233 uint32_t bcc:8;
234 uint32_t sc:8;
235 uint32_t pi:8;
236 uint32_t rid:8;
237 } s;
238 struct cvmx_pciercx_cfg002_s cn52xx;
239 struct cvmx_pciercx_cfg002_s cn52xxp1;
240 struct cvmx_pciercx_cfg002_s cn56xx;
241 struct cvmx_pciercx_cfg002_s cn56xxp1;
242};
243
244union cvmx_pciercx_cfg003 {
245 uint32_t u32;
246 struct cvmx_pciercx_cfg003_s {
247 uint32_t bist:8;
248 uint32_t mfd:1;
249 uint32_t chf:7;
250 uint32_t lt:8;
251 uint32_t cls:8;
252 } s;
253 struct cvmx_pciercx_cfg003_s cn52xx;
254 struct cvmx_pciercx_cfg003_s cn52xxp1;
255 struct cvmx_pciercx_cfg003_s cn56xx;
256 struct cvmx_pciercx_cfg003_s cn56xxp1;
257};
258
259union cvmx_pciercx_cfg004 {
260 uint32_t u32;
261 struct cvmx_pciercx_cfg004_s {
262 uint32_t reserved_0_31:32;
263 } s;
264 struct cvmx_pciercx_cfg004_s cn52xx;
265 struct cvmx_pciercx_cfg004_s cn52xxp1;
266 struct cvmx_pciercx_cfg004_s cn56xx;
267 struct cvmx_pciercx_cfg004_s cn56xxp1;
268};
269
270union cvmx_pciercx_cfg005 {
271 uint32_t u32;
272 struct cvmx_pciercx_cfg005_s {
273 uint32_t reserved_0_31:32;
274 } s;
275 struct cvmx_pciercx_cfg005_s cn52xx;
276 struct cvmx_pciercx_cfg005_s cn52xxp1;
277 struct cvmx_pciercx_cfg005_s cn56xx;
278 struct cvmx_pciercx_cfg005_s cn56xxp1;
279};
280
281union cvmx_pciercx_cfg006 {
282 uint32_t u32;
283 struct cvmx_pciercx_cfg006_s {
284 uint32_t slt:8;
285 uint32_t subbnum:8;
286 uint32_t sbnum:8;
287 uint32_t pbnum:8;
288 } s;
289 struct cvmx_pciercx_cfg006_s cn52xx;
290 struct cvmx_pciercx_cfg006_s cn52xxp1;
291 struct cvmx_pciercx_cfg006_s cn56xx;
292 struct cvmx_pciercx_cfg006_s cn56xxp1;
293};
294
295union cvmx_pciercx_cfg007 {
296 uint32_t u32;
297 struct cvmx_pciercx_cfg007_s {
298 uint32_t dpe:1;
299 uint32_t sse:1;
300 uint32_t rma:1;
301 uint32_t rta:1;
302 uint32_t sta:1;
303 uint32_t devt:2;
304 uint32_t mdpe:1;
305 uint32_t fbb:1;
306 uint32_t reserved_22_22:1;
307 uint32_t m66:1;
308 uint32_t reserved_16_20:5;
309 uint32_t lio_limi:4;
310 uint32_t reserved_9_11:3;
311 uint32_t io32b:1;
312 uint32_t lio_base:4;
313 uint32_t reserved_1_3:3;
314 uint32_t io32a:1;
315 } s;
316 struct cvmx_pciercx_cfg007_s cn52xx;
317 struct cvmx_pciercx_cfg007_s cn52xxp1;
318 struct cvmx_pciercx_cfg007_s cn56xx;
319 struct cvmx_pciercx_cfg007_s cn56xxp1;
320};
321
322union cvmx_pciercx_cfg008 {
323 uint32_t u32;
324 struct cvmx_pciercx_cfg008_s {
325 uint32_t ml_addr:12;
326 uint32_t reserved_16_19:4;
327 uint32_t mb_addr:12;
328 uint32_t reserved_0_3:4;
329 } s;
330 struct cvmx_pciercx_cfg008_s cn52xx;
331 struct cvmx_pciercx_cfg008_s cn52xxp1;
332 struct cvmx_pciercx_cfg008_s cn56xx;
333 struct cvmx_pciercx_cfg008_s cn56xxp1;
334};
335
336union cvmx_pciercx_cfg009 {
337 uint32_t u32;
338 struct cvmx_pciercx_cfg009_s {
339 uint32_t lmem_limit:12;
340 uint32_t reserved_17_19:3;
341 uint32_t mem64b:1;
342 uint32_t lmem_base:12;
343 uint32_t reserved_1_3:3;
344 uint32_t mem64a:1;
345 } s;
346 struct cvmx_pciercx_cfg009_s cn52xx;
347 struct cvmx_pciercx_cfg009_s cn52xxp1;
348 struct cvmx_pciercx_cfg009_s cn56xx;
349 struct cvmx_pciercx_cfg009_s cn56xxp1;
350};
351
352union cvmx_pciercx_cfg010 {
353 uint32_t u32;
354 struct cvmx_pciercx_cfg010_s {
355 uint32_t umem_base:32;
356 } s;
357 struct cvmx_pciercx_cfg010_s cn52xx;
358 struct cvmx_pciercx_cfg010_s cn52xxp1;
359 struct cvmx_pciercx_cfg010_s cn56xx;
360 struct cvmx_pciercx_cfg010_s cn56xxp1;
361};
362
363union cvmx_pciercx_cfg011 {
364 uint32_t u32;
365 struct cvmx_pciercx_cfg011_s {
366 uint32_t umem_limit:32;
367 } s;
368 struct cvmx_pciercx_cfg011_s cn52xx;
369 struct cvmx_pciercx_cfg011_s cn52xxp1;
370 struct cvmx_pciercx_cfg011_s cn56xx;
371 struct cvmx_pciercx_cfg011_s cn56xxp1;
372};
373
374union cvmx_pciercx_cfg012 {
375 uint32_t u32;
376 struct cvmx_pciercx_cfg012_s {
377 uint32_t uio_limit:16;
378 uint32_t uio_base:16;
379 } s;
380 struct cvmx_pciercx_cfg012_s cn52xx;
381 struct cvmx_pciercx_cfg012_s cn52xxp1;
382 struct cvmx_pciercx_cfg012_s cn56xx;
383 struct cvmx_pciercx_cfg012_s cn56xxp1;
384};
385
386union cvmx_pciercx_cfg013 {
387 uint32_t u32;
388 struct cvmx_pciercx_cfg013_s {
389 uint32_t reserved_8_31:24;
390 uint32_t cp:8;
391 } s;
392 struct cvmx_pciercx_cfg013_s cn52xx;
393 struct cvmx_pciercx_cfg013_s cn52xxp1;
394 struct cvmx_pciercx_cfg013_s cn56xx;
395 struct cvmx_pciercx_cfg013_s cn56xxp1;
396};
397
398union cvmx_pciercx_cfg014 {
399 uint32_t u32;
400 struct cvmx_pciercx_cfg014_s {
401 uint32_t reserved_0_31:32;
402 } s;
403 struct cvmx_pciercx_cfg014_s cn52xx;
404 struct cvmx_pciercx_cfg014_s cn52xxp1;
405 struct cvmx_pciercx_cfg014_s cn56xx;
406 struct cvmx_pciercx_cfg014_s cn56xxp1;
407};
408
409union cvmx_pciercx_cfg015 {
410 uint32_t u32;
411 struct cvmx_pciercx_cfg015_s {
412 uint32_t reserved_28_31:4;
413 uint32_t dtsees:1;
414 uint32_t dts:1;
415 uint32_t sdt:1;
416 uint32_t pdt:1;
417 uint32_t fbbe:1;
418 uint32_t sbrst:1;
419 uint32_t mam:1;
420 uint32_t vga16d:1;
421 uint32_t vgae:1;
422 uint32_t isae:1;
423 uint32_t see:1;
424 uint32_t pere:1;
425 uint32_t inta:8;
426 uint32_t il:8;
427 } s;
428 struct cvmx_pciercx_cfg015_s cn52xx;
429 struct cvmx_pciercx_cfg015_s cn52xxp1;
430 struct cvmx_pciercx_cfg015_s cn56xx;
431 struct cvmx_pciercx_cfg015_s cn56xxp1;
432};
433
434union cvmx_pciercx_cfg016 {
435 uint32_t u32;
436 struct cvmx_pciercx_cfg016_s {
437 uint32_t pmes:5;
438 uint32_t d2s:1;
439 uint32_t d1s:1;
440 uint32_t auxc:3;
441 uint32_t dsi:1;
442 uint32_t reserved_20_20:1;
443 uint32_t pme_clock:1;
444 uint32_t pmsv:3;
445 uint32_t ncp:8;
446 uint32_t pmcid:8;
447 } s;
448 struct cvmx_pciercx_cfg016_s cn52xx;
449 struct cvmx_pciercx_cfg016_s cn52xxp1;
450 struct cvmx_pciercx_cfg016_s cn56xx;
451 struct cvmx_pciercx_cfg016_s cn56xxp1;
452};
453
454union cvmx_pciercx_cfg017 {
455 uint32_t u32;
456 struct cvmx_pciercx_cfg017_s {
457 uint32_t pmdia:8;
458 uint32_t bpccee:1;
459 uint32_t bd3h:1;
460 uint32_t reserved_16_21:6;
461 uint32_t pmess:1;
462 uint32_t pmedsia:2;
463 uint32_t pmds:4;
464 uint32_t pmeens:1;
465 uint32_t reserved_4_7:4;
466 uint32_t nsr:1;
467 uint32_t reserved_2_2:1;
468 uint32_t ps:2;
469 } s;
470 struct cvmx_pciercx_cfg017_s cn52xx;
471 struct cvmx_pciercx_cfg017_s cn52xxp1;
472 struct cvmx_pciercx_cfg017_s cn56xx;
473 struct cvmx_pciercx_cfg017_s cn56xxp1;
474};
475
476union cvmx_pciercx_cfg020 {
477 uint32_t u32;
478 struct cvmx_pciercx_cfg020_s {
479 uint32_t reserved_24_31:8;
480 uint32_t m64:1;
481 uint32_t mme:3;
482 uint32_t mmc:3;
483 uint32_t msien:1;
484 uint32_t ncp:8;
485 uint32_t msicid:8;
486 } s;
487 struct cvmx_pciercx_cfg020_s cn52xx;
488 struct cvmx_pciercx_cfg020_s cn52xxp1;
489 struct cvmx_pciercx_cfg020_s cn56xx;
490 struct cvmx_pciercx_cfg020_s cn56xxp1;
491};
492
493union cvmx_pciercx_cfg021 {
494 uint32_t u32;
495 struct cvmx_pciercx_cfg021_s {
496 uint32_t lmsi:30;
497 uint32_t reserved_0_1:2;
498 } s;
499 struct cvmx_pciercx_cfg021_s cn52xx;
500 struct cvmx_pciercx_cfg021_s cn52xxp1;
501 struct cvmx_pciercx_cfg021_s cn56xx;
502 struct cvmx_pciercx_cfg021_s cn56xxp1;
503};
504
505union cvmx_pciercx_cfg022 {
506 uint32_t u32;
507 struct cvmx_pciercx_cfg022_s {
508 uint32_t umsi:32;
509 } s;
510 struct cvmx_pciercx_cfg022_s cn52xx;
511 struct cvmx_pciercx_cfg022_s cn52xxp1;
512 struct cvmx_pciercx_cfg022_s cn56xx;
513 struct cvmx_pciercx_cfg022_s cn56xxp1;
514};
515
516union cvmx_pciercx_cfg023 {
517 uint32_t u32;
518 struct cvmx_pciercx_cfg023_s {
519 uint32_t reserved_16_31:16;
520 uint32_t msimd:16;
521 } s;
522 struct cvmx_pciercx_cfg023_s cn52xx;
523 struct cvmx_pciercx_cfg023_s cn52xxp1;
524 struct cvmx_pciercx_cfg023_s cn56xx;
525 struct cvmx_pciercx_cfg023_s cn56xxp1;
526};
527
528union cvmx_pciercx_cfg028 {
529 uint32_t u32;
530 struct cvmx_pciercx_cfg028_s {
531 uint32_t reserved_30_31:2;
532 uint32_t imn:5;
533 uint32_t si:1;
534 uint32_t dpt:4;
535 uint32_t pciecv:4;
536 uint32_t ncp:8;
537 uint32_t pcieid:8;
538 } s;
539 struct cvmx_pciercx_cfg028_s cn52xx;
540 struct cvmx_pciercx_cfg028_s cn52xxp1;
541 struct cvmx_pciercx_cfg028_s cn56xx;
542 struct cvmx_pciercx_cfg028_s cn56xxp1;
543};
544
545union cvmx_pciercx_cfg029 {
546 uint32_t u32;
547 struct cvmx_pciercx_cfg029_s {
548 uint32_t reserved_28_31:4;
549 uint32_t cspls:2;
550 uint32_t csplv:8;
551 uint32_t reserved_16_17:2;
552 uint32_t rber:1;
553 uint32_t reserved_12_14:3;
554 uint32_t el1al:3;
555 uint32_t el0al:3;
556 uint32_t etfs:1;
557 uint32_t pfs:2;
558 uint32_t mpss:3;
559 } s;
560 struct cvmx_pciercx_cfg029_s cn52xx;
561 struct cvmx_pciercx_cfg029_s cn52xxp1;
562 struct cvmx_pciercx_cfg029_s cn56xx;
563 struct cvmx_pciercx_cfg029_s cn56xxp1;
564};
565
566union cvmx_pciercx_cfg030 {
567 uint32_t u32;
568 struct cvmx_pciercx_cfg030_s {
569 uint32_t reserved_22_31:10;
570 uint32_t tp:1;
571 uint32_t ap_d:1;
572 uint32_t ur_d:1;
573 uint32_t fe_d:1;
574 uint32_t nfe_d:1;
575 uint32_t ce_d:1;
576 uint32_t reserved_15_15:1;
577 uint32_t mrrs:3;
578 uint32_t ns_en:1;
579 uint32_t ap_en:1;
580 uint32_t pf_en:1;
581 uint32_t etf_en:1;
582 uint32_t mps:3;
583 uint32_t ro_en:1;
584 uint32_t ur_en:1;
585 uint32_t fe_en:1;
586 uint32_t nfe_en:1;
587 uint32_t ce_en:1;
588 } s;
589 struct cvmx_pciercx_cfg030_s cn52xx;
590 struct cvmx_pciercx_cfg030_s cn52xxp1;
591 struct cvmx_pciercx_cfg030_s cn56xx;
592 struct cvmx_pciercx_cfg030_s cn56xxp1;
593};
594
595union cvmx_pciercx_cfg031 {
596 uint32_t u32;
597 struct cvmx_pciercx_cfg031_s {
598 uint32_t pnum:8;
599 uint32_t reserved_22_23:2;
600 uint32_t lbnc:1;
601 uint32_t dllarc:1;
602 uint32_t sderc:1;
603 uint32_t cpm:1;
604 uint32_t l1el:3;
605 uint32_t l0el:3;
606 uint32_t aslpms:2;
607 uint32_t mlw:6;
608 uint32_t mls:4;
609 } s;
610 struct cvmx_pciercx_cfg031_s cn52xx;
611 struct cvmx_pciercx_cfg031_s cn52xxp1;
612 struct cvmx_pciercx_cfg031_s cn56xx;
613 struct cvmx_pciercx_cfg031_s cn56xxp1;
614};
615
616union cvmx_pciercx_cfg032 {
617 uint32_t u32;
618 struct cvmx_pciercx_cfg032_s {
619 uint32_t lab:1;
620 uint32_t lbm:1;
621 uint32_t dlla:1;
622 uint32_t scc:1;
623 uint32_t lt:1;
624 uint32_t reserved_26_26:1;
625 uint32_t nlw:6;
626 uint32_t ls:4;
627 uint32_t reserved_12_15:4;
628 uint32_t lab_int_enb:1;
629 uint32_t lbm_int_enb:1;
630 uint32_t hawd:1;
631 uint32_t ecpm:1;
632 uint32_t es:1;
633 uint32_t ccc:1;
634 uint32_t rl:1;
635 uint32_t ld:1;
636 uint32_t rcb:1;
637 uint32_t reserved_2_2:1;
638 uint32_t aslpc:2;
639 } s;
640 struct cvmx_pciercx_cfg032_s cn52xx;
641 struct cvmx_pciercx_cfg032_s cn52xxp1;
642 struct cvmx_pciercx_cfg032_s cn56xx;
643 struct cvmx_pciercx_cfg032_s cn56xxp1;
644};
645
646union cvmx_pciercx_cfg033 {
647 uint32_t u32;
648 struct cvmx_pciercx_cfg033_s {
649 uint32_t ps_num:13;
650 uint32_t nccs:1;
651 uint32_t emip:1;
652 uint32_t sp_ls:2;
653 uint32_t sp_lv:8;
654 uint32_t hp_c:1;
655 uint32_t hp_s:1;
656 uint32_t pip:1;
657 uint32_t aip:1;
658 uint32_t mrlsp:1;
659 uint32_t pcp:1;
660 uint32_t abp:1;
661 } s;
662 struct cvmx_pciercx_cfg033_s cn52xx;
663 struct cvmx_pciercx_cfg033_s cn52xxp1;
664 struct cvmx_pciercx_cfg033_s cn56xx;
665 struct cvmx_pciercx_cfg033_s cn56xxp1;
666};
667
668union cvmx_pciercx_cfg034 {
669 uint32_t u32;
670 struct cvmx_pciercx_cfg034_s {
671 uint32_t reserved_25_31:7;
672 uint32_t dlls_c:1;
673 uint32_t emis:1;
674 uint32_t pds:1;
675 uint32_t mrlss:1;
676 uint32_t ccint_d:1;
677 uint32_t pd_c:1;
678 uint32_t mrls_c:1;
679 uint32_t pf_d:1;
680 uint32_t abp_d:1;
681 uint32_t reserved_13_15:3;
682 uint32_t dlls_en:1;
683 uint32_t emic:1;
684 uint32_t pcc:1;
685 uint32_t pic:2;
686 uint32_t aic:2;
687 uint32_t hpint_en:1;
688 uint32_t ccint_en:1;
689 uint32_t pd_en:1;
690 uint32_t mrls_en:1;
691 uint32_t pf_en:1;
692 uint32_t abp_en:1;
693 } s;
694 struct cvmx_pciercx_cfg034_s cn52xx;
695 struct cvmx_pciercx_cfg034_s cn52xxp1;
696 struct cvmx_pciercx_cfg034_s cn56xx;
697 struct cvmx_pciercx_cfg034_s cn56xxp1;
698};
699
700union cvmx_pciercx_cfg035 {
701 uint32_t u32;
702 struct cvmx_pciercx_cfg035_s {
703 uint32_t reserved_17_31:15;
704 uint32_t crssv:1;
705 uint32_t reserved_5_15:11;
706 uint32_t crssve:1;
707 uint32_t pmeie:1;
708 uint32_t sefee:1;
709 uint32_t senfee:1;
710 uint32_t secee:1;
711 } s;
712 struct cvmx_pciercx_cfg035_s cn52xx;
713 struct cvmx_pciercx_cfg035_s cn52xxp1;
714 struct cvmx_pciercx_cfg035_s cn56xx;
715 struct cvmx_pciercx_cfg035_s cn56xxp1;
716};
717
718union cvmx_pciercx_cfg036 {
719 uint32_t u32;
720 struct cvmx_pciercx_cfg036_s {
721 uint32_t reserved_18_31:14;
722 uint32_t pme_pend:1;
723 uint32_t pme_stat:1;
724 uint32_t pme_rid:16;
725 } s;
726 struct cvmx_pciercx_cfg036_s cn52xx;
727 struct cvmx_pciercx_cfg036_s cn52xxp1;
728 struct cvmx_pciercx_cfg036_s cn56xx;
729 struct cvmx_pciercx_cfg036_s cn56xxp1;
730};
731
732union cvmx_pciercx_cfg037 {
733 uint32_t u32;
734 struct cvmx_pciercx_cfg037_s {
735 uint32_t reserved_5_31:27;
736 uint32_t ctds:1;
737 uint32_t ctrs:4;
738 } s;
739 struct cvmx_pciercx_cfg037_s cn52xx;
740 struct cvmx_pciercx_cfg037_s cn52xxp1;
741 struct cvmx_pciercx_cfg037_s cn56xx;
742 struct cvmx_pciercx_cfg037_s cn56xxp1;
743};
744
745union cvmx_pciercx_cfg038 {
746 uint32_t u32;
747 struct cvmx_pciercx_cfg038_s {
748 uint32_t reserved_5_31:27;
749 uint32_t ctd:1;
750 uint32_t ctv:4;
751 } s;
752 struct cvmx_pciercx_cfg038_s cn52xx;
753 struct cvmx_pciercx_cfg038_s cn52xxp1;
754 struct cvmx_pciercx_cfg038_s cn56xx;
755 struct cvmx_pciercx_cfg038_s cn56xxp1;
756};
757
758union cvmx_pciercx_cfg039 {
759 uint32_t u32;
760 struct cvmx_pciercx_cfg039_s {
761 uint32_t reserved_0_31:32;
762 } s;
763 struct cvmx_pciercx_cfg039_s cn52xx;
764 struct cvmx_pciercx_cfg039_s cn52xxp1;
765 struct cvmx_pciercx_cfg039_s cn56xx;
766 struct cvmx_pciercx_cfg039_s cn56xxp1;
767};
768
769union cvmx_pciercx_cfg040 {
770 uint32_t u32;
771 struct cvmx_pciercx_cfg040_s {
772 uint32_t reserved_0_31:32;
773 } s;
774 struct cvmx_pciercx_cfg040_s cn52xx;
775 struct cvmx_pciercx_cfg040_s cn52xxp1;
776 struct cvmx_pciercx_cfg040_s cn56xx;
777 struct cvmx_pciercx_cfg040_s cn56xxp1;
778};
779
780union cvmx_pciercx_cfg041 {
781 uint32_t u32;
782 struct cvmx_pciercx_cfg041_s {
783 uint32_t reserved_0_31:32;
784 } s;
785 struct cvmx_pciercx_cfg041_s cn52xx;
786 struct cvmx_pciercx_cfg041_s cn52xxp1;
787 struct cvmx_pciercx_cfg041_s cn56xx;
788 struct cvmx_pciercx_cfg041_s cn56xxp1;
789};
790
791union cvmx_pciercx_cfg042 {
792 uint32_t u32;
793 struct cvmx_pciercx_cfg042_s {
794 uint32_t reserved_0_31:32;
795 } s;
796 struct cvmx_pciercx_cfg042_s cn52xx;
797 struct cvmx_pciercx_cfg042_s cn52xxp1;
798 struct cvmx_pciercx_cfg042_s cn56xx;
799 struct cvmx_pciercx_cfg042_s cn56xxp1;
800};
801
802union cvmx_pciercx_cfg064 {
803 uint32_t u32;
804 struct cvmx_pciercx_cfg064_s {
805 uint32_t nco:12;
806 uint32_t cv:4;
807 uint32_t pcieec:16;
808 } s;
809 struct cvmx_pciercx_cfg064_s cn52xx;
810 struct cvmx_pciercx_cfg064_s cn52xxp1;
811 struct cvmx_pciercx_cfg064_s cn56xx;
812 struct cvmx_pciercx_cfg064_s cn56xxp1;
813};
814
815union cvmx_pciercx_cfg065 {
816 uint32_t u32;
817 struct cvmx_pciercx_cfg065_s {
818 uint32_t reserved_21_31:11;
819 uint32_t ures:1;
820 uint32_t ecrces:1;
821 uint32_t mtlps:1;
822 uint32_t ros:1;
823 uint32_t ucs:1;
824 uint32_t cas:1;
825 uint32_t cts:1;
826 uint32_t fcpes:1;
827 uint32_t ptlps:1;
828 uint32_t reserved_6_11:6;
829 uint32_t sdes:1;
830 uint32_t dlpes:1;
831 uint32_t reserved_0_3:4;
832 } s;
833 struct cvmx_pciercx_cfg065_s cn52xx;
834 struct cvmx_pciercx_cfg065_s cn52xxp1;
835 struct cvmx_pciercx_cfg065_s cn56xx;
836 struct cvmx_pciercx_cfg065_s cn56xxp1;
837};
838
839union cvmx_pciercx_cfg066 {
840 uint32_t u32;
841 struct cvmx_pciercx_cfg066_s {
842 uint32_t reserved_21_31:11;
843 uint32_t urem:1;
844 uint32_t ecrcem:1;
845 uint32_t mtlpm:1;
846 uint32_t rom:1;
847 uint32_t ucm:1;
848 uint32_t cam:1;
849 uint32_t ctm:1;
850 uint32_t fcpem:1;
851 uint32_t ptlpm:1;
852 uint32_t reserved_6_11:6;
853 uint32_t sdem:1;
854 uint32_t dlpem:1;
855 uint32_t reserved_0_3:4;
856 } s;
857 struct cvmx_pciercx_cfg066_s cn52xx;
858 struct cvmx_pciercx_cfg066_s cn52xxp1;
859 struct cvmx_pciercx_cfg066_s cn56xx;
860 struct cvmx_pciercx_cfg066_s cn56xxp1;
861};
862
863union cvmx_pciercx_cfg067 {
864 uint32_t u32;
865 struct cvmx_pciercx_cfg067_s {
866 uint32_t reserved_21_31:11;
867 uint32_t ures:1;
868 uint32_t ecrces:1;
869 uint32_t mtlps:1;
870 uint32_t ros:1;
871 uint32_t ucs:1;
872 uint32_t cas:1;
873 uint32_t cts:1;
874 uint32_t fcpes:1;
875 uint32_t ptlps:1;
876 uint32_t reserved_6_11:6;
877 uint32_t sdes:1;
878 uint32_t dlpes:1;
879 uint32_t reserved_0_3:4;
880 } s;
881 struct cvmx_pciercx_cfg067_s cn52xx;
882 struct cvmx_pciercx_cfg067_s cn52xxp1;
883 struct cvmx_pciercx_cfg067_s cn56xx;
884 struct cvmx_pciercx_cfg067_s cn56xxp1;
885};
886
887union cvmx_pciercx_cfg068 {
888 uint32_t u32;
889 struct cvmx_pciercx_cfg068_s {
890 uint32_t reserved_14_31:18;
891 uint32_t anfes:1;
892 uint32_t rtts:1;
893 uint32_t reserved_9_11:3;
894 uint32_t rnrs:1;
895 uint32_t bdllps:1;
896 uint32_t btlps:1;
897 uint32_t reserved_1_5:5;
898 uint32_t res:1;
899 } s;
900 struct cvmx_pciercx_cfg068_s cn52xx;
901 struct cvmx_pciercx_cfg068_s cn52xxp1;
902 struct cvmx_pciercx_cfg068_s cn56xx;
903 struct cvmx_pciercx_cfg068_s cn56xxp1;
904};
905
906union cvmx_pciercx_cfg069 {
907 uint32_t u32;
908 struct cvmx_pciercx_cfg069_s {
909 uint32_t reserved_14_31:18;
910 uint32_t anfem:1;
911 uint32_t rttm:1;
912 uint32_t reserved_9_11:3;
913 uint32_t rnrm:1;
914 uint32_t bdllpm:1;
915 uint32_t btlpm:1;
916 uint32_t reserved_1_5:5;
917 uint32_t rem:1;
918 } s;
919 struct cvmx_pciercx_cfg069_s cn52xx;
920 struct cvmx_pciercx_cfg069_s cn52xxp1;
921 struct cvmx_pciercx_cfg069_s cn56xx;
922 struct cvmx_pciercx_cfg069_s cn56xxp1;
923};
924
925union cvmx_pciercx_cfg070 {
926 uint32_t u32;
927 struct cvmx_pciercx_cfg070_s {
928 uint32_t reserved_9_31:23;
929 uint32_t ce:1;
930 uint32_t cc:1;
931 uint32_t ge:1;
932 uint32_t gc:1;
933 uint32_t fep:5;
934 } s;
935 struct cvmx_pciercx_cfg070_s cn52xx;
936 struct cvmx_pciercx_cfg070_s cn52xxp1;
937 struct cvmx_pciercx_cfg070_s cn56xx;
938 struct cvmx_pciercx_cfg070_s cn56xxp1;
939};
940
941union cvmx_pciercx_cfg071 {
942 uint32_t u32;
943 struct cvmx_pciercx_cfg071_s {
944 uint32_t dword1:32;
945 } s;
946 struct cvmx_pciercx_cfg071_s cn52xx;
947 struct cvmx_pciercx_cfg071_s cn52xxp1;
948 struct cvmx_pciercx_cfg071_s cn56xx;
949 struct cvmx_pciercx_cfg071_s cn56xxp1;
950};
951
952union cvmx_pciercx_cfg072 {
953 uint32_t u32;
954 struct cvmx_pciercx_cfg072_s {
955 uint32_t dword2:32;
956 } s;
957 struct cvmx_pciercx_cfg072_s cn52xx;
958 struct cvmx_pciercx_cfg072_s cn52xxp1;
959 struct cvmx_pciercx_cfg072_s cn56xx;
960 struct cvmx_pciercx_cfg072_s cn56xxp1;
961};
962
963union cvmx_pciercx_cfg073 {
964 uint32_t u32;
965 struct cvmx_pciercx_cfg073_s {
966 uint32_t dword3:32;
967 } s;
968 struct cvmx_pciercx_cfg073_s cn52xx;
969 struct cvmx_pciercx_cfg073_s cn52xxp1;
970 struct cvmx_pciercx_cfg073_s cn56xx;
971 struct cvmx_pciercx_cfg073_s cn56xxp1;
972};
973
974union cvmx_pciercx_cfg074 {
975 uint32_t u32;
976 struct cvmx_pciercx_cfg074_s {
977 uint32_t dword4:32;
978 } s;
979 struct cvmx_pciercx_cfg074_s cn52xx;
980 struct cvmx_pciercx_cfg074_s cn52xxp1;
981 struct cvmx_pciercx_cfg074_s cn56xx;
982 struct cvmx_pciercx_cfg074_s cn56xxp1;
983};
984
985union cvmx_pciercx_cfg075 {
986 uint32_t u32;
987 struct cvmx_pciercx_cfg075_s {
988 uint32_t reserved_3_31:29;
989 uint32_t fere:1;
990 uint32_t nfere:1;
991 uint32_t cere:1;
992 } s;
993 struct cvmx_pciercx_cfg075_s cn52xx;
994 struct cvmx_pciercx_cfg075_s cn52xxp1;
995 struct cvmx_pciercx_cfg075_s cn56xx;
996 struct cvmx_pciercx_cfg075_s cn56xxp1;
997};
998
999union cvmx_pciercx_cfg076 {
1000 uint32_t u32;
1001 struct cvmx_pciercx_cfg076_s {
1002 uint32_t aeimn:5;
1003 uint32_t reserved_7_26:20;
1004 uint32_t femr:1;
1005 uint32_t nfemr:1;
1006 uint32_t fuf:1;
1007 uint32_t multi_efnfr:1;
1008 uint32_t efnfr:1;
1009 uint32_t multi_ecr:1;
1010 uint32_t ecr:1;
1011 } s;
1012 struct cvmx_pciercx_cfg076_s cn52xx;
1013 struct cvmx_pciercx_cfg076_s cn52xxp1;
1014 struct cvmx_pciercx_cfg076_s cn56xx;
1015 struct cvmx_pciercx_cfg076_s cn56xxp1;
1016};
1017
1018union cvmx_pciercx_cfg077 {
1019 uint32_t u32;
1020 struct cvmx_pciercx_cfg077_s {
1021 uint32_t efnfsi:16;
1022 uint32_t ecsi:16;
1023 } s;
1024 struct cvmx_pciercx_cfg077_s cn52xx;
1025 struct cvmx_pciercx_cfg077_s cn52xxp1;
1026 struct cvmx_pciercx_cfg077_s cn56xx;
1027 struct cvmx_pciercx_cfg077_s cn56xxp1;
1028};
1029
1030union cvmx_pciercx_cfg448 {
1031 uint32_t u32;
1032 struct cvmx_pciercx_cfg448_s {
1033 uint32_t rtl:16;
1034 uint32_t rtltl:16;
1035 } s;
1036 struct cvmx_pciercx_cfg448_s cn52xx;
1037 struct cvmx_pciercx_cfg448_s cn52xxp1;
1038 struct cvmx_pciercx_cfg448_s cn56xx;
1039 struct cvmx_pciercx_cfg448_s cn56xxp1;
1040};
1041
1042union cvmx_pciercx_cfg449 {
1043 uint32_t u32;
1044 struct cvmx_pciercx_cfg449_s {
1045 uint32_t omr:32;
1046 } s;
1047 struct cvmx_pciercx_cfg449_s cn52xx;
1048 struct cvmx_pciercx_cfg449_s cn52xxp1;
1049 struct cvmx_pciercx_cfg449_s cn56xx;
1050 struct cvmx_pciercx_cfg449_s cn56xxp1;
1051};
1052
1053union cvmx_pciercx_cfg450 {
1054 uint32_t u32;
1055 struct cvmx_pciercx_cfg450_s {
1056 uint32_t lpec:8;
1057 uint32_t reserved_22_23:2;
1058 uint32_t link_state:6;
1059 uint32_t force_link:1;
1060 uint32_t reserved_8_14:7;
1061 uint32_t link_num:8;
1062 } s;
1063 struct cvmx_pciercx_cfg450_s cn52xx;
1064 struct cvmx_pciercx_cfg450_s cn52xxp1;
1065 struct cvmx_pciercx_cfg450_s cn56xx;
1066 struct cvmx_pciercx_cfg450_s cn56xxp1;
1067};
1068
1069union cvmx_pciercx_cfg451 {
1070 uint32_t u32;
1071 struct cvmx_pciercx_cfg451_s {
1072 uint32_t reserved_30_31:2;
1073 uint32_t l1el:3;
1074 uint32_t l0el:3;
1075 uint32_t n_fts_cc:8;
1076 uint32_t n_fts:8;
1077 uint32_t ack_freq:8;
1078 } s;
1079 struct cvmx_pciercx_cfg451_s cn52xx;
1080 struct cvmx_pciercx_cfg451_s cn52xxp1;
1081 struct cvmx_pciercx_cfg451_s cn56xx;
1082 struct cvmx_pciercx_cfg451_s cn56xxp1;
1083};
1084
1085union cvmx_pciercx_cfg452 {
1086 uint32_t u32;
1087 struct cvmx_pciercx_cfg452_s {
1088 uint32_t reserved_26_31:6;
1089 uint32_t eccrc:1;
1090 uint32_t reserved_22_24:3;
1091 uint32_t lme:6;
1092 uint32_t reserved_8_15:8;
1093 uint32_t flm:1;
1094 uint32_t reserved_6_6:1;
1095 uint32_t dllle:1;
1096 uint32_t reserved_4_4:1;
1097 uint32_t ra:1;
1098 uint32_t le:1;
1099 uint32_t sd:1;
1100 uint32_t omr:1;
1101 } s;
1102 struct cvmx_pciercx_cfg452_s cn52xx;
1103 struct cvmx_pciercx_cfg452_s cn52xxp1;
1104 struct cvmx_pciercx_cfg452_s cn56xx;
1105 struct cvmx_pciercx_cfg452_s cn56xxp1;
1106};
1107
1108union cvmx_pciercx_cfg453 {
1109 uint32_t u32;
1110 struct cvmx_pciercx_cfg453_s {
1111 uint32_t dlld:1;
1112 uint32_t reserved_26_30:5;
1113 uint32_t ack_nak:1;
1114 uint32_t fcd:1;
1115 uint32_t ilst:24;
1116 } s;
1117 struct cvmx_pciercx_cfg453_s cn52xx;
1118 struct cvmx_pciercx_cfg453_s cn52xxp1;
1119 struct cvmx_pciercx_cfg453_s cn56xx;
1120 struct cvmx_pciercx_cfg453_s cn56xxp1;
1121};
1122
1123union cvmx_pciercx_cfg454 {
1124 uint32_t u32;
1125 struct cvmx_pciercx_cfg454_s {
1126 uint32_t reserved_29_31:3;
1127 uint32_t tmfcwt:5;
1128 uint32_t tmanlt:5;
1129 uint32_t tmrt:5;
1130 uint32_t reserved_11_13:3;
1131 uint32_t nskps:3;
1132 uint32_t reserved_4_7:4;
1133 uint32_t ntss:4;
1134 } s;
1135 struct cvmx_pciercx_cfg454_s cn52xx;
1136 struct cvmx_pciercx_cfg454_s cn52xxp1;
1137 struct cvmx_pciercx_cfg454_s cn56xx;
1138 struct cvmx_pciercx_cfg454_s cn56xxp1;
1139};
1140
1141union cvmx_pciercx_cfg455 {
1142 uint32_t u32;
1143 struct cvmx_pciercx_cfg455_s {
1144 uint32_t m_cfg0_filt:1;
1145 uint32_t m_io_filt:1;
1146 uint32_t msg_ctrl:1;
1147 uint32_t m_cpl_ecrc_filt:1;
1148 uint32_t m_ecrc_filt:1;
1149 uint32_t m_cpl_len_err:1;
1150 uint32_t m_cpl_attr_err:1;
1151 uint32_t m_cpl_tc_err:1;
1152 uint32_t m_cpl_fun_err:1;
1153 uint32_t m_cpl_rid_err:1;
1154 uint32_t m_cpl_tag_err:1;
1155 uint32_t m_lk_filt:1;
1156 uint32_t m_cfg1_filt:1;
1157 uint32_t m_bar_match:1;
1158 uint32_t m_pois_filt:1;
1159 uint32_t m_fun:1;
1160 uint32_t dfcwt:1;
1161 uint32_t reserved_11_14:4;
1162 uint32_t skpiv:11;
1163 } s;
1164 struct cvmx_pciercx_cfg455_s cn52xx;
1165 struct cvmx_pciercx_cfg455_s cn52xxp1;
1166 struct cvmx_pciercx_cfg455_s cn56xx;
1167 struct cvmx_pciercx_cfg455_s cn56xxp1;
1168};
1169
1170union cvmx_pciercx_cfg456 {
1171 uint32_t u32;
1172 struct cvmx_pciercx_cfg456_s {
1173 uint32_t reserved_2_31:30;
1174 uint32_t m_vend1_drp:1;
1175 uint32_t m_vend0_drp:1;
1176 } s;
1177 struct cvmx_pciercx_cfg456_s cn52xx;
1178 struct cvmx_pciercx_cfg456_s cn52xxp1;
1179 struct cvmx_pciercx_cfg456_s cn56xx;
1180 struct cvmx_pciercx_cfg456_s cn56xxp1;
1181};
1182
1183union cvmx_pciercx_cfg458 {
1184 uint32_t u32;
1185 struct cvmx_pciercx_cfg458_s {
1186 uint32_t dbg_info_l32:32;
1187 } s;
1188 struct cvmx_pciercx_cfg458_s cn52xx;
1189 struct cvmx_pciercx_cfg458_s cn52xxp1;
1190 struct cvmx_pciercx_cfg458_s cn56xx;
1191 struct cvmx_pciercx_cfg458_s cn56xxp1;
1192};
1193
1194union cvmx_pciercx_cfg459 {
1195 uint32_t u32;
1196 struct cvmx_pciercx_cfg459_s {
1197 uint32_t dbg_info_u32:32;
1198 } s;
1199 struct cvmx_pciercx_cfg459_s cn52xx;
1200 struct cvmx_pciercx_cfg459_s cn52xxp1;
1201 struct cvmx_pciercx_cfg459_s cn56xx;
1202 struct cvmx_pciercx_cfg459_s cn56xxp1;
1203};
1204
1205union cvmx_pciercx_cfg460 {
1206 uint32_t u32;
1207 struct cvmx_pciercx_cfg460_s {
1208 uint32_t reserved_20_31:12;
1209 uint32_t tphfcc:8;
1210 uint32_t tpdfcc:12;
1211 } s;
1212 struct cvmx_pciercx_cfg460_s cn52xx;
1213 struct cvmx_pciercx_cfg460_s cn52xxp1;
1214 struct cvmx_pciercx_cfg460_s cn56xx;
1215 struct cvmx_pciercx_cfg460_s cn56xxp1;
1216};
1217
1218union cvmx_pciercx_cfg461 {
1219 uint32_t u32;
1220 struct cvmx_pciercx_cfg461_s {
1221 uint32_t reserved_20_31:12;
1222 uint32_t tchfcc:8;
1223 uint32_t tcdfcc:12;
1224 } s;
1225 struct cvmx_pciercx_cfg461_s cn52xx;
1226 struct cvmx_pciercx_cfg461_s cn52xxp1;
1227 struct cvmx_pciercx_cfg461_s cn56xx;
1228 struct cvmx_pciercx_cfg461_s cn56xxp1;
1229};
1230
1231union cvmx_pciercx_cfg462 {
1232 uint32_t u32;
1233 struct cvmx_pciercx_cfg462_s {
1234 uint32_t reserved_20_31:12;
1235 uint32_t tchfcc:8;
1236 uint32_t tcdfcc:12;
1237 } s;
1238 struct cvmx_pciercx_cfg462_s cn52xx;
1239 struct cvmx_pciercx_cfg462_s cn52xxp1;
1240 struct cvmx_pciercx_cfg462_s cn56xx;
1241 struct cvmx_pciercx_cfg462_s cn56xxp1;
1242};
1243
1244union cvmx_pciercx_cfg463 {
1245 uint32_t u32;
1246 struct cvmx_pciercx_cfg463_s {
1247 uint32_t reserved_3_31:29;
1248 uint32_t rqne:1;
1249 uint32_t trbne:1;
1250 uint32_t rtlpfccnr:1;
1251 } s;
1252 struct cvmx_pciercx_cfg463_s cn52xx;
1253 struct cvmx_pciercx_cfg463_s cn52xxp1;
1254 struct cvmx_pciercx_cfg463_s cn56xx;
1255 struct cvmx_pciercx_cfg463_s cn56xxp1;
1256};
1257
1258union cvmx_pciercx_cfg464 {
1259 uint32_t u32;
1260 struct cvmx_pciercx_cfg464_s {
1261 uint32_t wrr_vc3:8;
1262 uint32_t wrr_vc2:8;
1263 uint32_t wrr_vc1:8;
1264 uint32_t wrr_vc0:8;
1265 } s;
1266 struct cvmx_pciercx_cfg464_s cn52xx;
1267 struct cvmx_pciercx_cfg464_s cn52xxp1;
1268 struct cvmx_pciercx_cfg464_s cn56xx;
1269 struct cvmx_pciercx_cfg464_s cn56xxp1;
1270};
1271
1272union cvmx_pciercx_cfg465 {
1273 uint32_t u32;
1274 struct cvmx_pciercx_cfg465_s {
1275 uint32_t wrr_vc7:8;
1276 uint32_t wrr_vc6:8;
1277 uint32_t wrr_vc5:8;
1278 uint32_t wrr_vc4:8;
1279 } s;
1280 struct cvmx_pciercx_cfg465_s cn52xx;
1281 struct cvmx_pciercx_cfg465_s cn52xxp1;
1282 struct cvmx_pciercx_cfg465_s cn56xx;
1283 struct cvmx_pciercx_cfg465_s cn56xxp1;
1284};
1285
1286union cvmx_pciercx_cfg466 {
1287 uint32_t u32;
1288 struct cvmx_pciercx_cfg466_s {
1289 uint32_t rx_queue_order:1;
1290 uint32_t type_ordering:1;
1291 uint32_t reserved_24_29:6;
1292 uint32_t queue_mode:3;
1293 uint32_t reserved_20_20:1;
1294 uint32_t header_credits:8;
1295 uint32_t data_credits:12;
1296 } s;
1297 struct cvmx_pciercx_cfg466_s cn52xx;
1298 struct cvmx_pciercx_cfg466_s cn52xxp1;
1299 struct cvmx_pciercx_cfg466_s cn56xx;
1300 struct cvmx_pciercx_cfg466_s cn56xxp1;
1301};
1302
1303union cvmx_pciercx_cfg467 {
1304 uint32_t u32;
1305 struct cvmx_pciercx_cfg467_s {
1306 uint32_t reserved_24_31:8;
1307 uint32_t queue_mode:3;
1308 uint32_t reserved_20_20:1;
1309 uint32_t header_credits:8;
1310 uint32_t data_credits:12;
1311 } s;
1312 struct cvmx_pciercx_cfg467_s cn52xx;
1313 struct cvmx_pciercx_cfg467_s cn52xxp1;
1314 struct cvmx_pciercx_cfg467_s cn56xx;
1315 struct cvmx_pciercx_cfg467_s cn56xxp1;
1316};
1317
1318union cvmx_pciercx_cfg468 {
1319 uint32_t u32;
1320 struct cvmx_pciercx_cfg468_s {
1321 uint32_t reserved_24_31:8;
1322 uint32_t queue_mode:3;
1323 uint32_t reserved_20_20:1;
1324 uint32_t header_credits:8;
1325 uint32_t data_credits:12;
1326 } s;
1327 struct cvmx_pciercx_cfg468_s cn52xx;
1328 struct cvmx_pciercx_cfg468_s cn52xxp1;
1329 struct cvmx_pciercx_cfg468_s cn56xx;
1330 struct cvmx_pciercx_cfg468_s cn56xxp1;
1331};
1332
1333union cvmx_pciercx_cfg490 {
1334 uint32_t u32;
1335 struct cvmx_pciercx_cfg490_s {
1336 uint32_t reserved_26_31:6;
1337 uint32_t header_depth:10;
1338 uint32_t reserved_14_15:2;
1339 uint32_t data_depth:14;
1340 } s;
1341 struct cvmx_pciercx_cfg490_s cn52xx;
1342 struct cvmx_pciercx_cfg490_s cn52xxp1;
1343 struct cvmx_pciercx_cfg490_s cn56xx;
1344 struct cvmx_pciercx_cfg490_s cn56xxp1;
1345};
1346
1347union cvmx_pciercx_cfg491 {
1348 uint32_t u32;
1349 struct cvmx_pciercx_cfg491_s {
1350 uint32_t reserved_26_31:6;
1351 uint32_t header_depth:10;
1352 uint32_t reserved_14_15:2;
1353 uint32_t data_depth:14;
1354 } s;
1355 struct cvmx_pciercx_cfg491_s cn52xx;
1356 struct cvmx_pciercx_cfg491_s cn52xxp1;
1357 struct cvmx_pciercx_cfg491_s cn56xx;
1358 struct cvmx_pciercx_cfg491_s cn56xxp1;
1359};
1360
1361union cvmx_pciercx_cfg492 {
1362 uint32_t u32;
1363 struct cvmx_pciercx_cfg492_s {
1364 uint32_t reserved_26_31:6;
1365 uint32_t header_depth:10;
1366 uint32_t reserved_14_15:2;
1367 uint32_t data_depth:14;
1368 } s;
1369 struct cvmx_pciercx_cfg492_s cn52xx;
1370 struct cvmx_pciercx_cfg492_s cn52xxp1;
1371 struct cvmx_pciercx_cfg492_s cn56xx;
1372 struct cvmx_pciercx_cfg492_s cn56xxp1;
1373};
1374
1375union cvmx_pciercx_cfg516 {
1376 uint32_t u32;
1377 struct cvmx_pciercx_cfg516_s {
1378 uint32_t phy_stat:32;
1379 } s;
1380 struct cvmx_pciercx_cfg516_s cn52xx;
1381 struct cvmx_pciercx_cfg516_s cn52xxp1;
1382 struct cvmx_pciercx_cfg516_s cn56xx;
1383 struct cvmx_pciercx_cfg516_s cn56xxp1;
1384};
1385
1386union cvmx_pciercx_cfg517 {
1387 uint32_t u32;
1388 struct cvmx_pciercx_cfg517_s {
1389 uint32_t phy_ctrl:32;
1390 } s;
1391 struct cvmx_pciercx_cfg517_s cn52xx;
1392 struct cvmx_pciercx_cfg517_s cn52xxp1;
1393 struct cvmx_pciercx_cfg517_s cn56xx;
1394 struct cvmx_pciercx_cfg517_s cn56xxp1;
1395};
1396
1397#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-pescx-defs.h b/arch/mips/include/asm/octeon/cvmx-pescx-defs.h
new file mode 100644
index 000000000000..f40cfaf84454
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-pescx-defs.h
@@ -0,0 +1,410 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_PESCX_DEFS_H__
29#define __CVMX_PESCX_DEFS_H__
30
31#define CVMX_PESCX_BIST_STATUS(block_id) \
32 CVMX_ADD_IO_SEG(0x00011800C8000018ull + (((block_id) & 1) * 0x8000000ull))
33#define CVMX_PESCX_BIST_STATUS2(block_id) \
34 CVMX_ADD_IO_SEG(0x00011800C8000418ull + (((block_id) & 1) * 0x8000000ull))
35#define CVMX_PESCX_CFG_RD(block_id) \
36 CVMX_ADD_IO_SEG(0x00011800C8000030ull + (((block_id) & 1) * 0x8000000ull))
37#define CVMX_PESCX_CFG_WR(block_id) \
38 CVMX_ADD_IO_SEG(0x00011800C8000028ull + (((block_id) & 1) * 0x8000000ull))
39#define CVMX_PESCX_CPL_LUT_VALID(block_id) \
40 CVMX_ADD_IO_SEG(0x00011800C8000098ull + (((block_id) & 1) * 0x8000000ull))
41#define CVMX_PESCX_CTL_STATUS(block_id) \
42 CVMX_ADD_IO_SEG(0x00011800C8000000ull + (((block_id) & 1) * 0x8000000ull))
43#define CVMX_PESCX_CTL_STATUS2(block_id) \
44 CVMX_ADD_IO_SEG(0x00011800C8000400ull + (((block_id) & 1) * 0x8000000ull))
45#define CVMX_PESCX_DBG_INFO(block_id) \
46 CVMX_ADD_IO_SEG(0x00011800C8000008ull + (((block_id) & 1) * 0x8000000ull))
47#define CVMX_PESCX_DBG_INFO_EN(block_id) \
48 CVMX_ADD_IO_SEG(0x00011800C80000A0ull + (((block_id) & 1) * 0x8000000ull))
49#define CVMX_PESCX_DIAG_STATUS(block_id) \
50 CVMX_ADD_IO_SEG(0x00011800C8000020ull + (((block_id) & 1) * 0x8000000ull))
51#define CVMX_PESCX_P2N_BAR0_START(block_id) \
52 CVMX_ADD_IO_SEG(0x00011800C8000080ull + (((block_id) & 1) * 0x8000000ull))
53#define CVMX_PESCX_P2N_BAR1_START(block_id) \
54 CVMX_ADD_IO_SEG(0x00011800C8000088ull + (((block_id) & 1) * 0x8000000ull))
55#define CVMX_PESCX_P2N_BAR2_START(block_id) \
56 CVMX_ADD_IO_SEG(0x00011800C8000090ull + (((block_id) & 1) * 0x8000000ull))
57#define CVMX_PESCX_P2P_BARX_END(offset, block_id) \
58 CVMX_ADD_IO_SEG(0x00011800C8000048ull + (((offset) & 3) * 16) + (((block_id) & 1) * 0x8000000ull))
59#define CVMX_PESCX_P2P_BARX_START(offset, block_id) \
60 CVMX_ADD_IO_SEG(0x00011800C8000040ull + (((offset) & 3) * 16) + (((block_id) & 1) * 0x8000000ull))
61#define CVMX_PESCX_TLP_CREDITS(block_id) \
62 CVMX_ADD_IO_SEG(0x00011800C8000038ull + (((block_id) & 1) * 0x8000000ull))
63
64union cvmx_pescx_bist_status {
65 uint64_t u64;
66 struct cvmx_pescx_bist_status_s {
67 uint64_t reserved_13_63:51;
68 uint64_t rqdata5:1;
69 uint64_t ctlp_or:1;
70 uint64_t ntlp_or:1;
71 uint64_t ptlp_or:1;
72 uint64_t retry:1;
73 uint64_t rqdata0:1;
74 uint64_t rqdata1:1;
75 uint64_t rqdata2:1;
76 uint64_t rqdata3:1;
77 uint64_t rqdata4:1;
78 uint64_t rqhdr1:1;
79 uint64_t rqhdr0:1;
80 uint64_t sot:1;
81 } s;
82 struct cvmx_pescx_bist_status_s cn52xx;
83 struct cvmx_pescx_bist_status_cn52xxp1 {
84 uint64_t reserved_12_63:52;
85 uint64_t ctlp_or:1;
86 uint64_t ntlp_or:1;
87 uint64_t ptlp_or:1;
88 uint64_t retry:1;
89 uint64_t rqdata0:1;
90 uint64_t rqdata1:1;
91 uint64_t rqdata2:1;
92 uint64_t rqdata3:1;
93 uint64_t rqdata4:1;
94 uint64_t rqhdr1:1;
95 uint64_t rqhdr0:1;
96 uint64_t sot:1;
97 } cn52xxp1;
98 struct cvmx_pescx_bist_status_s cn56xx;
99 struct cvmx_pescx_bist_status_cn52xxp1 cn56xxp1;
100};
101
102union cvmx_pescx_bist_status2 {
103 uint64_t u64;
104 struct cvmx_pescx_bist_status2_s {
105 uint64_t reserved_14_63:50;
106 uint64_t cto_p2e:1;
107 uint64_t e2p_cpl:1;
108 uint64_t e2p_n:1;
109 uint64_t e2p_p:1;
110 uint64_t e2p_rsl:1;
111 uint64_t dbg_p2e:1;
112 uint64_t peai_p2e:1;
113 uint64_t rsl_p2e:1;
114 uint64_t pef_tpf1:1;
115 uint64_t pef_tpf0:1;
116 uint64_t pef_tnf:1;
117 uint64_t pef_tcf1:1;
118 uint64_t pef_tc0:1;
119 uint64_t ppf:1;
120 } s;
121 struct cvmx_pescx_bist_status2_s cn52xx;
122 struct cvmx_pescx_bist_status2_s cn52xxp1;
123 struct cvmx_pescx_bist_status2_s cn56xx;
124 struct cvmx_pescx_bist_status2_s cn56xxp1;
125};
126
127union cvmx_pescx_cfg_rd {
128 uint64_t u64;
129 struct cvmx_pescx_cfg_rd_s {
130 uint64_t data:32;
131 uint64_t addr:32;
132 } s;
133 struct cvmx_pescx_cfg_rd_s cn52xx;
134 struct cvmx_pescx_cfg_rd_s cn52xxp1;
135 struct cvmx_pescx_cfg_rd_s cn56xx;
136 struct cvmx_pescx_cfg_rd_s cn56xxp1;
137};
138
139union cvmx_pescx_cfg_wr {
140 uint64_t u64;
141 struct cvmx_pescx_cfg_wr_s {
142 uint64_t data:32;
143 uint64_t addr:32;
144 } s;
145 struct cvmx_pescx_cfg_wr_s cn52xx;
146 struct cvmx_pescx_cfg_wr_s cn52xxp1;
147 struct cvmx_pescx_cfg_wr_s cn56xx;
148 struct cvmx_pescx_cfg_wr_s cn56xxp1;
149};
150
151union cvmx_pescx_cpl_lut_valid {
152 uint64_t u64;
153 struct cvmx_pescx_cpl_lut_valid_s {
154 uint64_t reserved_32_63:32;
155 uint64_t tag:32;
156 } s;
157 struct cvmx_pescx_cpl_lut_valid_s cn52xx;
158 struct cvmx_pescx_cpl_lut_valid_s cn52xxp1;
159 struct cvmx_pescx_cpl_lut_valid_s cn56xx;
160 struct cvmx_pescx_cpl_lut_valid_s cn56xxp1;
161};
162
163union cvmx_pescx_ctl_status {
164 uint64_t u64;
165 struct cvmx_pescx_ctl_status_s {
166 uint64_t reserved_28_63:36;
167 uint64_t dnum:5;
168 uint64_t pbus:8;
169 uint64_t qlm_cfg:2;
170 uint64_t lane_swp:1;
171 uint64_t pm_xtoff:1;
172 uint64_t pm_xpme:1;
173 uint64_t ob_p_cmd:1;
174 uint64_t reserved_7_8:2;
175 uint64_t nf_ecrc:1;
176 uint64_t dly_one:1;
177 uint64_t lnk_enb:1;
178 uint64_t ro_ctlp:1;
179 uint64_t reserved_2_2:1;
180 uint64_t inv_ecrc:1;
181 uint64_t inv_lcrc:1;
182 } s;
183 struct cvmx_pescx_ctl_status_s cn52xx;
184 struct cvmx_pescx_ctl_status_s cn52xxp1;
185 struct cvmx_pescx_ctl_status_cn56xx {
186 uint64_t reserved_28_63:36;
187 uint64_t dnum:5;
188 uint64_t pbus:8;
189 uint64_t qlm_cfg:2;
190 uint64_t reserved_12_12:1;
191 uint64_t pm_xtoff:1;
192 uint64_t pm_xpme:1;
193 uint64_t ob_p_cmd:1;
194 uint64_t reserved_7_8:2;
195 uint64_t nf_ecrc:1;
196 uint64_t dly_one:1;
197 uint64_t lnk_enb:1;
198 uint64_t ro_ctlp:1;
199 uint64_t reserved_2_2:1;
200 uint64_t inv_ecrc:1;
201 uint64_t inv_lcrc:1;
202 } cn56xx;
203 struct cvmx_pescx_ctl_status_cn56xx cn56xxp1;
204};
205
206union cvmx_pescx_ctl_status2 {
207 uint64_t u64;
208 struct cvmx_pescx_ctl_status2_s {
209 uint64_t reserved_2_63:62;
210 uint64_t pclk_run:1;
211 uint64_t pcierst:1;
212 } s;
213 struct cvmx_pescx_ctl_status2_s cn52xx;
214 struct cvmx_pescx_ctl_status2_cn52xxp1 {
215 uint64_t reserved_1_63:63;
216 uint64_t pcierst:1;
217 } cn52xxp1;
218 struct cvmx_pescx_ctl_status2_s cn56xx;
219 struct cvmx_pescx_ctl_status2_cn52xxp1 cn56xxp1;
220};
221
222union cvmx_pescx_dbg_info {
223 uint64_t u64;
224 struct cvmx_pescx_dbg_info_s {
225 uint64_t reserved_31_63:33;
226 uint64_t ecrc_e:1;
227 uint64_t rawwpp:1;
228 uint64_t racpp:1;
229 uint64_t ramtlp:1;
230 uint64_t rarwdns:1;
231 uint64_t caar:1;
232 uint64_t racca:1;
233 uint64_t racur:1;
234 uint64_t rauc:1;
235 uint64_t rqo:1;
236 uint64_t fcuv:1;
237 uint64_t rpe:1;
238 uint64_t fcpvwt:1;
239 uint64_t dpeoosd:1;
240 uint64_t rtwdle:1;
241 uint64_t rdwdle:1;
242 uint64_t mre:1;
243 uint64_t rte:1;
244 uint64_t acto:1;
245 uint64_t rvdm:1;
246 uint64_t rumep:1;
247 uint64_t rptamrc:1;
248 uint64_t rpmerc:1;
249 uint64_t rfemrc:1;
250 uint64_t rnfemrc:1;
251 uint64_t rcemrc:1;
252 uint64_t rpoison:1;
253 uint64_t recrce:1;
254 uint64_t rtlplle:1;
255 uint64_t rtlpmal:1;
256 uint64_t spoison:1;
257 } s;
258 struct cvmx_pescx_dbg_info_s cn52xx;
259 struct cvmx_pescx_dbg_info_s cn52xxp1;
260 struct cvmx_pescx_dbg_info_s cn56xx;
261 struct cvmx_pescx_dbg_info_s cn56xxp1;
262};
263
264union cvmx_pescx_dbg_info_en {
265 uint64_t u64;
266 struct cvmx_pescx_dbg_info_en_s {
267 uint64_t reserved_31_63:33;
268 uint64_t ecrc_e:1;
269 uint64_t rawwpp:1;
270 uint64_t racpp:1;
271 uint64_t ramtlp:1;
272 uint64_t rarwdns:1;
273 uint64_t caar:1;
274 uint64_t racca:1;
275 uint64_t racur:1;
276 uint64_t rauc:1;
277 uint64_t rqo:1;
278 uint64_t fcuv:1;
279 uint64_t rpe:1;
280 uint64_t fcpvwt:1;
281 uint64_t dpeoosd:1;
282 uint64_t rtwdle:1;
283 uint64_t rdwdle:1;
284 uint64_t mre:1;
285 uint64_t rte:1;
286 uint64_t acto:1;
287 uint64_t rvdm:1;
288 uint64_t rumep:1;
289 uint64_t rptamrc:1;
290 uint64_t rpmerc:1;
291 uint64_t rfemrc:1;
292 uint64_t rnfemrc:1;
293 uint64_t rcemrc:1;
294 uint64_t rpoison:1;
295 uint64_t recrce:1;
296 uint64_t rtlplle:1;
297 uint64_t rtlpmal:1;
298 uint64_t spoison:1;
299 } s;
300 struct cvmx_pescx_dbg_info_en_s cn52xx;
301 struct cvmx_pescx_dbg_info_en_s cn52xxp1;
302 struct cvmx_pescx_dbg_info_en_s cn56xx;
303 struct cvmx_pescx_dbg_info_en_s cn56xxp1;
304};
305
306union cvmx_pescx_diag_status {
307 uint64_t u64;
308 struct cvmx_pescx_diag_status_s {
309 uint64_t reserved_4_63:60;
310 uint64_t pm_dst:1;
311 uint64_t pm_stat:1;
312 uint64_t pm_en:1;
313 uint64_t aux_en:1;
314 } s;
315 struct cvmx_pescx_diag_status_s cn52xx;
316 struct cvmx_pescx_diag_status_s cn52xxp1;
317 struct cvmx_pescx_diag_status_s cn56xx;
318 struct cvmx_pescx_diag_status_s cn56xxp1;
319};
320
321union cvmx_pescx_p2n_bar0_start {
322 uint64_t u64;
323 struct cvmx_pescx_p2n_bar0_start_s {
324 uint64_t addr:50;
325 uint64_t reserved_0_13:14;
326 } s;
327 struct cvmx_pescx_p2n_bar0_start_s cn52xx;
328 struct cvmx_pescx_p2n_bar0_start_s cn52xxp1;
329 struct cvmx_pescx_p2n_bar0_start_s cn56xx;
330 struct cvmx_pescx_p2n_bar0_start_s cn56xxp1;
331};
332
333union cvmx_pescx_p2n_bar1_start {
334 uint64_t u64;
335 struct cvmx_pescx_p2n_bar1_start_s {
336 uint64_t addr:38;
337 uint64_t reserved_0_25:26;
338 } s;
339 struct cvmx_pescx_p2n_bar1_start_s cn52xx;
340 struct cvmx_pescx_p2n_bar1_start_s cn52xxp1;
341 struct cvmx_pescx_p2n_bar1_start_s cn56xx;
342 struct cvmx_pescx_p2n_bar1_start_s cn56xxp1;
343};
344
345union cvmx_pescx_p2n_bar2_start {
346 uint64_t u64;
347 struct cvmx_pescx_p2n_bar2_start_s {
348 uint64_t addr:25;
349 uint64_t reserved_0_38:39;
350 } s;
351 struct cvmx_pescx_p2n_bar2_start_s cn52xx;
352 struct cvmx_pescx_p2n_bar2_start_s cn52xxp1;
353 struct cvmx_pescx_p2n_bar2_start_s cn56xx;
354 struct cvmx_pescx_p2n_bar2_start_s cn56xxp1;
355};
356
357union cvmx_pescx_p2p_barx_end {
358 uint64_t u64;
359 struct cvmx_pescx_p2p_barx_end_s {
360 uint64_t addr:52;
361 uint64_t reserved_0_11:12;
362 } s;
363 struct cvmx_pescx_p2p_barx_end_s cn52xx;
364 struct cvmx_pescx_p2p_barx_end_s cn52xxp1;
365 struct cvmx_pescx_p2p_barx_end_s cn56xx;
366 struct cvmx_pescx_p2p_barx_end_s cn56xxp1;
367};
368
369union cvmx_pescx_p2p_barx_start {
370 uint64_t u64;
371 struct cvmx_pescx_p2p_barx_start_s {
372 uint64_t addr:52;
373 uint64_t reserved_0_11:12;
374 } s;
375 struct cvmx_pescx_p2p_barx_start_s cn52xx;
376 struct cvmx_pescx_p2p_barx_start_s cn52xxp1;
377 struct cvmx_pescx_p2p_barx_start_s cn56xx;
378 struct cvmx_pescx_p2p_barx_start_s cn56xxp1;
379};
380
381union cvmx_pescx_tlp_credits {
382 uint64_t u64;
383 struct cvmx_pescx_tlp_credits_s {
384 uint64_t reserved_0_63:64;
385 } s;
386 struct cvmx_pescx_tlp_credits_cn52xx {
387 uint64_t reserved_56_63:8;
388 uint64_t peai_ppf:8;
389 uint64_t pesc_cpl:8;
390 uint64_t pesc_np:8;
391 uint64_t pesc_p:8;
392 uint64_t npei_cpl:8;
393 uint64_t npei_np:8;
394 uint64_t npei_p:8;
395 } cn52xx;
396 struct cvmx_pescx_tlp_credits_cn52xxp1 {
397 uint64_t reserved_38_63:26;
398 uint64_t peai_ppf:8;
399 uint64_t pesc_cpl:5;
400 uint64_t pesc_np:5;
401 uint64_t pesc_p:5;
402 uint64_t npei_cpl:5;
403 uint64_t npei_np:5;
404 uint64_t npei_p:5;
405 } cn52xxp1;
406 struct cvmx_pescx_tlp_credits_cn52xx cn56xx;
407 struct cvmx_pescx_tlp_credits_cn52xxp1 cn56xxp1;
408};
409
410#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-pexp-defs.h b/arch/mips/include/asm/octeon/cvmx-pexp-defs.h
new file mode 100644
index 000000000000..5ea5dc571b54
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-pexp-defs.h
@@ -0,0 +1,229 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28/**
29 * cvmx-pexp-defs.h
30 *
31 * Configuration and status register (CSR) definitions for
32 * OCTEON PEXP.
33 *
34 */
35#ifndef __CVMX_PEXP_DEFS_H__
36#define __CVMX_PEXP_DEFS_H__
37
38#define CVMX_PEXP_NPEI_BAR1_INDEXX(offset) \
39 CVMX_ADD_IO_SEG(0x00011F0000008000ull + (((offset) & 31) * 16))
40#define CVMX_PEXP_NPEI_BIST_STATUS \
41 CVMX_ADD_IO_SEG(0x00011F0000008580ull)
42#define CVMX_PEXP_NPEI_BIST_STATUS2 \
43 CVMX_ADD_IO_SEG(0x00011F0000008680ull)
44#define CVMX_PEXP_NPEI_CTL_PORT0 \
45 CVMX_ADD_IO_SEG(0x00011F0000008250ull)
46#define CVMX_PEXP_NPEI_CTL_PORT1 \
47 CVMX_ADD_IO_SEG(0x00011F0000008260ull)
48#define CVMX_PEXP_NPEI_CTL_STATUS \
49 CVMX_ADD_IO_SEG(0x00011F0000008570ull)
50#define CVMX_PEXP_NPEI_CTL_STATUS2 \
51 CVMX_ADD_IO_SEG(0x00011F000000BC00ull)
52#define CVMX_PEXP_NPEI_DATA_OUT_CNT \
53 CVMX_ADD_IO_SEG(0x00011F00000085F0ull)
54#define CVMX_PEXP_NPEI_DBG_DATA \
55 CVMX_ADD_IO_SEG(0x00011F0000008510ull)
56#define CVMX_PEXP_NPEI_DBG_SELECT \
57 CVMX_ADD_IO_SEG(0x00011F0000008500ull)
58#define CVMX_PEXP_NPEI_DMA0_INT_LEVEL \
59 CVMX_ADD_IO_SEG(0x00011F00000085C0ull)
60#define CVMX_PEXP_NPEI_DMA1_INT_LEVEL \
61 CVMX_ADD_IO_SEG(0x00011F00000085D0ull)
62#define CVMX_PEXP_NPEI_DMAX_COUNTS(offset) \
63 CVMX_ADD_IO_SEG(0x00011F0000008450ull + (((offset) & 7) * 16))
64#define CVMX_PEXP_NPEI_DMAX_DBELL(offset) \
65 CVMX_ADD_IO_SEG(0x00011F00000083B0ull + (((offset) & 7) * 16))
66#define CVMX_PEXP_NPEI_DMAX_IBUFF_SADDR(offset) \
67 CVMX_ADD_IO_SEG(0x00011F0000008400ull + (((offset) & 7) * 16))
68#define CVMX_PEXP_NPEI_DMAX_NADDR(offset) \
69 CVMX_ADD_IO_SEG(0x00011F00000084A0ull + (((offset) & 7) * 16))
70#define CVMX_PEXP_NPEI_DMA_CNTS \
71 CVMX_ADD_IO_SEG(0x00011F00000085E0ull)
72#define CVMX_PEXP_NPEI_DMA_CONTROL \
73 CVMX_ADD_IO_SEG(0x00011F00000083A0ull)
74#define CVMX_PEXP_NPEI_INT_A_ENB \
75 CVMX_ADD_IO_SEG(0x00011F0000008560ull)
76#define CVMX_PEXP_NPEI_INT_A_ENB2 \
77 CVMX_ADD_IO_SEG(0x00011F000000BCE0ull)
78#define CVMX_PEXP_NPEI_INT_A_SUM \
79 CVMX_ADD_IO_SEG(0x00011F0000008550ull)
80#define CVMX_PEXP_NPEI_INT_ENB \
81 CVMX_ADD_IO_SEG(0x00011F0000008540ull)
82#define CVMX_PEXP_NPEI_INT_ENB2 \
83 CVMX_ADD_IO_SEG(0x00011F000000BCD0ull)
84#define CVMX_PEXP_NPEI_INT_INFO \
85 CVMX_ADD_IO_SEG(0x00011F0000008590ull)
86#define CVMX_PEXP_NPEI_INT_SUM \
87 CVMX_ADD_IO_SEG(0x00011F0000008530ull)
88#define CVMX_PEXP_NPEI_INT_SUM2 \
89 CVMX_ADD_IO_SEG(0x00011F000000BCC0ull)
90#define CVMX_PEXP_NPEI_LAST_WIN_RDATA0 \
91 CVMX_ADD_IO_SEG(0x00011F0000008600ull)
92#define CVMX_PEXP_NPEI_LAST_WIN_RDATA1 \
93 CVMX_ADD_IO_SEG(0x00011F0000008610ull)
94#define CVMX_PEXP_NPEI_MEM_ACCESS_CTL \
95 CVMX_ADD_IO_SEG(0x00011F00000084F0ull)
96#define CVMX_PEXP_NPEI_MEM_ACCESS_SUBIDX(offset) \
97 CVMX_ADD_IO_SEG(0x00011F0000008280ull + (((offset) & 31) * 16) - 16 * 12)
98#define CVMX_PEXP_NPEI_MSI_ENB0 \
99 CVMX_ADD_IO_SEG(0x00011F000000BC50ull)
100#define CVMX_PEXP_NPEI_MSI_ENB1 \
101 CVMX_ADD_IO_SEG(0x00011F000000BC60ull)
102#define CVMX_PEXP_NPEI_MSI_ENB2 \
103 CVMX_ADD_IO_SEG(0x00011F000000BC70ull)
104#define CVMX_PEXP_NPEI_MSI_ENB3 \
105 CVMX_ADD_IO_SEG(0x00011F000000BC80ull)
106#define CVMX_PEXP_NPEI_MSI_RCV0 \
107 CVMX_ADD_IO_SEG(0x00011F000000BC10ull)
108#define CVMX_PEXP_NPEI_MSI_RCV1 \
109 CVMX_ADD_IO_SEG(0x00011F000000BC20ull)
110#define CVMX_PEXP_NPEI_MSI_RCV2 \
111 CVMX_ADD_IO_SEG(0x00011F000000BC30ull)
112#define CVMX_PEXP_NPEI_MSI_RCV3 \
113 CVMX_ADD_IO_SEG(0x00011F000000BC40ull)
114#define CVMX_PEXP_NPEI_MSI_RD_MAP \
115 CVMX_ADD_IO_SEG(0x00011F000000BCA0ull)
116#define CVMX_PEXP_NPEI_MSI_W1C_ENB0 \
117 CVMX_ADD_IO_SEG(0x00011F000000BCF0ull)
118#define CVMX_PEXP_NPEI_MSI_W1C_ENB1 \
119 CVMX_ADD_IO_SEG(0x00011F000000BD00ull)
120#define CVMX_PEXP_NPEI_MSI_W1C_ENB2 \
121 CVMX_ADD_IO_SEG(0x00011F000000BD10ull)
122#define CVMX_PEXP_NPEI_MSI_W1C_ENB3 \
123 CVMX_ADD_IO_SEG(0x00011F000000BD20ull)
124#define CVMX_PEXP_NPEI_MSI_W1S_ENB0 \
125 CVMX_ADD_IO_SEG(0x00011F000000BD30ull)
126#define CVMX_PEXP_NPEI_MSI_W1S_ENB1 \
127 CVMX_ADD_IO_SEG(0x00011F000000BD40ull)
128#define CVMX_PEXP_NPEI_MSI_W1S_ENB2 \
129 CVMX_ADD_IO_SEG(0x00011F000000BD50ull)
130#define CVMX_PEXP_NPEI_MSI_W1S_ENB3 \
131 CVMX_ADD_IO_SEG(0x00011F000000BD60ull)
132#define CVMX_PEXP_NPEI_MSI_WR_MAP \
133 CVMX_ADD_IO_SEG(0x00011F000000BC90ull)
134#define CVMX_PEXP_NPEI_PCIE_CREDIT_CNT \
135 CVMX_ADD_IO_SEG(0x00011F000000BD70ull)
136#define CVMX_PEXP_NPEI_PCIE_MSI_RCV \
137 CVMX_ADD_IO_SEG(0x00011F000000BCB0ull)
138#define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B1 \
139 CVMX_ADD_IO_SEG(0x00011F0000008650ull)
140#define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B2 \
141 CVMX_ADD_IO_SEG(0x00011F0000008660ull)
142#define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B3 \
143 CVMX_ADD_IO_SEG(0x00011F0000008670ull)
144#define CVMX_PEXP_NPEI_PKTX_CNTS(offset) \
145 CVMX_ADD_IO_SEG(0x00011F000000A400ull + (((offset) & 31) * 16))
146#define CVMX_PEXP_NPEI_PKTX_INSTR_BADDR(offset) \
147 CVMX_ADD_IO_SEG(0x00011F000000A800ull + (((offset) & 31) * 16))
148#define CVMX_PEXP_NPEI_PKTX_INSTR_BAOFF_DBELL(offset) \
149 CVMX_ADD_IO_SEG(0x00011F000000AC00ull + (((offset) & 31) * 16))
150#define CVMX_PEXP_NPEI_PKTX_INSTR_FIFO_RSIZE(offset) \
151 CVMX_ADD_IO_SEG(0x00011F000000B000ull + (((offset) & 31) * 16))
152#define CVMX_PEXP_NPEI_PKTX_INSTR_HEADER(offset) \
153 CVMX_ADD_IO_SEG(0x00011F000000B400ull + (((offset) & 31) * 16))
154#define CVMX_PEXP_NPEI_PKTX_IN_BP(offset) \
155 CVMX_ADD_IO_SEG(0x00011F000000B800ull + (((offset) & 31) * 16))
156#define CVMX_PEXP_NPEI_PKTX_SLIST_BADDR(offset) \
157 CVMX_ADD_IO_SEG(0x00011F0000009400ull + (((offset) & 31) * 16))
158#define CVMX_PEXP_NPEI_PKTX_SLIST_BAOFF_DBELL(offset) \
159 CVMX_ADD_IO_SEG(0x00011F0000009800ull + (((offset) & 31) * 16))
160#define CVMX_PEXP_NPEI_PKTX_SLIST_FIFO_RSIZE(offset) \
161 CVMX_ADD_IO_SEG(0x00011F0000009C00ull + (((offset) & 31) * 16))
162#define CVMX_PEXP_NPEI_PKT_CNT_INT \
163 CVMX_ADD_IO_SEG(0x00011F0000009110ull)
164#define CVMX_PEXP_NPEI_PKT_CNT_INT_ENB \
165 CVMX_ADD_IO_SEG(0x00011F0000009130ull)
166#define CVMX_PEXP_NPEI_PKT_DATA_OUT_ES \
167 CVMX_ADD_IO_SEG(0x00011F00000090B0ull)
168#define CVMX_PEXP_NPEI_PKT_DATA_OUT_NS \
169 CVMX_ADD_IO_SEG(0x00011F00000090A0ull)
170#define CVMX_PEXP_NPEI_PKT_DATA_OUT_ROR \
171 CVMX_ADD_IO_SEG(0x00011F0000009090ull)
172#define CVMX_PEXP_NPEI_PKT_DPADDR \
173 CVMX_ADD_IO_SEG(0x00011F0000009080ull)
174#define CVMX_PEXP_NPEI_PKT_INPUT_CONTROL \
175 CVMX_ADD_IO_SEG(0x00011F0000009150ull)
176#define CVMX_PEXP_NPEI_PKT_INSTR_ENB \
177 CVMX_ADD_IO_SEG(0x00011F0000009000ull)
178#define CVMX_PEXP_NPEI_PKT_INSTR_RD_SIZE \
179 CVMX_ADD_IO_SEG(0x00011F0000009190ull)
180#define CVMX_PEXP_NPEI_PKT_INSTR_SIZE \
181 CVMX_ADD_IO_SEG(0x00011F0000009020ull)
182#define CVMX_PEXP_NPEI_PKT_INT_LEVELS \
183 CVMX_ADD_IO_SEG(0x00011F0000009100ull)
184#define CVMX_PEXP_NPEI_PKT_IN_BP \
185 CVMX_ADD_IO_SEG(0x00011F00000086B0ull)
186#define CVMX_PEXP_NPEI_PKT_IN_DONEX_CNTS(offset) \
187 CVMX_ADD_IO_SEG(0x00011F000000A000ull + (((offset) & 31) * 16))
188#define CVMX_PEXP_NPEI_PKT_IN_INSTR_COUNTS \
189 CVMX_ADD_IO_SEG(0x00011F00000086A0ull)
190#define CVMX_PEXP_NPEI_PKT_IN_PCIE_PORT \
191 CVMX_ADD_IO_SEG(0x00011F00000091A0ull)
192#define CVMX_PEXP_NPEI_PKT_IPTR \
193 CVMX_ADD_IO_SEG(0x00011F0000009070ull)
194#define CVMX_PEXP_NPEI_PKT_OUTPUT_WMARK \
195 CVMX_ADD_IO_SEG(0x00011F0000009160ull)
196#define CVMX_PEXP_NPEI_PKT_OUT_BMODE \
197 CVMX_ADD_IO_SEG(0x00011F00000090D0ull)
198#define CVMX_PEXP_NPEI_PKT_OUT_ENB \
199 CVMX_ADD_IO_SEG(0x00011F0000009010ull)
200#define CVMX_PEXP_NPEI_PKT_PCIE_PORT \
201 CVMX_ADD_IO_SEG(0x00011F00000090E0ull)
202#define CVMX_PEXP_NPEI_PKT_PORT_IN_RST \
203 CVMX_ADD_IO_SEG(0x00011F0000008690ull)
204#define CVMX_PEXP_NPEI_PKT_SLIST_ES \
205 CVMX_ADD_IO_SEG(0x00011F0000009050ull)
206#define CVMX_PEXP_NPEI_PKT_SLIST_ID_SIZE \
207 CVMX_ADD_IO_SEG(0x00011F0000009180ull)
208#define CVMX_PEXP_NPEI_PKT_SLIST_NS \
209 CVMX_ADD_IO_SEG(0x00011F0000009040ull)
210#define CVMX_PEXP_NPEI_PKT_SLIST_ROR \
211 CVMX_ADD_IO_SEG(0x00011F0000009030ull)
212#define CVMX_PEXP_NPEI_PKT_TIME_INT \
213 CVMX_ADD_IO_SEG(0x00011F0000009120ull)
214#define CVMX_PEXP_NPEI_PKT_TIME_INT_ENB \
215 CVMX_ADD_IO_SEG(0x00011F0000009140ull)
216#define CVMX_PEXP_NPEI_RSL_INT_BLOCKS \
217 CVMX_ADD_IO_SEG(0x00011F0000008520ull)
218#define CVMX_PEXP_NPEI_SCRATCH_1 \
219 CVMX_ADD_IO_SEG(0x00011F0000008270ull)
220#define CVMX_PEXP_NPEI_STATE1 \
221 CVMX_ADD_IO_SEG(0x00011F0000008620ull)
222#define CVMX_PEXP_NPEI_STATE2 \
223 CVMX_ADD_IO_SEG(0x00011F0000008630ull)
224#define CVMX_PEXP_NPEI_STATE3 \
225 CVMX_ADD_IO_SEG(0x00011F0000008640ull)
226#define CVMX_PEXP_NPEI_WINDOW_CTL \
227 CVMX_ADD_IO_SEG(0x00011F0000008380ull)
228
229#endif
diff --git a/arch/mips/include/asm/octeon/cvmx.h b/arch/mips/include/asm/octeon/cvmx.h
index 03fddfa3e928..e31e3fe14f8a 100644
--- a/arch/mips/include/asm/octeon/cvmx.h
+++ b/arch/mips/include/asm/octeon/cvmx.h
@@ -376,6 +376,18 @@ static inline uint64_t cvmx_get_cycle(void)
376} 376}
377 377
378/** 378/**
379 * Wait for the specified number of cycle
380 *
381 */
382static inline void cvmx_wait(uint64_t cycles)
383{
384 uint64_t done = cvmx_get_cycle() + cycles;
385
386 while (cvmx_get_cycle() < done)
387 ; /* Spin */
388}
389
390/**
379 * Reads a chip global cycle counter. This counts CPU cycles since 391 * Reads a chip global cycle counter. This counts CPU cycles since
380 * chip reset. The counter is 64 bit. 392 * chip reset. The counter is 64 bit.
381 * This register does not exist on CN38XX pass 1 silicion 393 * This register does not exist on CN38XX pass 1 silicion
diff --git a/arch/mips/include/asm/octeon/octeon-feature.h b/arch/mips/include/asm/octeon/octeon-feature.h
index 04fac684069c..ef24a7b4ea57 100644
--- a/arch/mips/include/asm/octeon/octeon-feature.h
+++ b/arch/mips/include/asm/octeon/octeon-feature.h
@@ -57,6 +57,13 @@ enum octeon_feature {
57 OCTEON_FEATURE_RAID, 57 OCTEON_FEATURE_RAID,
58 /* Octeon has a builtin USB */ 58 /* Octeon has a builtin USB */
59 OCTEON_FEATURE_USB, 59 OCTEON_FEATURE_USB,
60 /* Octeon IPD can run without using work queue entries */
61 OCTEON_FEATURE_NO_WPTR,
62 /* Octeon has DFA state machines */
63 OCTEON_FEATURE_DFA,
64 /* Octeon MDIO block supports clause 45 transactions for 10
65 * Gig support */
66 OCTEON_FEATURE_MDIO_CLAUSE_45,
60}; 67};
61 68
62static inline int cvmx_fuse_read(int fuse); 69static inline int cvmx_fuse_read(int fuse);
@@ -112,6 +119,26 @@ static inline int octeon_has_feature(enum octeon_feature feature)
112 case OCTEON_FEATURE_USB: 119 case OCTEON_FEATURE_USB:
113 return !(OCTEON_IS_MODEL(OCTEON_CN38XX) 120 return !(OCTEON_IS_MODEL(OCTEON_CN38XX)
114 || OCTEON_IS_MODEL(OCTEON_CN58XX)); 121 || OCTEON_IS_MODEL(OCTEON_CN58XX));
122 case OCTEON_FEATURE_NO_WPTR:
123 return (OCTEON_IS_MODEL(OCTEON_CN56XX)
124 || OCTEON_IS_MODEL(OCTEON_CN52XX))
125 && !OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X)
126 && !OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X);
127 case OCTEON_FEATURE_DFA:
128 if (!OCTEON_IS_MODEL(OCTEON_CN38XX)
129 && !OCTEON_IS_MODEL(OCTEON_CN31XX)
130 && !OCTEON_IS_MODEL(OCTEON_CN58XX))
131 return 0;
132 else if (OCTEON_IS_MODEL(OCTEON_CN3020))
133 return 0;
134 else if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS1))
135 return 1;
136 else
137 return !cvmx_fuse_read(120);
138 case OCTEON_FEATURE_MDIO_CLAUSE_45:
139 return !(OCTEON_IS_MODEL(OCTEON_CN3XXX)
140 || OCTEON_IS_MODEL(OCTEON_CN58XX)
141 || OCTEON_IS_MODEL(OCTEON_CN50XX));
115 } 142 }
116 return 0; 143 return 0;
117} 144}
diff --git a/arch/mips/include/asm/octeon/octeon.h b/arch/mips/include/asm/octeon/octeon.h
index edc676084cda..cac9b1a206fc 100644
--- a/arch/mips/include/asm/octeon/octeon.h
+++ b/arch/mips/include/asm/octeon/octeon.h
@@ -245,4 +245,6 @@ static inline uint32_t octeon_npi_read32(uint64_t address)
245 return cvmx_read64_uint32(address ^ 4); 245 return cvmx_read64_uint32(address ^ 4);
246} 246}
247 247
248extern struct cvmx_bootinfo *octeon_bootinfo;
249
248#endif /* __ASM_OCTEON_OCTEON_H */ 250#endif /* __ASM_OCTEON_OCTEON_H */
diff --git a/arch/mips/include/asm/page.h b/arch/mips/include/asm/page.h
index 72c80d2034c2..dc0eaa731281 100644
--- a/arch/mips/include/asm/page.h
+++ b/arch/mips/include/asm/page.h
@@ -32,6 +32,11 @@
32#define PAGE_SIZE (1UL << PAGE_SHIFT) 32#define PAGE_SIZE (1UL << PAGE_SHIFT)
33#define PAGE_MASK (~((1 << PAGE_SHIFT) - 1)) 33#define PAGE_MASK (~((1 << PAGE_SHIFT) - 1))
34 34
35#define HPAGE_SHIFT (PAGE_SHIFT + PAGE_SHIFT - 3)
36#define HPAGE_SIZE ((1UL) << HPAGE_SHIFT)
37#define HPAGE_MASK (~(HPAGE_SIZE - 1))
38#define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT)
39
35#ifndef __ASSEMBLY__ 40#ifndef __ASSEMBLY__
36 41
37#include <linux/pfn.h> 42#include <linux/pfn.h>
diff --git a/arch/mips/include/asm/pci.h b/arch/mips/include/asm/pci.h
index 053e4634acee..a68d111e55e9 100644
--- a/arch/mips/include/asm/pci.h
+++ b/arch/mips/include/asm/pci.h
@@ -142,19 +142,6 @@ extern void pcibios_resource_to_bus(struct pci_dev *dev,
142extern void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res, 142extern void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
143 struct pci_bus_region *region); 143 struct pci_bus_region *region);
144 144
145static inline struct resource *
146pcibios_select_root(struct pci_dev *pdev, struct resource *res)
147{
148 struct resource *root = NULL;
149
150 if (res->flags & IORESOURCE_IO)
151 root = &ioport_resource;
152 if (res->flags & IORESOURCE_MEM)
153 root = &iomem_resource;
154
155 return root;
156}
157
158#define pci_domain_nr(bus) ((struct pci_controller *)(bus)->sysdata)->index 145#define pci_domain_nr(bus) ((struct pci_controller *)(bus)->sysdata)->index
159 146
160static inline int pci_proc_domain(struct pci_bus *bus) 147static inline int pci_proc_domain(struct pci_bus *bus)
diff --git a/arch/mips/include/asm/pgtable-bits.h b/arch/mips/include/asm/pgtable-bits.h
index 51b34a48c84a..1073e6df8621 100644
--- a/arch/mips/include/asm/pgtable-bits.h
+++ b/arch/mips/include/asm/pgtable-bits.h
@@ -72,6 +72,7 @@
72#else 72#else
73 73
74#define _PAGE_R4KBUG (1<<5) /* workaround for r4k bug */ 74#define _PAGE_R4KBUG (1<<5) /* workaround for r4k bug */
75#define _PAGE_HUGE (1<<5) /* huge tlb page */
75#define _PAGE_GLOBAL (1<<6) 76#define _PAGE_GLOBAL (1<<6)
76#define _PAGE_VALID (1<<7) 77#define _PAGE_VALID (1<<7)
77#define _PAGE_SILENT_READ (1<<7) /* synonym */ 78#define _PAGE_SILENT_READ (1<<7) /* synonym */
diff --git a/arch/mips/include/asm/pgtable.h b/arch/mips/include/asm/pgtable.h
index 6a0edf72ffbc..1a9f9b257551 100644
--- a/arch/mips/include/asm/pgtable.h
+++ b/arch/mips/include/asm/pgtable.h
@@ -292,6 +292,16 @@ static inline pte_t pte_mkyoung(pte_t pte)
292 pte_val(pte) |= _PAGE_SILENT_READ; 292 pte_val(pte) |= _PAGE_SILENT_READ;
293 return pte; 293 return pte;
294} 294}
295
296#ifdef _PAGE_HUGE
297static inline int pte_huge(pte_t pte) { return pte_val(pte) & _PAGE_HUGE; }
298
299static inline pte_t pte_mkhuge(pte_t pte)
300{
301 pte_val(pte) |= _PAGE_HUGE;
302 return pte;
303}
304#endif /* _PAGE_HUGE */
295#endif 305#endif
296static inline int pte_special(pte_t pte) { return 0; } 306static inline int pte_special(pte_t pte) { return 0; }
297static inline pte_t pte_mkspecial(pte_t pte) { return pte; } 307static inline pte_t pte_mkspecial(pte_t pte) { return pte; }
diff --git a/arch/mips/include/asm/r4kcache.h b/arch/mips/include/asm/r4kcache.h
index 4c140db36786..387bf59f1e37 100644
--- a/arch/mips/include/asm/r4kcache.h
+++ b/arch/mips/include/asm/r4kcache.h
@@ -399,6 +399,7 @@ __BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16)
399__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32) 399__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32)
400__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32) 400__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32)
401__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32) 401__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32)
402__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 64)
402__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64) 403__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64)
403__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64) 404__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64)
404__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128) 405__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128)
diff --git a/arch/mips/include/asm/suspend.h b/arch/mips/include/asm/suspend.h
new file mode 100644
index 000000000000..294cdb66c5fc
--- /dev/null
+++ b/arch/mips/include/asm/suspend.h
@@ -0,0 +1,9 @@
1#ifndef __ASM_SUSPEND_H
2#define __ASM_SUSPEND_H
3
4static inline int arch_prepare_suspend(void) { return 0; }
5
6/* References to section boundaries */
7extern const void __nosave_begin, __nosave_end;
8
9#endif /* __ASM_SUSPEND_H */
diff --git a/arch/mips/include/asm/txx9/dmac.h b/arch/mips/include/asm/txx9/dmac.h
new file mode 100644
index 000000000000..5e9151fccbb4
--- /dev/null
+++ b/arch/mips/include/asm/txx9/dmac.h
@@ -0,0 +1,51 @@
1/*
2 * TXx9 SoC DMA Controller
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#ifndef __ASM_TXX9_DMAC_H
10#define __ASM_TXX9_DMAC_H
11
12#include <linux/dmaengine.h>
13
14#define TXX9_DMA_MAX_NR_CHANNELS 4
15
16/**
17 * struct txx9dmac_platform_data - Controller configuration parameters
18 * @memcpy_chan: Channel used for DMA_MEMCPY
19 * @have_64bit_regs: DMAC have 64 bit registers
20 */
21struct txx9dmac_platform_data {
22 int memcpy_chan;
23 bool have_64bit_regs;
24};
25
26/**
27 * struct txx9dmac_chan_platform_data - Channel configuration parameters
28 * @dmac_dev: A platform device for DMAC
29 */
30struct txx9dmac_chan_platform_data {
31 struct platform_device *dmac_dev;
32};
33
34/**
35 * struct txx9dmac_slave - Controller-specific information about a slave
36 * @tx_reg: physical address of data register used for
37 * memory-to-peripheral transfers
38 * @rx_reg: physical address of data register used for
39 * peripheral-to-memory transfers
40 * @reg_width: peripheral register width
41 */
42struct txx9dmac_slave {
43 u64 tx_reg;
44 u64 rx_reg;
45 unsigned int reg_width;
46};
47
48void txx9_dmac_init(int id, unsigned long baseaddr, int irq,
49 const struct txx9dmac_platform_data *pdata);
50
51#endif /* __ASM_TXX9_DMAC_H */
diff --git a/arch/mips/include/asm/txx9/generic.h b/arch/mips/include/asm/txx9/generic.h
index 9cde0090cbf6..827dc22be2ea 100644
--- a/arch/mips/include/asm/txx9/generic.h
+++ b/arch/mips/include/asm/txx9/generic.h
@@ -91,4 +91,10 @@ void txx9_7segled_init(unsigned int num,
91 void (*putc)(unsigned int pos, unsigned char val)); 91 void (*putc)(unsigned int pos, unsigned char val));
92int txx9_7segled_putc(unsigned int pos, char c); 92int txx9_7segled_putc(unsigned int pos, char c);
93 93
94void __init txx9_aclc_init(unsigned long baseaddr, int irq,
95 unsigned int dmac_id,
96 unsigned int dma_chan_out,
97 unsigned int dma_chan_in);
98void __init txx9_sramc_init(struct resource *r);
99
94#endif /* __ASM_TXX9_GENERIC_H */ 100#endif /* __ASM_TXX9_GENERIC_H */
diff --git a/arch/mips/include/asm/txx9/tx4927.h b/arch/mips/include/asm/txx9/tx4927.h
index 7d813f1cb98d..18c98c52afdb 100644
--- a/arch/mips/include/asm/txx9/tx4927.h
+++ b/arch/mips/include/asm/txx9/tx4927.h
@@ -41,6 +41,7 @@
41 41
42#define TX4927_SDRAMC_REG (TX4927_REG_BASE + 0x8000) 42#define TX4927_SDRAMC_REG (TX4927_REG_BASE + 0x8000)
43#define TX4927_EBUSC_REG (TX4927_REG_BASE + 0x9000) 43#define TX4927_EBUSC_REG (TX4927_REG_BASE + 0x9000)
44#define TX4927_DMA_REG (TX4927_REG_BASE + 0xb000)
44#define TX4927_PCIC_REG (TX4927_REG_BASE + 0xd000) 45#define TX4927_PCIC_REG (TX4927_REG_BASE + 0xd000)
45#define TX4927_CCFG_REG (TX4927_REG_BASE + 0xe000) 46#define TX4927_CCFG_REG (TX4927_REG_BASE + 0xe000)
46#define TX4927_IRC_REG (TX4927_REG_BASE + 0xf600) 47#define TX4927_IRC_REG (TX4927_REG_BASE + 0xf600)
@@ -49,6 +50,7 @@
49#define TX4927_NR_SIO 2 50#define TX4927_NR_SIO 2
50#define TX4927_SIO_REG(ch) (TX4927_REG_BASE + 0xf300 + (ch) * 0x100) 51#define TX4927_SIO_REG(ch) (TX4927_REG_BASE + 0xf300 + (ch) * 0x100)
51#define TX4927_PIO_REG (TX4927_REG_BASE + 0xf500) 52#define TX4927_PIO_REG (TX4927_REG_BASE + 0xf500)
53#define TX4927_ACLC_REG (TX4927_REG_BASE + 0xf700)
52 54
53#define TX4927_IR_ECCERR 0 55#define TX4927_IR_ECCERR 0
54#define TX4927_IR_WTOERR 1 56#define TX4927_IR_WTOERR 1
@@ -265,5 +267,7 @@ int tx4927_pciclk66_setup(void);
265void tx4927_setup_pcierr_irq(void); 267void tx4927_setup_pcierr_irq(void);
266void tx4927_irq_init(void); 268void tx4927_irq_init(void);
267void tx4927_mtd_init(int ch); 269void tx4927_mtd_init(int ch);
270void tx4927_dmac_init(int memcpy_chan);
271void tx4927_aclc_init(unsigned int dma_chan_out, unsigned int dma_chan_in);
268 272
269#endif /* __ASM_TXX9_TX4927_H */ 273#endif /* __ASM_TXX9_TX4927_H */
diff --git a/arch/mips/include/asm/txx9/tx4938.h b/arch/mips/include/asm/txx9/tx4938.h
index cd8bc2021755..8a178f186f7d 100644
--- a/arch/mips/include/asm/txx9/tx4938.h
+++ b/arch/mips/include/asm/txx9/tx4938.h
@@ -305,5 +305,8 @@ struct tx4938ide_platform_info {
305}; 305};
306 306
307void tx4938_ata_init(unsigned int irq, unsigned int shift, int tune); 307void tx4938_ata_init(unsigned int irq, unsigned int shift, int tune);
308void tx4938_dmac_init(int memcpy_chan0, int memcpy_chan1);
309void tx4938_aclc_init(void);
310void tx4938_sramc_init(void);
308 311
309#endif 312#endif
diff --git a/arch/mips/include/asm/txx9/tx4939.h b/arch/mips/include/asm/txx9/tx4939.h
index f02c50b3abfb..d4f342cd5939 100644
--- a/arch/mips/include/asm/txx9/tx4939.h
+++ b/arch/mips/include/asm/txx9/tx4939.h
@@ -45,6 +45,8 @@
45#define TX4939_RTC_REG (TX4939_REG_BASE + 0xfb00) 45#define TX4939_RTC_REG (TX4939_REG_BASE + 0xfb00)
46#define TX4939_CIR_REG (TX4939_REG_BASE + 0xfc00) 46#define TX4939_CIR_REG (TX4939_REG_BASE + 0xfc00)
47 47
48#define TX4939_RNG_REG (TX4939_CRYPTO_REG + 0xb0)
49
48struct tx4939_le_reg { 50struct tx4939_le_reg {
49 __u32 r; 51 __u32 r;
50 __u32 unused; 52 __u32 unused;
@@ -544,5 +546,9 @@ void tx4939_ata_init(void);
544void tx4939_rtc_init(void); 546void tx4939_rtc_init(void);
545void tx4939_ndfmc_init(unsigned int hold, unsigned int spw, 547void tx4939_ndfmc_init(unsigned int hold, unsigned int spw,
546 unsigned char ch_mask, unsigned char wide_mask); 548 unsigned char ch_mask, unsigned char wide_mask);
549void tx4939_dmac_init(int memcpy_chan0, int memcpy_chan1);
550void tx4939_aclc_init(void);
551void tx4939_sramc_init(void);
552void tx4939_rng_init(void);
547 553
548#endif /* __ASM_TXX9_TX4939_H */ 554#endif /* __ASM_TXX9_TX4939_H */
generated by cgit v1.2.2 (git 2.25.0) at 2026-01-07 19:27:27 -0500