diff options
Diffstat (limited to 'arch/mips/include/asm/war.h')
| -rw-r--r-- | arch/mips/include/asm/war.h | 46 |
1 files changed, 23 insertions, 23 deletions
diff --git a/arch/mips/include/asm/war.h b/arch/mips/include/asm/war.h index 65e344532ded..9344e247a6c8 100644 --- a/arch/mips/include/asm/war.h +++ b/arch/mips/include/asm/war.h | |||
| @@ -83,30 +83,30 @@ | |||
| 83 | #endif | 83 | #endif |
| 84 | 84 | ||
| 85 | /* | 85 | /* |
| 86 | * Pleasures of the R4600 V1.x. Cite from the IDT R4600 V1.7 errata: | 86 | * Pleasures of the R4600 V1.x. Cite from the IDT R4600 V1.7 errata: |
| 87 | * | 87 | * |
| 88 | * 18. The CACHE instructions Hit_Writeback_Invalidate_D, Hit_Writeback_D, | 88 | * 18. The CACHE instructions Hit_Writeback_Invalidate_D, Hit_Writeback_D, |
| 89 | * Hit_Invalidate_D and Create_Dirty_Excl_D should only be | 89 | * Hit_Invalidate_D and Create_Dirty_Excl_D should only be |
| 90 | * executed if there is no other dcache activity. If the dcache is | 90 | * executed if there is no other dcache activity. If the dcache is |
| 91 | * accessed for another instruction immeidately preceding when these | 91 | * accessed for another instruction immeidately preceding when these |
| 92 | * cache instructions are executing, it is possible that the dcache | 92 | * cache instructions are executing, it is possible that the dcache |
| 93 | * tag match outputs used by these cache instructions will be | 93 | * tag match outputs used by these cache instructions will be |
| 94 | * incorrect. These cache instructions should be preceded by at least | 94 | * incorrect. These cache instructions should be preceded by at least |
| 95 | * four instructions that are not any kind of load or store | 95 | * four instructions that are not any kind of load or store |
| 96 | * instruction. | 96 | * instruction. |
| 97 | * | 97 | * |
| 98 | * This is not allowed: lw | 98 | * This is not allowed: lw |
| 99 | * nop | 99 | * nop |
| 100 | * nop | 100 | * nop |
| 101 | * nop | 101 | * nop |
| 102 | * cache Hit_Writeback_Invalidate_D | 102 | * cache Hit_Writeback_Invalidate_D |
| 103 | * | 103 | * |
| 104 | * This is allowed: lw | 104 | * This is allowed: lw |
| 105 | * nop | 105 | * nop |
| 106 | * nop | 106 | * nop |
| 107 | * nop | 107 | * nop |
| 108 | * nop | 108 | * nop |
| 109 | * cache Hit_Writeback_Invalidate_D | 109 | * cache Hit_Writeback_Invalidate_D |
| 110 | */ | 110 | */ |
| 111 | #ifndef R4600_V1_HIT_CACHEOP_WAR | 111 | #ifndef R4600_V1_HIT_CACHEOP_WAR |
| 112 | #error Check setting of R4600_V1_HIT_CACHEOP_WAR for your platform | 112 | #error Check setting of R4600_V1_HIT_CACHEOP_WAR for your platform |
| @@ -118,7 +118,7 @@ | |||
| 118 | * | 118 | * |
| 119 | * R4600 v2.0 bug: "The CACHE instructions Hit_Writeback_Inv_D, | 119 | * R4600 v2.0 bug: "The CACHE instructions Hit_Writeback_Inv_D, |
| 120 | * Hit_Writeback_D, Hit_Invalidate_D and Create_Dirty_Exclusive_D will only | 120 | * Hit_Writeback_D, Hit_Invalidate_D and Create_Dirty_Exclusive_D will only |
| 121 | * operate correctly if the internal data cache refill buffer is empty. These | 121 | * operate correctly if the internal data cache refill buffer is empty. These |
| 122 | * CACHE instructions should be separated from any potential data cache miss | 122 | * CACHE instructions should be separated from any potential data cache miss |
| 123 | * by a load instruction to an uncached address to empty the response buffer." | 123 | * by a load instruction to an uncached address to empty the response buffer." |
| 124 | * (Revision 2.0 device errata from IDT available on http://www.idt.com/ | 124 | * (Revision 2.0 device errata from IDT available on http://www.idt.com/ |