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-rw-r--r--arch/mips/include/asm/txx9/boards.h13
-rw-r--r--arch/mips/include/asm/txx9/generic.h89
-rw-r--r--arch/mips/include/asm/txx9/jmr3927.h180
-rw-r--r--arch/mips/include/asm/txx9/pci.h39
-rw-r--r--arch/mips/include/asm/txx9/rbtx4927.h92
-rw-r--r--arch/mips/include/asm/txx9/rbtx4938.h145
-rw-r--r--arch/mips/include/asm/txx9/rbtx4939.h133
-rw-r--r--arch/mips/include/asm/txx9/smsc_fdc37m81x.h68
-rw-r--r--arch/mips/include/asm/txx9/spi.h34
-rw-r--r--arch/mips/include/asm/txx9/tx3927.h341
-rw-r--r--arch/mips/include/asm/txx9/tx4927.h269
-rw-r--r--arch/mips/include/asm/txx9/tx4927pcic.h203
-rw-r--r--arch/mips/include/asm/txx9/tx4938.h295
-rw-r--r--arch/mips/include/asm/txx9/tx4939.h545
14 files changed, 2446 insertions, 0 deletions
diff --git a/arch/mips/include/asm/txx9/boards.h b/arch/mips/include/asm/txx9/boards.h
new file mode 100644
index 000000000000..cbe9476d963e
--- /dev/null
+++ b/arch/mips/include/asm/txx9/boards.h
@@ -0,0 +1,13 @@
1#ifdef CONFIG_TOSHIBA_JMR3927
2BOARD_VEC(jmr3927_vec)
3#endif
4#ifdef CONFIG_TOSHIBA_RBTX4927
5BOARD_VEC(rbtx4927_vec)
6BOARD_VEC(rbtx4937_vec)
7#endif
8#ifdef CONFIG_TOSHIBA_RBTX4938
9BOARD_VEC(rbtx4938_vec)
10#endif
11#ifdef CONFIG_TOSHIBA_RBTX4939
12BOARD_VEC(rbtx4939_vec)
13#endif
diff --git a/arch/mips/include/asm/txx9/generic.h b/arch/mips/include/asm/txx9/generic.h
new file mode 100644
index 000000000000..4316a3e57678
--- /dev/null
+++ b/arch/mips/include/asm/txx9/generic.h
@@ -0,0 +1,89 @@
1/*
2 * linux/include/asm-mips/txx9/generic.h
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 */
8#ifndef __ASM_TXX9_GENERIC_H
9#define __ASM_TXX9_GENERIC_H
10
11#include <linux/init.h>
12#include <linux/ioport.h> /* for struct resource */
13
14extern struct resource txx9_ce_res[];
15#define TXX9_CE(n) (unsigned long)(txx9_ce_res[(n)].start)
16extern unsigned int txx9_pcode;
17extern char txx9_pcode_str[8];
18void txx9_reg_res_init(unsigned int pcode, unsigned long base,
19 unsigned long size);
20
21extern unsigned int txx9_master_clock;
22extern unsigned int txx9_cpu_clock;
23extern unsigned int txx9_gbus_clock;
24#define TXX9_IMCLK (txx9_gbus_clock / 2)
25
26extern int txx9_ccfg_toeon;
27struct uart_port;
28int early_serial_txx9_setup(struct uart_port *port);
29
30struct pci_dev;
31struct txx9_board_vec {
32 const char *system;
33 void (*prom_init)(void);
34 void (*mem_setup)(void);
35 void (*irq_setup)(void);
36 void (*time_init)(void);
37 void (*arch_init)(void);
38 void (*device_init)(void);
39#ifdef CONFIG_PCI
40 int (*pci_map_irq)(const struct pci_dev *dev, u8 slot, u8 pin);
41#endif
42};
43extern struct txx9_board_vec *txx9_board_vec;
44extern int (*txx9_irq_dispatch)(int pending);
45char *prom_getcmdline(void);
46const char *prom_getenv(const char *name);
47void txx9_wdt_init(unsigned long base);
48void txx9_wdt_now(unsigned long base);
49void txx9_spi_init(int busid, unsigned long base, int irq);
50void txx9_ethaddr_init(unsigned int id, unsigned char *ethaddr);
51void txx9_sio_init(unsigned long baseaddr, int irq,
52 unsigned int line, unsigned int sclk, int nocts);
53void prom_putchar(char c);
54#ifdef CONFIG_EARLY_PRINTK
55extern void (*txx9_prom_putchar)(char c);
56void txx9_sio_putchar_init(unsigned long baseaddr);
57#else
58static inline void txx9_sio_putchar_init(unsigned long baseaddr)
59{
60}
61#endif
62
63struct physmap_flash_data;
64void txx9_physmap_flash_init(int no, unsigned long addr, unsigned long size,
65 const struct physmap_flash_data *pdata);
66
67/* 8 bit version of __fls(): find first bit set (returns 0..7) */
68static inline unsigned int __fls8(unsigned char x)
69{
70 int r = 7;
71
72 if (!(x & 0xf0)) {
73 r -= 4;
74 x <<= 4;
75 }
76 if (!(x & 0xc0)) {
77 r -= 2;
78 x <<= 2;
79 }
80 if (!(x & 0x80))
81 r -= 1;
82 return r;
83}
84
85void txx9_iocled_init(unsigned long baseaddr,
86 int basenum, unsigned int num, int lowactive,
87 const char *color, char **deftriggers);
88
89#endif /* __ASM_TXX9_GENERIC_H */
diff --git a/arch/mips/include/asm/txx9/jmr3927.h b/arch/mips/include/asm/txx9/jmr3927.h
new file mode 100644
index 000000000000..a409c446bf18
--- /dev/null
+++ b/arch/mips/include/asm/txx9/jmr3927.h
@@ -0,0 +1,180 @@
1/*
2 * Defines for the TJSYS JMR-TX3927
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 2000-2001 Toshiba Corporation
9 */
10#ifndef __ASM_TXX9_JMR3927_H
11#define __ASM_TXX9_JMR3927_H
12
13#include <asm/txx9/tx3927.h>
14#include <asm/addrspace.h>
15#include <asm/system.h>
16#include <asm/txx9irq.h>
17
18/* CS */
19#define JMR3927_ROMCE0 0x1fc00000 /* 4M */
20#define JMR3927_ROMCE1 0x1e000000 /* 4M */
21#define JMR3927_ROMCE2 0x14000000 /* 16M */
22#define JMR3927_ROMCE3 0x10000000 /* 64M */
23#define JMR3927_ROMCE5 0x1d000000 /* 4M */
24#define JMR3927_SDCS0 0x00000000 /* 32M */
25#define JMR3927_SDCS1 0x02000000 /* 32M */
26/* PCI Direct Mappings */
27
28#define JMR3927_PCIMEM 0x08000000
29#define JMR3927_PCIMEM_SIZE 0x08000000 /* 128M */
30#define JMR3927_PCIIO 0x15000000
31#define JMR3927_PCIIO_SIZE 0x01000000 /* 16M */
32
33#define JMR3927_SDRAM_SIZE 0x02000000 /* 32M */
34#define JMR3927_PORT_BASE KSEG1
35
36/* Address map (virtual address) */
37#define JMR3927_ROM0_BASE (KSEG1 + JMR3927_ROMCE0)
38#define JMR3927_ROM1_BASE (KSEG1 + JMR3927_ROMCE1)
39#define JMR3927_IOC_BASE (KSEG1 + JMR3927_ROMCE2)
40#define JMR3927_PCIMEM_BASE (KSEG1 + JMR3927_PCIMEM)
41#define JMR3927_PCIIO_BASE (KSEG1 + JMR3927_PCIIO)
42
43#define JMR3927_IOC_REV_ADDR (JMR3927_IOC_BASE + 0x00000000)
44#define JMR3927_IOC_NVRAMB_ADDR (JMR3927_IOC_BASE + 0x00010000)
45#define JMR3927_IOC_LED_ADDR (JMR3927_IOC_BASE + 0x00020000)
46#define JMR3927_IOC_DIPSW_ADDR (JMR3927_IOC_BASE + 0x00030000)
47#define JMR3927_IOC_BREV_ADDR (JMR3927_IOC_BASE + 0x00040000)
48#define JMR3927_IOC_DTR_ADDR (JMR3927_IOC_BASE + 0x00050000)
49#define JMR3927_IOC_INTS1_ADDR (JMR3927_IOC_BASE + 0x00080000)
50#define JMR3927_IOC_INTS2_ADDR (JMR3927_IOC_BASE + 0x00090000)
51#define JMR3927_IOC_INTM_ADDR (JMR3927_IOC_BASE + 0x000a0000)
52#define JMR3927_IOC_INTP_ADDR (JMR3927_IOC_BASE + 0x000b0000)
53#define JMR3927_IOC_RESET_ADDR (JMR3927_IOC_BASE + 0x000f0000)
54
55/* Flash ROM */
56#define JMR3927_FLASH_BASE (JMR3927_ROM0_BASE)
57#define JMR3927_FLASH_SIZE 0x00400000
58
59/* bits for IOC_REV/IOC_BREV (high byte) */
60#define JMR3927_IDT_MASK 0xfc
61#define JMR3927_REV_MASK 0x03
62#define JMR3927_IOC_IDT 0xe0
63
64/* bits for IOC_INTS1/IOC_INTS2/IOC_INTM/IOC_INTP (high byte) */
65#define JMR3927_IOC_INTB_PCIA 0
66#define JMR3927_IOC_INTB_PCIB 1
67#define JMR3927_IOC_INTB_PCIC 2
68#define JMR3927_IOC_INTB_PCID 3
69#define JMR3927_IOC_INTB_MODEM 4
70#define JMR3927_IOC_INTB_INT6 5
71#define JMR3927_IOC_INTB_INT7 6
72#define JMR3927_IOC_INTB_SOFT 7
73#define JMR3927_IOC_INTF_PCIA (1 << JMR3927_IOC_INTF_PCIA)
74#define JMR3927_IOC_INTF_PCIB (1 << JMR3927_IOC_INTB_PCIB)
75#define JMR3927_IOC_INTF_PCIC (1 << JMR3927_IOC_INTB_PCIC)
76#define JMR3927_IOC_INTF_PCID (1 << JMR3927_IOC_INTB_PCID)
77#define JMR3927_IOC_INTF_MODEM (1 << JMR3927_IOC_INTB_MODEM)
78#define JMR3927_IOC_INTF_INT6 (1 << JMR3927_IOC_INTB_INT6)
79#define JMR3927_IOC_INTF_INT7 (1 << JMR3927_IOC_INTB_INT7)
80#define JMR3927_IOC_INTF_SOFT (1 << JMR3927_IOC_INTB_SOFT)
81
82/* bits for IOC_RESET (high byte) */
83#define JMR3927_IOC_RESET_CPU 1
84#define JMR3927_IOC_RESET_PCI 2
85
86#if defined(__BIG_ENDIAN)
87#define jmr3927_ioc_reg_out(d, a) ((*(volatile unsigned char *)(a)) = (d))
88#define jmr3927_ioc_reg_in(a) (*(volatile unsigned char *)(a))
89#elif defined(__LITTLE_ENDIAN)
90#define jmr3927_ioc_reg_out(d, a) ((*(volatile unsigned char *)((a)^1)) = (d))
91#define jmr3927_ioc_reg_in(a) (*(volatile unsigned char *)((a)^1))
92#else
93#error "No Endian"
94#endif
95
96/* LED macro */
97#define jmr3927_led_set(n/*0-16*/) jmr3927_ioc_reg_out(~(n), JMR3927_IOC_LED_ADDR)
98
99#define jmr3927_led_and_set(n/*0-16*/) jmr3927_ioc_reg_out((~(n)) & jmr3927_ioc_reg_in(JMR3927_IOC_LED_ADDR), JMR3927_IOC_LED_ADDR)
100
101/* DIPSW4 macro */
102#define jmr3927_dipsw1() (gpio_get_value(11) == 0)
103#define jmr3927_dipsw2() (gpio_get_value(10) == 0)
104#define jmr3927_dipsw3() ((jmr3927_ioc_reg_in(JMR3927_IOC_DIPSW_ADDR) & 2) == 0)
105#define jmr3927_dipsw4() ((jmr3927_ioc_reg_in(JMR3927_IOC_DIPSW_ADDR) & 1) == 0)
106
107/*
108 * IRQ mappings
109 */
110
111/* These are the virtual IRQ numbers, we divide all IRQ's into
112 * 'spaces', the 'space' determines where and how to enable/disable
113 * that particular IRQ on an JMR machine. Add new 'spaces' as new
114 * IRQ hardware is supported.
115 */
116#define JMR3927_NR_IRQ_IRC 16 /* On-Chip IRC */
117#define JMR3927_NR_IRQ_IOC 8 /* PCI/MODEM/INT[6:7] */
118
119#define JMR3927_IRQ_IRC TXX9_IRQ_BASE
120#define JMR3927_IRQ_IOC (JMR3927_IRQ_IRC + JMR3927_NR_IRQ_IRC)
121#define JMR3927_IRQ_END (JMR3927_IRQ_IOC + JMR3927_NR_IRQ_IOC)
122
123#define JMR3927_IRQ_IRC_INT0 (JMR3927_IRQ_IRC + TX3927_IR_INT0)
124#define JMR3927_IRQ_IRC_INT1 (JMR3927_IRQ_IRC + TX3927_IR_INT1)
125#define JMR3927_IRQ_IRC_INT2 (JMR3927_IRQ_IRC + TX3927_IR_INT2)
126#define JMR3927_IRQ_IRC_INT3 (JMR3927_IRQ_IRC + TX3927_IR_INT3)
127#define JMR3927_IRQ_IRC_INT4 (JMR3927_IRQ_IRC + TX3927_IR_INT4)
128#define JMR3927_IRQ_IRC_INT5 (JMR3927_IRQ_IRC + TX3927_IR_INT5)
129#define JMR3927_IRQ_IRC_SIO0 (JMR3927_IRQ_IRC + TX3927_IR_SIO0)
130#define JMR3927_IRQ_IRC_SIO1 (JMR3927_IRQ_IRC + TX3927_IR_SIO1)
131#define JMR3927_IRQ_IRC_SIO(ch) (JMR3927_IRQ_IRC + TX3927_IR_SIO(ch))
132#define JMR3927_IRQ_IRC_DMA (JMR3927_IRQ_IRC + TX3927_IR_DMA)
133#define JMR3927_IRQ_IRC_PIO (JMR3927_IRQ_IRC + TX3927_IR_PIO)
134#define JMR3927_IRQ_IRC_PCI (JMR3927_IRQ_IRC + TX3927_IR_PCI)
135#define JMR3927_IRQ_IRC_TMR(ch) (JMR3927_IRQ_IRC + TX3927_IR_TMR(ch))
136#define JMR3927_IRQ_IOC_PCIA (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCIA)
137#define JMR3927_IRQ_IOC_PCIB (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCIB)
138#define JMR3927_IRQ_IOC_PCIC (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCIC)
139#define JMR3927_IRQ_IOC_PCID (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCID)
140#define JMR3927_IRQ_IOC_MODEM (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_MODEM)
141#define JMR3927_IRQ_IOC_INT6 (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_INT6)
142#define JMR3927_IRQ_IOC_INT7 (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_INT7)
143#define JMR3927_IRQ_IOC_SOFT (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_SOFT)
144
145/* IOC (PCI, MODEM) */
146#define JMR3927_IRQ_IOCINT JMR3927_IRQ_IRC_INT1
147/* TC35815 100M Ether (JMR-TX3912:JPW4:2-3 Short) */
148#define JMR3927_IRQ_ETHER0 JMR3927_IRQ_IRC_INT3
149
150/* Clocks */
151#define JMR3927_CORECLK 132710400 /* 132.7MHz */
152
153/*
154 * TX3927 Pin Configuration:
155 *
156 * PCFG bits Avail Dead
157 * SELSIO[1:0]:11 RXD[1:0], TXD[1:0] PIO[6:3]
158 * SELSIOC[0]:1 CTS[0], RTS[0] INT[5:4]
159 * SELSIOC[1]:0,SELDSF:0, GSDAO[0],GPCST[3] CTS[1], RTS[1],DSF,
160 * GDBGE* PIO[2:1]
161 * SELDMA[2]:1 DMAREQ[2],DMAACK[2] PIO[13:12]
162 * SELTMR[2:0]:000 TIMER[1:0]
163 * SELCS:0,SELDMA[1]:0 PIO[11;10] SDCS_CE[7:6],
164 * DMAREQ[1],DMAACK[1]
165 * SELDMA[0]:1 DMAREQ[0],DMAACK[0] PIO[9:8]
166 * SELDMA[3]:1 DMAREQ[3],DMAACK[3] PIO[15:14]
167 * SELDONE:1 DMADONE PIO[7]
168 *
169 * Usable pins are:
170 * RXD[1;0],TXD[1:0],CTS[0],RTS[0],
171 * DMAREQ[0,2,3],DMAACK[0,2,3],DMADONE,PIO[0,10,11]
172 * INT[3:0]
173 */
174
175void jmr3927_prom_init(void);
176void jmr3927_irq_setup(void);
177struct pci_dev;
178int jmr3927_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
179
180#endif /* __ASM_TXX9_JMR3927_H */
diff --git a/arch/mips/include/asm/txx9/pci.h b/arch/mips/include/asm/txx9/pci.h
new file mode 100644
index 000000000000..3d32529060aa
--- /dev/null
+++ b/arch/mips/include/asm/txx9/pci.h
@@ -0,0 +1,39 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 */
6#ifndef __ASM_TXX9_PCI_H
7#define __ASM_TXX9_PCI_H
8
9#include <linux/pci.h>
10
11extern struct pci_controller txx9_primary_pcic;
12struct pci_controller *
13txx9_alloc_pci_controller(struct pci_controller *pcic,
14 unsigned long mem_base, unsigned long mem_size,
15 unsigned long io_base, unsigned long io_size);
16
17int txx9_pci66_check(struct pci_controller *hose, int top_bus,
18 int current_bus);
19extern int txx9_pci_mem_high __initdata;
20
21extern int txx9_pci_option;
22#define TXX9_PCI_OPT_PICMG 0x0002
23#define TXX9_PCI_OPT_CLK_33 0x0008
24#define TXX9_PCI_OPT_CLK_66 0x0010
25#define TXX9_PCI_OPT_CLK_MASK \
26 (TXX9_PCI_OPT_CLK_33 | TXX9_PCI_OPT_CLK_66)
27#define TXX9_PCI_OPT_CLK_AUTO TXX9_PCI_OPT_CLK_MASK
28
29enum txx9_pci_err_action {
30 TXX9_PCI_ERR_REPORT,
31 TXX9_PCI_ERR_IGNORE,
32 TXX9_PCI_ERR_PANIC,
33};
34extern enum txx9_pci_err_action txx9_pci_err_action;
35
36extern char * (*txx9_board_pcibios_setup)(char *str);
37char *txx9_pcibios_setup(char *str);
38
39#endif /* __ASM_TXX9_PCI_H */
diff --git a/arch/mips/include/asm/txx9/rbtx4927.h b/arch/mips/include/asm/txx9/rbtx4927.h
new file mode 100644
index 000000000000..b2adab3d1acc
--- /dev/null
+++ b/arch/mips/include/asm/txx9/rbtx4927.h
@@ -0,0 +1,92 @@
1/*
2 * Author: MontaVista Software, Inc.
3 * source@mvista.com
4 *
5 * Copyright 2001-2002 MontaVista Software Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
13 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
15 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
16 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
17 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
18 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
19 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
20 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
21 * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
22 *
23 * You should have received a copy of the GNU General Public License along
24 * with this program; if not, write to the Free Software Foundation, Inc.,
25 * 675 Mass Ave, Cambridge, MA 02139, USA.
26 */
27#ifndef __ASM_TXX9_RBTX4927_H
28#define __ASM_TXX9_RBTX4927_H
29
30#include <asm/txx9/tx4927.h>
31
32#define RBTX4927_PCIMEM 0x08000000
33#define RBTX4927_PCIMEM_SIZE 0x08000000
34#define RBTX4927_PCIIO 0x16000000
35#define RBTX4927_PCIIO_SIZE 0x01000000
36
37#define RBTX4927_LED_ADDR (IO_BASE + TXX9_CE(2) + 0x00001000)
38#define RBTX4927_IMASK_ADDR (IO_BASE + TXX9_CE(2) + 0x00002000)
39#define RBTX4927_IMSTAT_ADDR (IO_BASE + TXX9_CE(2) + 0x00002006)
40#define RBTX4927_SOFTINT_ADDR (IO_BASE + TXX9_CE(2) + 0x00003000)
41#define RBTX4927_SOFTRESET_ADDR (IO_BASE + TXX9_CE(2) + 0x0000f000)
42#define RBTX4927_SOFTRESETLOCK_ADDR (IO_BASE + TXX9_CE(2) + 0x0000f002)
43#define RBTX4927_PCIRESET_ADDR (IO_BASE + TXX9_CE(2) + 0x0000f006)
44#define RBTX4927_BRAMRTC_BASE (IO_BASE + TXX9_CE(2) + 0x00010000)
45#define RBTX4927_ETHER_BASE (IO_BASE + TXX9_CE(2) + 0x00020000)
46
47/* Ethernet port address */
48#define RBTX4927_ETHER_ADDR (RBTX4927_ETHER_BASE + 0x280)
49
50#define rbtx4927_imask_addr ((__u8 __iomem *)RBTX4927_IMASK_ADDR)
51#define rbtx4927_imstat_addr ((__u8 __iomem *)RBTX4927_IMSTAT_ADDR)
52#define rbtx4927_softint_addr ((__u8 __iomem *)RBTX4927_SOFTINT_ADDR)
53#define rbtx4927_softreset_addr ((__u8 __iomem *)RBTX4927_SOFTRESET_ADDR)
54#define rbtx4927_softresetlock_addr \
55 ((__u8 __iomem *)RBTX4927_SOFTRESETLOCK_ADDR)
56#define rbtx4927_pcireset_addr ((__u8 __iomem *)RBTX4927_PCIRESET_ADDR)
57
58/* bits for ISTAT/IMASK/IMSTAT */
59#define RBTX4927_INTB_PCID 0
60#define RBTX4927_INTB_PCIC 1
61#define RBTX4927_INTB_PCIB 2
62#define RBTX4927_INTB_PCIA 3
63#define RBTX4927_INTF_PCID (1 << RBTX4927_INTB_PCID)
64#define RBTX4927_INTF_PCIC (1 << RBTX4927_INTB_PCIC)
65#define RBTX4927_INTF_PCIB (1 << RBTX4927_INTB_PCIB)
66#define RBTX4927_INTF_PCIA (1 << RBTX4927_INTB_PCIA)
67
68#define RBTX4927_NR_IRQ_IOC 8 /* IOC */
69
70#define RBTX4927_IRQ_IOC (TXX9_IRQ_BASE + TX4927_NUM_IR)
71#define RBTX4927_IRQ_IOC_PCID (RBTX4927_IRQ_IOC + RBTX4927_INTB_PCID)
72#define RBTX4927_IRQ_IOC_PCIC (RBTX4927_IRQ_IOC + RBTX4927_INTB_PCIC)
73#define RBTX4927_IRQ_IOC_PCIB (RBTX4927_IRQ_IOC + RBTX4927_INTB_PCIB)
74#define RBTX4927_IRQ_IOC_PCIA (RBTX4927_IRQ_IOC + RBTX4927_INTB_PCIA)
75
76#define RBTX4927_IRQ_IOCINT (TXX9_IRQ_BASE + TX4927_IR_INT(1))
77
78#ifdef CONFIG_PCI
79#define RBTX4927_ISA_IO_OFFSET RBTX4927_PCIIO
80#else
81#define RBTX4927_ISA_IO_OFFSET 0
82#endif
83
84#define RBTX4927_RTL_8019_BASE (RBTX4927_ETHER_ADDR - mips_io_port_base)
85#define RBTX4927_RTL_8019_IRQ (TXX9_IRQ_BASE + TX4927_IR_INT(3))
86
87void rbtx4927_prom_init(void);
88void rbtx4927_irq_setup(void);
89struct pci_dev;
90int rbtx4927_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
91
92#endif /* __ASM_TXX9_RBTX4927_H */
diff --git a/arch/mips/include/asm/txx9/rbtx4938.h b/arch/mips/include/asm/txx9/rbtx4938.h
new file mode 100644
index 000000000000..9f0441a28126
--- /dev/null
+++ b/arch/mips/include/asm/txx9/rbtx4938.h
@@ -0,0 +1,145 @@
1/*
2 * Definitions for TX4937/TX4938
3 *
4 * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
5 * terms of the GNU General Public License version 2. This program is
6 * licensed "as is" without any warranty of any kind, whether express
7 * or implied.
8 *
9 * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
10 */
11#ifndef __ASM_TXX9_RBTX4938_H
12#define __ASM_TXX9_RBTX4938_H
13
14#include <asm/addrspace.h>
15#include <asm/txx9irq.h>
16#include <asm/txx9/tx4938.h>
17
18/* Address map */
19#define RBTX4938_FPGA_REG_ADDR (IO_BASE + TXX9_CE(2) + 0x00000000)
20#define RBTX4938_FPGA_REV_ADDR (IO_BASE + TXX9_CE(2) + 0x00000002)
21#define RBTX4938_CONFIG1_ADDR (IO_BASE + TXX9_CE(2) + 0x00000004)
22#define RBTX4938_CONFIG2_ADDR (IO_BASE + TXX9_CE(2) + 0x00000006)
23#define RBTX4938_CONFIG3_ADDR (IO_BASE + TXX9_CE(2) + 0x00000008)
24#define RBTX4938_LED_ADDR (IO_BASE + TXX9_CE(2) + 0x00001000)
25#define RBTX4938_DIPSW_ADDR (IO_BASE + TXX9_CE(2) + 0x00001002)
26#define RBTX4938_BDIPSW_ADDR (IO_BASE + TXX9_CE(2) + 0x00001004)
27#define RBTX4938_IMASK_ADDR (IO_BASE + TXX9_CE(2) + 0x00002000)
28#define RBTX4938_IMASK2_ADDR (IO_BASE + TXX9_CE(2) + 0x00002002)
29#define RBTX4938_INTPOL_ADDR (IO_BASE + TXX9_CE(2) + 0x00002004)
30#define RBTX4938_ISTAT_ADDR (IO_BASE + TXX9_CE(2) + 0x00002006)
31#define RBTX4938_ISTAT2_ADDR (IO_BASE + TXX9_CE(2) + 0x00002008)
32#define RBTX4938_IMSTAT_ADDR (IO_BASE + TXX9_CE(2) + 0x0000200a)
33#define RBTX4938_IMSTAT2_ADDR (IO_BASE + TXX9_CE(2) + 0x0000200c)
34#define RBTX4938_SOFTINT_ADDR (IO_BASE + TXX9_CE(2) + 0x00003000)
35#define RBTX4938_PIOSEL_ADDR (IO_BASE + TXX9_CE(2) + 0x00005000)
36#define RBTX4938_SPICS_ADDR (IO_BASE + TXX9_CE(2) + 0x00005002)
37#define RBTX4938_SFPWR_ADDR (IO_BASE + TXX9_CE(2) + 0x00005008)
38#define RBTX4938_SFVOL_ADDR (IO_BASE + TXX9_CE(2) + 0x0000500a)
39#define RBTX4938_SOFTRESET_ADDR (IO_BASE + TXX9_CE(2) + 0x00007000)
40#define RBTX4938_SOFTRESETLOCK_ADDR (IO_BASE + TXX9_CE(2) + 0x00007002)
41#define RBTX4938_PCIRESET_ADDR (IO_BASE + TXX9_CE(2) + 0x00007004)
42#define RBTX4938_ETHER_BASE (IO_BASE + TXX9_CE(2) + 0x00020000)
43
44/* Ethernet port address (Jumperless Mode (W12:Open)) */
45#define RBTX4938_ETHER_ADDR (RBTX4938_ETHER_BASE + 0x280)
46
47/* bits for ISTAT/IMASK/IMSTAT */
48#define RBTX4938_INTB_PCID 0
49#define RBTX4938_INTB_PCIC 1
50#define RBTX4938_INTB_PCIB 2
51#define RBTX4938_INTB_PCIA 3
52#define RBTX4938_INTB_RTC 4
53#define RBTX4938_INTB_ATA 5
54#define RBTX4938_INTB_MODEM 6
55#define RBTX4938_INTB_SWINT 7
56#define RBTX4938_INTF_PCID (1 << RBTX4938_INTB_PCID)
57#define RBTX4938_INTF_PCIC (1 << RBTX4938_INTB_PCIC)
58#define RBTX4938_INTF_PCIB (1 << RBTX4938_INTB_PCIB)
59#define RBTX4938_INTF_PCIA (1 << RBTX4938_INTB_PCIA)
60#define RBTX4938_INTF_RTC (1 << RBTX4938_INTB_RTC)
61#define RBTX4938_INTF_ATA (1 << RBTX4938_INTB_ATA)
62#define RBTX4938_INTF_MODEM (1 << RBTX4938_INTB_MODEM)
63#define RBTX4938_INTF_SWINT (1 << RBTX4938_INTB_SWINT)
64
65#define rbtx4938_fpga_rev_addr ((__u8 __iomem *)RBTX4938_FPGA_REV_ADDR)
66#define rbtx4938_led_addr ((__u8 __iomem *)RBTX4938_LED_ADDR)
67#define rbtx4938_dipsw_addr ((__u8 __iomem *)RBTX4938_DIPSW_ADDR)
68#define rbtx4938_bdipsw_addr ((__u8 __iomem *)RBTX4938_BDIPSW_ADDR)
69#define rbtx4938_imask_addr ((__u8 __iomem *)RBTX4938_IMASK_ADDR)
70#define rbtx4938_imask2_addr ((__u8 __iomem *)RBTX4938_IMASK2_ADDR)
71#define rbtx4938_intpol_addr ((__u8 __iomem *)RBTX4938_INTPOL_ADDR)
72#define rbtx4938_istat_addr ((__u8 __iomem *)RBTX4938_ISTAT_ADDR)
73#define rbtx4938_istat2_addr ((__u8 __iomem *)RBTX4938_ISTAT2_ADDR)
74#define rbtx4938_imstat_addr ((__u8 __iomem *)RBTX4938_IMSTAT_ADDR)
75#define rbtx4938_imstat2_addr ((__u8 __iomem *)RBTX4938_IMSTAT2_ADDR)
76#define rbtx4938_softint_addr ((__u8 __iomem *)RBTX4938_SOFTINT_ADDR)
77#define rbtx4938_piosel_addr ((__u8 __iomem *)RBTX4938_PIOSEL_ADDR)
78#define rbtx4938_spics_addr ((__u8 __iomem *)RBTX4938_SPICS_ADDR)
79#define rbtx4938_sfpwr_addr ((__u8 __iomem *)RBTX4938_SFPWR_ADDR)
80#define rbtx4938_sfvol_addr ((__u8 __iomem *)RBTX4938_SFVOL_ADDR)
81#define rbtx4938_softreset_addr ((__u8 __iomem *)RBTX4938_SOFTRESET_ADDR)
82#define rbtx4938_softresetlock_addr \
83 ((__u8 __iomem *)RBTX4938_SOFTRESETLOCK_ADDR)
84#define rbtx4938_pcireset_addr ((__u8 __iomem *)RBTX4938_PCIRESET_ADDR)
85
86/*
87 * IRQ mappings
88 */
89
90#define RBTX4938_SOFT_INT0 0 /* not used */
91#define RBTX4938_SOFT_INT1 1 /* not used */
92#define RBTX4938_IRC_INT 2
93#define RBTX4938_TIMER_INT 7
94
95/* These are the virtual IRQ numbers, we divide all IRQ's into
96 * 'spaces', the 'space' determines where and how to enable/disable
97 * that particular IRQ on an RBTX4938 machine. Add new 'spaces' as new
98 * IRQ hardware is supported.
99 */
100#define RBTX4938_NR_IRQ_IOC 8
101
102#define RBTX4938_IRQ_IRC TXX9_IRQ_BASE
103#define RBTX4938_IRQ_IOC (TXX9_IRQ_BASE + TX4938_NUM_IR)
104#define RBTX4938_IRQ_END (RBTX4938_IRQ_IOC + RBTX4938_NR_IRQ_IOC)
105
106#define RBTX4938_IRQ_IRC_ECCERR (RBTX4938_IRQ_IRC + TX4938_IR_ECCERR)
107#define RBTX4938_IRQ_IRC_WTOERR (RBTX4938_IRQ_IRC + TX4938_IR_WTOERR)
108#define RBTX4938_IRQ_IRC_INT(n) (RBTX4938_IRQ_IRC + TX4938_IR_INT(n))
109#define RBTX4938_IRQ_IRC_SIO(n) (RBTX4938_IRQ_IRC + TX4938_IR_SIO(n))
110#define RBTX4938_IRQ_IRC_DMA(ch, n) (RBTX4938_IRQ_IRC + TX4938_IR_DMA(ch, n))
111#define RBTX4938_IRQ_IRC_PIO (RBTX4938_IRQ_IRC + TX4938_IR_PIO)
112#define RBTX4938_IRQ_IRC_PDMAC (RBTX4938_IRQ_IRC + TX4938_IR_PDMAC)
113#define RBTX4938_IRQ_IRC_PCIC (RBTX4938_IRQ_IRC + TX4938_IR_PCIC)
114#define RBTX4938_IRQ_IRC_TMR(n) (RBTX4938_IRQ_IRC + TX4938_IR_TMR(n))
115#define RBTX4938_IRQ_IRC_NDFMC (RBTX4938_IRQ_IRC + TX4938_IR_NDFMC)
116#define RBTX4938_IRQ_IRC_PCIERR (RBTX4938_IRQ_IRC + TX4938_IR_PCIERR)
117#define RBTX4938_IRQ_IRC_PCIPME (RBTX4938_IRQ_IRC + TX4938_IR_PCIPME)
118#define RBTX4938_IRQ_IRC_ACLC (RBTX4938_IRQ_IRC + TX4938_IR_ACLC)
119#define RBTX4938_IRQ_IRC_ACLCPME (RBTX4938_IRQ_IRC + TX4938_IR_ACLCPME)
120#define RBTX4938_IRQ_IRC_PCIC1 (RBTX4938_IRQ_IRC + TX4938_IR_PCIC1)
121#define RBTX4938_IRQ_IRC_SPI (RBTX4938_IRQ_IRC + TX4938_IR_SPI)
122#define RBTX4938_IRQ_IOC_PCID (RBTX4938_IRQ_IOC + RBTX4938_INTB_PCID)
123#define RBTX4938_IRQ_IOC_PCIC (RBTX4938_IRQ_IOC + RBTX4938_INTB_PCIC)
124#define RBTX4938_IRQ_IOC_PCIB (RBTX4938_IRQ_IOC + RBTX4938_INTB_PCIB)
125#define RBTX4938_IRQ_IOC_PCIA (RBTX4938_IRQ_IOC + RBTX4938_INTB_PCIA)
126#define RBTX4938_IRQ_IOC_RTC (RBTX4938_IRQ_IOC + RBTX4938_INTB_RTC)
127#define RBTX4938_IRQ_IOC_ATA (RBTX4938_IRQ_IOC + RBTX4938_INTB_ATA)
128#define RBTX4938_IRQ_IOC_MODEM (RBTX4938_IRQ_IOC + RBTX4938_INTB_MODEM)
129#define RBTX4938_IRQ_IOC_SWINT (RBTX4938_IRQ_IOC + RBTX4938_INTB_SWINT)
130
131
132/* IOC (PCI, etc) */
133#define RBTX4938_IRQ_IOCINT (TXX9_IRQ_BASE + TX4938_IR_INT(0))
134/* Onboard 10M Ether */
135#define RBTX4938_IRQ_ETHER (TXX9_IRQ_BASE + TX4938_IR_INT(1))
136
137#define RBTX4938_RTL_8019_BASE (RBTX4938_ETHER_ADDR - mips_io_port_base)
138#define RBTX4938_RTL_8019_IRQ (RBTX4938_IRQ_ETHER)
139
140void rbtx4938_prom_init(void);
141void rbtx4938_irq_setup(void);
142struct pci_dev;
143int rbtx4938_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
144
145#endif /* __ASM_TXX9_RBTX4938_H */
diff --git a/arch/mips/include/asm/txx9/rbtx4939.h b/arch/mips/include/asm/txx9/rbtx4939.h
new file mode 100644
index 000000000000..1acf428c0b4f
--- /dev/null
+++ b/arch/mips/include/asm/txx9/rbtx4939.h
@@ -0,0 +1,133 @@
1/*
2 * Definitions for RBTX4939
3 *
4 * (C) Copyright TOSHIBA CORPORATION 2005-2006
5 * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
6 * terms of the GNU General Public License version 2. This program is
7 * licensed "as is" without any warranty of any kind, whether express
8 * or implied.
9 */
10#ifndef __ASM_TXX9_RBTX4939_H
11#define __ASM_TXX9_RBTX4939_H
12
13#include <asm/addrspace.h>
14#include <asm/txx9irq.h>
15#include <asm/txx9/generic.h>
16#include <asm/txx9/tx4939.h>
17
18/* Address map */
19#define RBTX4939_IOC_REG_ADDR (IO_BASE + TXX9_CE(1) + 0x00000000)
20#define RBTX4939_BOARD_REV_ADDR (IO_BASE + TXX9_CE(1) + 0x00000000)
21#define RBTX4939_IOC_REV_ADDR (IO_BASE + TXX9_CE(1) + 0x00000002)
22#define RBTX4939_CONFIG1_ADDR (IO_BASE + TXX9_CE(1) + 0x00000004)
23#define RBTX4939_CONFIG2_ADDR (IO_BASE + TXX9_CE(1) + 0x00000006)
24#define RBTX4939_CONFIG3_ADDR (IO_BASE + TXX9_CE(1) + 0x00000008)
25#define RBTX4939_CONFIG4_ADDR (IO_BASE + TXX9_CE(1) + 0x0000000a)
26#define RBTX4939_USTAT_ADDR (IO_BASE + TXX9_CE(1) + 0x00001000)
27#define RBTX4939_UDIPSW_ADDR (IO_BASE + TXX9_CE(1) + 0x00001002)
28#define RBTX4939_BDIPSW_ADDR (IO_BASE + TXX9_CE(1) + 0x00001004)
29#define RBTX4939_IEN_ADDR (IO_BASE + TXX9_CE(1) + 0x00002000)
30#define RBTX4939_IPOL_ADDR (IO_BASE + TXX9_CE(1) + 0x00002002)
31#define RBTX4939_IFAC1_ADDR (IO_BASE + TXX9_CE(1) + 0x00002004)
32#define RBTX4939_IFAC2_ADDR (IO_BASE + TXX9_CE(1) + 0x00002006)
33#define RBTX4939_SOFTINT_ADDR (IO_BASE + TXX9_CE(1) + 0x00003000)
34#define RBTX4939_ISASTAT_ADDR (IO_BASE + TXX9_CE(1) + 0x00004000)
35#define RBTX4939_PCISTAT_ADDR (IO_BASE + TXX9_CE(1) + 0x00004002)
36#define RBTX4939_ROME_ADDR (IO_BASE + TXX9_CE(1) + 0x00004004)
37#define RBTX4939_SPICS_ADDR (IO_BASE + TXX9_CE(1) + 0x00004006)
38#define RBTX4939_AUDI_ADDR (IO_BASE + TXX9_CE(1) + 0x00004008)
39#define RBTX4939_ISAGPIO_ADDR (IO_BASE + TXX9_CE(1) + 0x0000400a)
40#define RBTX4939_PE1_ADDR (IO_BASE + TXX9_CE(1) + 0x00005000)
41#define RBTX4939_PE2_ADDR (IO_BASE + TXX9_CE(1) + 0x00005002)
42#define RBTX4939_PE3_ADDR (IO_BASE + TXX9_CE(1) + 0x00005004)
43#define RBTX4939_VP_ADDR (IO_BASE + TXX9_CE(1) + 0x00005006)
44#define RBTX4939_VPRESET_ADDR (IO_BASE + TXX9_CE(1) + 0x00005008)
45#define RBTX4939_VPSOUT_ADDR (IO_BASE + TXX9_CE(1) + 0x0000500a)
46#define RBTX4939_VPSIN_ADDR (IO_BASE + TXX9_CE(1) + 0x0000500c)
47#define RBTX4939_7SEG_ADDR(s, ch) \
48 (IO_BASE + TXX9_CE(1) + 0x00006000 + (s) * 16 + ((ch) & 3) * 2)
49#define RBTX4939_SOFTRESET_ADDR (IO_BASE + TXX9_CE(1) + 0x00007000)
50#define RBTX4939_RESETEN_ADDR (IO_BASE + TXX9_CE(1) + 0x00007002)
51#define RBTX4939_RESETSTAT_ADDR (IO_BASE + TXX9_CE(1) + 0x00007004)
52#define RBTX4939_ETHER_BASE (IO_BASE + TXX9_CE(1) + 0x00020000)
53
54/* Ethernet port address */
55#define RBTX4939_ETHER_ADDR (RBTX4939_ETHER_BASE + 0x300)
56
57/* bits for IEN/IPOL/IFAC */
58#define RBTX4938_INTB_ISA0 0
59#define RBTX4938_INTB_ISA11 1
60#define RBTX4938_INTB_ISA12 2
61#define RBTX4938_INTB_ISA15 3
62#define RBTX4938_INTB_I2S 4
63#define RBTX4938_INTB_SW 5
64#define RBTX4938_INTF_ISA0 (1 << RBTX4938_INTB_ISA0)
65#define RBTX4938_INTF_ISA11 (1 << RBTX4938_INTB_ISA11)
66#define RBTX4938_INTF_ISA12 (1 << RBTX4938_INTB_ISA12)
67#define RBTX4938_INTF_ISA15 (1 << RBTX4938_INTB_ISA15)
68#define RBTX4938_INTF_I2S (1 << RBTX4938_INTB_I2S)
69#define RBTX4938_INTF_SW (1 << RBTX4938_INTB_SW)
70
71/* bits for PE1,PE2,PE3 */
72#define RBTX4939_PE1_ATA(ch) (0x01 << (ch))
73#define RBTX4939_PE1_RMII(ch) (0x04 << (ch))
74#define RBTX4939_PE2_SIO0 0x01
75#define RBTX4939_PE2_SIO2 0x02
76#define RBTX4939_PE2_SIO3 0x04
77#define RBTX4939_PE2_CIR 0x08
78#define RBTX4939_PE2_SPI 0x10
79#define RBTX4939_PE2_GPIO 0x20
80#define RBTX4939_PE3_VP 0x01
81#define RBTX4939_PE3_VP_P 0x02
82#define RBTX4939_PE3_VP_S 0x04
83
84#define rbtx4939_board_rev_addr ((u8 __iomem *)RBTX4939_BOARD_REV_ADDR)
85#define rbtx4939_ioc_rev_addr ((u8 __iomem *)RBTX4939_IOC_REV_ADDR)
86#define rbtx4939_config1_addr ((u8 __iomem *)RBTX4939_CONFIG1_ADDR)
87#define rbtx4939_config2_addr ((u8 __iomem *)RBTX4939_CONFIG2_ADDR)
88#define rbtx4939_config3_addr ((u8 __iomem *)RBTX4939_CONFIG3_ADDR)
89#define rbtx4939_config4_addr ((u8 __iomem *)RBTX4939_CONFIG4_ADDR)
90#define rbtx4939_ustat_addr ((u8 __iomem *)RBTX4939_USTAT_ADDR)
91#define rbtx4939_udipsw_addr ((u8 __iomem *)RBTX4939_UDIPSW_ADDR)
92#define rbtx4939_bdipsw_addr ((u8 __iomem *)RBTX4939_BDIPSW_ADDR)
93#define rbtx4939_ien_addr ((u8 __iomem *)RBTX4939_IEN_ADDR)
94#define rbtx4939_ipol_addr ((u8 __iomem *)RBTX4939_IPOL_ADDR)
95#define rbtx4939_ifac1_addr ((u8 __iomem *)RBTX4939_IFAC1_ADDR)
96#define rbtx4939_ifac2_addr ((u8 __iomem *)RBTX4939_IFAC2_ADDR)
97#define rbtx4939_softint_addr ((u8 __iomem *)RBTX4939_SOFTINT_ADDR)
98#define rbtx4939_isastat_addr ((u8 __iomem *)RBTX4939_ISASTAT_ADDR)
99#define rbtx4939_pcistat_addr ((u8 __iomem *)RBTX4939_PCISTAT_ADDR)
100#define rbtx4939_rome_addr ((u8 __iomem *)RBTX4939_ROME_ADDR)
101#define rbtx4939_spics_addr ((u8 __iomem *)RBTX4939_SPICS_ADDR)
102#define rbtx4939_audi_addr ((u8 __iomem *)RBTX4939_AUDI_ADDR)
103#define rbtx4939_isagpio_addr ((u8 __iomem *)RBTX4939_ISAGPIO_ADDR)
104#define rbtx4939_pe1_addr ((u8 __iomem *)RBTX4939_PE1_ADDR)
105#define rbtx4939_pe2_addr ((u8 __iomem *)RBTX4939_PE2_ADDR)
106#define rbtx4939_pe3_addr ((u8 __iomem *)RBTX4939_PE3_ADDR)
107#define rbtx4939_vp_addr ((u8 __iomem *)RBTX4939_VP_ADDR)
108#define rbtx4939_vpreset_addr ((u8 __iomem *)RBTX4939_VPRESET_ADDR)
109#define rbtx4939_vpsout_addr ((u8 __iomem *)RBTX4939_VPSOUT_ADDR)
110#define rbtx4939_vpsin_addr ((u8 __iomem *)RBTX4939_VPSIN_ADDR)
111#define rbtx4939_7seg_addr(s, ch) \
112 ((u8 __iomem *)RBTX4939_7SEG_ADDR(s, ch))
113#define rbtx4939_softreset_addr ((u8 __iomem *)RBTX4939_SOFTRESET_ADDR)
114#define rbtx4939_reseten_addr ((u8 __iomem *)RBTX4939_RESETEN_ADDR)
115#define rbtx4939_resetstat_addr ((u8 __iomem *)RBTX4939_RESETSTAT_ADDR)
116
117/*
118 * IRQ mappings
119 */
120#define RBTX4939_NR_IRQ_IOC 8
121
122#define RBTX4939_IRQ_IOC (TXX9_IRQ_BASE + TX4939_NUM_IR)
123#define RBTX4939_IRQ_END (RBTX4939_IRQ_IOC + RBTX4939_NR_IRQ_IOC)
124
125/* IOC (ISA, etc) */
126#define RBTX4939_IRQ_IOCINT (TXX9_IRQ_BASE + TX4939_IR_INT(0))
127/* Onboard 10M Ether */
128#define RBTX4939_IRQ_ETHER (TXX9_IRQ_BASE + TX4939_IR_INT(1))
129
130void rbtx4939_prom_init(void);
131void rbtx4939_irq_setup(void);
132
133#endif /* __ASM_TXX9_RBTX4939_H */
diff --git a/arch/mips/include/asm/txx9/smsc_fdc37m81x.h b/arch/mips/include/asm/txx9/smsc_fdc37m81x.h
new file mode 100644
index 000000000000..d1d6332b4ca6
--- /dev/null
+++ b/arch/mips/include/asm/txx9/smsc_fdc37m81x.h
@@ -0,0 +1,68 @@
1/*
2 * Interface for smsc fdc48m81x Super IO chip
3 *
4 * Author: MontaVista Software, Inc. source@mvista.com
5 *
6 * 2001-2003 (c) MontaVista Software, Inc. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 *
11 * Copyright (C) 2004 MontaVista Software Inc.
12 * Manish Lachwani, mlachwani@mvista.com
13 */
14
15#ifndef _SMSC_FDC37M81X_H_
16#define _SMSC_FDC37M81X_H_
17
18/* Common Registers */
19#define SMSC_FDC37M81X_CONFIG_INDEX 0x00
20#define SMSC_FDC37M81X_CONFIG_DATA 0x01
21#define SMSC_FDC37M81X_CONF 0x02
22#define SMSC_FDC37M81X_INDEX 0x03
23#define SMSC_FDC37M81X_DNUM 0x07
24#define SMSC_FDC37M81X_DID 0x20
25#define SMSC_FDC37M81X_DREV 0x21
26#define SMSC_FDC37M81X_PCNT 0x22
27#define SMSC_FDC37M81X_PMGT 0x23
28#define SMSC_FDC37M81X_OSC 0x24
29#define SMSC_FDC37M81X_CONFPA0 0x26
30#define SMSC_FDC37M81X_CONFPA1 0x27
31#define SMSC_FDC37M81X_TEST4 0x2B
32#define SMSC_FDC37M81X_TEST5 0x2C
33#define SMSC_FDC37M81X_TEST1 0x2D
34#define SMSC_FDC37M81X_TEST2 0x2E
35#define SMSC_FDC37M81X_TEST3 0x2F
36
37/* Logical device numbers */
38#define SMSC_FDC37M81X_FDD 0x00
39#define SMSC_FDC37M81X_PARALLEL 0x03
40#define SMSC_FDC37M81X_SERIAL1 0x04
41#define SMSC_FDC37M81X_SERIAL2 0x05
42#define SMSC_FDC37M81X_KBD 0x07
43#define SMSC_FDC37M81X_AUXIO 0x08
44#define SMSC_FDC37M81X_NONE 0xff
45
46/* Logical device Config Registers */
47#define SMSC_FDC37M81X_ACTIVE 0x30
48#define SMSC_FDC37M81X_BASEADDR0 0x60
49#define SMSC_FDC37M81X_BASEADDR1 0x61
50#define SMSC_FDC37M81X_INT 0x70
51#define SMSC_FDC37M81X_INT2 0x72
52#define SMSC_FDC37M81X_LDCR_F0 0xF0
53
54/* Chip Config Values */
55#define SMSC_FDC37M81X_CONFIG_ENTER 0x55
56#define SMSC_FDC37M81X_CONFIG_EXIT 0xaa
57#define SMSC_FDC37M81X_CHIP_ID 0x4d
58
59unsigned long smsc_fdc37m81x_init(unsigned long port);
60
61void smsc_fdc37m81x_config_beg(void);
62
63void smsc_fdc37m81x_config_end(void);
64
65u8 smsc_fdc37m81x_config_get(u8 reg);
66void smsc_fdc37m81x_config_set(u8 reg, u8 val);
67
68#endif
diff --git a/arch/mips/include/asm/txx9/spi.h b/arch/mips/include/asm/txx9/spi.h
new file mode 100644
index 000000000000..0d727f354557
--- /dev/null
+++ b/arch/mips/include/asm/txx9/spi.h
@@ -0,0 +1,34 @@
1/*
2 * Definitions for TX4937/TX4938 SPI
3 *
4 * Copyright (C) 2000-2001 Toshiba Corporation
5 *
6 * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
7 * terms of the GNU General Public License version 2. This program is
8 * licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 *
11 * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
12 */
13#ifndef __ASM_TXX9_SPI_H
14#define __ASM_TXX9_SPI_H
15
16#include <linux/errno.h>
17
18#ifdef CONFIG_SPI
19int spi_eeprom_register(int busid, int chipid, int size);
20int spi_eeprom_read(int busid, int chipid,
21 int address, unsigned char *buf, int len);
22#else
23static inline int spi_eeprom_register(int busid, int chipid, int size)
24{
25 return -ENODEV;
26}
27static inline int spi_eeprom_read(int busid, int chipid,
28 int address, unsigned char *buf, int len)
29{
30 return -ENODEV;
31}
32#endif
33
34#endif /* __ASM_TXX9_SPI_H */
diff --git a/arch/mips/include/asm/txx9/tx3927.h b/arch/mips/include/asm/txx9/tx3927.h
new file mode 100644
index 000000000000..dc30c8d42061
--- /dev/null
+++ b/arch/mips/include/asm/txx9/tx3927.h
@@ -0,0 +1,341 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2000 Toshiba Corporation
7 */
8#ifndef __ASM_TXX9_TX3927_H
9#define __ASM_TXX9_TX3927_H
10
11#define TX3927_REG_BASE 0xfffe0000UL
12#define TX3927_REG_SIZE 0x00010000
13#define TX3927_SDRAMC_REG (TX3927_REG_BASE + 0x8000)
14#define TX3927_ROMC_REG (TX3927_REG_BASE + 0x9000)
15#define TX3927_DMA_REG (TX3927_REG_BASE + 0xb000)
16#define TX3927_IRC_REG (TX3927_REG_BASE + 0xc000)
17#define TX3927_PCIC_REG (TX3927_REG_BASE + 0xd000)
18#define TX3927_CCFG_REG (TX3927_REG_BASE + 0xe000)
19#define TX3927_NR_TMR 3
20#define TX3927_TMR_REG(ch) (TX3927_REG_BASE + 0xf000 + (ch) * 0x100)
21#define TX3927_NR_SIO 2
22#define TX3927_SIO_REG(ch) (TX3927_REG_BASE + 0xf300 + (ch) * 0x100)
23#define TX3927_PIO_REG (TX3927_REG_BASE + 0xf500)
24
25struct tx3927_sdramc_reg {
26 volatile unsigned long cr[8];
27 volatile unsigned long tr[3];
28 volatile unsigned long cmd;
29 volatile unsigned long smrs[2];
30};
31
32struct tx3927_romc_reg {
33 volatile unsigned long cr[8];
34};
35
36struct tx3927_dma_reg {
37 struct tx3927_dma_ch_reg {
38 volatile unsigned long cha;
39 volatile unsigned long sar;
40 volatile unsigned long dar;
41 volatile unsigned long cntr;
42 volatile unsigned long sair;
43 volatile unsigned long dair;
44 volatile unsigned long ccr;
45 volatile unsigned long csr;
46 } ch[4];
47 volatile unsigned long dbr[8];
48 volatile unsigned long tdhr;
49 volatile unsigned long mcr;
50 volatile unsigned long unused0;
51};
52
53#include <asm/byteorder.h>
54
55#ifdef __BIG_ENDIAN
56#define endian_def_s2(e1, e2) \
57 volatile unsigned short e1, e2
58#define endian_def_sb2(e1, e2, e3) \
59 volatile unsigned short e1;volatile unsigned char e2, e3
60#define endian_def_b2s(e1, e2, e3) \
61 volatile unsigned char e1, e2;volatile unsigned short e3
62#define endian_def_b4(e1, e2, e3, e4) \
63 volatile unsigned char e1, e2, e3, e4
64#else
65#define endian_def_s2(e1, e2) \
66 volatile unsigned short e2, e1
67#define endian_def_sb2(e1, e2, e3) \
68 volatile unsigned char e3, e2;volatile unsigned short e1
69#define endian_def_b2s(e1, e2, e3) \
70 volatile unsigned short e3;volatile unsigned char e2, e1
71#define endian_def_b4(e1, e2, e3, e4) \
72 volatile unsigned char e4, e3, e2, e1
73#endif
74
75struct tx3927_pcic_reg {
76 endian_def_s2(did, vid);
77 endian_def_s2(pcistat, pcicmd);
78 endian_def_b4(cc, scc, rpli, rid);
79 endian_def_b4(unused0, ht, mlt, cls);
80 volatile unsigned long ioba; /* +10 */
81 volatile unsigned long mba;
82 volatile unsigned long unused1[5];
83 endian_def_s2(svid, ssvid);
84 volatile unsigned long unused2; /* +30 */
85 endian_def_sb2(unused3, unused4, capptr);
86 volatile unsigned long unused5;
87 endian_def_b4(ml, mg, ip, il);
88 volatile unsigned long unused6; /* +40 */
89 volatile unsigned long istat;
90 volatile unsigned long iim;
91 volatile unsigned long rrt;
92 volatile unsigned long unused7[3]; /* +50 */
93 volatile unsigned long ipbmma;
94 volatile unsigned long ipbioma; /* +60 */
95 volatile unsigned long ilbmma;
96 volatile unsigned long ilbioma;
97 volatile unsigned long unused8[9];
98 volatile unsigned long tc; /* +90 */
99 volatile unsigned long tstat;
100 volatile unsigned long tim;
101 volatile unsigned long tccmd;
102 volatile unsigned long pcirrt; /* +a0 */
103 volatile unsigned long pcirrt_cmd;
104 volatile unsigned long pcirrdt;
105 volatile unsigned long unused9[3];
106 volatile unsigned long tlboap;
107 volatile unsigned long tlbiap;
108 volatile unsigned long tlbmma; /* +c0 */
109 volatile unsigned long tlbioma;
110 volatile unsigned long sc_msg;
111 volatile unsigned long sc_be;
112 volatile unsigned long tbl; /* +d0 */
113 volatile unsigned long unused10[3];
114 volatile unsigned long pwmng; /* +e0 */
115 volatile unsigned long pwmngs;
116 volatile unsigned long unused11[6];
117 volatile unsigned long req_trace; /* +100 */
118 volatile unsigned long pbapmc;
119 volatile unsigned long pbapms;
120 volatile unsigned long pbapmim;
121 volatile unsigned long bm; /* +110 */
122 volatile unsigned long cpcibrs;
123 volatile unsigned long cpcibgs;
124 volatile unsigned long pbacs;
125 volatile unsigned long iobas; /* +120 */
126 volatile unsigned long mbas;
127 volatile unsigned long lbc;
128 volatile unsigned long lbstat;
129 volatile unsigned long lbim; /* +130 */
130 volatile unsigned long pcistatim;
131 volatile unsigned long ica;
132 volatile unsigned long icd;
133 volatile unsigned long iiadp; /* +140 */
134 volatile unsigned long iscdp;
135 volatile unsigned long mmas;
136 volatile unsigned long iomas;
137 volatile unsigned long ipciaddr; /* +150 */
138 volatile unsigned long ipcidata;
139 volatile unsigned long ipcibe;
140};
141
142struct tx3927_ccfg_reg {
143 volatile unsigned long ccfg;
144 volatile unsigned long crir;
145 volatile unsigned long pcfg;
146 volatile unsigned long tear;
147 volatile unsigned long pdcr;
148};
149
150/*
151 * SDRAMC
152 */
153
154/*
155 * ROMC
156 */
157
158/*
159 * DMA
160 */
161/* bits for MCR */
162#define TX3927_DMA_MCR_EIS(ch) (0x10000000<<(ch))
163#define TX3927_DMA_MCR_DIS(ch) (0x01000000<<(ch))
164#define TX3927_DMA_MCR_RSFIF 0x00000080
165#define TX3927_DMA_MCR_FIFUM(ch) (0x00000008<<(ch))
166#define TX3927_DMA_MCR_LE 0x00000004
167#define TX3927_DMA_MCR_RPRT 0x00000002
168#define TX3927_DMA_MCR_MSTEN 0x00000001
169
170/* bits for CCRn */
171#define TX3927_DMA_CCR_DBINH 0x04000000
172#define TX3927_DMA_CCR_SBINH 0x02000000
173#define TX3927_DMA_CCR_CHRST 0x01000000
174#define TX3927_DMA_CCR_RVBYTE 0x00800000
175#define TX3927_DMA_CCR_ACKPOL 0x00400000
176#define TX3927_DMA_CCR_REQPL 0x00200000
177#define TX3927_DMA_CCR_EGREQ 0x00100000
178#define TX3927_DMA_CCR_CHDN 0x00080000
179#define TX3927_DMA_CCR_DNCTL 0x00060000
180#define TX3927_DMA_CCR_EXTRQ 0x00010000
181#define TX3927_DMA_CCR_INTRQD 0x0000e000
182#define TX3927_DMA_CCR_INTENE 0x00001000
183#define TX3927_DMA_CCR_INTENC 0x00000800
184#define TX3927_DMA_CCR_INTENT 0x00000400
185#define TX3927_DMA_CCR_CHNEN 0x00000200
186#define TX3927_DMA_CCR_XFACT 0x00000100
187#define TX3927_DMA_CCR_SNOP 0x00000080
188#define TX3927_DMA_CCR_DSTINC 0x00000040
189#define TX3927_DMA_CCR_SRCINC 0x00000020
190#define TX3927_DMA_CCR_XFSZ(order) (((order) << 2) & 0x0000001c)
191#define TX3927_DMA_CCR_XFSZ_1W TX3927_DMA_CCR_XFSZ(2)
192#define TX3927_DMA_CCR_XFSZ_4W TX3927_DMA_CCR_XFSZ(4)
193#define TX3927_DMA_CCR_XFSZ_8W TX3927_DMA_CCR_XFSZ(5)
194#define TX3927_DMA_CCR_XFSZ_16W TX3927_DMA_CCR_XFSZ(6)
195#define TX3927_DMA_CCR_XFSZ_32W TX3927_DMA_CCR_XFSZ(7)
196#define TX3927_DMA_CCR_MEMIO 0x00000002
197#define TX3927_DMA_CCR_ONEAD 0x00000001
198
199/* bits for CSRn */
200#define TX3927_DMA_CSR_CHNACT 0x00000100
201#define TX3927_DMA_CSR_ABCHC 0x00000080
202#define TX3927_DMA_CSR_NCHNC 0x00000040
203#define TX3927_DMA_CSR_NTRNFC 0x00000020
204#define TX3927_DMA_CSR_EXTDN 0x00000010
205#define TX3927_DMA_CSR_CFERR 0x00000008
206#define TX3927_DMA_CSR_CHERR 0x00000004
207#define TX3927_DMA_CSR_DESERR 0x00000002
208#define TX3927_DMA_CSR_SORERR 0x00000001
209
210/*
211 * IRC
212 */
213#define TX3927_IR_INT0 0
214#define TX3927_IR_INT1 1
215#define TX3927_IR_INT2 2
216#define TX3927_IR_INT3 3
217#define TX3927_IR_INT4 4
218#define TX3927_IR_INT5 5
219#define TX3927_IR_SIO0 6
220#define TX3927_IR_SIO1 7
221#define TX3927_IR_SIO(ch) (6 + (ch))
222#define TX3927_IR_DMA 8
223#define TX3927_IR_PIO 9
224#define TX3927_IR_PCI 10
225#define TX3927_IR_TMR(ch) (13 + (ch))
226#define TX3927_NUM_IR 16
227
228/*
229 * PCIC
230 */
231/* bits for PCICMD */
232/* see PCI_COMMAND_XXX in linux/pci.h */
233
234/* bits for PCISTAT */
235/* see PCI_STATUS_XXX in linux/pci.h */
236#define PCI_STATUS_NEW_CAP 0x0010
237
238/* bits for ISTAT/IIM */
239#define TX3927_PCIC_IIM_ALL 0x00001600
240
241/* bits for TC */
242#define TX3927_PCIC_TC_OF16E 0x00000020
243#define TX3927_PCIC_TC_IF8E 0x00000010
244#define TX3927_PCIC_TC_OF8E 0x00000008
245
246/* bits for TSTAT/TIM */
247#define TX3927_PCIC_TIM_ALL 0x0003ffff
248
249/* bits for IOBA/MBA */
250/* see PCI_BASE_ADDRESS_XXX in linux/pci.h */
251
252/* bits for PBAPMC */
253#define TX3927_PCIC_PBAPMC_RPBA 0x00000004
254#define TX3927_PCIC_PBAPMC_PBAEN 0x00000002
255#define TX3927_PCIC_PBAPMC_BMCEN 0x00000001
256
257/* bits for LBSTAT/LBIM */
258#define TX3927_PCIC_LBIM_ALL 0x0000003e
259
260/* bits for PCISTATIM (see also PCI_STATUS_XXX in linux/pci.h */
261#define TX3927_PCIC_PCISTATIM_ALL 0x0000f900
262
263/* bits for LBC */
264#define TX3927_PCIC_LBC_IBSE 0x00004000
265#define TX3927_PCIC_LBC_TIBSE 0x00002000
266#define TX3927_PCIC_LBC_TMFBSE 0x00001000
267#define TX3927_PCIC_LBC_HRST 0x00000800
268#define TX3927_PCIC_LBC_SRST 0x00000400
269#define TX3927_PCIC_LBC_EPCAD 0x00000200
270#define TX3927_PCIC_LBC_MSDSE 0x00000100
271#define TX3927_PCIC_LBC_CRR 0x00000080
272#define TX3927_PCIC_LBC_ILMDE 0x00000040
273#define TX3927_PCIC_LBC_ILIDE 0x00000020
274
275#define TX3927_PCIC_IDSEL_AD_TO_SLOT(ad) ((ad) - 11)
276#define TX3927_PCIC_MAX_DEVNU TX3927_PCIC_IDSEL_AD_TO_SLOT(32)
277
278/*
279 * CCFG
280 */
281/* CCFG : Chip Configuration */
282#define TX3927_CCFG_TLBOFF 0x00020000
283#define TX3927_CCFG_BEOW 0x00010000
284#define TX3927_CCFG_WR 0x00008000
285#define TX3927_CCFG_TOE 0x00004000
286#define TX3927_CCFG_PCIXARB 0x00002000
287#define TX3927_CCFG_PCI3 0x00001000
288#define TX3927_CCFG_PSNP 0x00000800
289#define TX3927_CCFG_PPRI 0x00000400
290#define TX3927_CCFG_PLLM 0x00000030
291#define TX3927_CCFG_ENDIAN 0x00000004
292#define TX3927_CCFG_HALT 0x00000002
293#define TX3927_CCFG_ACEHOLD 0x00000001
294
295/* PCFG : Pin Configuration */
296#define TX3927_PCFG_SYSCLKEN 0x08000000
297#define TX3927_PCFG_SDRCLKEN_ALL 0x07c00000
298#define TX3927_PCFG_SDRCLKEN(ch) (0x00400000<<(ch))
299#define TX3927_PCFG_PCICLKEN_ALL 0x003c0000
300#define TX3927_PCFG_PCICLKEN(ch) (0x00040000<<(ch))
301#define TX3927_PCFG_SELALL 0x0003ffff
302#define TX3927_PCFG_SELCS 0x00020000
303#define TX3927_PCFG_SELDSF 0x00010000
304#define TX3927_PCFG_SELSIOC_ALL 0x0000c000
305#define TX3927_PCFG_SELSIOC(ch) (0x00004000<<(ch))
306#define TX3927_PCFG_SELSIO_ALL 0x00003000
307#define TX3927_PCFG_SELSIO(ch) (0x00001000<<(ch))
308#define TX3927_PCFG_SELTMR_ALL 0x00000e00
309#define TX3927_PCFG_SELTMR(ch) (0x00000200<<(ch))
310#define TX3927_PCFG_SELDONE 0x00000100
311#define TX3927_PCFG_INTDMA_ALL 0x000000f0
312#define TX3927_PCFG_INTDMA(ch) (0x00000010<<(ch))
313#define TX3927_PCFG_SELDMA_ALL 0x0000000f
314#define TX3927_PCFG_SELDMA(ch) (0x00000001<<(ch))
315
316#define tx3927_sdramcptr ((struct tx3927_sdramc_reg *)TX3927_SDRAMC_REG)
317#define tx3927_romcptr ((struct tx3927_romc_reg *)TX3927_ROMC_REG)
318#define tx3927_dmaptr ((struct tx3927_dma_reg *)TX3927_DMA_REG)
319#define tx3927_pcicptr ((struct tx3927_pcic_reg *)TX3927_PCIC_REG)
320#define tx3927_ccfgptr ((struct tx3927_ccfg_reg *)TX3927_CCFG_REG)
321#define tx3927_sioptr(ch) ((struct txx927_sio_reg *)TX3927_SIO_REG(ch))
322#define tx3927_pioptr ((struct txx9_pio_reg __iomem *)TX3927_PIO_REG)
323
324#define TX3927_REV_PCODE() (tx3927_ccfgptr->crir >> 16)
325#define TX3927_ROMC_BA(ch) (tx3927_romcptr->cr[(ch)] & 0xfff00000)
326#define TX3927_ROMC_SIZE(ch) \
327 (0x00100000 << ((tx3927_romcptr->cr[(ch)] >> 8) & 0xf))
328#define TX3927_ROMC_WIDTH(ch) (32 >> ((tx3927_romcptr->cr[(ch)] >> 7) & 0x1))
329
330void tx3927_wdt_init(void);
331void tx3927_setup(void);
332void tx3927_time_init(unsigned int evt_tmrnr, unsigned int src_tmrnr);
333void tx3927_sio_init(unsigned int sclk, unsigned int cts_mask);
334struct pci_controller;
335void tx3927_pcic_setup(struct pci_controller *channel,
336 unsigned long sdram_size, int extarb);
337void tx3927_setup_pcierr_irq(void);
338void tx3927_irq_init(void);
339void tx3927_mtd_init(int ch);
340
341#endif /* __ASM_TXX9_TX3927_H */
diff --git a/arch/mips/include/asm/txx9/tx4927.h b/arch/mips/include/asm/txx9/tx4927.h
new file mode 100644
index 000000000000..7d813f1cb98d
--- /dev/null
+++ b/arch/mips/include/asm/txx9/tx4927.h
@@ -0,0 +1,269 @@
1/*
2 * Author: MontaVista Software, Inc.
3 * source@mvista.com
4 *
5 * Copyright 2001-2006 MontaVista Software Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
13 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
15 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
16 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
17 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
18 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
19 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
20 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
21 * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
22 *
23 * You should have received a copy of the GNU General Public License along
24 * with this program; if not, write to the Free Software Foundation, Inc.,
25 * 675 Mass Ave, Cambridge, MA 02139, USA.
26 */
27#ifndef __ASM_TXX9_TX4927_H
28#define __ASM_TXX9_TX4927_H
29
30#include <linux/types.h>
31#include <linux/io.h>
32#include <asm/txx9irq.h>
33#include <asm/txx9/tx4927pcic.h>
34
35#ifdef CONFIG_64BIT
36#define TX4927_REG_BASE 0xffffffffff1f0000UL
37#else
38#define TX4927_REG_BASE 0xff1f0000UL
39#endif
40#define TX4927_REG_SIZE 0x00010000
41
42#define TX4927_SDRAMC_REG (TX4927_REG_BASE + 0x8000)
43#define TX4927_EBUSC_REG (TX4927_REG_BASE + 0x9000)
44#define TX4927_PCIC_REG (TX4927_REG_BASE + 0xd000)
45#define TX4927_CCFG_REG (TX4927_REG_BASE + 0xe000)
46#define TX4927_IRC_REG (TX4927_REG_BASE + 0xf600)
47#define TX4927_NR_TMR 3
48#define TX4927_TMR_REG(ch) (TX4927_REG_BASE + 0xf000 + (ch) * 0x100)
49#define TX4927_NR_SIO 2
50#define TX4927_SIO_REG(ch) (TX4927_REG_BASE + 0xf300 + (ch) * 0x100)
51#define TX4927_PIO_REG (TX4927_REG_BASE + 0xf500)
52
53#define TX4927_IR_ECCERR 0
54#define TX4927_IR_WTOERR 1
55#define TX4927_NUM_IR_INT 6
56#define TX4927_IR_INT(n) (2 + (n))
57#define TX4927_NUM_IR_SIO 2
58#define TX4927_IR_SIO(n) (8 + (n))
59#define TX4927_NUM_IR_DMA 4
60#define TX4927_IR_DMA(n) (10 + (n))
61#define TX4927_IR_PIO 14
62#define TX4927_IR_PDMAC 15
63#define TX4927_IR_PCIC 16
64#define TX4927_NUM_IR_TMR 3
65#define TX4927_IR_TMR(n) (17 + (n))
66#define TX4927_IR_PCIERR 22
67#define TX4927_IR_PCIPME 23
68#define TX4927_IR_ACLC 24
69#define TX4927_IR_ACLCPME 25
70#define TX4927_NUM_IR 32
71
72#define TX4927_IRC_INT 2 /* IP[2] in Status register */
73
74#define TX4927_NUM_PIO 16
75
76struct tx4927_sdramc_reg {
77 u64 cr[4];
78 u64 unused0[4];
79 u64 tr;
80 u64 unused1[2];
81 u64 cmd;
82};
83
84struct tx4927_ebusc_reg {
85 u64 cr[8];
86};
87
88struct tx4927_ccfg_reg {
89 u64 ccfg;
90 u64 crir;
91 u64 pcfg;
92 u64 toea;
93 u64 clkctr;
94 u64 unused0;
95 u64 garbc;
96 u64 unused1;
97 u64 unused2;
98 u64 ramp;
99};
100
101/*
102 * CCFG
103 */
104/* CCFG : Chip Configuration */
105#define TX4927_CCFG_WDRST 0x0000020000000000ULL
106#define TX4927_CCFG_WDREXEN 0x0000010000000000ULL
107#define TX4927_CCFG_BCFG_MASK 0x000000ff00000000ULL
108#define TX4927_CCFG_TINTDIS 0x01000000
109#define TX4927_CCFG_PCI66 0x00800000
110#define TX4927_CCFG_PCIMODE 0x00400000
111#define TX4927_CCFG_DIVMODE_MASK 0x000e0000
112#define TX4927_CCFG_DIVMODE_8 (0x0 << 17)
113#define TX4927_CCFG_DIVMODE_12 (0x1 << 17)
114#define TX4927_CCFG_DIVMODE_16 (0x2 << 17)
115#define TX4927_CCFG_DIVMODE_10 (0x3 << 17)
116#define TX4927_CCFG_DIVMODE_2 (0x4 << 17)
117#define TX4927_CCFG_DIVMODE_3 (0x5 << 17)
118#define TX4927_CCFG_DIVMODE_4 (0x6 << 17)
119#define TX4927_CCFG_DIVMODE_2_5 (0x7 << 17)
120#define TX4927_CCFG_BEOW 0x00010000
121#define TX4927_CCFG_WR 0x00008000
122#define TX4927_CCFG_TOE 0x00004000
123#define TX4927_CCFG_PCIARB 0x00002000
124#define TX4927_CCFG_PCIDIVMODE_MASK 0x00001800
125#define TX4927_CCFG_PCIDIVMODE_2_5 0x00000000
126#define TX4927_CCFG_PCIDIVMODE_3 0x00000800
127#define TX4927_CCFG_PCIDIVMODE_5 0x00001000
128#define TX4927_CCFG_PCIDIVMODE_6 0x00001800
129#define TX4927_CCFG_SYSSP_MASK 0x000000c0
130#define TX4927_CCFG_ENDIAN 0x00000004
131#define TX4927_CCFG_HALT 0x00000002
132#define TX4927_CCFG_ACEHOLD 0x00000001
133#define TX4927_CCFG_W1CBITS (TX4927_CCFG_WDRST | TX4927_CCFG_BEOW)
134
135/* PCFG : Pin Configuration */
136#define TX4927_PCFG_SDCLKDLY_MASK 0x30000000
137#define TX4927_PCFG_SDCLKDLY(d) ((d)<<28)
138#define TX4927_PCFG_SYSCLKEN 0x08000000
139#define TX4927_PCFG_SDCLKEN_ALL 0x07800000
140#define TX4927_PCFG_SDCLKEN(ch) (0x00800000<<(ch))
141#define TX4927_PCFG_PCICLKEN_ALL 0x003f0000
142#define TX4927_PCFG_PCICLKEN(ch) (0x00010000<<(ch))
143#define TX4927_PCFG_SEL2 0x00000200
144#define TX4927_PCFG_SEL1 0x00000100
145#define TX4927_PCFG_DMASEL_ALL 0x000000ff
146#define TX4927_PCFG_DMASEL0_MASK 0x00000003
147#define TX4927_PCFG_DMASEL1_MASK 0x0000000c
148#define TX4927_PCFG_DMASEL2_MASK 0x00000030
149#define TX4927_PCFG_DMASEL3_MASK 0x000000c0
150#define TX4927_PCFG_DMASEL0_DRQ0 0x00000000
151#define TX4927_PCFG_DMASEL0_SIO1 0x00000001
152#define TX4927_PCFG_DMASEL0_ACL0 0x00000002
153#define TX4927_PCFG_DMASEL0_ACL2 0x00000003
154#define TX4927_PCFG_DMASEL1_DRQ1 0x00000000
155#define TX4927_PCFG_DMASEL1_SIO1 0x00000004
156#define TX4927_PCFG_DMASEL1_ACL1 0x00000008
157#define TX4927_PCFG_DMASEL1_ACL3 0x0000000c
158#define TX4927_PCFG_DMASEL2_DRQ2 0x00000000 /* SEL2=0 */
159#define TX4927_PCFG_DMASEL2_SIO0 0x00000010 /* SEL2=0 */
160#define TX4927_PCFG_DMASEL2_ACL1 0x00000000 /* SEL2=1 */
161#define TX4927_PCFG_DMASEL2_ACL2 0x00000020 /* SEL2=1 */
162#define TX4927_PCFG_DMASEL2_ACL0 0x00000030 /* SEL2=1 */
163#define TX4927_PCFG_DMASEL3_DRQ3 0x00000000
164#define TX4927_PCFG_DMASEL3_SIO0 0x00000040
165#define TX4927_PCFG_DMASEL3_ACL3 0x00000080
166#define TX4927_PCFG_DMASEL3_ACL1 0x000000c0
167
168/* CLKCTR : Clock Control */
169#define TX4927_CLKCTR_ACLCKD 0x02000000
170#define TX4927_CLKCTR_PIOCKD 0x01000000
171#define TX4927_CLKCTR_DMACKD 0x00800000
172#define TX4927_CLKCTR_PCICKD 0x00400000
173#define TX4927_CLKCTR_TM0CKD 0x00100000
174#define TX4927_CLKCTR_TM1CKD 0x00080000
175#define TX4927_CLKCTR_TM2CKD 0x00040000
176#define TX4927_CLKCTR_SIO0CKD 0x00020000
177#define TX4927_CLKCTR_SIO1CKD 0x00010000
178#define TX4927_CLKCTR_ACLRST 0x00000200
179#define TX4927_CLKCTR_PIORST 0x00000100
180#define TX4927_CLKCTR_DMARST 0x00000080
181#define TX4927_CLKCTR_PCIRST 0x00000040
182#define TX4927_CLKCTR_TM0RST 0x00000010
183#define TX4927_CLKCTR_TM1RST 0x00000008
184#define TX4927_CLKCTR_TM2RST 0x00000004
185#define TX4927_CLKCTR_SIO0RST 0x00000002
186#define TX4927_CLKCTR_SIO1RST 0x00000001
187
188#define tx4927_sdramcptr \
189 ((struct tx4927_sdramc_reg __iomem *)TX4927_SDRAMC_REG)
190#define tx4927_pcicptr \
191 ((struct tx4927_pcic_reg __iomem *)TX4927_PCIC_REG)
192#define tx4927_ccfgptr \
193 ((struct tx4927_ccfg_reg __iomem *)TX4927_CCFG_REG)
194#define tx4927_ebuscptr \
195 ((struct tx4927_ebusc_reg __iomem *)TX4927_EBUSC_REG)
196#define tx4927_pioptr ((struct txx9_pio_reg __iomem *)TX4927_PIO_REG)
197
198#define TX4927_REV_PCODE() \
199 ((__u32)__raw_readq(&tx4927_ccfgptr->crir) >> 16)
200
201#define TX4927_SDRAMC_CR(ch) __raw_readq(&tx4927_sdramcptr->cr[(ch)])
202#define TX4927_SDRAMC_BA(ch) ((TX4927_SDRAMC_CR(ch) >> 49) << 21)
203#define TX4927_SDRAMC_SIZE(ch) \
204 ((((TX4927_SDRAMC_CR(ch) >> 33) & 0x7fff) + 1) << 21)
205
206#define TX4927_EBUSC_CR(ch) __raw_readq(&tx4927_ebuscptr->cr[(ch)])
207#define TX4927_EBUSC_BA(ch) ((TX4927_EBUSC_CR(ch) >> 48) << 20)
208#define TX4927_EBUSC_SIZE(ch) \
209 (0x00100000 << ((unsigned long)(TX4927_EBUSC_CR(ch) >> 8) & 0xf))
210#define TX4927_EBUSC_WIDTH(ch) \
211 (64 >> ((__u32)(TX4927_EBUSC_CR(ch) >> 20) & 0x3))
212
213/* utilities */
214static inline void txx9_clear64(__u64 __iomem *adr, __u64 bits)
215{
216#ifdef CONFIG_32BIT
217 unsigned long flags;
218 local_irq_save(flags);
219#endif
220 ____raw_writeq(____raw_readq(adr) & ~bits, adr);
221#ifdef CONFIG_32BIT
222 local_irq_restore(flags);
223#endif
224}
225static inline void txx9_set64(__u64 __iomem *adr, __u64 bits)
226{
227#ifdef CONFIG_32BIT
228 unsigned long flags;
229 local_irq_save(flags);
230#endif
231 ____raw_writeq(____raw_readq(adr) | bits, adr);
232#ifdef CONFIG_32BIT
233 local_irq_restore(flags);
234#endif
235}
236
237/* These functions are not interrupt safe. */
238static inline void tx4927_ccfg_clear(__u64 bits)
239{
240 ____raw_writeq(____raw_readq(&tx4927_ccfgptr->ccfg)
241 & ~(TX4927_CCFG_W1CBITS | bits),
242 &tx4927_ccfgptr->ccfg);
243}
244static inline void tx4927_ccfg_set(__u64 bits)
245{
246 ____raw_writeq((____raw_readq(&tx4927_ccfgptr->ccfg)
247 & ~TX4927_CCFG_W1CBITS) | bits,
248 &tx4927_ccfgptr->ccfg);
249}
250static inline void tx4927_ccfg_change(__u64 change, __u64 new)
251{
252 ____raw_writeq((____raw_readq(&tx4927_ccfgptr->ccfg)
253 & ~(TX4927_CCFG_W1CBITS | change)) |
254 new,
255 &tx4927_ccfgptr->ccfg);
256}
257
258unsigned int tx4927_get_mem_size(void);
259void tx4927_wdt_init(void);
260void tx4927_setup(void);
261void tx4927_time_init(unsigned int tmrnr);
262void tx4927_sio_init(unsigned int sclk, unsigned int cts_mask);
263int tx4927_report_pciclk(void);
264int tx4927_pciclk66_setup(void);
265void tx4927_setup_pcierr_irq(void);
266void tx4927_irq_init(void);
267void tx4927_mtd_init(int ch);
268
269#endif /* __ASM_TXX9_TX4927_H */
diff --git a/arch/mips/include/asm/txx9/tx4927pcic.h b/arch/mips/include/asm/txx9/tx4927pcic.h
new file mode 100644
index 000000000000..c470b8a5fe57
--- /dev/null
+++ b/arch/mips/include/asm/txx9/tx4927pcic.h
@@ -0,0 +1,203 @@
1/*
2 * include/asm-mips/txx9/tx4927pcic.h
3 * TX4927 PCI controller definitions.
4 *
5 * This file is subject to the terms and conditions of the GNU General Public
6 * License. See the file "COPYING" in the main directory of this archive
7 * for more details.
8 */
9#ifndef __ASM_TXX9_TX4927PCIC_H
10#define __ASM_TXX9_TX4927PCIC_H
11
12#include <linux/pci.h>
13#include <linux/irqreturn.h>
14
15struct tx4927_pcic_reg {
16 u32 pciid;
17 u32 pcistatus;
18 u32 pciccrev;
19 u32 pcicfg1;
20 u32 p2gm0plbase; /* +10 */
21 u32 p2gm0pubase;
22 u32 p2gm1plbase;
23 u32 p2gm1pubase;
24 u32 p2gm2pbase; /* +20 */
25 u32 p2giopbase;
26 u32 unused0;
27 u32 pcisid;
28 u32 unused1; /* +30 */
29 u32 pcicapptr;
30 u32 unused2;
31 u32 pcicfg2;
32 u32 g2ptocnt; /* +40 */
33 u32 unused3[15];
34 u32 g2pstatus; /* +80 */
35 u32 g2pmask;
36 u32 pcisstatus;
37 u32 pcimask;
38 u32 p2gcfg; /* +90 */
39 u32 p2gstatus;
40 u32 p2gmask;
41 u32 p2gccmd;
42 u32 unused4[24]; /* +a0 */
43 u32 pbareqport; /* +100 */
44 u32 pbacfg;
45 u32 pbastatus;
46 u32 pbamask;
47 u32 pbabm; /* +110 */
48 u32 pbacreq;
49 u32 pbacgnt;
50 u32 pbacstate;
51 u64 g2pmgbase[3]; /* +120 */
52 u64 g2piogbase;
53 u32 g2pmmask[3]; /* +140 */
54 u32 g2piomask;
55 u64 g2pmpbase[3]; /* +150 */
56 u64 g2piopbase;
57 u32 pciccfg; /* +170 */
58 u32 pcicstatus;
59 u32 pcicmask;
60 u32 unused5;
61 u64 p2gmgbase[3]; /* +180 */
62 u64 p2giogbase;
63 u32 g2pcfgadrs; /* +1a0 */
64 u32 g2pcfgdata;
65 u32 unused6[8];
66 u32 g2pintack;
67 u32 g2pspc;
68 u32 unused7[12]; /* +1d0 */
69 u64 pdmca; /* +200 */
70 u64 pdmga;
71 u64 pdmpa;
72 u64 pdmctr;
73 u64 pdmcfg; /* +220 */
74 u64 pdmsts;
75};
76
77/* bits for PCICMD */
78/* see PCI_COMMAND_XXX in linux/pci_regs.h */
79
80/* bits for PCISTAT */
81/* see PCI_STATUS_XXX in linux/pci_regs.h */
82
83/* bits for IOBA/MBA */
84/* see PCI_BASE_ADDRESS_XXX in linux/pci_regs.h */
85
86/* bits for G2PSTATUS/G2PMASK */
87#define TX4927_PCIC_G2PSTATUS_ALL 0x00000003
88#define TX4927_PCIC_G2PSTATUS_TTOE 0x00000002
89#define TX4927_PCIC_G2PSTATUS_RTOE 0x00000001
90
91/* bits for PCIMASK (see also PCI_STATUS_XXX in linux/pci_regs.h */
92#define TX4927_PCIC_PCISTATUS_ALL 0x0000f900
93
94/* bits for PBACFG */
95#define TX4927_PCIC_PBACFG_FIXPA 0x00000008
96#define TX4927_PCIC_PBACFG_RPBA 0x00000004
97#define TX4927_PCIC_PBACFG_PBAEN 0x00000002
98#define TX4927_PCIC_PBACFG_BMCEN 0x00000001
99
100/* bits for PBASTATUS/PBAMASK */
101#define TX4927_PCIC_PBASTATUS_ALL 0x00000001
102#define TX4927_PCIC_PBASTATUS_BM 0x00000001
103
104/* bits for G2PMnGBASE */
105#define TX4927_PCIC_G2PMnGBASE_BSDIS 0x0000002000000000ULL
106#define TX4927_PCIC_G2PMnGBASE_ECHG 0x0000001000000000ULL
107
108/* bits for G2PIOGBASE */
109#define TX4927_PCIC_G2PIOGBASE_BSDIS 0x0000002000000000ULL
110#define TX4927_PCIC_G2PIOGBASE_ECHG 0x0000001000000000ULL
111
112/* bits for PCICSTATUS/PCICMASK */
113#define TX4927_PCIC_PCICSTATUS_ALL 0x000007b8
114#define TX4927_PCIC_PCICSTATUS_PME 0x00000400
115#define TX4927_PCIC_PCICSTATUS_TLB 0x00000200
116#define TX4927_PCIC_PCICSTATUS_NIB 0x00000100
117#define TX4927_PCIC_PCICSTATUS_ZIB 0x00000080
118#define TX4927_PCIC_PCICSTATUS_PERR 0x00000020
119#define TX4927_PCIC_PCICSTATUS_SERR 0x00000010
120#define TX4927_PCIC_PCICSTATUS_GBE 0x00000008
121#define TX4927_PCIC_PCICSTATUS_IWB 0x00000002
122#define TX4927_PCIC_PCICSTATUS_E2PDONE 0x00000001
123
124/* bits for PCICCFG */
125#define TX4927_PCIC_PCICCFG_GBWC_MASK 0x0fff0000
126#define TX4927_PCIC_PCICCFG_HRST 0x00000800
127#define TX4927_PCIC_PCICCFG_SRST 0x00000400
128#define TX4927_PCIC_PCICCFG_IRBER 0x00000200
129#define TX4927_PCIC_PCICCFG_G2PMEN(ch) (0x00000100>>(ch))
130#define TX4927_PCIC_PCICCFG_G2PM0EN 0x00000100
131#define TX4927_PCIC_PCICCFG_G2PM1EN 0x00000080
132#define TX4927_PCIC_PCICCFG_G2PM2EN 0x00000040
133#define TX4927_PCIC_PCICCFG_G2PIOEN 0x00000020
134#define TX4927_PCIC_PCICCFG_TCAR 0x00000010
135#define TX4927_PCIC_PCICCFG_ICAEN 0x00000008
136
137/* bits for P2GMnGBASE */
138#define TX4927_PCIC_P2GMnGBASE_TMEMEN 0x0000004000000000ULL
139#define TX4927_PCIC_P2GMnGBASE_TBSDIS 0x0000002000000000ULL
140#define TX4927_PCIC_P2GMnGBASE_TECHG 0x0000001000000000ULL
141
142/* bits for P2GIOGBASE */
143#define TX4927_PCIC_P2GIOGBASE_TIOEN 0x0000004000000000ULL
144#define TX4927_PCIC_P2GIOGBASE_TBSDIS 0x0000002000000000ULL
145#define TX4927_PCIC_P2GIOGBASE_TECHG 0x0000001000000000ULL
146
147#define TX4927_PCIC_IDSEL_AD_TO_SLOT(ad) ((ad) - 11)
148#define TX4927_PCIC_MAX_DEVNU TX4927_PCIC_IDSEL_AD_TO_SLOT(32)
149
150/* bits for PDMCFG */
151#define TX4927_PCIC_PDMCFG_RSTFIFO 0x00200000
152#define TX4927_PCIC_PDMCFG_EXFER 0x00100000
153#define TX4927_PCIC_PDMCFG_REQDLY_MASK 0x00003800
154#define TX4927_PCIC_PDMCFG_REQDLY_NONE (0 << 11)
155#define TX4927_PCIC_PDMCFG_REQDLY_16 (1 << 11)
156#define TX4927_PCIC_PDMCFG_REQDLY_32 (2 << 11)
157#define TX4927_PCIC_PDMCFG_REQDLY_64 (3 << 11)
158#define TX4927_PCIC_PDMCFG_REQDLY_128 (4 << 11)
159#define TX4927_PCIC_PDMCFG_REQDLY_256 (5 << 11)
160#define TX4927_PCIC_PDMCFG_REQDLY_512 (6 << 11)
161#define TX4927_PCIC_PDMCFG_REQDLY_1024 (7 << 11)
162#define TX4927_PCIC_PDMCFG_ERRIE 0x00000400
163#define TX4927_PCIC_PDMCFG_NCCMPIE 0x00000200
164#define TX4927_PCIC_PDMCFG_NTCMPIE 0x00000100
165#define TX4927_PCIC_PDMCFG_CHNEN 0x00000080
166#define TX4927_PCIC_PDMCFG_XFRACT 0x00000040
167#define TX4927_PCIC_PDMCFG_BSWAP 0x00000020
168#define TX4927_PCIC_PDMCFG_XFRSIZE_MASK 0x0000000c
169#define TX4927_PCIC_PDMCFG_XFRSIZE_1DW 0x00000000
170#define TX4927_PCIC_PDMCFG_XFRSIZE_1QW 0x00000004
171#define TX4927_PCIC_PDMCFG_XFRSIZE_4QW 0x00000008
172#define TX4927_PCIC_PDMCFG_XFRDIRC 0x00000002
173#define TX4927_PCIC_PDMCFG_CHRST 0x00000001
174
175/* bits for PDMSTS */
176#define TX4927_PCIC_PDMSTS_REQCNT_MASK 0x3f000000
177#define TX4927_PCIC_PDMSTS_FIFOCNT_MASK 0x00f00000
178#define TX4927_PCIC_PDMSTS_FIFOWP_MASK 0x000c0000
179#define TX4927_PCIC_PDMSTS_FIFORP_MASK 0x00030000
180#define TX4927_PCIC_PDMSTS_ERRINT 0x00000800
181#define TX4927_PCIC_PDMSTS_DONEINT 0x00000400
182#define TX4927_PCIC_PDMSTS_CHNEN 0x00000200
183#define TX4927_PCIC_PDMSTS_XFRACT 0x00000100
184#define TX4927_PCIC_PDMSTS_ACCMP 0x00000080
185#define TX4927_PCIC_PDMSTS_NCCMP 0x00000040
186#define TX4927_PCIC_PDMSTS_NTCMP 0x00000020
187#define TX4927_PCIC_PDMSTS_CFGERR 0x00000008
188#define TX4927_PCIC_PDMSTS_PCIERR 0x00000004
189#define TX4927_PCIC_PDMSTS_CHNERR 0x00000002
190#define TX4927_PCIC_PDMSTS_DATAERR 0x00000001
191#define TX4927_PCIC_PDMSTS_ALL_CMP 0x000000e0
192#define TX4927_PCIC_PDMSTS_ALL_ERR 0x0000000f
193
194struct tx4927_pcic_reg __iomem *get_tx4927_pcicptr(
195 struct pci_controller *channel);
196void tx4927_pcic_setup(struct tx4927_pcic_reg __iomem *pcicptr,
197 struct pci_controller *channel, int extarb);
198void tx4927_report_pcic_status(void);
199char *tx4927_pcibios_setup(char *str);
200void tx4927_dump_pcic_settings(void);
201irqreturn_t tx4927_pcierr_interrupt(int irq, void *dev_id);
202
203#endif /* __ASM_TXX9_TX4927PCIC_H */
diff --git a/arch/mips/include/asm/txx9/tx4938.h b/arch/mips/include/asm/txx9/tx4938.h
new file mode 100644
index 000000000000..989e7751135a
--- /dev/null
+++ b/arch/mips/include/asm/txx9/tx4938.h
@@ -0,0 +1,295 @@
1/*
2 * Definitions for TX4937/TX4938
3 * Copyright (C) 2000-2001 Toshiba Corporation
4 *
5 * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
6 * terms of the GNU General Public License version 2. This program is
7 * licensed "as is" without any warranty of any kind, whether express
8 * or implied.
9 *
10 * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
11 */
12#ifndef __ASM_TXX9_TX4938_H
13#define __ASM_TXX9_TX4938_H
14
15/* some controllers are compatible with 4927 */
16#include <asm/txx9/tx4927.h>
17
18#ifdef CONFIG_64BIT
19#define TX4938_REG_BASE 0xffffffffff1f0000UL /* == TX4937_REG_BASE */
20#else
21#define TX4938_REG_BASE 0xff1f0000UL /* == TX4937_REG_BASE */
22#endif
23#define TX4938_REG_SIZE 0x00010000 /* == TX4937_REG_SIZE */
24
25/* NDFMC, SRAMC, PCIC1, SPIC: TX4938 only */
26#define TX4938_NDFMC_REG (TX4938_REG_BASE + 0x5000)
27#define TX4938_SRAMC_REG (TX4938_REG_BASE + 0x6000)
28#define TX4938_PCIC1_REG (TX4938_REG_BASE + 0x7000)
29#define TX4938_SDRAMC_REG (TX4938_REG_BASE + 0x8000)
30#define TX4938_EBUSC_REG (TX4938_REG_BASE + 0x9000)
31#define TX4938_DMA_REG(ch) (TX4938_REG_BASE + 0xb000 + (ch) * 0x800)
32#define TX4938_PCIC_REG (TX4938_REG_BASE + 0xd000)
33#define TX4938_CCFG_REG (TX4938_REG_BASE + 0xe000)
34#define TX4938_NR_TMR 3
35#define TX4938_TMR_REG(ch) ((TX4938_REG_BASE + 0xf000) + (ch) * 0x100)
36#define TX4938_NR_SIO 2
37#define TX4938_SIO_REG(ch) ((TX4938_REG_BASE + 0xf300) + (ch) * 0x100)
38#define TX4938_PIO_REG (TX4938_REG_BASE + 0xf500)
39#define TX4938_IRC_REG (TX4938_REG_BASE + 0xf600)
40#define TX4938_ACLC_REG (TX4938_REG_BASE + 0xf700)
41#define TX4938_SPI_REG (TX4938_REG_BASE + 0xf800)
42
43struct tx4938_sramc_reg {
44 u64 cr;
45};
46
47struct tx4938_ccfg_reg {
48 u64 ccfg;
49 u64 crir;
50 u64 pcfg;
51 u64 toea;
52 u64 clkctr;
53 u64 unused0;
54 u64 garbc;
55 u64 unused1;
56 u64 unused2;
57 u64 ramp;
58 u64 unused3;
59 u64 jmpadr;
60};
61
62/*
63 * IRC
64 */
65
66#define TX4938_IR_ECCERR 0
67#define TX4938_IR_WTOERR 1
68#define TX4938_NUM_IR_INT 6
69#define TX4938_IR_INT(n) (2 + (n))
70#define TX4938_NUM_IR_SIO 2
71#define TX4938_IR_SIO(n) (8 + (n))
72#define TX4938_NUM_IR_DMA 4
73#define TX4938_IR_DMA(ch, n) ((ch ? 27 : 10) + (n)) /* 10-13, 27-30 */
74#define TX4938_IR_PIO 14
75#define TX4938_IR_PDMAC 15
76#define TX4938_IR_PCIC 16
77#define TX4938_NUM_IR_TMR 3
78#define TX4938_IR_TMR(n) (17 + (n))
79#define TX4938_IR_NDFMC 21
80#define TX4938_IR_PCIERR 22
81#define TX4938_IR_PCIPME 23
82#define TX4938_IR_ACLC 24
83#define TX4938_IR_ACLCPME 25
84#define TX4938_IR_PCIC1 26
85#define TX4938_IR_SPI 31
86#define TX4938_NUM_IR 32
87/* multiplex */
88#define TX4938_IR_ETH0 TX4938_IR_INT(4)
89#define TX4938_IR_ETH1 TX4938_IR_INT(3)
90
91#define TX4938_IRC_INT 2 /* IP[2] in Status register */
92
93#define TX4938_NUM_PIO 16
94
95/*
96 * CCFG
97 */
98/* CCFG : Chip Configuration */
99#define TX4938_CCFG_WDRST 0x0000020000000000ULL
100#define TX4938_CCFG_WDREXEN 0x0000010000000000ULL
101#define TX4938_CCFG_BCFG_MASK 0x000000ff00000000ULL
102#define TX4938_CCFG_TINTDIS 0x01000000
103#define TX4938_CCFG_PCI66 0x00800000
104#define TX4938_CCFG_PCIMODE 0x00400000
105#define TX4938_CCFG_PCI1_66 0x00200000
106#define TX4938_CCFG_DIVMODE_MASK 0x001e0000
107#define TX4938_CCFG_DIVMODE_2 (0x4 << 17)
108#define TX4938_CCFG_DIVMODE_2_5 (0xf << 17)
109#define TX4938_CCFG_DIVMODE_3 (0x5 << 17)
110#define TX4938_CCFG_DIVMODE_4 (0x6 << 17)
111#define TX4938_CCFG_DIVMODE_4_5 (0xd << 17)
112#define TX4938_CCFG_DIVMODE_8 (0x0 << 17)
113#define TX4938_CCFG_DIVMODE_10 (0xb << 17)
114#define TX4938_CCFG_DIVMODE_12 (0x1 << 17)
115#define TX4938_CCFG_DIVMODE_16 (0x2 << 17)
116#define TX4938_CCFG_DIVMODE_18 (0x9 << 17)
117#define TX4938_CCFG_BEOW 0x00010000
118#define TX4938_CCFG_WR 0x00008000
119#define TX4938_CCFG_TOE 0x00004000
120#define TX4938_CCFG_PCIARB 0x00002000
121#define TX4938_CCFG_PCIDIVMODE_MASK 0x00001c00
122#define TX4938_CCFG_PCIDIVMODE_4 (0x1 << 10)
123#define TX4938_CCFG_PCIDIVMODE_4_5 (0x3 << 10)
124#define TX4938_CCFG_PCIDIVMODE_5 (0x5 << 10)
125#define TX4938_CCFG_PCIDIVMODE_5_5 (0x7 << 10)
126#define TX4938_CCFG_PCIDIVMODE_8 (0x0 << 10)
127#define TX4938_CCFG_PCIDIVMODE_9 (0x2 << 10)
128#define TX4938_CCFG_PCIDIVMODE_10 (0x4 << 10)
129#define TX4938_CCFG_PCIDIVMODE_11 (0x6 << 10)
130#define TX4938_CCFG_PCI1DMD 0x00000100
131#define TX4938_CCFG_SYSSP_MASK 0x000000c0
132#define TX4938_CCFG_ENDIAN 0x00000004
133#define TX4938_CCFG_HALT 0x00000002
134#define TX4938_CCFG_ACEHOLD 0x00000001
135
136/* PCFG : Pin Configuration */
137#define TX4938_PCFG_ETH0_SEL 0x8000000000000000ULL
138#define TX4938_PCFG_ETH1_SEL 0x4000000000000000ULL
139#define TX4938_PCFG_ATA_SEL 0x2000000000000000ULL
140#define TX4938_PCFG_ISA_SEL 0x1000000000000000ULL
141#define TX4938_PCFG_SPI_SEL 0x0800000000000000ULL
142#define TX4938_PCFG_NDF_SEL 0x0400000000000000ULL
143#define TX4938_PCFG_SDCLKDLY_MASK 0x30000000
144#define TX4938_PCFG_SDCLKDLY(d) ((d)<<28)
145#define TX4938_PCFG_SYSCLKEN 0x08000000
146#define TX4938_PCFG_SDCLKEN_ALL 0x07800000
147#define TX4938_PCFG_SDCLKEN(ch) (0x00800000<<(ch))
148#define TX4938_PCFG_PCICLKEN_ALL 0x003f0000
149#define TX4938_PCFG_PCICLKEN(ch) (0x00010000<<(ch))
150#define TX4938_PCFG_SEL2 0x00000200
151#define TX4938_PCFG_SEL1 0x00000100
152#define TX4938_PCFG_DMASEL_ALL 0x0000000f
153#define TX4938_PCFG_DMASEL0_DRQ0 0x00000000
154#define TX4938_PCFG_DMASEL0_SIO1 0x00000001
155#define TX4938_PCFG_DMASEL1_DRQ1 0x00000000
156#define TX4938_PCFG_DMASEL1_SIO1 0x00000002
157#define TX4938_PCFG_DMASEL2_DRQ2 0x00000000
158#define TX4938_PCFG_DMASEL2_SIO0 0x00000004
159#define TX4938_PCFG_DMASEL3_DRQ3 0x00000000
160#define TX4938_PCFG_DMASEL3_SIO0 0x00000008
161
162/* CLKCTR : Clock Control */
163#define TX4938_CLKCTR_NDFCKD 0x0001000000000000ULL
164#define TX4938_CLKCTR_NDFRST 0x0000000100000000ULL
165#define TX4938_CLKCTR_ETH1CKD 0x80000000
166#define TX4938_CLKCTR_ETH0CKD 0x40000000
167#define TX4938_CLKCTR_SPICKD 0x20000000
168#define TX4938_CLKCTR_SRAMCKD 0x10000000
169#define TX4938_CLKCTR_PCIC1CKD 0x08000000
170#define TX4938_CLKCTR_DMA1CKD 0x04000000
171#define TX4938_CLKCTR_ACLCKD 0x02000000
172#define TX4938_CLKCTR_PIOCKD 0x01000000
173#define TX4938_CLKCTR_DMACKD 0x00800000
174#define TX4938_CLKCTR_PCICKD 0x00400000
175#define TX4938_CLKCTR_TM0CKD 0x00100000
176#define TX4938_CLKCTR_TM1CKD 0x00080000
177#define TX4938_CLKCTR_TM2CKD 0x00040000
178#define TX4938_CLKCTR_SIO0CKD 0x00020000
179#define TX4938_CLKCTR_SIO1CKD 0x00010000
180#define TX4938_CLKCTR_ETH1RST 0x00008000
181#define TX4938_CLKCTR_ETH0RST 0x00004000
182#define TX4938_CLKCTR_SPIRST 0x00002000
183#define TX4938_CLKCTR_SRAMRST 0x00001000
184#define TX4938_CLKCTR_PCIC1RST 0x00000800
185#define TX4938_CLKCTR_DMA1RST 0x00000400
186#define TX4938_CLKCTR_ACLRST 0x00000200
187#define TX4938_CLKCTR_PIORST 0x00000100
188#define TX4938_CLKCTR_DMARST 0x00000080
189#define TX4938_CLKCTR_PCIRST 0x00000040
190#define TX4938_CLKCTR_TM0RST 0x00000010
191#define TX4938_CLKCTR_TM1RST 0x00000008
192#define TX4938_CLKCTR_TM2RST 0x00000004
193#define TX4938_CLKCTR_SIO0RST 0x00000002
194#define TX4938_CLKCTR_SIO1RST 0x00000001
195
196/*
197 * DMA
198 */
199/* bits for MCR */
200#define TX4938_DMA_MCR_EIS(ch) (0x10000000<<(ch))
201#define TX4938_DMA_MCR_DIS(ch) (0x01000000<<(ch))
202#define TX4938_DMA_MCR_RSFIF 0x00000080
203#define TX4938_DMA_MCR_FIFUM(ch) (0x00000008<<(ch))
204#define TX4938_DMA_MCR_RPRT 0x00000002
205#define TX4938_DMA_MCR_MSTEN 0x00000001
206
207/* bits for CCRn */
208#define TX4938_DMA_CCR_IMMCHN 0x20000000
209#define TX4938_DMA_CCR_USEXFSZ 0x10000000
210#define TX4938_DMA_CCR_LE 0x08000000
211#define TX4938_DMA_CCR_DBINH 0x04000000
212#define TX4938_DMA_CCR_SBINH 0x02000000
213#define TX4938_DMA_CCR_CHRST 0x01000000
214#define TX4938_DMA_CCR_RVBYTE 0x00800000
215#define TX4938_DMA_CCR_ACKPOL 0x00400000
216#define TX4938_DMA_CCR_REQPL 0x00200000
217#define TX4938_DMA_CCR_EGREQ 0x00100000
218#define TX4938_DMA_CCR_CHDN 0x00080000
219#define TX4938_DMA_CCR_DNCTL 0x00060000
220#define TX4938_DMA_CCR_EXTRQ 0x00010000
221#define TX4938_DMA_CCR_INTRQD 0x0000e000
222#define TX4938_DMA_CCR_INTENE 0x00001000
223#define TX4938_DMA_CCR_INTENC 0x00000800
224#define TX4938_DMA_CCR_INTENT 0x00000400
225#define TX4938_DMA_CCR_CHNEN 0x00000200
226#define TX4938_DMA_CCR_XFACT 0x00000100
227#define TX4938_DMA_CCR_SMPCHN 0x00000020
228#define TX4938_DMA_CCR_XFSZ(order) (((order) << 2) & 0x0000001c)
229#define TX4938_DMA_CCR_XFSZ_1W TX4938_DMA_CCR_XFSZ(2)
230#define TX4938_DMA_CCR_XFSZ_2W TX4938_DMA_CCR_XFSZ(3)
231#define TX4938_DMA_CCR_XFSZ_4W TX4938_DMA_CCR_XFSZ(4)
232#define TX4938_DMA_CCR_XFSZ_8W TX4938_DMA_CCR_XFSZ(5)
233#define TX4938_DMA_CCR_XFSZ_16W TX4938_DMA_CCR_XFSZ(6)
234#define TX4938_DMA_CCR_XFSZ_32W TX4938_DMA_CCR_XFSZ(7)
235#define TX4938_DMA_CCR_MEMIO 0x00000002
236#define TX4938_DMA_CCR_SNGAD 0x00000001
237
238/* bits for CSRn */
239#define TX4938_DMA_CSR_CHNEN 0x00000400
240#define TX4938_DMA_CSR_STLXFER 0x00000200
241#define TX4938_DMA_CSR_CHNACT 0x00000100
242#define TX4938_DMA_CSR_ABCHC 0x00000080
243#define TX4938_DMA_CSR_NCHNC 0x00000040
244#define TX4938_DMA_CSR_NTRNFC 0x00000020
245#define TX4938_DMA_CSR_EXTDN 0x00000010
246#define TX4938_DMA_CSR_CFERR 0x00000008
247#define TX4938_DMA_CSR_CHERR 0x00000004
248#define TX4938_DMA_CSR_DESERR 0x00000002
249#define TX4938_DMA_CSR_SORERR 0x00000001
250
251#define tx4938_sdramcptr tx4927_sdramcptr
252#define tx4938_ebuscptr tx4927_ebuscptr
253#define tx4938_pcicptr tx4927_pcicptr
254#define tx4938_pcic1ptr \
255 ((struct tx4927_pcic_reg __iomem *)TX4938_PCIC1_REG)
256#define tx4938_ccfgptr \
257 ((struct tx4938_ccfg_reg __iomem *)TX4938_CCFG_REG)
258#define tx4938_pioptr ((struct txx9_pio_reg __iomem *)TX4938_PIO_REG)
259#define tx4938_sramcptr \
260 ((struct tx4938_sramc_reg __iomem *)TX4938_SRAMC_REG)
261
262
263#define TX4938_REV_PCODE() \
264 ((__u32)__raw_readq(&tx4938_ccfgptr->crir) >> 16)
265
266#define tx4938_ccfg_clear(bits) tx4927_ccfg_clear(bits)
267#define tx4938_ccfg_set(bits) tx4927_ccfg_set(bits)
268#define tx4938_ccfg_change(change, new) tx4927_ccfg_change(change, new)
269
270#define TX4938_SDRAMC_CR(ch) TX4927_SDRAMC_CR(ch)
271#define TX4938_SDRAMC_BA(ch) TX4927_SDRAMC_BA(ch)
272#define TX4938_SDRAMC_SIZE(ch) TX4927_SDRAMC_SIZE(ch)
273
274#define TX4938_EBUSC_CR(ch) TX4927_EBUSC_CR(ch)
275#define TX4938_EBUSC_BA(ch) TX4927_EBUSC_BA(ch)
276#define TX4938_EBUSC_SIZE(ch) TX4927_EBUSC_SIZE(ch)
277#define TX4938_EBUSC_WIDTH(ch) TX4927_EBUSC_WIDTH(ch)
278
279#define tx4938_get_mem_size() tx4927_get_mem_size()
280void tx4938_wdt_init(void);
281void tx4938_setup(void);
282void tx4938_time_init(unsigned int tmrnr);
283void tx4938_sio_init(unsigned int sclk, unsigned int cts_mask);
284void tx4938_spi_init(int busid);
285void tx4938_ethaddr_init(unsigned char *addr0, unsigned char *addr1);
286int tx4938_report_pciclk(void);
287void tx4938_report_pci1clk(void);
288int tx4938_pciclk66_setup(void);
289struct pci_dev;
290int tx4938_pcic1_map_irq(const struct pci_dev *dev, u8 slot);
291void tx4938_setup_pcierr_irq(void);
292void tx4938_irq_init(void);
293void tx4938_mtd_init(int ch);
294
295#endif
diff --git a/arch/mips/include/asm/txx9/tx4939.h b/arch/mips/include/asm/txx9/tx4939.h
new file mode 100644
index 000000000000..88badb423010
--- /dev/null
+++ b/arch/mips/include/asm/txx9/tx4939.h
@@ -0,0 +1,545 @@
1/*
2 * Definitions for TX4939
3 *
4 * Copyright (C) 2000-2001,2005-2006 Toshiba Corporation
5 * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
6 * terms of the GNU General Public License version 2. This program is
7 * licensed "as is" without any warranty of any kind, whether express
8 * or implied.
9 */
10#ifndef __ASM_TXX9_TX4939_H
11#define __ASM_TXX9_TX4939_H
12
13/* some controllers are compatible with 4927/4938 */
14#include <asm/txx9/tx4938.h>
15
16#ifdef CONFIG_64BIT
17#define TX4939_REG_BASE 0xffffffffff1f0000UL /* == TX4938_REG_BASE */
18#else
19#define TX4939_REG_BASE 0xff1f0000UL /* == TX4938_REG_BASE */
20#endif
21#define TX4939_REG_SIZE 0x00010000 /* == TX4938_REG_SIZE */
22
23#define TX4939_ATA_REG(ch) (TX4939_REG_BASE + 0x3000 + (ch) * 0x1000)
24#define TX4939_NDFMC_REG (TX4939_REG_BASE + 0x5000)
25#define TX4939_SRAMC_REG (TX4939_REG_BASE + 0x6000)
26#define TX4939_CRYPTO_REG (TX4939_REG_BASE + 0x6800)
27#define TX4939_PCIC1_REG (TX4939_REG_BASE + 0x7000)
28#define TX4939_DDRC_REG (TX4939_REG_BASE + 0x8000)
29#define TX4939_EBUSC_REG (TX4939_REG_BASE + 0x9000)
30#define TX4939_VPC_REG (TX4939_REG_BASE + 0xa000)
31#define TX4939_DMA_REG(ch) (TX4939_REG_BASE + 0xb000 + (ch) * 0x800)
32#define TX4939_PCIC_REG (TX4939_REG_BASE + 0xd000)
33#define TX4939_CCFG_REG (TX4939_REG_BASE + 0xe000)
34#define TX4939_IRC_REG (TX4939_REG_BASE + 0xe800)
35#define TX4939_NR_TMR 6 /* 0xf000,0xf100,0xf200,0xfd00,0xfe00,0xff00 */
36#define TX4939_TMR_REG(ch) \
37 (TX4939_REG_BASE + 0xf000 + ((ch) + ((ch) >= 3) * 10) * 0x100)
38#define TX4939_NR_SIO 4 /* 0xf300, 0xf400, 0xf380, 0xf480 */
39#define TX4939_SIO_REG(ch) \
40 (TX4939_REG_BASE + 0xf300 + (((ch) & 1) << 8) + (((ch) & 2) << 6))
41#define TX4939_ACLC_REG (TX4939_REG_BASE + 0xf700)
42#define TX4939_SPI_REG (TX4939_REG_BASE + 0xf800)
43#define TX4939_I2C_REG (TX4939_REG_BASE + 0xf900)
44#define TX4939_I2S_REG (TX4939_REG_BASE + 0xfa00)
45#define TX4939_RTC_REG (TX4939_REG_BASE + 0xfb00)
46#define TX4939_CIR_REG (TX4939_REG_BASE + 0xfc00)
47
48struct tx4939_le_reg {
49 __u32 r;
50 __u32 unused;
51};
52
53struct tx4939_ddrc_reg {
54 struct tx4939_le_reg ctl[47];
55 __u64 unused0[17];
56 __u64 winen;
57 __u64 win[4];
58};
59
60struct tx4939_ccfg_reg {
61 __u64 ccfg;
62 __u64 crir;
63 __u64 pcfg;
64 __u64 toea;
65 __u64 clkctr;
66 __u64 unused0;
67 __u64 garbc;
68 __u64 unused1[2];
69 __u64 ramp;
70 __u64 unused2[2];
71 __u64 dskwctrl;
72 __u64 mclkosc;
73 __u64 mclkctl;
74 __u64 unused3[17];
75 struct {
76 __u64 mr;
77 __u64 dr;
78 } gpio[2];
79};
80
81struct tx4939_irc_reg {
82 struct tx4939_le_reg den;
83 struct tx4939_le_reg scipb;
84 struct tx4939_le_reg dm[2];
85 struct tx4939_le_reg lvl[16];
86 struct tx4939_le_reg msk;
87 struct tx4939_le_reg edc;
88 struct tx4939_le_reg pnd0;
89 struct tx4939_le_reg cs;
90 struct tx4939_le_reg pnd1;
91 struct tx4939_le_reg dm2[2];
92 struct tx4939_le_reg dbr[2];
93 struct tx4939_le_reg dben;
94 struct tx4939_le_reg unused0[2];
95 struct tx4939_le_reg flag[2];
96 struct tx4939_le_reg pol;
97 struct tx4939_le_reg cnt;
98 struct tx4939_le_reg maskint;
99 struct tx4939_le_reg maskext;
100};
101
102struct tx4939_rtc_reg {
103 __u32 ctl;
104 __u32 adr;
105 __u32 dat;
106 __u32 tbc;
107};
108
109struct tx4939_crypto_reg {
110 struct tx4939_le_reg csr;
111 struct tx4939_le_reg idesptr;
112 struct tx4939_le_reg cdesptr;
113 struct tx4939_le_reg buserr;
114 struct tx4939_le_reg cip_tout;
115 struct tx4939_le_reg cir;
116 union {
117 struct {
118 struct tx4939_le_reg data[8];
119 struct tx4939_le_reg ctrl;
120 } gen;
121 struct {
122 struct {
123 struct tx4939_le_reg l;
124 struct tx4939_le_reg u;
125 } key[3], ini;
126 struct tx4939_le_reg ctrl;
127 } des;
128 struct {
129 struct tx4939_le_reg key[4];
130 struct tx4939_le_reg ini[4];
131 struct tx4939_le_reg ctrl;
132 } aes;
133 struct {
134 struct {
135 struct tx4939_le_reg l;
136 struct tx4939_le_reg u;
137 } cnt;
138 struct tx4939_le_reg ini[5];
139 struct tx4939_le_reg unused;
140 struct tx4939_le_reg ctrl;
141 } hash;
142 } cdr;
143 struct tx4939_le_reg unused0[7];
144 struct tx4939_le_reg rcsr;
145 struct tx4939_le_reg rpr;
146 __u64 rdr;
147 __u64 ror[3];
148 struct tx4939_le_reg unused1[2];
149 struct tx4939_le_reg xorslr;
150 struct tx4939_le_reg xorsur;
151};
152
153struct tx4939_crypto_desc {
154 __u32 src;
155 __u32 dst;
156 __u32 next;
157 __u32 ctrl;
158 __u32 index;
159 __u32 xor;
160};
161
162struct tx4939_vpc_reg {
163 struct tx4939_le_reg csr;
164 struct {
165 struct tx4939_le_reg ctrlA;
166 struct tx4939_le_reg ctrlB;
167 struct tx4939_le_reg idesptr;
168 struct tx4939_le_reg cdesptr;
169 } port[3];
170 struct tx4939_le_reg buserr;
171};
172
173struct tx4939_vpc_desc {
174 __u32 src;
175 __u32 next;
176 __u32 ctrl1;
177 __u32 ctrl2;
178};
179
180/*
181 * IRC
182 */
183#define TX4939_IR_NONE 0
184#define TX4939_IR_DDR 1
185#define TX4939_IR_WTOERR 2
186#define TX4939_NUM_IR_INT 3
187#define TX4939_IR_INT(n) (3 + (n))
188#define TX4939_NUM_IR_ETH 2
189#define TX4939_IR_ETH(n) ((n) ? 43 : 6)
190#define TX4939_IR_VIDEO 7
191#define TX4939_IR_CIR 8
192#define TX4939_NUM_IR_SIO 4
193#define TX4939_IR_SIO(n) ((n) ? 43 + (n) : 9) /* 9,44-46 */
194#define TX4939_NUM_IR_DMA 4
195#define TX4939_IR_DMA(ch, n) (((ch) ? 22 : 10) + (n)) /* 10-13,22-25 */
196#define TX4939_IR_IRC 14
197#define TX4939_IR_PDMAC 15
198#define TX4939_NUM_IR_TMR 6
199#define TX4939_IR_TMR(n) (((n) >= 3 ? 45 : 16) + (n)) /* 16-18,48-50 */
200#define TX4939_NUM_IR_ATA 2
201#define TX4939_IR_ATA(n) (19 + (n))
202#define TX4939_IR_ACLC 21
203#define TX4939_IR_CIPHER 26
204#define TX4939_IR_INTA 27
205#define TX4939_IR_INTB 28
206#define TX4939_IR_INTC 29
207#define TX4939_IR_INTD 30
208#define TX4939_IR_I2C 33
209#define TX4939_IR_SPI 34
210#define TX4939_IR_PCIC 35
211#define TX4939_IR_PCIC1 36
212#define TX4939_IR_PCIERR 37
213#define TX4939_IR_PCIPME 38
214#define TX4939_IR_NDFMC 39
215#define TX4939_IR_ACLCPME 40
216#define TX4939_IR_RTC 41
217#define TX4939_IR_RND 42
218#define TX4939_IR_I2S 47
219#define TX4939_NUM_IR 64
220
221#define TX4939_IRC_INT 2 /* IP[2] in Status register */
222
223/*
224 * CCFG
225 */
226/* CCFG : Chip Configuration */
227#define TX4939_CCFG_PCIBOOT 0x0000040000000000ULL
228#define TX4939_CCFG_WDRST 0x0000020000000000ULL
229#define TX4939_CCFG_WDREXEN 0x0000010000000000ULL
230#define TX4939_CCFG_BCFG_MASK 0x000000ff00000000ULL
231#define TX4939_CCFG_GTOT_MASK 0x06000000
232#define TX4939_CCFG_GTOT_4096 0x06000000
233#define TX4939_CCFG_GTOT_2048 0x04000000
234#define TX4939_CCFG_GTOT_1024 0x02000000
235#define TX4939_CCFG_GTOT_512 0x00000000
236#define TX4939_CCFG_TINTDIS 0x01000000
237#define TX4939_CCFG_PCI66 0x00800000
238#define TX4939_CCFG_PCIMODE 0x00400000
239#define TX4939_CCFG_SSCG 0x00100000
240#define TX4939_CCFG_MULCLK_MASK 0x000e0000
241#define TX4939_CCFG_MULCLK_8 (0x7 << 17)
242#define TX4939_CCFG_MULCLK_9 (0x0 << 17)
243#define TX4939_CCFG_MULCLK_10 (0x1 << 17)
244#define TX4939_CCFG_MULCLK_11 (0x2 << 17)
245#define TX4939_CCFG_MULCLK_12 (0x3 << 17)
246#define TX4939_CCFG_MULCLK_13 (0x4 << 17)
247#define TX4939_CCFG_MULCLK_14 (0x5 << 17)
248#define TX4939_CCFG_MULCLK_15 (0x6 << 17)
249#define TX4939_CCFG_BEOW 0x00010000
250#define TX4939_CCFG_WR 0x00008000
251#define TX4939_CCFG_TOE 0x00004000
252#define TX4939_CCFG_PCIARB 0x00002000
253#define TX4939_CCFG_YDIVMODE_MASK 0x00001c00
254#define TX4939_CCFG_YDIVMODE_2 (0x0 << 10)
255#define TX4939_CCFG_YDIVMODE_3 (0x1 << 10)
256#define TX4939_CCFG_YDIVMODE_5 (0x6 << 10)
257#define TX4939_CCFG_YDIVMODE_6 (0x7 << 10)
258#define TX4939_CCFG_PTSEL 0x00000200
259#define TX4939_CCFG_BESEL 0x00000100
260#define TX4939_CCFG_SYSSP_MASK 0x000000c0
261#define TX4939_CCFG_ACKSEL 0x00000020
262#define TX4939_CCFG_ROMW 0x00000010
263#define TX4939_CCFG_ENDIAN 0x00000004
264#define TX4939_CCFG_ARMODE 0x00000002
265#define TX4939_CCFG_ACEHOLD 0x00000001
266
267/* PCFG : Pin Configuration */
268#define TX4939_PCFG_SIO2MODE_MASK 0xc000000000000000ULL
269#define TX4939_PCFG_SIO2MODE_GPIO 0x8000000000000000ULL
270#define TX4939_PCFG_SIO2MODE_SIO2 0x4000000000000000ULL
271#define TX4939_PCFG_SIO2MODE_SIO0 0x0000000000000000ULL
272#define TX4939_PCFG_SPIMODE 0x2000000000000000ULL
273#define TX4939_PCFG_I2CMODE 0x1000000000000000ULL
274#define TX4939_PCFG_I2SMODE_MASK 0x0c00000000000000ULL
275#define TX4939_PCFG_I2SMODE_GPIO 0x0c00000000000000ULL
276#define TX4939_PCFG_I2SMODE_I2S 0x0800000000000000ULL
277#define TX4939_PCFG_I2SMODE_I2S_ALT 0x0400000000000000ULL
278#define TX4939_PCFG_I2SMODE_ACLC 0x0000000000000000ULL
279#define TX4939_PCFG_SIO3MODE 0x0200000000000000ULL
280#define TX4939_PCFG_DMASEL3 0x0004000000000000ULL
281#define TX4939_PCFG_DMASEL3_SIO0 0x0004000000000000ULL
282#define TX4939_PCFG_DMASEL3_NDFC 0x0000000000000000ULL
283#define TX4939_PCFG_VSSMODE 0x0000200000000000ULL
284#define TX4939_PCFG_VPSMODE 0x0000100000000000ULL
285#define TX4939_PCFG_ET1MODE 0x0000080000000000ULL
286#define TX4939_PCFG_ET0MODE 0x0000040000000000ULL
287#define TX4939_PCFG_ATA1MODE 0x0000020000000000ULL
288#define TX4939_PCFG_ATA0MODE 0x0000010000000000ULL
289#define TX4939_PCFG_BP_PLL 0x0000000100000000ULL
290
291#define TX4939_PCFG_SYSCLKEN 0x08000000
292#define TX4939_PCFG_PCICLKEN_ALL 0x000f0000
293#define TX4939_PCFG_PCICLKEN(ch) (0x00010000<<(ch))
294#define TX4939_PCFG_SPEED1 0x00002000
295#define TX4939_PCFG_SPEED0 0x00001000
296#define TX4939_PCFG_ITMODE 0x00000300
297#define TX4939_PCFG_DMASEL_ALL (0x00000007 | TX4939_PCFG_DMASEL3)
298#define TX4939_PCFG_DMASEL2 0x00000004
299#define TX4939_PCFG_DMASEL2_DRQ2 0x00000000
300#define TX4939_PCFG_DMASEL2_SIO0 0x00000004
301#define TX4939_PCFG_DMASEL1 0x00000002
302#define TX4939_PCFG_DMASEL1_DRQ1 0x00000000
303#define TX4939_PCFG_DMASEL0 0x00000001
304#define TX4939_PCFG_DMASEL0_DRQ0 0x00000000
305
306/* CLKCTR : Clock Control */
307#define TX4939_CLKCTR_IOSCKD 0x8000000000000000ULL
308#define TX4939_CLKCTR_SYSCKD 0x4000000000000000ULL
309#define TX4939_CLKCTR_TM5CKD 0x2000000000000000ULL
310#define TX4939_CLKCTR_TM4CKD 0x1000000000000000ULL
311#define TX4939_CLKCTR_TM3CKD 0x0800000000000000ULL
312#define TX4939_CLKCTR_CIRCKD 0x0400000000000000ULL
313#define TX4939_CLKCTR_SIO3CKD 0x0200000000000000ULL
314#define TX4939_CLKCTR_SIO2CKD 0x0100000000000000ULL
315#define TX4939_CLKCTR_SIO1CKD 0x0080000000000000ULL
316#define TX4939_CLKCTR_VPCCKD 0x0040000000000000ULL
317#define TX4939_CLKCTR_EPCICKD 0x0020000000000000ULL
318#define TX4939_CLKCTR_ETH1CKD 0x0008000000000000ULL
319#define TX4939_CLKCTR_ATA1CKD 0x0004000000000000ULL
320#define TX4939_CLKCTR_BROMCKD 0x0002000000000000ULL
321#define TX4939_CLKCTR_NDCCKD 0x0001000000000000ULL
322#define TX4939_CLKCTR_I2CCKD 0x0000800000000000ULL
323#define TX4939_CLKCTR_ETH0CKD 0x0000400000000000ULL
324#define TX4939_CLKCTR_SPICKD 0x0000200000000000ULL
325#define TX4939_CLKCTR_SRAMCKD 0x0000100000000000ULL
326#define TX4939_CLKCTR_PCI1CKD 0x0000080000000000ULL
327#define TX4939_CLKCTR_DMA1CKD 0x0000040000000000ULL
328#define TX4939_CLKCTR_ACLCKD 0x0000020000000000ULL
329#define TX4939_CLKCTR_ATA0CKD 0x0000010000000000ULL
330#define TX4939_CLKCTR_DMA0CKD 0x0000008000000000ULL
331#define TX4939_CLKCTR_PCICCKD 0x0000004000000000ULL
332#define TX4939_CLKCTR_I2SCKD 0x0000002000000000ULL
333#define TX4939_CLKCTR_TM0CKD 0x0000001000000000ULL
334#define TX4939_CLKCTR_TM1CKD 0x0000000800000000ULL
335#define TX4939_CLKCTR_TM2CKD 0x0000000400000000ULL
336#define TX4939_CLKCTR_SIO0CKD 0x0000000200000000ULL
337#define TX4939_CLKCTR_CYPCKD 0x0000000100000000ULL
338#define TX4939_CLKCTR_IOSRST 0x80000000
339#define TX4939_CLKCTR_SYSRST 0x40000000
340#define TX4939_CLKCTR_TM5RST 0x20000000
341#define TX4939_CLKCTR_TM4RST 0x10000000
342#define TX4939_CLKCTR_TM3RST 0x08000000
343#define TX4939_CLKCTR_CIRRST 0x04000000
344#define TX4939_CLKCTR_SIO3RST 0x02000000
345#define TX4939_CLKCTR_SIO2RST 0x01000000
346#define TX4939_CLKCTR_SIO1RST 0x00800000
347#define TX4939_CLKCTR_VPCRST 0x00400000
348#define TX4939_CLKCTR_EPCIRST 0x00200000
349#define TX4939_CLKCTR_ETH1RST 0x00080000
350#define TX4939_CLKCTR_ATA1RST 0x00040000
351#define TX4939_CLKCTR_BROMRST 0x00020000
352#define TX4939_CLKCTR_NDCRST 0x00010000
353#define TX4939_CLKCTR_I2CRST 0x00008000
354#define TX4939_CLKCTR_ETH0RST 0x00004000
355#define TX4939_CLKCTR_SPIRST 0x00002000
356#define TX4939_CLKCTR_SRAMRST 0x00001000
357#define TX4939_CLKCTR_PCI1RST 0x00000800
358#define TX4939_CLKCTR_DMA1RST 0x00000400
359#define TX4939_CLKCTR_ACLRST 0x00000200
360#define TX4939_CLKCTR_ATA0RST 0x00000100
361#define TX4939_CLKCTR_DMA0RST 0x00000080
362#define TX4939_CLKCTR_PCICRST 0x00000040
363#define TX4939_CLKCTR_I2SRST 0x00000020
364#define TX4939_CLKCTR_TM0RST 0x00000010
365#define TX4939_CLKCTR_TM1RST 0x00000008
366#define TX4939_CLKCTR_TM2RST 0x00000004
367#define TX4939_CLKCTR_SIO0RST 0x00000002
368#define TX4939_CLKCTR_CYPRST 0x00000001
369
370/*
371 * RTC
372 */
373#define TX4939_RTCCTL_ALME 0x00000080
374#define TX4939_RTCCTL_ALMD 0x00000040
375#define TX4939_RTCCTL_BUSY 0x00000020
376
377#define TX4939_RTCCTL_COMMAND 0x00000007
378#define TX4939_RTCCTL_COMMAND_NOP 0x00000000
379#define TX4939_RTCCTL_COMMAND_GETTIME 0x00000001
380#define TX4939_RTCCTL_COMMAND_SETTIME 0x00000002
381#define TX4939_RTCCTL_COMMAND_GETALARM 0x00000003
382#define TX4939_RTCCTL_COMMAND_SETALARM 0x00000004
383
384#define TX4939_RTCTBC_PM 0x00000080
385#define TX4939_RTCTBC_COMP 0x0000007f
386
387#define TX4939_RTC_REG_RAMSIZE 0x00000100
388#define TX4939_RTC_REG_RWBSIZE 0x00000006
389
390/*
391 * CRYPTO
392 */
393#define TX4939_CRYPTO_CSR_SAESO 0x08000000
394#define TX4939_CRYPTO_CSR_SAESI 0x04000000
395#define TX4939_CRYPTO_CSR_SDESO 0x02000000
396#define TX4939_CRYPTO_CSR_SDESI 0x01000000
397#define TX4939_CRYPTO_CSR_INDXBST_MASK 0x00700000
398#define TX4939_CRYPTO_CSR_INDXBST(n) ((n) << 20)
399#define TX4939_CRYPTO_CSR_TOINT 0x00080000
400#define TX4939_CRYPTO_CSR_DCINT 0x00040000
401#define TX4939_CRYPTO_CSR_GBINT 0x00010000
402#define TX4939_CRYPTO_CSR_INDXAST_MASK 0x0000e000
403#define TX4939_CRYPTO_CSR_INDXAST(n) ((n) << 13)
404#define TX4939_CRYPTO_CSR_CSWAP_MASK 0x00001800
405#define TX4939_CRYPTO_CSR_CSWAP_NONE 0x00000000
406#define TX4939_CRYPTO_CSR_CSWAP_IN 0x00000800
407#define TX4939_CRYPTO_CSR_CSWAP_OUT 0x00001000
408#define TX4939_CRYPTO_CSR_CSWAP_BOTH 0x00001800
409#define TX4939_CRYPTO_CSR_CDIV_MASK 0x00000600
410#define TX4939_CRYPTO_CSR_CDIV_DIV2 0x00000000
411#define TX4939_CRYPTO_CSR_CDIV_DIV1 0x00000200
412#define TX4939_CRYPTO_CSR_CDIV_DIV2ALT 0x00000400
413#define TX4939_CRYPTO_CSR_CDIV_DIV1ALT 0x00000600
414#define TX4939_CRYPTO_CSR_PDINT_MASK 0x000000c0
415#define TX4939_CRYPTO_CSR_PDINT_ALL 0x00000000
416#define TX4939_CRYPTO_CSR_PDINT_END 0x00000040
417#define TX4939_CRYPTO_CSR_PDINT_NEXT 0x00000080
418#define TX4939_CRYPTO_CSR_PDINT_NONE 0x000000c0
419#define TX4939_CRYPTO_CSR_GINTE 0x00000008
420#define TX4939_CRYPTO_CSR_RSTD 0x00000004
421#define TX4939_CRYPTO_CSR_RSTC 0x00000002
422#define TX4939_CRYPTO_CSR_ENCR 0x00000001
423
424/* bits for tx4939_crypto_reg.cdr.gen.ctrl */
425#define TX4939_CRYPTO_CTX_ENGINE_MASK 0x00000003
426#define TX4939_CRYPTO_CTX_ENGINE_DES 0x00000000
427#define TX4939_CRYPTO_CTX_ENGINE_AES 0x00000001
428#define TX4939_CRYPTO_CTX_ENGINE_MD5 0x00000002
429#define TX4939_CRYPTO_CTX_ENGINE_SHA1 0x00000003
430#define TX4939_CRYPTO_CTX_TDMS 0x00000010
431#define TX4939_CRYPTO_CTX_CMS 0x00000020
432#define TX4939_CRYPTO_CTX_DMS 0x00000040
433#define TX4939_CRYPTO_CTX_UPDATE 0x00000080
434
435/* bits for tx4939_crypto_desc.ctrl */
436#define TX4939_CRYPTO_DESC_OB_CNT_MASK 0xffe00000
437#define TX4939_CRYPTO_DESC_OB_CNT(cnt) ((cnt) << 21)
438#define TX4939_CRYPTO_DESC_IB_CNT_MASK 0x001ffc00
439#define TX4939_CRYPTO_DESC_IB_CNT(cnt) ((cnt) << 10)
440#define TX4939_CRYPTO_DESC_START 0x00000200
441#define TX4939_CRYPTO_DESC_END 0x00000100
442#define TX4939_CRYPTO_DESC_XOR 0x00000010
443#define TX4939_CRYPTO_DESC_LAST 0x00000008
444#define TX4939_CRYPTO_DESC_ERR_MASK 0x00000006
445#define TX4939_CRYPTO_DESC_ERR_NONE 0x00000000
446#define TX4939_CRYPTO_DESC_ERR_TOUT 0x00000002
447#define TX4939_CRYPTO_DESC_ERR_DIGEST 0x00000004
448#define TX4939_CRYPTO_DESC_OWN 0x00000001
449
450/* bits for tx4939_crypto_desc.index */
451#define TX4939_CRYPTO_DESC_HASH_IDX_MASK 0x00000070
452#define TX4939_CRYPTO_DESC_HASH_IDX(idx) ((idx) << 4)
453#define TX4939_CRYPTO_DESC_ENCRYPT_IDX_MASK 0x00000007
454#define TX4939_CRYPTO_DESC_ENCRYPT_IDX(idx) ((idx) << 0)
455
456#define TX4939_CRYPTO_NR_SET 6
457
458#define TX4939_CRYPTO_RCSR_INTE 0x00000008
459#define TX4939_CRYPTO_RCSR_RST 0x00000004
460#define TX4939_CRYPTO_RCSR_FIN 0x00000002
461#define TX4939_CRYPTO_RCSR_ST 0x00000001
462
463/*
464 * VPC
465 */
466#define TX4939_VPC_CSR_GBINT 0x00010000
467#define TX4939_VPC_CSR_SWAPO 0x00000020
468#define TX4939_VPC_CSR_SWAPI 0x00000010
469#define TX4939_VPC_CSR_GINTE 0x00000008
470#define TX4939_VPC_CSR_RSTD 0x00000004
471#define TX4939_VPC_CSR_RSTVPC 0x00000002
472
473#define TX4939_VPC_CTRLA_VDPSN 0x00000200
474#define TX4939_VPC_CTRLA_PBUSY 0x00000100
475#define TX4939_VPC_CTRLA_DCINT 0x00000080
476#define TX4939_VPC_CTRLA_UOINT 0x00000040
477#define TX4939_VPC_CTRLA_PDINT_MASK 0x00000030
478#define TX4939_VPC_CTRLA_PDINT_ALL 0x00000000
479#define TX4939_VPC_CTRLA_PDINT_NEXT 0x00000010
480#define TX4939_VPC_CTRLA_PDINT_NONE 0x00000030
481#define TX4939_VPC_CTRLA_VDVLDP 0x00000008
482#define TX4939_VPC_CTRLA_VDMODE 0x00000004
483#define TX4939_VPC_CTRLA_VDFOR 0x00000002
484#define TX4939_VPC_CTRLA_ENVPC 0x00000001
485
486/* bits for tx4939_vpc_desc.ctrl1 */
487#define TX4939_VPC_DESC_CTRL1_ERR_MASK 0x00000006
488#define TX4939_VPC_DESC_CTRL1_OWN 0x00000001
489
490#define tx4939_ddrcptr ((struct tx4939_ddrc_reg __iomem *)TX4939_DDRC_REG)
491#define tx4939_ebuscptr tx4938_ebuscptr
492#define tx4939_ircptr \
493 ((struct tx4939_irc_reg __iomem *)TX4939_IRC_REG)
494#define tx4939_pcicptr tx4938_pcicptr
495#define tx4939_pcic1ptr tx4938_pcic1ptr
496#define tx4939_ccfgptr \
497 ((struct tx4939_ccfg_reg __iomem *)TX4939_CCFG_REG)
498#define tx4939_sramcptr tx4938_sramcptr
499#define tx4939_rtcptr \
500 ((struct tx4939_rtc_reg __iomem *)TX4939_RTC_REG)
501#define tx4939_cryptoptr \
502 ((struct tx4939_crypto_reg __iomem *)TX4939_CRYPTO_REG)
503#define tx4939_vpcptr ((struct tx4939_vpc_reg __iomem *)TX4939_VPC_REG)
504
505#define TX4939_REV_MAJ_MIN() \
506 ((__u32)__raw_readq(&tx4939_ccfgptr->crir) & 0x00ff)
507#define TX4939_REV_PCODE() \
508 ((__u32)__raw_readq(&tx4939_ccfgptr->crir) >> 16)
509#define TX4939_CCFG_BCFG() \
510 ((__u32)((__raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_BCFG_MASK) \
511 >> 32))
512
513#define tx4939_ccfg_clear(bits) tx4938_ccfg_clear(bits)
514#define tx4939_ccfg_set(bits) tx4938_ccfg_set(bits)
515#define tx4939_ccfg_change(change, new) tx4938_ccfg_change(change, new)
516
517#define TX4939_EBUSC_CR(ch) TX4927_EBUSC_CR(ch)
518#define TX4939_EBUSC_BA(ch) TX4927_EBUSC_BA(ch)
519#define TX4939_EBUSC_SIZE(ch) TX4927_EBUSC_SIZE(ch)
520#define TX4939_EBUSC_WIDTH(ch) \
521 (16 >> ((__u32)(TX4939_EBUSC_CR(ch) >> 20) & 0x1))
522
523/* SCLK0 = MSTCLK * 429/19 * 16/245 / 2 (14.745MHz for MST 20MHz) */
524#define TX4939_SCLK0(mst) \
525 ((((mst) + 245/2) / 245UL * 429 * 16 + 19) / 19 / 2)
526
527void tx4939_wdt_init(void);
528void tx4939_add_memory_regions(void);
529void tx4939_setup(void);
530void tx4939_time_init(unsigned int tmrnr);
531void tx4939_sio_init(unsigned int sclk, unsigned int cts_mask);
532void tx4939_spi_init(int busid);
533void tx4939_ethaddr_init(unsigned char *addr0, unsigned char *addr1);
534int tx4939_report_pciclk(void);
535void tx4939_report_pci1clk(void);
536struct pci_dev;
537int tx4939_pcic1_map_irq(const struct pci_dev *dev, u8 slot);
538int tx4939_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
539void tx4939_setup_pcierr_irq(void);
540void tx4939_irq_init(void);
541int tx4939_irq(void);
542void tx4939_mtd_init(int ch);
543void tx4939_ata_init(void);
544
545#endif /* __ASM_TXX9_TX4939_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-22 11:33:12 -0500