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-rw-r--r--arch/mips/include/asm/sn/addrs.h430
-rw-r--r--arch/mips/include/asm/sn/agent.h46
-rw-r--r--arch/mips/include/asm/sn/arch.h64
-rw-r--r--arch/mips/include/asm/sn/fru.h44
-rw-r--r--arch/mips/include/asm/sn/gda.h107
-rw-r--r--arch/mips/include/asm/sn/hub.h16
-rw-r--r--arch/mips/include/asm/sn/intr.h129
-rw-r--r--arch/mips/include/asm/sn/io.h59
-rw-r--r--arch/mips/include/asm/sn/ioc3.h663
-rw-r--r--arch/mips/include/asm/sn/klconfig.h898
-rw-r--r--arch/mips/include/asm/sn/kldir.h217
-rw-r--r--arch/mips/include/asm/sn/klkernvars.h29
-rw-r--r--arch/mips/include/asm/sn/launch.h106
-rw-r--r--arch/mips/include/asm/sn/mapped_kernel.h54
-rw-r--r--arch/mips/include/asm/sn/nmi.h125
-rw-r--r--arch/mips/include/asm/sn/sn0/addrs.h288
-rw-r--r--arch/mips/include/asm/sn/sn0/arch.h72
-rw-r--r--arch/mips/include/asm/sn/sn0/hub.h40
-rw-r--r--arch/mips/include/asm/sn/sn0/hubio.h972
-rw-r--r--arch/mips/include/asm/sn/sn0/hubmd.h789
-rw-r--r--arch/mips/include/asm/sn/sn0/hubni.h255
-rw-r--r--arch/mips/include/asm/sn/sn0/hubpi.h409
-rw-r--r--arch/mips/include/asm/sn/sn0/ip27.h85
-rw-r--r--arch/mips/include/asm/sn/sn_private.h19
-rw-r--r--arch/mips/include/asm/sn/types.h26
25 files changed, 5942 insertions, 0 deletions
diff --git a/arch/mips/include/asm/sn/addrs.h b/arch/mips/include/asm/sn/addrs.h
new file mode 100644
index 000000000000..fec9bdd34913
--- /dev/null
+++ b/arch/mips/include/asm/sn/addrs.h
@@ -0,0 +1,430 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1992 - 1997, 1999, 2000 Silicon Graphics, Inc.
7 * Copyright (C) 1999, 2000 by Ralf Baechle
8 */
9#ifndef _ASM_SN_ADDRS_H
10#define _ASM_SN_ADDRS_H
11
12
13#ifndef __ASSEMBLY__
14#include <linux/types.h>
15#endif /* !__ASSEMBLY__ */
16
17#include <asm/addrspace.h>
18#include <asm/sn/kldir.h>
19
20#if defined(CONFIG_SGI_IP27)
21#include <asm/sn/sn0/addrs.h>
22#elif defined(CONFIG_SGI_IP35)
23#include <asm/sn/sn1/addrs.h>
24#endif
25
26
27#ifndef __ASSEMBLY__
28
29#define PS_UINT_CAST (unsigned long)
30#define UINT64_CAST (unsigned long)
31
32#define HUBREG_CAST (volatile hubreg_t *)
33
34#else /* __ASSEMBLY__ */
35
36#define PS_UINT_CAST
37#define UINT64_CAST
38#define HUBREG_CAST
39
40#endif /* __ASSEMBLY__ */
41
42
43#define NASID_GET_META(_n) ((_n) >> NASID_LOCAL_BITS)
44#ifdef CONFIG_SGI_IP27
45#define NASID_GET_LOCAL(_n) ((_n) & 0xf)
46#endif
47#define NASID_MAKE(_m, _l) (((_m) << NASID_LOCAL_BITS) | (_l))
48
49#define NODE_ADDRSPACE_MASK (NODE_ADDRSPACE_SIZE - 1)
50#define TO_NODE_ADDRSPACE(_pa) (UINT64_CAST (_pa) & NODE_ADDRSPACE_MASK)
51
52#define CHANGE_ADDR_NASID(_pa, _nasid) \
53 ((UINT64_CAST(_pa) & ~NASID_MASK) | \
54 (UINT64_CAST(_nasid) << NASID_SHFT))
55
56
57/*
58 * The following macros are used to index to the beginning of a specific
59 * node's address space.
60 */
61
62#define NODE_OFFSET(_n) (UINT64_CAST (_n) << NODE_SIZE_BITS)
63
64#define NODE_CAC_BASE(_n) (CAC_BASE + NODE_OFFSET(_n))
65#define NODE_HSPEC_BASE(_n) (HSPEC_BASE + NODE_OFFSET(_n))
66#define NODE_IO_BASE(_n) (IO_BASE + NODE_OFFSET(_n))
67#define NODE_MSPEC_BASE(_n) (MSPEC_BASE + NODE_OFFSET(_n))
68#define NODE_UNCAC_BASE(_n) (UNCAC_BASE + NODE_OFFSET(_n))
69
70#define TO_NODE(_n, _x) (NODE_OFFSET(_n) | ((_x) ))
71#define TO_NODE_CAC(_n, _x) (NODE_CAC_BASE(_n) | ((_x) & TO_PHYS_MASK))
72#define TO_NODE_UNCAC(_n, _x) (NODE_UNCAC_BASE(_n) | ((_x) & TO_PHYS_MASK))
73#define TO_NODE_MSPEC(_n, _x) (NODE_MSPEC_BASE(_n) | ((_x) & TO_PHYS_MASK))
74#define TO_NODE_HSPEC(_n, _x) (NODE_HSPEC_BASE(_n) | ((_x) & TO_PHYS_MASK))
75
76
77#define RAW_NODE_SWIN_BASE(nasid, widget) \
78 (NODE_IO_BASE(nasid) + (UINT64_CAST(widget) << SWIN_SIZE_BITS))
79
80#define WIDGETID_GET(addr) ((unsigned char)((addr >> SWIN_SIZE_BITS) & 0xff))
81
82/*
83 * The following definitions pertain to the IO special address
84 * space. They define the location of the big and little windows
85 * of any given node.
86 */
87
88#define SWIN_SIZE_BITS 24
89#define SWIN_SIZE (UINT64_CAST 1 << 24)
90#define SWIN_SIZEMASK (SWIN_SIZE - 1)
91#define SWIN_WIDGET_MASK 0xF
92
93/*
94 * Convert smallwindow address to xtalk address.
95 *
96 * 'addr' can be physical or virtual address, but will be converted
97 * to Xtalk address in the range 0 -> SWINZ_SIZEMASK
98 */
99#define SWIN_WIDGETADDR(addr) ((addr) & SWIN_SIZEMASK)
100#define SWIN_WIDGETNUM(addr) (((addr) >> SWIN_SIZE_BITS) & SWIN_WIDGET_MASK)
101/*
102 * Verify if addr belongs to small window address on node with "nasid"
103 *
104 *
105 * NOTE: "addr" is expected to be XKPHYS address, and NOT physical
106 * address
107 *
108 *
109 */
110#define NODE_SWIN_ADDR(nasid, addr) \
111 (((addr) >= NODE_SWIN_BASE(nasid, 0)) && \
112 ((addr) < (NODE_SWIN_BASE(nasid, HUB_NUM_WIDGET) + SWIN_SIZE)\
113 ))
114
115/*
116 * The following define the major position-independent aliases used
117 * in SN.
118 * UALIAS -- 256MB in size, reads in the UALIAS result in
119 * uncached references to the memory of the reader's node.
120 * CPU_UALIAS -- 128kb in size, the bottom part of UALIAS is flipped
121 * depending on which CPU does the access to provide
122 * all CPUs with unique uncached memory at low addresses.
123 * LBOOT -- 256MB in size, reads in the LBOOT area result in
124 * uncached references to the local hub's boot prom and
125 * other directory-bus connected devices.
126 * IALIAS -- 8MB in size, reads in the IALIAS result in uncached
127 * references to the local hub's registers.
128 */
129
130#define UALIAS_BASE HSPEC_BASE
131#define UALIAS_SIZE 0x10000000 /* 256 Megabytes */
132#define UALIAS_LIMIT (UALIAS_BASE + UALIAS_SIZE)
133
134/*
135 * The bottom of ualias space is flipped depending on whether you're
136 * processor 0 or 1 within a node.
137 */
138#ifdef CONFIG_SGI_IP27
139#define UALIAS_FLIP_BASE UALIAS_BASE
140#define UALIAS_FLIP_SIZE 0x20000
141#define UALIAS_FLIP_BIT 0x10000
142#define UALIAS_FLIP_ADDR(_x) (cputoslice(smp_processor_id()) ? \
143 (_x) ^ UALIAS_FLIP_BIT : (_x))
144
145#define LBOOT_BASE (HSPEC_BASE + 0x10000000)
146#define LBOOT_SIZE 0x10000000
147#define LBOOT_LIMIT (LBOOT_BASE + LBOOT_SIZE)
148#define LBOOT_STRIDE 0 /* IP27 has only one CPU PROM */
149
150#endif
151
152#define HUB_REGISTER_WIDGET 1
153#define IALIAS_BASE NODE_SWIN_BASE(0, HUB_REGISTER_WIDGET)
154#define IALIAS_SIZE 0x800000 /* 8 Megabytes */
155#define IS_IALIAS(_a) (((_a) >= IALIAS_BASE) && \
156 ((_a) < (IALIAS_BASE + IALIAS_SIZE)))
157
158/*
159 * Macro for referring to Hub's RBOOT space
160 */
161
162#ifdef CONFIG_SGI_IP27
163#define RBOOT_SIZE 0x10000000 /* 256 Megabytes */
164#define NODE_RBOOT_BASE(_n) (NODE_HSPEC_BASE(_n) + 0x30000000)
165#define NODE_RBOOT_LIMIT(_n) (NODE_RBOOT_BASE(_n) + RBOOT_SIZE)
166
167#endif
168
169/*
170 * Macros for referring the Hub's back door space
171 *
172 * These macros correctly process addresses in any node's space.
173 * WARNING: They won't work in assembler.
174 *
175 * BDDIR_ENTRY_LO returns the address of the low double-word of the dir
176 * entry corresponding to a physical (Cac or Uncac) address.
177 * BDDIR_ENTRY_HI returns the address of the high double-word of the entry.
178 * BDPRT_ENTRY returns the address of the double-word protection entry
179 * corresponding to the page containing the physical address.
180 * BDPRT_ENTRY_S Stores the value into the protection entry.
181 * BDPRT_ENTRY_L Load the value from the protection entry.
182 * BDECC_ENTRY returns the address of the ECC byte corresponding to a
183 * double-word at a specified physical address.
184 * BDECC_ENTRY_H returns the address of the two ECC bytes corresponding to a
185 * quad-word at a specified physical address.
186 */
187#define NODE_BDOOR_BASE(_n) (NODE_HSPEC_BASE(_n) + (NODE_ADDRSPACE_SIZE/2))
188
189#define NODE_BDECC_BASE(_n) (NODE_BDOOR_BASE(_n))
190#define NODE_BDDIR_BASE(_n) (NODE_BDOOR_BASE(_n) + (NODE_ADDRSPACE_SIZE/4))
191#ifdef CONFIG_SGI_IP27
192#define BDDIR_ENTRY_LO(_pa) ((HSPEC_BASE + \
193 NODE_ADDRSPACE_SIZE * 3 / 4 + \
194 0x200) | \
195 UINT64_CAST(_pa) & NASID_MASK | \
196 UINT64_CAST(_pa) >> 2 & BDDIR_UPPER_MASK | \
197 UINT64_CAST(_pa) >> 3 & 0x1f << 4)
198
199#define BDDIR_ENTRY_HI(_pa) ((HSPEC_BASE + \
200 NODE_ADDRSPACE_SIZE * 3 / 4 + \
201 0x208) | \
202 UINT64_CAST(_pa) & NASID_MASK | \
203 UINT64_CAST(_pa) >> 2 & BDDIR_UPPER_MASK | \
204 UINT64_CAST(_pa) >> 3 & 0x1f << 4)
205
206#define BDPRT_ENTRY(_pa, _rgn) ((HSPEC_BASE + \
207 NODE_ADDRSPACE_SIZE * 3 / 4) | \
208 UINT64_CAST(_pa) & NASID_MASK | \
209 UINT64_CAST(_pa) >> 2 & BDDIR_UPPER_MASK | \
210 (_rgn) << 3)
211#define BDPRT_ENTRY_ADDR(_pa, _rgn) (BDPRT_ENTRY((_pa), (_rgn)))
212#define BDPRT_ENTRY_S(_pa, _rgn, _val) (*(__psunsigned_t *)BDPRT_ENTRY((_pa), (_rgn))=(_val))
213#define BDPRT_ENTRY_L(_pa, _rgn) (*(__psunsigned_t *)BDPRT_ENTRY((_pa), (_rgn)))
214
215#define BDECC_ENTRY(_pa) ((HSPEC_BASE + \
216 NODE_ADDRSPACE_SIZE / 2) | \
217 UINT64_CAST(_pa) & NASID_MASK | \
218 UINT64_CAST(_pa) >> 2 & BDECC_UPPER_MASK | \
219 UINT64_CAST(_pa) >> 3 & 3)
220
221/*
222 * Macro to convert a back door directory or protection address into the
223 * raw physical address of the associated cache line or protection page.
224 */
225#define BDADDR_IS_DIR(_ba) ((UINT64_CAST (_ba) & 0x200) != 0)
226#define BDADDR_IS_PRT(_ba) ((UINT64_CAST (_ba) & 0x200) == 0)
227
228#define BDDIR_TO_MEM(_ba) (UINT64_CAST (_ba) & NASID_MASK | \
229 (UINT64_CAST(_ba) & BDDIR_UPPER_MASK)<<2 | \
230 (UINT64_CAST(_ba) & 0x1f << 4) << 3)
231
232#define BDPRT_TO_MEM(_ba) (UINT64_CAST (_ba) & NASID_MASK | \
233 (UINT64_CAST(_ba) & BDDIR_UPPER_MASK)<<2)
234
235#define BDECC_TO_MEM(_ba) (UINT64_CAST (_ba) & NASID_MASK | \
236 (UINT64_CAST(_ba) & BDECC_UPPER_MASK)<<2 | \
237 (UINT64_CAST(_ba) & 3) << 3)
238#endif /* CONFIG_SGI_IP27 */
239
240
241/*
242 * The following macros produce the correct base virtual address for
243 * the hub registers. The LOCAL_HUB_* macros produce the appropriate
244 * address for the local registers. The REMOTE_HUB_* macro produce
245 * the address for the specified hub's registers. The intent is
246 * that the appropriate PI, MD, NI, or II register would be substituted
247 * for _x.
248 */
249
250/*
251 * WARNING:
252 * When certain Hub chip workaround are defined, it's not sufficient
253 * to dereference the *_HUB_ADDR() macros. You should instead use
254 * HUB_L() and HUB_S() if you must deal with pointers to hub registers.
255 * Otherwise, the recommended approach is to use *_HUB_L() and *_HUB_S().
256 * They're always safe.
257 */
258#define LOCAL_HUB_ADDR(_x) (HUBREG_CAST (IALIAS_BASE + (_x)))
259#define REMOTE_HUB_ADDR(_n, _x) (HUBREG_CAST (NODE_SWIN_BASE(_n, 1) + \
260 0x800000 + (_x)))
261#ifdef CONFIG_SGI_IP27
262#define REMOTE_HUB_PI_ADDR(_n, _sn, _x) (HUBREG_CAST (NODE_SWIN_BASE(_n, 1) + \
263 0x800000 + (_x)))
264#endif /* CONFIG_SGI_IP27 */
265
266#ifndef __ASSEMBLY__
267
268#define HUB_L(_a) *(_a)
269#define HUB_S(_a, _d) *(_a) = (_d)
270
271#define LOCAL_HUB_L(_r) HUB_L(LOCAL_HUB_ADDR(_r))
272#define LOCAL_HUB_S(_r, _d) HUB_S(LOCAL_HUB_ADDR(_r), (_d))
273#define REMOTE_HUB_L(_n, _r) HUB_L(REMOTE_HUB_ADDR((_n), (_r)))
274#define REMOTE_HUB_S(_n, _r, _d) HUB_S(REMOTE_HUB_ADDR((_n), (_r)), (_d))
275#define REMOTE_HUB_PI_L(_n, _sn, _r) HUB_L(REMOTE_HUB_PI_ADDR((_n), (_sn), (_r)))
276#define REMOTE_HUB_PI_S(_n, _sn, _r, _d) HUB_S(REMOTE_HUB_PI_ADDR((_n), (_sn), (_r)), (_d))
277
278#endif /* !__ASSEMBLY__ */
279
280/*
281 * The following macros are used to get to a hub/bridge register, given
282 * the base of the register space.
283 */
284#define HUB_REG_PTR(_base, _off) \
285 (HUBREG_CAST((__psunsigned_t)(_base) + (__psunsigned_t)(_off)))
286
287#define HUB_REG_PTR_L(_base, _off) \
288 HUB_L(HUB_REG_PTR((_base), (_off)))
289
290#define HUB_REG_PTR_S(_base, _off, _data) \
291 HUB_S(HUB_REG_PTR((_base), (_off)), (_data))
292
293/*
294 * Software structure locations -- permanently fixed
295 * See diagram in kldir.h
296 */
297
298#define PHYS_RAMBASE 0x0
299#define K0_RAMBASE PHYS_TO_K0(PHYS_RAMBASE)
300
301#define EX_HANDLER_OFFSET(slice) ((slice) << 16)
302#define EX_HANDLER_ADDR(nasid, slice) \
303 PHYS_TO_K0(NODE_OFFSET(nasid) | EX_HANDLER_OFFSET(slice))
304#define EX_HANDLER_SIZE 0x0400
305
306#define EX_FRAME_OFFSET(slice) ((slice) << 16 | 0x400)
307#define EX_FRAME_ADDR(nasid, slice) \
308 PHYS_TO_K0(NODE_OFFSET(nasid) | EX_FRAME_OFFSET(slice))
309#define EX_FRAME_SIZE 0x0c00
310
311#define ARCS_SPB_OFFSET 0x1000
312#define ARCS_SPB_ADDR(nasid) \
313 PHYS_TO_K0(NODE_OFFSET(nasid) | ARCS_SPB_OFFSET)
314#define ARCS_SPB_SIZE 0x0400
315
316#define KLDIR_OFFSET 0x2000
317#define KLDIR_ADDR(nasid) \
318 TO_NODE_UNCAC((nasid), KLDIR_OFFSET)
319#define KLDIR_SIZE 0x0400
320
321
322/*
323 * Software structure locations -- indirected through KLDIR
324 * See diagram in kldir.h
325 *
326 * Important: All low memory structures must only be accessed
327 * uncached, except for the symmon stacks.
328 */
329
330#define KLI_LAUNCH 0 /* Dir. entries */
331#define KLI_KLCONFIG 1
332#define KLI_NMI 2
333#define KLI_GDA 3
334#define KLI_FREEMEM 4
335#define KLI_SYMMON_STK 5
336#define KLI_PI_ERROR 6
337#define KLI_KERN_VARS 7
338#define KLI_KERN_XP 8
339#define KLI_KERN_PARTID 9
340
341#ifndef __ASSEMBLY__
342
343#define KLD_BASE(nasid) ((kldir_ent_t *) KLDIR_ADDR(nasid))
344#define KLD_LAUNCH(nasid) (KLD_BASE(nasid) + KLI_LAUNCH)
345#define KLD_NMI(nasid) (KLD_BASE(nasid) + KLI_NMI)
346#define KLD_KLCONFIG(nasid) (KLD_BASE(nasid) + KLI_KLCONFIG)
347#define KLD_PI_ERROR(nasid) (KLD_BASE(nasid) + KLI_PI_ERROR)
348#define KLD_GDA(nasid) (KLD_BASE(nasid) + KLI_GDA)
349#define KLD_SYMMON_STK(nasid) (KLD_BASE(nasid) + KLI_SYMMON_STK)
350#define KLD_FREEMEM(nasid) (KLD_BASE(nasid) + KLI_FREEMEM)
351#define KLD_KERN_VARS(nasid) (KLD_BASE(nasid) + KLI_KERN_VARS)
352#define KLD_KERN_XP(nasid) (KLD_BASE(nasid) + KLI_KERN_XP)
353#define KLD_KERN_PARTID(nasid) (KLD_BASE(nasid) + KLI_KERN_PARTID)
354
355#define LAUNCH_OFFSET(nasid, slice) \
356 (KLD_LAUNCH(nasid)->offset + \
357 KLD_LAUNCH(nasid)->stride * (slice))
358#define LAUNCH_ADDR(nasid, slice) \
359 TO_NODE_UNCAC((nasid), LAUNCH_OFFSET(nasid, slice))
360#define LAUNCH_SIZE(nasid) KLD_LAUNCH(nasid)->size
361
362#define NMI_OFFSET(nasid, slice) \
363 (KLD_NMI(nasid)->offset + \
364 KLD_NMI(nasid)->stride * (slice))
365#define NMI_ADDR(nasid, slice) \
366 TO_NODE_UNCAC((nasid), NMI_OFFSET(nasid, slice))
367#define NMI_SIZE(nasid) KLD_NMI(nasid)->size
368
369#define KLCONFIG_OFFSET(nasid) KLD_KLCONFIG(nasid)->offset
370#define KLCONFIG_ADDR(nasid) \
371 TO_NODE_UNCAC((nasid), KLCONFIG_OFFSET(nasid))
372#define KLCONFIG_SIZE(nasid) KLD_KLCONFIG(nasid)->size
373
374#define GDA_ADDR(nasid) KLD_GDA(nasid)->pointer
375#define GDA_SIZE(nasid) KLD_GDA(nasid)->size
376
377#define SYMMON_STK_OFFSET(nasid, slice) \
378 (KLD_SYMMON_STK(nasid)->offset + \
379 KLD_SYMMON_STK(nasid)->stride * (slice))
380#define SYMMON_STK_STRIDE(nasid) KLD_SYMMON_STK(nasid)->stride
381
382#define SYMMON_STK_ADDR(nasid, slice) \
383 TO_NODE_CAC((nasid), SYMMON_STK_OFFSET(nasid, slice))
384
385#define SYMMON_STK_SIZE(nasid) KLD_SYMMON_STK(nasid)->stride
386
387#define SYMMON_STK_END(nasid) (SYMMON_STK_ADDR(nasid, 0) + KLD_SYMMON_STK(nasid)->size)
388
389/* loading symmon 4k below UNIX. the arcs loader needs the topaddr for a
390 * relocatable program
391 */
392#define UNIX_DEBUG_LOADADDR 0x300000
393#define SYMMON_LOADADDR(nasid) \
394 TO_NODE(nasid, PHYS_TO_K0(UNIX_DEBUG_LOADADDR - 0x1000))
395
396#define FREEMEM_OFFSET(nasid) KLD_FREEMEM(nasid)->offset
397#define FREEMEM_ADDR(nasid) SYMMON_STK_END(nasid)
398/*
399 * XXX
400 * Fix this. FREEMEM_ADDR should be aware of if symmon is loaded.
401 * Also, it should take into account what prom thinks to be a safe
402 * address
403 PHYS_TO_K0(NODE_OFFSET(nasid) + FREEMEM_OFFSET(nasid))
404 */
405#define FREEMEM_SIZE(nasid) KLD_FREEMEM(nasid)->size
406
407#define PI_ERROR_OFFSET(nasid) KLD_PI_ERROR(nasid)->offset
408#define PI_ERROR_ADDR(nasid) \
409 TO_NODE_UNCAC((nasid), PI_ERROR_OFFSET(nasid))
410#define PI_ERROR_SIZE(nasid) KLD_PI_ERROR(nasid)->size
411
412#define NODE_OFFSET_TO_K0(_nasid, _off) \
413 PHYS_TO_K0((NODE_OFFSET(_nasid) + (_off)) | CAC_BASE)
414#define NODE_OFFSET_TO_K1(_nasid, _off) \
415 TO_UNCAC((NODE_OFFSET(_nasid) + (_off)) | UNCAC_BASE)
416#define K0_TO_NODE_OFFSET(_k0addr) \
417 ((__psunsigned_t)(_k0addr) & NODE_ADDRSPACE_MASK)
418
419#define KERN_VARS_ADDR(nasid) KLD_KERN_VARS(nasid)->pointer
420#define KERN_VARS_SIZE(nasid) KLD_KERN_VARS(nasid)->size
421
422#define KERN_XP_ADDR(nasid) KLD_KERN_XP(nasid)->pointer
423#define KERN_XP_SIZE(nasid) KLD_KERN_XP(nasid)->size
424
425#define GPDA_ADDR(nasid) TO_NODE_CAC(nasid, GPDA_OFFSET)
426
427#endif /* !__ASSEMBLY__ */
428
429
430#endif /* _ASM_SN_ADDRS_H */
diff --git a/arch/mips/include/asm/sn/agent.h b/arch/mips/include/asm/sn/agent.h
new file mode 100644
index 000000000000..ac4ea85c3a5c
--- /dev/null
+++ b/arch/mips/include/asm/sn/agent.h
@@ -0,0 +1,46 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * This file has definitions for the hub and snac interfaces.
7 *
8 * Copyright (C) 1992 - 1997, 1999, 2000 Silcon Graphics, Inc.
9 * Copyright (C) 1999, 2000 Ralf Baechle (ralf@gnu.org)
10 */
11#ifndef _ASM_SGI_SN_AGENT_H
12#define _ASM_SGI_SN_AGENT_H
13
14#include <linux/topology.h>
15#include <asm/sn/addrs.h>
16#include <asm/sn/arch.h>
17
18#if defined(CONFIG_SGI_IP27)
19#include <asm/sn/sn0/hub.h>
20#elif defined(CONFIG_SGI_IP35)
21#include <asm/sn/sn1/hub.h>
22#endif /* !CONFIG_SGI_IP27 && !CONFIG_SGI_IP35 */
23
24/*
25 * NIC register macros
26 */
27
28#if defined(CONFIG_SGI_IP27)
29#define HUB_NIC_ADDR(_cpuid) \
30 REMOTE_HUB_ADDR(COMPACT_TO_NASID_NODEID(cpu_to_node(_cpuid)), \
31 MD_MLAN_CTL)
32#endif
33
34#define SET_HUB_NIC(_my_cpuid, _val) \
35 (HUB_S(HUB_NIC_ADDR(_my_cpuid), (_val)))
36
37#define SET_MY_HUB_NIC(_v) \
38 SET_HUB_NIC(cpuid(), (_v))
39
40#define GET_HUB_NIC(_my_cpuid) \
41 (HUB_L(HUB_NIC_ADDR(_my_cpuid)))
42
43#define GET_MY_HUB_NIC() \
44 GET_HUB_NIC(cpuid())
45
46#endif /* _ASM_SGI_SN_AGENT_H */
diff --git a/arch/mips/include/asm/sn/arch.h b/arch/mips/include/asm/sn/arch.h
new file mode 100644
index 000000000000..bd75945e10ff
--- /dev/null
+++ b/arch/mips/include/asm/sn/arch.h
@@ -0,0 +1,64 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * SGI specific setup.
7 *
8 * Copyright (C) 1995 - 1997, 1999 Silcon Graphics, Inc.
9 * Copyright (C) 1999 Ralf Baechle (ralf@gnu.org)
10 */
11#ifndef _ASM_SN_ARCH_H
12#define _ASM_SN_ARCH_H
13
14#include <linux/types.h>
15#include <asm/sn/types.h>
16#ifdef CONFIG_SGI_IP27
17#include <asm/sn/sn0/arch.h>
18#endif
19
20typedef u64 hubreg_t;
21
22#define cputonasid(cpu) (sn_cpu_info[(cpu)].p_nasid)
23#define cputoslice(cpu) (sn_cpu_info[(cpu)].p_slice)
24#define makespnum(_nasid, _slice) \
25 (((_nasid) << CPUS_PER_NODE_SHFT) | (_slice))
26
27#define INVALID_NASID (nasid_t)-1
28#define INVALID_CNODEID (cnodeid_t)-1
29#define INVALID_PNODEID (pnodeid_t)-1
30#define INVALID_MODULE (moduleid_t)-1
31#define INVALID_PARTID (partid_t)-1
32
33extern nasid_t get_nasid(void);
34extern cnodeid_t get_cpu_cnode(cpuid_t);
35extern int get_cpu_slice(cpuid_t);
36
37/*
38 * NO ONE should access these arrays directly. The only reason we refer to
39 * them here is to avoid the procedure call that would be required in the
40 * macros below. (Really want private data members here :-)
41 */
42extern cnodeid_t nasid_to_compact_node[MAX_NASIDS];
43extern nasid_t compact_to_nasid_node[MAX_COMPACT_NODES];
44
45/*
46 * These macros are used by various parts of the kernel to convert
47 * between the three different kinds of node numbering. At least some
48 * of them may change to procedure calls in the future, but the macros
49 * will continue to work. Don't use the arrays above directly.
50 */
51
52#define NASID_TO_REGION(nnode) \
53 ((nnode) >> \
54 (is_fine_dirmode() ? NASID_TO_FINEREG_SHFT : NASID_TO_COARSEREG_SHFT))
55
56extern cnodeid_t nasid_to_compact_node[MAX_NASIDS];
57extern nasid_t compact_to_nasid_node[MAX_COMPACT_NODES];
58extern cnodeid_t cpuid_to_compact_node[MAXCPUS];
59
60#define NASID_TO_COMPACT_NODEID(nnode) (nasid_to_compact_node[nnode])
61#define COMPACT_TO_NASID_NODEID(cnode) (compact_to_nasid_node[cnode])
62#define CPUID_TO_COMPACT_NODEID(cpu) (cpuid_to_compact_node[(cpu)])
63
64#endif /* _ASM_SN_ARCH_H */
diff --git a/arch/mips/include/asm/sn/fru.h b/arch/mips/include/asm/sn/fru.h
new file mode 100644
index 000000000000..b3e3606723b7
--- /dev/null
+++ b/arch/mips/include/asm/sn/fru.h
@@ -0,0 +1,44 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Derived from IRIX <sys/SN/SN0/sn0_fru.h>
7 *
8 * Copyright (C) 1992 - 1997, 1999 Silcon Graphics, Inc.
9 * Copyright (C) 1999, 2006 Ralf Baechle (ralf@linux-mips)
10 */
11#ifndef __ASM_SN_FRU_H
12#define __ASM_SN_FRU_H
13
14#define MAX_DIMMS 8 /* max # of dimm banks */
15#define MAX_PCIDEV 8 /* max # of pci devices on a pci bus */
16
17typedef unsigned char confidence_t;
18
19typedef struct kf_mem_s {
20 confidence_t km_confidence; /* confidence level that the memory is bad
21 * is this necessary ?
22 */
23 confidence_t km_dimm[MAX_DIMMS];
24 /* confidence level that dimm[i] is bad
25 *I think this is the right number
26 */
27
28} kf_mem_t;
29
30typedef struct kf_cpu_s {
31 confidence_t kc_confidence; /* confidence level that cpu is bad */
32 confidence_t kc_icache; /* confidence level that instr. cache is bad */
33 confidence_t kc_dcache; /* confidence level that data cache is bad */
34 confidence_t kc_scache; /* confidence level that sec. cache is bad */
35 confidence_t kc_sysbus; /* confidence level that sysad/cmd/state bus is bad */
36} kf_cpu_t;
37
38typedef struct kf_pci_bus_s {
39 confidence_t kpb_belief; /* confidence level that the pci bus is bad */
40 confidence_t kpb_pcidev_belief[MAX_PCIDEV];
41 /* confidence level that the pci dev is bad */
42} kf_pci_bus_t;
43
44#endif /* __ASM_SN_FRU_H */
diff --git a/arch/mips/include/asm/sn/gda.h b/arch/mips/include/asm/sn/gda.h
new file mode 100644
index 000000000000..9cb6ff770915
--- /dev/null
+++ b/arch/mips/include/asm/sn/gda.h
@@ -0,0 +1,107 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Derived from IRIX <sys/SN/gda.h>.
7 *
8 * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
9 *
10 * gda.h -- Contains the data structure for the global data area,
11 * The GDA contains information communicated between the
12 * PROM, SYMMON, and the kernel.
13 */
14#ifndef _ASM_SN_GDA_H
15#define _ASM_SN_GDA_H
16
17#include <asm/sn/addrs.h>
18
19#define GDA_MAGIC 0x58464552
20
21/*
22 * GDA Version History
23 *
24 * Version # | Change
25 * -------------+-------------------------------------------------------
26 * 1 | Initial SN0 version
27 * 2 | Prom sets g_partid field to the partition number. 0 IS
28 * | a valid partition #.
29 */
30
31#define GDA_VERSION 2 /* Current GDA version # */
32
33#define G_MAGICOFF 0
34#define G_VERSIONOFF 4
35#define G_PROMOPOFF 6
36#define G_MASTEROFF 8
37#define G_VDSOFF 12
38#define G_HKDNORMOFF 16
39#define G_HKDUTLBOFF 24
40#define G_HKDXUTLBOFF 32
41#define G_PARTIDOFF 40
42#define G_TABLEOFF 128
43
44#ifndef __ASSEMBLY__
45
46typedef struct gda {
47 u32 g_magic; /* GDA magic number */
48 u16 g_version; /* Version of this structure */
49 u16 g_masterid; /* The NASID:CPUNUM of the master cpu */
50 u32 g_promop; /* Passes requests from the kernel to prom */
51 u32 g_vds; /* Store the virtual dipswitches here */
52 void **g_hooked_norm;/* ptr to pda loc for norm hndlr */
53 void **g_hooked_utlb;/* ptr to pda loc for utlb hndlr */
54 void **g_hooked_xtlb;/* ptr to pda loc for xtlb hndlr */
55 int g_partid; /* partition id */
56 int g_symmax; /* Max symbols in name table. */
57 void *g_dbstab; /* Address of idbg symbol table */
58 char *g_nametab; /* Address of idbg name table */
59 void *g_ktext_repmask;
60 /* Pointer to a mask of nodes with copies
61 * of the kernel. */
62 char g_padding[56]; /* pad out to 128 bytes */
63 nasid_t g_nasidtable[MAX_COMPACT_NODES]; /* NASID of each node,
64 * indexed by cnodeid.
65 */
66} gda_t;
67
68#define GDA ((gda_t*) GDA_ADDR(get_nasid()))
69
70#endif /* !__ASSEMBLY__ */
71/*
72 * Define: PART_GDA_VERSION
73 * Purpose: Define the minimum version of the GDA required, lower
74 * revisions assume GDA is NOT set up, and read partition
75 * information from the board info.
76 */
77#define PART_GDA_VERSION 2
78
79/*
80 * The following requests can be sent to the PROM during startup.
81 */
82
83#define PROMOP_MAGIC 0x0ead0000
84#define PROMOP_MAGIC_MASK 0x0fff0000
85
86#define PROMOP_BIST_SHIFT 11
87#define PROMOP_BIST_MASK (0x3 << 11)
88
89#define PROMOP_REG PI_ERR_STACK_ADDR_A
90
91#define PROMOP_INVALID (PROMOP_MAGIC | 0x00)
92#define PROMOP_HALT (PROMOP_MAGIC | 0x10)
93#define PROMOP_POWERDOWN (PROMOP_MAGIC | 0x20)
94#define PROMOP_RESTART (PROMOP_MAGIC | 0x30)
95#define PROMOP_REBOOT (PROMOP_MAGIC | 0x40)
96#define PROMOP_IMODE (PROMOP_MAGIC | 0x50)
97
98#define PROMOP_CMD_MASK 0x00f0
99#define PROMOP_OPTIONS_MASK 0xfff0
100
101#define PROMOP_SKIP_DIAGS 0x0100 /* don't bother running diags */
102#define PROMOP_SKIP_MEMINIT 0x0200 /* don't bother initing memory */
103#define PROMOP_SKIP_DEVINIT 0x0400 /* don't bother initing devices */
104#define PROMOP_BIST1 0x0800 /* keep track of which BIST ran */
105#define PROMOP_BIST2 0x1000 /* keep track of which BIST ran */
106
107#endif /* _ASM_SN_GDA_H */
diff --git a/arch/mips/include/asm/sn/hub.h b/arch/mips/include/asm/sn/hub.h
new file mode 100644
index 000000000000..1992d9254a08
--- /dev/null
+++ b/arch/mips/include/asm/sn/hub.h
@@ -0,0 +1,16 @@
1#ifndef __ASM_SN_HUB_H
2#define __ASM_SN_HUB_H
3
4#include <linux/types.h>
5#include <linux/cpumask.h>
6#include <asm/sn/types.h>
7#include <asm/sn/io.h>
8#include <asm/sn/klkernvars.h>
9#include <asm/xtalk/xtalk.h>
10
11/* ip27-hubio.c */
12extern unsigned long hub_pio_map(cnodeid_t cnode, xwidgetnum_t widget,
13 unsigned long xtalk_addr, size_t size);
14extern void hub_pio_init(cnodeid_t cnode);
15
16#endif /* __ASM_SN_HUB_H */
diff --git a/arch/mips/include/asm/sn/intr.h b/arch/mips/include/asm/sn/intr.h
new file mode 100644
index 000000000000..6718b644b970
--- /dev/null
+++ b/arch/mips/include/asm/sn/intr.h
@@ -0,0 +1,129 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1992 - 1997 Silicon Graphics, Inc.
7 */
8#ifndef __ASM_SN_INTR_H
9#define __ASM_SN_INTR_H
10
11/* Number of interrupt levels associated with each interrupt register. */
12#define N_INTPEND_BITS 64
13
14#define INT_PEND0_BASELVL 0
15#define INT_PEND1_BASELVL 64
16
17#define N_INTPENDJUNK_BITS 8
18#define INTPENDJUNK_CLRBIT 0x80
19
20/*
21 * Macros to manipulate the interrupt register on the calling hub chip.
22 */
23
24#define LOCAL_HUB_SEND_INTR(level) \
25 LOCAL_HUB_S(PI_INT_PEND_MOD, (0x100 | (level)))
26#define REMOTE_HUB_SEND_INTR(hub, level) \
27 REMOTE_HUB_S((hub), PI_INT_PEND_MOD, (0x100 | (level)))
28
29/*
30 * When clearing the interrupt, make sure this clear does make it
31 * to the hub. Otherwise we could end up losing interrupts.
32 * We do an uncached load of the int_pend0 register to ensure this.
33 */
34
35#define LOCAL_HUB_CLR_INTR(level) \
36do { \
37 LOCAL_HUB_S(PI_INT_PEND_MOD, (level)); \
38 LOCAL_HUB_L(PI_INT_PEND0); \
39} while (0);
40
41#define REMOTE_HUB_CLR_INTR(hub, level) \
42do { \
43 nasid_t __hub = (hub); \
44 \
45 REMOTE_HUB_S(__hub, PI_INT_PEND_MOD, (level)); \
46 REMOTE_HUB_L(__hub, PI_INT_PEND0); \
47} while (0);
48
49/*
50 * Hard-coded interrupt levels:
51 */
52
53/*
54 * L0 = SW1
55 * L1 = SW2
56 * L2 = INT_PEND0
57 * L3 = INT_PEND1
58 * L4 = RTC
59 * L5 = Profiling Timer
60 * L6 = Hub Errors
61 * L7 = Count/Compare (T5 counters)
62 */
63
64
65/*
66 * INT_PEND0 hard-coded bits.
67 */
68
69/*
70 * INT_PEND0 bits determined by hardware:
71 */
72#define RESERVED_INTR 0 /* What is this bit? */
73#define GFX_INTR_A 1
74#define GFX_INTR_B 2
75#define PG_MIG_INTR 3
76#define UART_INTR 4
77#define CC_PEND_A 5
78#define CC_PEND_B 6
79
80/*
81 * INT_PEND0 used by the kernel for itself ...
82 */
83#define CPU_RESCHED_A_IRQ 7
84#define CPU_RESCHED_B_IRQ 8
85#define CPU_CALL_A_IRQ 9
86#define CPU_CALL_B_IRQ 10
87#define MSC_MESG_INTR 11
88#define BASE_PCI_IRQ 12
89
90/*
91 * INT_PEND0 again, bits determined by hardware / hardcoded:
92 */
93#define SDISK_INTR 63 /* SABLE name */
94#define IP_PEND0_6_63 63 /* What is this bit? */
95
96/*
97 * INT_PEND1 hard-coded bits:
98 */
99#define NI_BRDCAST_ERR_A 39
100#define NI_BRDCAST_ERR_B 40
101
102#define LLP_PFAIL_INTR_A 41 /* see ml/SN/SN0/sysctlr.c */
103#define LLP_PFAIL_INTR_B 42
104
105#define TLB_INTR_A 43 /* used for tlb flush random */
106#define TLB_INTR_B 44
107
108#define IP27_INTR_0 45 /* Reserved for PROM use */
109#define IP27_INTR_1 46 /* do not use in Kernel */
110#define IP27_INTR_2 47
111#define IP27_INTR_3 48
112#define IP27_INTR_4 49
113#define IP27_INTR_5 50
114#define IP27_INTR_6 51
115#define IP27_INTR_7 52
116
117#define BRIDGE_ERROR_INTR 53 /* Setup by PROM to catch */
118 /* Bridge Errors */
119#define DEBUG_INTR_A 54
120#define DEBUG_INTR_B 55 /* Used by symmon to stop all cpus */
121#define IO_ERROR_INTR 57 /* Setup by PROM */
122#define CLK_ERR_INTR 58
123#define COR_ERR_INTR_A 59
124#define COR_ERR_INTR_B 60
125#define MD_COR_ERR_INTR 61
126#define NI_ERROR_INTR 62
127#define MSC_PANIC_INTR 63
128
129#endif /* __ASM_SN_INTR_H */
diff --git a/arch/mips/include/asm/sn/io.h b/arch/mips/include/asm/sn/io.h
new file mode 100644
index 000000000000..24c6775fbb0f
--- /dev/null
+++ b/arch/mips/include/asm/sn/io.h
@@ -0,0 +1,59 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2000, 2003 Ralf Baechle
7 * Copyright (C) 2000 Silicon Graphics, Inc.
8 */
9#ifndef _ASM_SN_IO_H
10#define _ASM_SN_IO_H
11
12#if defined(CONFIG_SGI_IP27)
13#include <asm/sn/sn0/hubio.h>
14#endif
15
16
17#define IIO_ITTE_BASE 0x400160 /* base of translation table entries */
18#define IIO_ITTE(bigwin) (IIO_ITTE_BASE + 8*(bigwin))
19
20#define IIO_ITTE_OFFSET_BITS 5 /* size of offset field */
21#define IIO_ITTE_OFFSET_MASK ((1<<IIO_ITTE_OFFSET_BITS)-1)
22#define IIO_ITTE_OFFSET_SHIFT 0
23
24#define IIO_ITTE_WIDGET_BITS 4 /* size of widget field */
25#define IIO_ITTE_WIDGET_MASK ((1<<IIO_ITTE_WIDGET_BITS)-1)
26#define IIO_ITTE_WIDGET_SHIFT 8
27
28#define IIO_ITTE_IOSP 1 /* I/O Space bit */
29#define IIO_ITTE_IOSP_MASK 1
30#define IIO_ITTE_IOSP_SHIFT 12
31#define HUB_PIO_MAP_TO_MEM 0
32#define HUB_PIO_MAP_TO_IO 1
33
34#define IIO_ITTE_INVALID_WIDGET 3 /* an invalid widget */
35
36#define IIO_ITTE_PUT(nasid, bigwin, io_or_mem, widget, addr) \
37 REMOTE_HUB_S((nasid), IIO_ITTE(bigwin), \
38 (((((addr) >> BWIN_SIZE_BITS) & \
39 IIO_ITTE_OFFSET_MASK) << IIO_ITTE_OFFSET_SHIFT) | \
40 (io_or_mem << IIO_ITTE_IOSP_SHIFT) | \
41 (((widget) & IIO_ITTE_WIDGET_MASK) << IIO_ITTE_WIDGET_SHIFT)))
42
43#define IIO_ITTE_DISABLE(nasid, bigwin) \
44 IIO_ITTE_PUT((nasid), HUB_PIO_MAP_TO_MEM, \
45 (bigwin), IIO_ITTE_INVALID_WIDGET, 0)
46
47#define IIO_ITTE_GET(nasid, bigwin) REMOTE_HUB_ADDR((nasid), IIO_ITTE(bigwin))
48
49/*
50 * Macro which takes the widget number, and returns the
51 * IO PRB address of that widget.
52 * value _x is expected to be a widget number in the range
53 * 0, 8 - 0xF
54 */
55#define IIO_IOPRB(_x) (IIO_IOPRB_0 + ( ( (_x) < HUB_WIDGET_ID_MIN ? \
56 (_x) : \
57 (_x) - (HUB_WIDGET_ID_MIN-1)) << 3) )
58
59#endif /* _ASM_SN_IO_H */
diff --git a/arch/mips/include/asm/sn/ioc3.h b/arch/mips/include/asm/sn/ioc3.h
new file mode 100644
index 000000000000..099677774d71
--- /dev/null
+++ b/arch/mips/include/asm/sn/ioc3.h
@@ -0,0 +1,663 @@
1/*
2 * Copyright (C) 1999, 2000 Ralf Baechle
3 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
4 */
5#ifndef _IOC3_H
6#define _IOC3_H
7
8#include <linux/types.h>
9
10/* SUPERIO uart register map */
11typedef volatile struct ioc3_uartregs {
12 union {
13 volatile u8 rbr; /* read only, DLAB == 0 */
14 volatile u8 thr; /* write only, DLAB == 0 */
15 volatile u8 dll; /* DLAB == 1 */
16 } u1;
17 union {
18 volatile u8 ier; /* DLAB == 0 */
19 volatile u8 dlm; /* DLAB == 1 */
20 } u2;
21 union {
22 volatile u8 iir; /* read only */
23 volatile u8 fcr; /* write only */
24 } u3;
25 volatile u8 iu_lcr;
26 volatile u8 iu_mcr;
27 volatile u8 iu_lsr;
28 volatile u8 iu_msr;
29 volatile u8 iu_scr;
30} ioc3_uregs_t;
31
32#define iu_rbr u1.rbr
33#define iu_thr u1.thr
34#define iu_dll u1.dll
35#define iu_ier u2.ier
36#define iu_dlm u2.dlm
37#define iu_iir u3.iir
38#define iu_fcr u3.fcr
39
40struct ioc3_sioregs {
41 volatile u8 fill[0x141]; /* starts at 0x141 */
42
43 volatile u8 uartc;
44 volatile u8 kbdcg;
45
46 volatile u8 fill0[0x150 - 0x142 - 1];
47
48 volatile u8 pp_data;
49 volatile u8 pp_dsr;
50 volatile u8 pp_dcr;
51
52 volatile u8 fill1[0x158 - 0x152 - 1];
53
54 volatile u8 pp_fifa;
55 volatile u8 pp_cfgb;
56 volatile u8 pp_ecr;
57
58 volatile u8 fill2[0x168 - 0x15a - 1];
59
60 volatile u8 rtcad;
61 volatile u8 rtcdat;
62
63 volatile u8 fill3[0x170 - 0x169 - 1];
64
65 struct ioc3_uartregs uartb; /* 0x20170 */
66 struct ioc3_uartregs uarta; /* 0x20178 */
67};
68
69/* Register layout of IOC3 in configuration space. */
70struct ioc3 {
71 volatile u32 pad0[7]; /* 0x00000 */
72 volatile u32 sio_ir; /* 0x0001c */
73 volatile u32 sio_ies; /* 0x00020 */
74 volatile u32 sio_iec; /* 0x00024 */
75 volatile u32 sio_cr; /* 0x00028 */
76 volatile u32 int_out; /* 0x0002c */
77 volatile u32 mcr; /* 0x00030 */
78
79 /* General Purpose I/O registers */
80 volatile u32 gpcr_s; /* 0x00034 */
81 volatile u32 gpcr_c; /* 0x00038 */
82 volatile u32 gpdr; /* 0x0003c */
83 volatile u32 gppr_0; /* 0x00040 */
84 volatile u32 gppr_1; /* 0x00044 */
85 volatile u32 gppr_2; /* 0x00048 */
86 volatile u32 gppr_3; /* 0x0004c */
87 volatile u32 gppr_4; /* 0x00050 */
88 volatile u32 gppr_5; /* 0x00054 */
89 volatile u32 gppr_6; /* 0x00058 */
90 volatile u32 gppr_7; /* 0x0005c */
91 volatile u32 gppr_8; /* 0x00060 */
92 volatile u32 gppr_9; /* 0x00064 */
93 volatile u32 gppr_10; /* 0x00068 */
94 volatile u32 gppr_11; /* 0x0006c */
95 volatile u32 gppr_12; /* 0x00070 */
96 volatile u32 gppr_13; /* 0x00074 */
97 volatile u32 gppr_14; /* 0x00078 */
98 volatile u32 gppr_15; /* 0x0007c */
99
100 /* Parallel Port Registers */
101 volatile u32 ppbr_h_a; /* 0x00080 */
102 volatile u32 ppbr_l_a; /* 0x00084 */
103 volatile u32 ppcr_a; /* 0x00088 */
104 volatile u32 ppcr; /* 0x0008c */
105 volatile u32 ppbr_h_b; /* 0x00090 */
106 volatile u32 ppbr_l_b; /* 0x00094 */
107 volatile u32 ppcr_b; /* 0x00098 */
108
109 /* Keyboard and Mouse Registers */
110 volatile u32 km_csr; /* 0x0009c */
111 volatile u32 k_rd; /* 0x000a0 */
112 volatile u32 m_rd; /* 0x000a4 */
113 volatile u32 k_wd; /* 0x000a8 */
114 volatile u32 m_wd; /* 0x000ac */
115
116 /* Serial Port Registers */
117 volatile u32 sbbr_h; /* 0x000b0 */
118 volatile u32 sbbr_l; /* 0x000b4 */
119 volatile u32 sscr_a; /* 0x000b8 */
120 volatile u32 stpir_a; /* 0x000bc */
121 volatile u32 stcir_a; /* 0x000c0 */
122 volatile u32 srpir_a; /* 0x000c4 */
123 volatile u32 srcir_a; /* 0x000c8 */
124 volatile u32 srtr_a; /* 0x000cc */
125 volatile u32 shadow_a; /* 0x000d0 */
126 volatile u32 sscr_b; /* 0x000d4 */
127 volatile u32 stpir_b; /* 0x000d8 */
128 volatile u32 stcir_b; /* 0x000dc */
129 volatile u32 srpir_b; /* 0x000e0 */
130 volatile u32 srcir_b; /* 0x000e4 */
131 volatile u32 srtr_b; /* 0x000e8 */
132 volatile u32 shadow_b; /* 0x000ec */
133
134 /* Ethernet Registers */
135 volatile u32 emcr; /* 0x000f0 */
136 volatile u32 eisr; /* 0x000f4 */
137 volatile u32 eier; /* 0x000f8 */
138 volatile u32 ercsr; /* 0x000fc */
139 volatile u32 erbr_h; /* 0x00100 */
140 volatile u32 erbr_l; /* 0x00104 */
141 volatile u32 erbar; /* 0x00108 */
142 volatile u32 ercir; /* 0x0010c */
143 volatile u32 erpir; /* 0x00110 */
144 volatile u32 ertr; /* 0x00114 */
145 volatile u32 etcsr; /* 0x00118 */
146 volatile u32 ersr; /* 0x0011c */
147 volatile u32 etcdc; /* 0x00120 */
148 volatile u32 ebir; /* 0x00124 */
149 volatile u32 etbr_h; /* 0x00128 */
150 volatile u32 etbr_l; /* 0x0012c */
151 volatile u32 etcir; /* 0x00130 */
152 volatile u32 etpir; /* 0x00134 */
153 volatile u32 emar_h; /* 0x00138 */
154 volatile u32 emar_l; /* 0x0013c */
155 volatile u32 ehar_h; /* 0x00140 */
156 volatile u32 ehar_l; /* 0x00144 */
157 volatile u32 micr; /* 0x00148 */
158 volatile u32 midr_r; /* 0x0014c */
159 volatile u32 midr_w; /* 0x00150 */
160 volatile u32 pad1[(0x20000 - 0x00154) / 4];
161
162 /* SuperIO Registers XXX */
163 struct ioc3_sioregs sregs; /* 0x20000 */
164 volatile u32 pad2[(0x40000 - 0x20180) / 4];
165
166 /* SSRAM Diagnostic Access */
167 volatile u32 ssram[(0x80000 - 0x40000) / 4];
168
169 /* Bytebus device offsets
170 0x80000 - Access to the generic devices selected with DEV0
171 0x9FFFF bytebus DEV_SEL_0
172 0xA0000 - Access to the generic devices selected with DEV1
173 0xBFFFF bytebus DEV_SEL_1
174 0xC0000 - Access to the generic devices selected with DEV2
175 0xDFFFF bytebus DEV_SEL_2
176 0xE0000 - Access to the generic devices selected with DEV3
177 0xFFFFF bytebus DEV_SEL_3 */
178};
179
180/*
181 * Ethernet RX Buffer
182 */
183struct ioc3_erxbuf {
184 u32 w0; /* first word (valid,bcnt,cksum) */
185 u32 err; /* second word various errors */
186 /* next comes n bytes of padding */
187 /* then the received ethernet frame itself */
188};
189
190#define ERXBUF_IPCKSUM_MASK 0x0000ffff
191#define ERXBUF_BYTECNT_MASK 0x07ff0000
192#define ERXBUF_BYTECNT_SHIFT 16
193#define ERXBUF_V 0x80000000
194
195#define ERXBUF_CRCERR 0x00000001 /* aka RSV15 */
196#define ERXBUF_FRAMERR 0x00000002 /* aka RSV14 */
197#define ERXBUF_CODERR 0x00000004 /* aka RSV13 */
198#define ERXBUF_INVPREAMB 0x00000008 /* aka RSV18 */
199#define ERXBUF_LOLEN 0x00007000 /* aka RSV2_0 */
200#define ERXBUF_HILEN 0x03ff0000 /* aka RSV12_3 */
201#define ERXBUF_MULTICAST 0x04000000 /* aka RSV16 */
202#define ERXBUF_BROADCAST 0x08000000 /* aka RSV17 */
203#define ERXBUF_LONGEVENT 0x10000000 /* aka RSV19 */
204#define ERXBUF_BADPKT 0x20000000 /* aka RSV20 */
205#define ERXBUF_GOODPKT 0x40000000 /* aka RSV21 */
206#define ERXBUF_CARRIER 0x80000000 /* aka RSV22 */
207
208/*
209 * Ethernet TX Descriptor
210 */
211#define ETXD_DATALEN 104
212struct ioc3_etxd {
213 u32 cmd; /* command field */
214 u32 bufcnt; /* buffer counts field */
215 u64 p1; /* buffer pointer 1 */
216 u64 p2; /* buffer pointer 2 */
217 u8 data[ETXD_DATALEN]; /* opt. tx data */
218};
219
220#define ETXD_BYTECNT_MASK 0x000007ff /* total byte count */
221#define ETXD_INTWHENDONE 0x00001000 /* intr when done */
222#define ETXD_D0V 0x00010000 /* data 0 valid */
223#define ETXD_B1V 0x00020000 /* buf 1 valid */
224#define ETXD_B2V 0x00040000 /* buf 2 valid */
225#define ETXD_DOCHECKSUM 0x00080000 /* insert ip cksum */
226#define ETXD_CHKOFF_MASK 0x07f00000 /* cksum byte offset */
227#define ETXD_CHKOFF_SHIFT 20
228
229#define ETXD_D0CNT_MASK 0x0000007f
230#define ETXD_B1CNT_MASK 0x0007ff00
231#define ETXD_B1CNT_SHIFT 8
232#define ETXD_B2CNT_MASK 0x7ff00000
233#define ETXD_B2CNT_SHIFT 20
234
235/*
236 * Bytebus device space
237 */
238#define IOC3_BYTEBUS_DEV0 0x80000L
239#define IOC3_BYTEBUS_DEV1 0xa0000L
240#define IOC3_BYTEBUS_DEV2 0xc0000L
241#define IOC3_BYTEBUS_DEV3 0xe0000L
242
243/* ------------------------------------------------------------------------- */
244
245/* Superio Registers (PIO Access) */
246#define IOC3_SIO_BASE 0x20000
247#define IOC3_SIO_UARTC (IOC3_SIO_BASE+0x141) /* UART Config */
248#define IOC3_SIO_KBDCG (IOC3_SIO_BASE+0x142) /* KBD Config */
249#define IOC3_SIO_PP_BASE (IOC3_SIO_BASE+PP_BASE) /* Parallel Port */
250#define IOC3_SIO_RTC_BASE (IOC3_SIO_BASE+0x168) /* Real Time Clock */
251#define IOC3_SIO_UB_BASE (IOC3_SIO_BASE+UARTB_BASE) /* UART B */
252#define IOC3_SIO_UA_BASE (IOC3_SIO_BASE+UARTA_BASE) /* UART A */
253
254/* SSRAM Diagnostic Access */
255#define IOC3_SSRAM IOC3_RAM_OFF /* base of SSRAM diagnostic access */
256#define IOC3_SSRAM_LEN 0x40000 /* 256kb (address space size, may not be fully populated) */
257#define IOC3_SSRAM_DM 0x0000ffff /* data mask */
258#define IOC3_SSRAM_PM 0x00010000 /* parity mask */
259
260/* bitmasks for PCI_SCR */
261#define PCI_SCR_PAR_RESP_EN 0x00000040 /* enb PCI parity checking */
262#define PCI_SCR_SERR_EN 0x00000100 /* enable the SERR# driver */
263#define PCI_SCR_DROP_MODE_EN 0x00008000 /* drop pios on parity err */
264#define PCI_SCR_RX_SERR (0x1 << 16)
265#define PCI_SCR_DROP_MODE (0x1 << 17)
266#define PCI_SCR_SIG_PAR_ERR (0x1 << 24)
267#define PCI_SCR_SIG_TAR_ABRT (0x1 << 27)
268#define PCI_SCR_RX_TAR_ABRT (0x1 << 28)
269#define PCI_SCR_SIG_MST_ABRT (0x1 << 29)
270#define PCI_SCR_SIG_SERR (0x1 << 30)
271#define PCI_SCR_PAR_ERR (0x1 << 31)
272
273/* bitmasks for IOC3_KM_CSR */
274#define KM_CSR_K_WRT_PEND 0x00000001 /* kbd port xmitting or resetting */
275#define KM_CSR_M_WRT_PEND 0x00000002 /* mouse port xmitting or resetting */
276#define KM_CSR_K_LCB 0x00000004 /* Line Cntrl Bit for last KBD write */
277#define KM_CSR_M_LCB 0x00000008 /* same for mouse */
278#define KM_CSR_K_DATA 0x00000010 /* state of kbd data line */
279#define KM_CSR_K_CLK 0x00000020 /* state of kbd clock line */
280#define KM_CSR_K_PULL_DATA 0x00000040 /* pull kbd data line low */
281#define KM_CSR_K_PULL_CLK 0x00000080 /* pull kbd clock line low */
282#define KM_CSR_M_DATA 0x00000100 /* state of ms data line */
283#define KM_CSR_M_CLK 0x00000200 /* state of ms clock line */
284#define KM_CSR_M_PULL_DATA 0x00000400 /* pull ms data line low */
285#define KM_CSR_M_PULL_CLK 0x00000800 /* pull ms clock line low */
286#define KM_CSR_EMM_MODE 0x00001000 /* emulation mode */
287#define KM_CSR_SIM_MODE 0x00002000 /* clock X8 */
288#define KM_CSR_K_SM_IDLE 0x00004000 /* Keyboard is idle */
289#define KM_CSR_M_SM_IDLE 0x00008000 /* Mouse is idle */
290#define KM_CSR_K_TO 0x00010000 /* Keyboard trying to send/receive */
291#define KM_CSR_M_TO 0x00020000 /* Mouse trying to send/receive */
292#define KM_CSR_K_TO_EN 0x00040000 /* KM_CSR_K_TO + KM_CSR_K_TO_EN = cause
293 SIO_IR to assert */
294#define KM_CSR_M_TO_EN 0x00080000 /* KM_CSR_M_TO + KM_CSR_M_TO_EN = cause
295 SIO_IR to assert */
296#define KM_CSR_K_CLAMP_ONE 0x00100000 /* Pull K_CLK low after rec. one char */
297#define KM_CSR_M_CLAMP_ONE 0x00200000 /* Pull M_CLK low after rec. one char */
298#define KM_CSR_K_CLAMP_THREE 0x00400000 /* Pull K_CLK low after rec. three chars */
299#define KM_CSR_M_CLAMP_THREE 0x00800000 /* Pull M_CLK low after rec. three char */
300
301/* bitmasks for IOC3_K_RD and IOC3_M_RD */
302#define KM_RD_DATA_2 0x000000ff /* 3rd char recvd since last read */
303#define KM_RD_DATA_2_SHIFT 0
304#define KM_RD_DATA_1 0x0000ff00 /* 2nd char recvd since last read */
305#define KM_RD_DATA_1_SHIFT 8
306#define KM_RD_DATA_0 0x00ff0000 /* 1st char recvd since last read */
307#define KM_RD_DATA_0_SHIFT 16
308#define KM_RD_FRAME_ERR_2 0x01000000 /* framing or parity error in byte 2 */
309#define KM_RD_FRAME_ERR_1 0x02000000 /* same for byte 1 */
310#define KM_RD_FRAME_ERR_0 0x04000000 /* same for byte 0 */
311
312#define KM_RD_KBD_MSE 0x08000000 /* 0 if from kbd, 1 if from mouse */
313#define KM_RD_OFLO 0x10000000 /* 4th char recvd before this read */
314#define KM_RD_VALID_2 0x20000000 /* DATA_2 valid */
315#define KM_RD_VALID_1 0x40000000 /* DATA_1 valid */
316#define KM_RD_VALID_0 0x80000000 /* DATA_0 valid */
317#define KM_RD_VALID_ALL (KM_RD_VALID_0|KM_RD_VALID_1|KM_RD_VALID_2)
318
319/* bitmasks for IOC3_K_WD & IOC3_M_WD */
320#define KM_WD_WRT_DATA 0x000000ff /* write to keyboard/mouse port */
321#define KM_WD_WRT_DATA_SHIFT 0
322
323/* bitmasks for serial RX status byte */
324#define RXSB_OVERRUN 0x01 /* char(s) lost */
325#define RXSB_PAR_ERR 0x02 /* parity error */
326#define RXSB_FRAME_ERR 0x04 /* framing error */
327#define RXSB_BREAK 0x08 /* break character */
328#define RXSB_CTS 0x10 /* state of CTS */
329#define RXSB_DCD 0x20 /* state of DCD */
330#define RXSB_MODEM_VALID 0x40 /* DCD, CTS and OVERRUN are valid */
331#define RXSB_DATA_VALID 0x80 /* data byte, FRAME_ERR PAR_ERR & BREAK valid */
332
333/* bitmasks for serial TX control byte */
334#define TXCB_INT_WHEN_DONE 0x20 /* interrupt after this byte is sent */
335#define TXCB_INVALID 0x00 /* byte is invalid */
336#define TXCB_VALID 0x40 /* byte is valid */
337#define TXCB_MCR 0x80 /* data<7:0> to modem control register */
338#define TXCB_DELAY 0xc0 /* delay data<7:0> mSec */
339
340/* bitmasks for IOC3_SBBR_L */
341#define SBBR_L_SIZE 0x00000001 /* 0 == 1KB rings, 1 == 4KB rings */
342#define SBBR_L_BASE 0xfffff000 /* lower serial ring base addr */
343
344/* bitmasks for IOC3_SSCR_<A:B> */
345#define SSCR_RX_THRESHOLD 0x000001ff /* hiwater mark */
346#define SSCR_TX_TIMER_BUSY 0x00010000 /* TX timer in progress */
347#define SSCR_HFC_EN 0x00020000 /* hardware flow control enabled */
348#define SSCR_RX_RING_DCD 0x00040000 /* post RX record on delta-DCD */
349#define SSCR_RX_RING_CTS 0x00080000 /* post RX record on delta-CTS */
350#define SSCR_HIGH_SPD 0x00100000 /* 4X speed */
351#define SSCR_DIAG 0x00200000 /* bypass clock divider for sim */
352#define SSCR_RX_DRAIN 0x08000000 /* drain RX buffer to memory */
353#define SSCR_DMA_EN 0x10000000 /* enable ring buffer DMA */
354#define SSCR_DMA_PAUSE 0x20000000 /* pause DMA */
355#define SSCR_PAUSE_STATE 0x40000000 /* sets when PAUSE takes effect */
356#define SSCR_RESET 0x80000000 /* reset DMA channels */
357
358/* all producer/comsumer pointers are the same bitfield */
359#define PROD_CONS_PTR_4K 0x00000ff8 /* for 4K buffers */
360#define PROD_CONS_PTR_1K 0x000003f8 /* for 1K buffers */
361#define PROD_CONS_PTR_OFF 3
362
363/* bitmasks for IOC3_SRCIR_<A:B> */
364#define SRCIR_ARM 0x80000000 /* arm RX timer */
365
366/* bitmasks for IOC3_SRPIR_<A:B> */
367#define SRPIR_BYTE_CNT 0x07000000 /* bytes in packer */
368#define SRPIR_BYTE_CNT_SHIFT 24
369
370/* bitmasks for IOC3_STCIR_<A:B> */
371#define STCIR_BYTE_CNT 0x0f000000 /* bytes in unpacker */
372#define STCIR_BYTE_CNT_SHIFT 24
373
374/* bitmasks for IOC3_SHADOW_<A:B> */
375#define SHADOW_DR 0x00000001 /* data ready */
376#define SHADOW_OE 0x00000002 /* overrun error */
377#define SHADOW_PE 0x00000004 /* parity error */
378#define SHADOW_FE 0x00000008 /* framing error */
379#define SHADOW_BI 0x00000010 /* break interrupt */
380#define SHADOW_THRE 0x00000020 /* transmit holding register empty */
381#define SHADOW_TEMT 0x00000040 /* transmit shift register empty */
382#define SHADOW_RFCE 0x00000080 /* char in RX fifo has an error */
383#define SHADOW_DCTS 0x00010000 /* delta clear to send */
384#define SHADOW_DDCD 0x00080000 /* delta data carrier detect */
385#define SHADOW_CTS 0x00100000 /* clear to send */
386#define SHADOW_DCD 0x00800000 /* data carrier detect */
387#define SHADOW_DTR 0x01000000 /* data terminal ready */
388#define SHADOW_RTS 0x02000000 /* request to send */
389#define SHADOW_OUT1 0x04000000 /* 16550 OUT1 bit */
390#define SHADOW_OUT2 0x08000000 /* 16550 OUT2 bit */
391#define SHADOW_LOOP 0x10000000 /* loopback enabled */
392
393/* bitmasks for IOC3_SRTR_<A:B> */
394#define SRTR_CNT 0x00000fff /* reload value for RX timer */
395#define SRTR_CNT_VAL 0x0fff0000 /* current value of RX timer */
396#define SRTR_CNT_VAL_SHIFT 16
397#define SRTR_HZ 16000 /* SRTR clock frequency */
398
399/* bitmasks for IOC3_SIO_IR, IOC3_SIO_IEC and IOC3_SIO_IES */
400#define SIO_IR_SA_TX_MT 0x00000001 /* Serial port A TX empty */
401#define SIO_IR_SA_RX_FULL 0x00000002 /* port A RX buf full */
402#define SIO_IR_SA_RX_HIGH 0x00000004 /* port A RX hiwat */
403#define SIO_IR_SA_RX_TIMER 0x00000008 /* port A RX timeout */
404#define SIO_IR_SA_DELTA_DCD 0x00000010 /* port A delta DCD */
405#define SIO_IR_SA_DELTA_CTS 0x00000020 /* port A delta CTS */
406#define SIO_IR_SA_INT 0x00000040 /* port A pass-thru intr */
407#define SIO_IR_SA_TX_EXPLICIT 0x00000080 /* port A explicit TX thru */
408#define SIO_IR_SA_MEMERR 0x00000100 /* port A PCI error */
409#define SIO_IR_SB_TX_MT 0x00000200 /* */
410#define SIO_IR_SB_RX_FULL 0x00000400 /* */
411#define SIO_IR_SB_RX_HIGH 0x00000800 /* */
412#define SIO_IR_SB_RX_TIMER 0x00001000 /* */
413#define SIO_IR_SB_DELTA_DCD 0x00002000 /* */
414#define SIO_IR_SB_DELTA_CTS 0x00004000 /* */
415#define SIO_IR_SB_INT 0x00008000 /* */
416#define SIO_IR_SB_TX_EXPLICIT 0x00010000 /* */
417#define SIO_IR_SB_MEMERR 0x00020000 /* */
418#define SIO_IR_PP_INT 0x00040000 /* P port pass-thru intr */
419#define SIO_IR_PP_INTA 0x00080000 /* PP context A thru */
420#define SIO_IR_PP_INTB 0x00100000 /* PP context B thru */
421#define SIO_IR_PP_MEMERR 0x00200000 /* PP PCI error */
422#define SIO_IR_KBD_INT 0x00400000 /* kbd/mouse intr */
423#define SIO_IR_RT_INT 0x08000000 /* RT output pulse */
424#define SIO_IR_GEN_INT1 0x10000000 /* RT input pulse */
425#define SIO_IR_GEN_INT_SHIFT 28
426
427/* per device interrupt masks */
428#define SIO_IR_SA (SIO_IR_SA_TX_MT | SIO_IR_SA_RX_FULL | \
429 SIO_IR_SA_RX_HIGH | SIO_IR_SA_RX_TIMER | \
430 SIO_IR_SA_DELTA_DCD | SIO_IR_SA_DELTA_CTS | \
431 SIO_IR_SA_INT | SIO_IR_SA_TX_EXPLICIT | \
432 SIO_IR_SA_MEMERR)
433#define SIO_IR_SB (SIO_IR_SB_TX_MT | SIO_IR_SB_RX_FULL | \
434 SIO_IR_SB_RX_HIGH | SIO_IR_SB_RX_TIMER | \
435 SIO_IR_SB_DELTA_DCD | SIO_IR_SB_DELTA_CTS | \
436 SIO_IR_SB_INT | SIO_IR_SB_TX_EXPLICIT | \
437 SIO_IR_SB_MEMERR)
438#define SIO_IR_PP (SIO_IR_PP_INT | SIO_IR_PP_INTA | \
439 SIO_IR_PP_INTB | SIO_IR_PP_MEMERR)
440#define SIO_IR_RT (SIO_IR_RT_INT | SIO_IR_GEN_INT1)
441
442/* macro to load pending interrupts */
443#define IOC3_PENDING_INTRS(mem) (PCI_INW(&((mem)->sio_ir)) & \
444 PCI_INW(&((mem)->sio_ies_ro)))
445
446/* bitmasks for SIO_CR */
447#define SIO_CR_SIO_RESET 0x00000001 /* reset the SIO */
448#define SIO_CR_SER_A_BASE 0x000000fe /* DMA poll addr port A */
449#define SIO_CR_SER_A_BASE_SHIFT 1
450#define SIO_CR_SER_B_BASE 0x00007f00 /* DMA poll addr port B */
451#define SIO_CR_SER_B_BASE_SHIFT 8
452#define SIO_SR_CMD_PULSE 0x00078000 /* byte bus strobe length */
453#define SIO_CR_CMD_PULSE_SHIFT 15
454#define SIO_CR_ARB_DIAG 0x00380000 /* cur !enet PCI requet (ro) */
455#define SIO_CR_ARB_DIAG_TXA 0x00000000
456#define SIO_CR_ARB_DIAG_RXA 0x00080000
457#define SIO_CR_ARB_DIAG_TXB 0x00100000
458#define SIO_CR_ARB_DIAG_RXB 0x00180000
459#define SIO_CR_ARB_DIAG_PP 0x00200000
460#define SIO_CR_ARB_DIAG_IDLE 0x00400000 /* 0 -> active request (ro) */
461
462/* bitmasks for INT_OUT */
463#define INT_OUT_COUNT 0x0000ffff /* pulse interval timer */
464#define INT_OUT_MODE 0x00070000 /* mode mask */
465#define INT_OUT_MODE_0 0x00000000 /* set output to 0 */
466#define INT_OUT_MODE_1 0x00040000 /* set output to 1 */
467#define INT_OUT_MODE_1PULSE 0x00050000 /* send 1 pulse */
468#define INT_OUT_MODE_PULSES 0x00060000 /* send 1 pulse every interval */
469#define INT_OUT_MODE_SQW 0x00070000 /* toggle output every interval */
470#define INT_OUT_DIAG 0x40000000 /* diag mode */
471#define INT_OUT_INT_OUT 0x80000000 /* current state of INT_OUT */
472
473/* time constants for INT_OUT */
474#define INT_OUT_NS_PER_TICK (30 * 260) /* 30 ns PCI clock, divisor=260 */
475#define INT_OUT_TICKS_PER_PULSE 3 /* outgoing pulse lasts 3 ticks */
476#define INT_OUT_US_TO_COUNT(x) /* convert uS to a count value */ \
477 (((x) * 10 + INT_OUT_NS_PER_TICK / 200) * \
478 100 / INT_OUT_NS_PER_TICK - 1)
479#define INT_OUT_COUNT_TO_US(x) /* convert count value to uS */ \
480 (((x) + 1) * INT_OUT_NS_PER_TICK / 1000)
481#define INT_OUT_MIN_TICKS 3 /* min period is width of pulse in "ticks" */
482#define INT_OUT_MAX_TICKS INT_OUT_COUNT /* largest possible count */
483
484/* bitmasks for GPCR */
485#define GPCR_DIR 0x000000ff /* tristate pin input or output */
486#define GPCR_DIR_PIN(x) (1<<(x)) /* access one of the DIR bits */
487#define GPCR_EDGE 0x000f0000 /* extint edge or level sensitive */
488#define GPCR_EDGE_PIN(x) (1<<((x)+15)) /* access one of the EDGE bits */
489
490/* values for GPCR */
491#define GPCR_INT_OUT_EN 0x00100000 /* enable INT_OUT to pin 0 */
492#define GPCR_MLAN_EN 0x00200000 /* enable MCR to pin 8 */
493#define GPCR_DIR_SERA_XCVR 0x00000080 /* Port A Transceiver select enable */
494#define GPCR_DIR_SERB_XCVR 0x00000040 /* Port B Transceiver select enable */
495#define GPCR_DIR_PHY_RST 0x00000020 /* ethernet PHY reset enable */
496
497/* defs for some of the generic I/O pins */
498#define GPCR_PHY_RESET 0x20 /* pin is output to PHY reset */
499#define GPCR_UARTB_MODESEL 0x40 /* pin is output to port B mode sel */
500#define GPCR_UARTA_MODESEL 0x80 /* pin is output to port A mode sel */
501
502#define GPPR_PHY_RESET_PIN 5 /* GIO pin controlling phy reset */
503#define GPPR_UARTB_MODESEL_PIN 6 /* GIO pin controlling uart b mode select */
504#define GPPR_UARTA_MODESEL_PIN 7 /* GIO pin controlling uart a mode select */
505
506#define EMCR_DUPLEX 0x00000001
507#define EMCR_PROMISC 0x00000002
508#define EMCR_PADEN 0x00000004
509#define EMCR_RXOFF_MASK 0x000001f8
510#define EMCR_RXOFF_SHIFT 3
511#define EMCR_RAMPAR 0x00000200
512#define EMCR_BADPAR 0x00000800
513#define EMCR_BUFSIZ 0x00001000
514#define EMCR_TXDMAEN 0x00002000
515#define EMCR_TXEN 0x00004000
516#define EMCR_RXDMAEN 0x00008000
517#define EMCR_RXEN 0x00010000
518#define EMCR_LOOPBACK 0x00020000
519#define EMCR_ARB_DIAG 0x001c0000
520#define EMCR_ARB_DIAG_IDLE 0x00200000
521#define EMCR_RST 0x80000000
522
523#define EISR_RXTIMERINT 0x00000001
524#define EISR_RXTHRESHINT 0x00000002
525#define EISR_RXOFLO 0x00000004
526#define EISR_RXBUFOFLO 0x00000008
527#define EISR_RXMEMERR 0x00000010
528#define EISR_RXPARERR 0x00000020
529#define EISR_TXEMPTY 0x00010000
530#define EISR_TXRTRY 0x00020000
531#define EISR_TXEXDEF 0x00040000
532#define EISR_TXLCOL 0x00080000
533#define EISR_TXGIANT 0x00100000
534#define EISR_TXBUFUFLO 0x00200000
535#define EISR_TXEXPLICIT 0x00400000
536#define EISR_TXCOLLWRAP 0x00800000
537#define EISR_TXDEFERWRAP 0x01000000
538#define EISR_TXMEMERR 0x02000000
539#define EISR_TXPARERR 0x04000000
540
541#define ERCSR_THRESH_MASK 0x000001ff /* enet RX threshold */
542#define ERCSR_RX_TMR 0x40000000 /* simulation only */
543#define ERCSR_DIAG_OFLO 0x80000000 /* simulation only */
544
545#define ERBR_ALIGNMENT 4096
546#define ERBR_L_RXRINGBASE_MASK 0xfffff000
547
548#define ERBAR_BARRIER_BIT 0x0100
549#define ERBAR_RXBARR_MASK 0xffff0000
550#define ERBAR_RXBARR_SHIFT 16
551
552#define ERCIR_RXCONSUME_MASK 0x00000fff
553
554#define ERPIR_RXPRODUCE_MASK 0x00000fff
555#define ERPIR_ARM 0x80000000
556
557#define ERTR_CNT_MASK 0x000007ff
558
559#define ETCSR_IPGT_MASK 0x0000007f
560#define ETCSR_IPGR1_MASK 0x00007f00
561#define ETCSR_IPGR1_SHIFT 8
562#define ETCSR_IPGR2_MASK 0x007f0000
563#define ETCSR_IPGR2_SHIFT 16
564#define ETCSR_NOTXCLK 0x80000000
565
566#define ETCDC_COLLCNT_MASK 0x0000ffff
567#define ETCDC_DEFERCNT_MASK 0xffff0000
568#define ETCDC_DEFERCNT_SHIFT 16
569
570#define ETBR_ALIGNMENT (64*1024)
571#define ETBR_L_RINGSZ_MASK 0x00000001
572#define ETBR_L_RINGSZ128 0
573#define ETBR_L_RINGSZ512 1
574#define ETBR_L_TXRINGBASE_MASK 0xffffc000
575
576#define ETCIR_TXCONSUME_MASK 0x0000ffff
577#define ETCIR_IDLE 0x80000000
578
579#define ETPIR_TXPRODUCE_MASK 0x0000ffff
580
581#define EBIR_TXBUFPROD_MASK 0x0000001f
582#define EBIR_TXBUFCONS_MASK 0x00001f00
583#define EBIR_TXBUFCONS_SHIFT 8
584#define EBIR_RXBUFPROD_MASK 0x007fc000
585#define EBIR_RXBUFPROD_SHIFT 14
586#define EBIR_RXBUFCONS_MASK 0xff800000
587#define EBIR_RXBUFCONS_SHIFT 23
588
589#define MICR_REGADDR_MASK 0x0000001f
590#define MICR_PHYADDR_MASK 0x000003e0
591#define MICR_PHYADDR_SHIFT 5
592#define MICR_READTRIG 0x00000400
593#define MICR_BUSY 0x00000800
594
595#define MIDR_DATA_MASK 0x0000ffff
596
597#define ERXBUF_IPCKSUM_MASK 0x0000ffff
598#define ERXBUF_BYTECNT_MASK 0x07ff0000
599#define ERXBUF_BYTECNT_SHIFT 16
600#define ERXBUF_V 0x80000000
601
602#define ERXBUF_CRCERR 0x00000001 /* aka RSV15 */
603#define ERXBUF_FRAMERR 0x00000002 /* aka RSV14 */
604#define ERXBUF_CODERR 0x00000004 /* aka RSV13 */
605#define ERXBUF_INVPREAMB 0x00000008 /* aka RSV18 */
606#define ERXBUF_LOLEN 0x00007000 /* aka RSV2_0 */
607#define ERXBUF_HILEN 0x03ff0000 /* aka RSV12_3 */
608#define ERXBUF_MULTICAST 0x04000000 /* aka RSV16 */
609#define ERXBUF_BROADCAST 0x08000000 /* aka RSV17 */
610#define ERXBUF_LONGEVENT 0x10000000 /* aka RSV19 */
611#define ERXBUF_BADPKT 0x20000000 /* aka RSV20 */
612#define ERXBUF_GOODPKT 0x40000000 /* aka RSV21 */
613#define ERXBUF_CARRIER 0x80000000 /* aka RSV22 */
614
615#define ETXD_BYTECNT_MASK 0x000007ff /* total byte count */
616#define ETXD_INTWHENDONE 0x00001000 /* intr when done */
617#define ETXD_D0V 0x00010000 /* data 0 valid */
618#define ETXD_B1V 0x00020000 /* buf 1 valid */
619#define ETXD_B2V 0x00040000 /* buf 2 valid */
620#define ETXD_DOCHECKSUM 0x00080000 /* insert ip cksum */
621#define ETXD_CHKOFF_MASK 0x07f00000 /* cksum byte offset */
622#define ETXD_CHKOFF_SHIFT 20
623
624#define ETXD_D0CNT_MASK 0x0000007f
625#define ETXD_B1CNT_MASK 0x0007ff00
626#define ETXD_B1CNT_SHIFT 8
627#define ETXD_B2CNT_MASK 0x7ff00000
628#define ETXD_B2CNT_SHIFT 20
629
630typedef enum ioc3_subdevs_e {
631 ioc3_subdev_ether,
632 ioc3_subdev_generic,
633 ioc3_subdev_nic,
634 ioc3_subdev_kbms,
635 ioc3_subdev_ttya,
636 ioc3_subdev_ttyb,
637 ioc3_subdev_ecpp,
638 ioc3_subdev_rt,
639 ioc3_nsubdevs
640} ioc3_subdev_t;
641
642/* subdevice disable bits,
643 * from the standard INFO_LBL_SUBDEVS
644 */
645#define IOC3_SDB_ETHER (1<<ioc3_subdev_ether)
646#define IOC3_SDB_GENERIC (1<<ioc3_subdev_generic)
647#define IOC3_SDB_NIC (1<<ioc3_subdev_nic)
648#define IOC3_SDB_KBMS (1<<ioc3_subdev_kbms)
649#define IOC3_SDB_TTYA (1<<ioc3_subdev_ttya)
650#define IOC3_SDB_TTYB (1<<ioc3_subdev_ttyb)
651#define IOC3_SDB_ECPP (1<<ioc3_subdev_ecpp)
652#define IOC3_SDB_RT (1<<ioc3_subdev_rt)
653
654#define IOC3_ALL_SUBDEVS ((1<<ioc3_nsubdevs)-1)
655
656#define IOC3_SDB_SERIAL (IOC3_SDB_TTYA|IOC3_SDB_TTYB)
657
658#define IOC3_STD_SUBDEVS IOC3_ALL_SUBDEVS
659
660#define IOC3_INTA_SUBDEVS IOC3_SDB_ETHER
661#define IOC3_INTB_SUBDEVS (IOC3_SDB_GENERIC|IOC3_SDB_KBMS|IOC3_SDB_SERIAL|IOC3_SDB_ECPP|IOC3_SDB_RT)
662
663#endif /* _IOC3_H */
diff --git a/arch/mips/include/asm/sn/klconfig.h b/arch/mips/include/asm/sn/klconfig.h
new file mode 100644
index 000000000000..09e590daca17
--- /dev/null
+++ b/arch/mips/include/asm/sn/klconfig.h
@@ -0,0 +1,898 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Derived from IRIX <sys/SN/klconfig.h>.
7 *
8 * Copyright (C) 1992 - 1997, 1999, 2000 Silicon Graphics, Inc.
9 * Copyright (C) 1999, 2000 by Ralf Baechle
10 */
11#ifndef _ASM_SN_KLCONFIG_H
12#define _ASM_SN_KLCONFIG_H
13
14/*
15 * The KLCONFIG structures store info about the various BOARDs found
16 * during Hardware Discovery. In addition, it stores info about the
17 * components found on the BOARDs.
18 */
19
20/*
21 * WARNING:
22 * Certain assembly language routines (notably xxxxx.s) in the IP27PROM
23 * will depend on the format of the data structures in this file. In
24 * most cases, rearranging the fields can seriously break things.
25 * Adding fields in the beginning or middle can also break things.
26 * Add fields if necessary, to the end of a struct in such a way
27 * that offsets of existing fields do not change.
28 */
29
30#include <linux/types.h>
31#include <asm/sn/types.h>
32
33#if defined(CONFIG_SGI_IP27)
34
35#include <asm/sn/sn0/addrs.h>
36//#include <sys/SN/router.h>
37// XXX Stolen from <sys/SN/router.h>:
38#define MAX_ROUTER_PORTS (6) /* Max. number of ports on a router */
39#include <asm/sn/fru.h>
40//#include <sys/graph.h>
41//#include <sys/xtalk/xbow.h>
42
43#elif defined(CONFIG_SGI_IP35)
44
45#include <asm/sn/sn1/addrs.h>
46#include <sys/sn/router.h>
47#include <sys/graph.h>
48#include <asm/xtalk/xbow.h>
49
50#endif /* !CONFIG_SGI_IP27 && !CONFIG_SGI_IP35 */
51
52#if defined(CONFIG_SGI_IP27) || defined(CONFIG_SGI_IP35)
53#include <asm/sn/agent.h>
54#include <asm/fw/arc/types.h>
55#include <asm/fw/arc/hinv.h>
56#if defined(CONFIG_SGI_IP35)
57// The hack file has to be before vector and after sn0_fru....
58#include <asm/hack.h>
59#include <asm/sn/vector.h>
60#include <asm/xtalk/xtalk.h>
61#endif /* CONFIG_SGI_IP35 */
62#endif /* CONFIG_SGI_IP27 || CONFIG_SGI_IP35 */
63
64typedef u64 nic_t;
65
66#define KLCFGINFO_MAGIC 0xbeedbabe
67
68typedef s32 klconf_off_t;
69
70/*
71 * Some IMPORTANT OFFSETS. These are the offsets on all NODES.
72 */
73#define MAX_MODULE_ID 255
74#define SIZE_PAD 4096 /* 4k padding for structures */
75/*
76 * 1 NODE brd, 2 Router brd (1 8p, 1 meta), 6 Widgets,
77 * 2 Midplanes assuming no pci card cages
78 */
79#define MAX_SLOTS_PER_NODE (1 + 2 + 6 + 2)
80
81/* XXX if each node is guranteed to have some memory */
82
83#define MAX_PCI_DEVS 8
84
85/* lboard_t->brd_flags fields */
86/* All bits in this field are currently used. Try the pad fields if
87 you need more flag bits */
88
89#define ENABLE_BOARD 0x01
90#define FAILED_BOARD 0x02
91#define DUPLICATE_BOARD 0x04 /* Boards like midplanes/routers which
92 are discovered twice. Use one of them */
93#define VISITED_BOARD 0x08 /* Used for compact hub numbering. */
94#define LOCAL_MASTER_IO6 0x10 /* master io6 for that node */
95#define GLOBAL_MASTER_IO6 0x20
96#define THIRD_NIC_PRESENT 0x40 /* for future use */
97#define SECOND_NIC_PRESENT 0x80 /* addons like MIO are present */
98
99/* klinfo->flags fields */
100
101#define KLINFO_ENABLE 0x01 /* This component is enabled */
102#define KLINFO_FAILED 0x02 /* This component failed */
103#define KLINFO_DEVICE 0x04 /* This component is a device */
104#define KLINFO_VISITED 0x08 /* This component has been visited */
105#define KLINFO_CONTROLLER 0x10 /* This component is a device controller */
106#define KLINFO_INSTALL 0x20 /* Install a driver */
107#define KLINFO_HEADLESS 0x40 /* Headless (or hubless) component */
108#define IS_CONSOLE_IOC3(i) ((((klinfo_t *)i)->flags) & KLINFO_INSTALL)
109
110#define GB2 0x80000000
111
112#define MAX_RSV_PTRS 32
113
114/* Structures to manage various data storage areas */
115/* The numbers must be contiguous since the array index i
116 is used in the code to allocate various areas.
117*/
118
119#define BOARD_STRUCT 0
120#define COMPONENT_STRUCT 1
121#define ERRINFO_STRUCT 2
122#define KLMALLOC_TYPE_MAX (ERRINFO_STRUCT + 1)
123#define DEVICE_STRUCT 3
124
125
126typedef struct console_s {
127 unsigned long uart_base;
128 unsigned long config_base;
129 unsigned long memory_base;
130 short baud;
131 short flag;
132 int type;
133 nasid_t nasid;
134 char wid;
135 char npci;
136 nic_t baseio_nic;
137} console_t;
138
139typedef struct klc_malloc_hdr {
140 klconf_off_t km_base;
141 klconf_off_t km_limit;
142 klconf_off_t km_current;
143} klc_malloc_hdr_t;
144
145/* Functions/macros needed to use this structure */
146
147typedef struct kl_config_hdr {
148 u64 ch_magic; /* set this to KLCFGINFO_MAGIC */
149 u32 ch_version; /* structure version number */
150 klconf_off_t ch_malloc_hdr_off; /* offset of ch_malloc_hdr */
151 klconf_off_t ch_cons_off; /* offset of ch_cons */
152 klconf_off_t ch_board_info; /* the link list of boards */
153 console_t ch_cons_info; /* address info of the console */
154 klc_malloc_hdr_t ch_malloc_hdr[KLMALLOC_TYPE_MAX];
155 confidence_t ch_sw_belief; /* confidence that software is bad*/
156 confidence_t ch_sn0net_belief; /* confidence that sn0net is bad */
157} kl_config_hdr_t;
158
159
160#define KL_CONFIG_HDR(_nasid) ((kl_config_hdr_t *)(KLCONFIG_ADDR(_nasid)))
161#define KL_CONFIG_INFO_OFFSET(_nasid) \
162 (KL_CONFIG_HDR(_nasid)->ch_board_info)
163#define KL_CONFIG_INFO_SET_OFFSET(_nasid, _off) \
164 (KL_CONFIG_HDR(_nasid)->ch_board_info = (_off))
165
166#define KL_CONFIG_INFO(_nasid) \
167 (lboard_t *)((KL_CONFIG_HDR(_nasid)->ch_board_info) ? \
168 NODE_OFFSET_TO_K1((_nasid), KL_CONFIG_HDR(_nasid)->ch_board_info) : \
169 0)
170#define KL_CONFIG_MAGIC(_nasid) (KL_CONFIG_HDR(_nasid)->ch_magic)
171
172#define KL_CONFIG_CHECK_MAGIC(_nasid) \
173 (KL_CONFIG_HDR(_nasid)->ch_magic == KLCFGINFO_MAGIC)
174
175#define KL_CONFIG_HDR_INIT_MAGIC(_nasid) \
176 (KL_CONFIG_HDR(_nasid)->ch_magic = KLCFGINFO_MAGIC)
177
178/* --- New Macros for the changed kl_config_hdr_t structure --- */
179
180#define PTR_CH_MALLOC_HDR(_k) ((klc_malloc_hdr_t *)\
181 ((unsigned long)_k + (_k->ch_malloc_hdr_off)))
182
183#define KL_CONFIG_CH_MALLOC_HDR(_n) PTR_CH_MALLOC_HDR(KL_CONFIG_HDR(_n))
184
185#define PTR_CH_CONS_INFO(_k) ((console_t *)\
186 ((unsigned long)_k + (_k->ch_cons_off)))
187
188#define KL_CONFIG_CH_CONS_INFO(_n) PTR_CH_CONS_INFO(KL_CONFIG_HDR(_n))
189
190/* ------------------------------------------------------------- */
191
192#define KL_CONFIG_INFO_START(_nasid) \
193 (klconf_off_t)(KLCONFIG_OFFSET(_nasid) + sizeof(kl_config_hdr_t))
194
195#define KL_CONFIG_BOARD_NASID(_brd) ((_brd)->brd_nasid)
196#define KL_CONFIG_BOARD_SET_NEXT(_brd, _off) ((_brd)->brd_next = (_off))
197
198#define KL_CONFIG_DUPLICATE_BOARD(_brd) ((_brd)->brd_flags & DUPLICATE_BOARD)
199
200#define XBOW_PORT_TYPE_HUB(_xbowp, _link) \
201 ((_xbowp)->xbow_port_info[(_link) - BASE_XBOW_PORT].port_flag & XBOW_PORT_HUB)
202#define XBOW_PORT_TYPE_IO(_xbowp, _link) \
203 ((_xbowp)->xbow_port_info[(_link) - BASE_XBOW_PORT].port_flag & XBOW_PORT_IO)
204
205#define XBOW_PORT_IS_ENABLED(_xbowp, _link) \
206 ((_xbowp)->xbow_port_info[(_link) - BASE_XBOW_PORT].port_flag & XBOW_PORT_ENABLE)
207#define XBOW_PORT_NASID(_xbowp, _link) \
208 ((_xbowp)->xbow_port_info[(_link) - BASE_XBOW_PORT].port_nasid)
209
210#define XBOW_PORT_IO 0x1
211#define XBOW_PORT_HUB 0x2
212#define XBOW_PORT_ENABLE 0x4
213
214#define SN0_PORT_FENCE_SHFT 0
215#define SN0_PORT_FENCE_MASK (1 << SN0_PORT_FENCE_SHFT)
216
217/*
218 * The KLCONFIG area is organized as a LINKED LIST of BOARDs. A BOARD
219 * can be either 'LOCAL' or 'REMOTE'. LOCAL means it is attached to
220 * the LOCAL/current NODE. REMOTE means it is attached to a different
221 * node.(TBD - Need a way to treat ROUTER boards.)
222 *
223 * There are 2 different structures to represent these boards -
224 * lboard - Local board, rboard - remote board. These 2 structures
225 * can be arbitrarily mixed in the LINKED LIST of BOARDs. (Refer
226 * Figure below). The first byte of the rboard or lboard structure
227 * is used to find out its type - no unions are used.
228 * If it is a lboard, then the config info of this board will be found
229 * on the local node. (LOCAL NODE BASE + offset value gives pointer to
230 * the structure.
231 * If it is a rboard, the local structure contains the node number
232 * and the offset of the beginning of the LINKED LIST on the remote node.
233 * The details of the hardware on a remote node can be built locally,
234 * if required, by reading the LINKED LIST on the remote node and
235 * ignoring all the rboards on that node.
236 *
237 * The local node uses the REMOTE NODE NUMBER + OFFSET to point to the
238 * First board info on the remote node. The remote node list is
239 * traversed as the local list, using the REMOTE BASE ADDRESS and not
240 * the local base address and ignoring all rboard values.
241 *
242 *
243 KLCONFIG
244
245 +------------+ +------------+ +------------+ +------------+
246 | lboard | +-->| lboard | +-->| rboard | +-->| lboard |
247 +------------+ | +------------+ | +------------+ | +------------+
248 | board info | | | board info | | |errinfo,bptr| | | board info |
249 +------------+ | +------------+ | +------------+ | +------------+
250 | offset |--+ | offset |--+ | offset |--+ |offset=NULL |
251 +------------+ +------------+ +------------+ +------------+
252
253
254 +------------+
255 | board info |
256 +------------+ +--------------------------------+
257 | compt 1 |------>| type, rev, diaginfo, size ... | (CPU)
258 +------------+ +--------------------------------+
259 | compt 2 |--+
260 +------------+ | +--------------------------------+
261 | ... | +--->| type, rev, diaginfo, size ... | (MEM_BANK)
262 +------------+ +--------------------------------+
263 | errinfo |--+
264 +------------+ | +--------------------------------+
265 +--->|r/l brd errinfo,compt err flags |
266 +--------------------------------+
267
268 *
269 * Each BOARD consists of COMPONENTs and the BOARD structure has
270 * pointers (offsets) to its COMPONENT structure.
271 * The COMPONENT structure has version info, size and speed info, revision,
272 * error info and the NIC info. This structure can accommodate any
273 * BOARD with arbitrary COMPONENT composition.
274 *
275 * The ERRORINFO part of each BOARD has error information
276 * that describes errors about the BOARD itself. It also has flags to
277 * indicate the COMPONENT(s) on the board that have errors. The error
278 * information specific to the COMPONENT is present in the respective
279 * COMPONENT structure.
280 *
281 * The ERRORINFO structure is also treated like a COMPONENT, ie. the
282 * BOARD has pointers(offset) to the ERRORINFO structure. The rboard
283 * structure also has a pointer to the ERRORINFO structure. This is
284 * the place to store ERRORINFO about a REMOTE NODE, if the HUB on
285 * that NODE is not working or if the REMOTE MEMORY is BAD. In cases where
286 * only the CPU of the REMOTE NODE is disabled, the ERRORINFO pointer can
287 * be a NODE NUMBER, REMOTE OFFSET combination, pointing to error info
288 * which is present on the REMOTE NODE.(TBD)
289 * REMOTE ERRINFO can be stored on any of the nearest nodes
290 * or on all the nearest nodes.(TBD)
291 * Like BOARD structures, REMOTE ERRINFO structures can be built locally
292 * using the rboard errinfo pointer.
293 *
294 * In order to get useful information from this Data organization, a set of
295 * interface routines are provided (TBD). The important thing to remember while
296 * manipulating the structures, is that, the NODE number information should
297 * be used. If the NODE is non-zero (remote) then each offset should
298 * be added to the REMOTE BASE ADDR else it should be added to the LOCAL BASE ADDR.
299 * This includes offsets for BOARDS, COMPONENTS and ERRORINFO.
300 *
301 * Note that these structures do not provide much info about connectivity.
302 * That info will be part of HWGRAPH, which is an extension of the cfg_t
303 * data structure. (ref IP27prom/cfg.h) It has to be extended to include
304 * the IO part of the Network(TBD).
305 *
306 * The data structures below define the above concepts.
307 */
308
309/*
310 * Values for CPU types
311 */
312#define KL_CPU_R4000 0x1 /* Standard R4000 */
313#define KL_CPU_TFP 0x2 /* TFP processor */
314#define KL_CPU_R10000 0x3 /* R10000 (T5) */
315#define KL_CPU_NONE (-1) /* no cpu present in slot */
316
317/*
318 * IP27 BOARD classes
319 */
320
321#define KLCLASS_MASK 0xf0
322#define KLCLASS_NONE 0x00
323#define KLCLASS_NODE 0x10 /* CPU, Memory and HUB board */
324#define KLCLASS_CPU KLCLASS_NODE
325#define KLCLASS_IO 0x20 /* BaseIO, 4 ch SCSI, ethernet, FDDI
326 and the non-graphics widget boards */
327#define KLCLASS_ROUTER 0x30 /* Router board */
328#define KLCLASS_MIDPLANE 0x40 /* We need to treat this as a board
329 so that we can record error info */
330#define KLCLASS_GFX 0x50 /* graphics boards */
331
332#define KLCLASS_PSEUDO_GFX 0x60 /* HDTV type cards that use a gfx
333 * hw ifc to xtalk and are not gfx
334 * class for sw purposes */
335
336#define KLCLASS_MAX 7 /* Bump this if a new CLASS is added */
337#define KLTYPE_MAX 10 /* Bump this if a new CLASS is added */
338
339#define KLCLASS_UNKNOWN 0xf0
340
341#define KLCLASS(_x) ((_x) & KLCLASS_MASK)
342
343/*
344 * IP27 board types
345 */
346
347#define KLTYPE_MASK 0x0f
348#define KLTYPE_NONE 0x00
349#define KLTYPE_EMPTY 0x00
350
351#define KLTYPE_WEIRDCPU (KLCLASS_CPU | 0x0)
352#define KLTYPE_IP27 (KLCLASS_CPU | 0x1) /* 2 CPUs(R10K) per board */
353
354#define KLTYPE_WEIRDIO (KLCLASS_IO | 0x0)
355#define KLTYPE_BASEIO (KLCLASS_IO | 0x1) /* IOC3, SuperIO, Bridge, SCSI */
356#define KLTYPE_IO6 KLTYPE_BASEIO /* Additional name */
357#define KLTYPE_4CHSCSI (KLCLASS_IO | 0x2)
358#define KLTYPE_MSCSI KLTYPE_4CHSCSI /* Additional name */
359#define KLTYPE_ETHERNET (KLCLASS_IO | 0x3)
360#define KLTYPE_MENET KLTYPE_ETHERNET /* Additional name */
361#define KLTYPE_FDDI (KLCLASS_IO | 0x4)
362#define KLTYPE_UNUSED (KLCLASS_IO | 0x5) /* XXX UNUSED */
363#define KLTYPE_HAROLD (KLCLASS_IO | 0x6) /* PCI SHOE BOX */
364#define KLTYPE_PCI KLTYPE_HAROLD
365#define KLTYPE_VME (KLCLASS_IO | 0x7) /* Any 3rd party VME card */
366#define KLTYPE_MIO (KLCLASS_IO | 0x8)
367#define KLTYPE_FC (KLCLASS_IO | 0x9)
368#define KLTYPE_LINC (KLCLASS_IO | 0xA)
369#define KLTYPE_TPU (KLCLASS_IO | 0xB) /* Tensor Processing Unit */
370#define KLTYPE_GSN_A (KLCLASS_IO | 0xC) /* Main GSN board */
371#define KLTYPE_GSN_B (KLCLASS_IO | 0xD) /* Auxiliary GSN board */
372
373#define KLTYPE_GFX (KLCLASS_GFX | 0x0) /* unknown graphics type */
374#define KLTYPE_GFX_KONA (KLCLASS_GFX | 0x1) /* KONA graphics on IP27 */
375#define KLTYPE_GFX_MGRA (KLCLASS_GFX | 0x3) /* MGRAS graphics on IP27 */
376
377#define KLTYPE_WEIRDROUTER (KLCLASS_ROUTER | 0x0)
378#define KLTYPE_ROUTER (KLCLASS_ROUTER | 0x1)
379#define KLTYPE_ROUTER2 KLTYPE_ROUTER /* Obsolete! */
380#define KLTYPE_NULL_ROUTER (KLCLASS_ROUTER | 0x2)
381#define KLTYPE_META_ROUTER (KLCLASS_ROUTER | 0x3)
382
383#define KLTYPE_WEIRDMIDPLANE (KLCLASS_MIDPLANE | 0x0)
384#define KLTYPE_MIDPLANE8 (KLCLASS_MIDPLANE | 0x1) /* 8 slot backplane */
385#define KLTYPE_MIDPLANE KLTYPE_MIDPLANE8
386#define KLTYPE_PBRICK_XBOW (KLCLASS_MIDPLANE | 0x2)
387
388#define KLTYPE_IOBRICK (KLCLASS_IOBRICK | 0x0)
389#define KLTYPE_IBRICK (KLCLASS_IOBRICK | 0x1)
390#define KLTYPE_PBRICK (KLCLASS_IOBRICK | 0x2)
391#define KLTYPE_XBRICK (KLCLASS_IOBRICK | 0x3)
392
393#define KLTYPE_PBRICK_BRIDGE KLTYPE_PBRICK
394
395/* The value of type should be more than 8 so that hinv prints
396 * out the board name from the NIC string. For values less than
397 * 8 the name of the board needs to be hard coded in a few places.
398 * When bringup started nic names had not standardized and so we
399 * had to hard code. (For people interested in history.)
400 */
401#define KLTYPE_XTHD (KLCLASS_PSEUDO_GFX | 0x9)
402
403#define KLTYPE_UNKNOWN (KLCLASS_UNKNOWN | 0xf)
404
405#define KLTYPE(_x) ((_x) & KLTYPE_MASK)
406#define IS_MIO_PRESENT(l) ((l->brd_type == KLTYPE_BASEIO) && \
407 (l->brd_flags & SECOND_NIC_PRESENT))
408#define IS_MIO_IOC3(l, n) (IS_MIO_PRESENT(l) && (n > 2))
409
410/*
411 * board structures
412 */
413
414#define MAX_COMPTS_PER_BRD 24
415
416#define LOCAL_BOARD 1
417#define REMOTE_BOARD 2
418
419#define LBOARD_STRUCT_VERSION 2
420
421typedef struct lboard_s {
422 klconf_off_t brd_next; /* Next BOARD */
423 unsigned char struct_type; /* type of structure, local or remote */
424 unsigned char brd_type; /* type+class */
425 unsigned char brd_sversion; /* version of this structure */
426 unsigned char brd_brevision; /* board revision */
427 unsigned char brd_promver; /* board prom version, if any */
428 unsigned char brd_flags; /* Enabled, Disabled etc */
429 unsigned char brd_slot; /* slot number */
430 unsigned short brd_debugsw; /* Debug switches */
431 moduleid_t brd_module; /* module to which it belongs */
432 partid_t brd_partition; /* Partition number */
433 unsigned short brd_diagval; /* diagnostic value */
434 unsigned short brd_diagparm; /* diagnostic parameter */
435 unsigned char brd_inventory; /* inventory history */
436 unsigned char brd_numcompts; /* Number of components */
437 nic_t brd_nic; /* Number in CAN */
438 nasid_t brd_nasid; /* passed parameter */
439 klconf_off_t brd_compts[MAX_COMPTS_PER_BRD]; /* pointers to COMPONENTS */
440 klconf_off_t brd_errinfo; /* Board's error information */
441 struct lboard_s *brd_parent; /* Logical parent for this brd */
442 vertex_hdl_t brd_graph_link; /* vertex hdl to connect extern compts */
443 confidence_t brd_confidence; /* confidence that the board is bad */
444 nasid_t brd_owner; /* who owns this board */
445 unsigned char brd_nic_flags; /* To handle 8 more NICs */
446 char brd_name[32];
447} lboard_t;
448
449
450/*
451 * Make sure we pass back the calias space address for local boards.
452 * klconfig board traversal and error structure extraction defines.
453 */
454
455#define BOARD_SLOT(_brd) ((_brd)->brd_slot)
456
457#define KLCF_CLASS(_brd) KLCLASS((_brd)->brd_type)
458#define KLCF_TYPE(_brd) KLTYPE((_brd)->brd_type)
459#define KLCF_REMOTE(_brd) (((_brd)->struct_type & LOCAL_BOARD) ? 0 : 1)
460#define KLCF_NUM_COMPS(_brd) ((_brd)->brd_numcompts)
461#define KLCF_MODULE_ID(_brd) ((_brd)->brd_module)
462
463#define KLCF_NEXT(_brd) \
464 ((_brd)->brd_next ? \
465 (lboard_t *)(NODE_OFFSET_TO_K1(NASID_GET(_brd), (_brd)->brd_next)):\
466 NULL)
467#define KLCF_COMP(_brd, _ndx) \
468 (klinfo_t *)(NODE_OFFSET_TO_K1(NASID_GET(_brd), \
469 (_brd)->brd_compts[(_ndx)]))
470
471#define KLCF_COMP_ERROR(_brd, _comp) \
472 (NODE_OFFSET_TO_K1(NASID_GET(_brd), (_comp)->errinfo))
473
474#define KLCF_COMP_TYPE(_comp) ((_comp)->struct_type)
475#define KLCF_BRIDGE_W_ID(_comp) ((_comp)->physid) /* Widget ID */
476
477
478
479/*
480 * Generic info structure. This stores common info about a
481 * component.
482 */
483
484typedef struct klinfo_s { /* Generic info */
485 unsigned char struct_type; /* type of this structure */
486 unsigned char struct_version; /* version of this structure */
487 unsigned char flags; /* Enabled, disabled etc */
488 unsigned char revision; /* component revision */
489 unsigned short diagval; /* result of diagnostics */
490 unsigned short diagparm; /* diagnostic parameter */
491 unsigned char inventory; /* previous inventory status */
492 nic_t nic; /* MUst be aligned properly */
493 unsigned char physid; /* physical id of component */
494 unsigned int virtid; /* virtual id as seen by system */
495 unsigned char widid; /* Widget id - if applicable */
496 nasid_t nasid; /* node number - from parent */
497 char pad1; /* pad out structure. */
498 char pad2; /* pad out structure. */
499 COMPONENT *arcs_compt; /* ptr to the arcs struct for ease*/
500 klconf_off_t errinfo; /* component specific errors */
501 unsigned short pad3; /* pci fields have moved over to */
502 unsigned short pad4; /* klbri_t */
503} klinfo_t ;
504
505#define KLCONFIG_INFO_ENABLED(_i) ((_i)->flags & KLINFO_ENABLE)
506/*
507 * Component structures.
508 * Following are the currently identified components:
509 * CPU, HUB, MEM_BANK,
510 * XBOW(consists of 16 WIDGETs, each of which can be HUB or GRAPHICS or BRIDGE)
511 * BRIDGE, IOC3, SuperIO, SCSI, FDDI
512 * ROUTER
513 * GRAPHICS
514 */
515#define KLSTRUCT_UNKNOWN 0
516#define KLSTRUCT_CPU 1
517#define KLSTRUCT_HUB 2
518#define KLSTRUCT_MEMBNK 3
519#define KLSTRUCT_XBOW 4
520#define KLSTRUCT_BRI 5
521#define KLSTRUCT_IOC3 6
522#define KLSTRUCT_PCI 7
523#define KLSTRUCT_VME 8
524#define KLSTRUCT_ROU 9
525#define KLSTRUCT_GFX 10
526#define KLSTRUCT_SCSI 11
527#define KLSTRUCT_FDDI 12
528#define KLSTRUCT_MIO 13
529#define KLSTRUCT_DISK 14
530#define KLSTRUCT_TAPE 15
531#define KLSTRUCT_CDROM 16
532#define KLSTRUCT_HUB_UART 17
533#define KLSTRUCT_IOC3ENET 18
534#define KLSTRUCT_IOC3UART 19
535#define KLSTRUCT_UNUSED 20 /* XXX UNUSED */
536#define KLSTRUCT_IOC3PCKM 21
537#define KLSTRUCT_RAD 22
538#define KLSTRUCT_HUB_TTY 23
539#define KLSTRUCT_IOC3_TTY 24
540
541/* Early Access IO proms are compatible
542 only with KLSTRUCT values upto 24. */
543
544#define KLSTRUCT_FIBERCHANNEL 25
545#define KLSTRUCT_MOD_SERIAL_NUM 26
546#define KLSTRUCT_IOC3MS 27
547#define KLSTRUCT_TPU 28
548#define KLSTRUCT_GSN_A 29
549#define KLSTRUCT_GSN_B 30
550#define KLSTRUCT_XTHD 31
551
552/*
553 * These are the indices of various components within a lboard structure.
554 */
555
556#define IP27_CPU0_INDEX 0
557#define IP27_CPU1_INDEX 1
558#define IP27_HUB_INDEX 2
559#define IP27_MEM_INDEX 3
560
561#define BASEIO_BRIDGE_INDEX 0
562#define BASEIO_IOC3_INDEX 1
563#define BASEIO_SCSI1_INDEX 2
564#define BASEIO_SCSI2_INDEX 3
565
566#define MIDPLANE_XBOW_INDEX 0
567#define ROUTER_COMPONENT_INDEX 0
568
569#define CH4SCSI_BRIDGE_INDEX 0
570
571/* Info holders for various hardware components */
572
573typedef u64 *pci_t;
574typedef u64 *vmeb_t;
575typedef u64 *vmed_t;
576typedef u64 *fddi_t;
577typedef u64 *scsi_t;
578typedef u64 *mio_t;
579typedef u64 *graphics_t;
580typedef u64 *router_t;
581
582/*
583 * The port info in ip27_cfg area translates to a lboart_t in the
584 * KLCONFIG area. But since KLCONFIG does not use pointers, lboart_t
585 * is stored in terms of a nasid and a offset from start of KLCONFIG
586 * area on that nasid.
587 */
588typedef struct klport_s {
589 nasid_t port_nasid;
590 unsigned char port_flag;
591 klconf_off_t port_offset;
592} klport_t;
593
594typedef struct klcpu_s { /* CPU */
595 klinfo_t cpu_info;
596 unsigned short cpu_prid; /* Processor PRID value */
597 unsigned short cpu_fpirr; /* FPU IRR value */
598 unsigned short cpu_speed; /* Speed in MHZ */
599 unsigned short cpu_scachesz; /* secondary cache size in MB */
600 unsigned short cpu_scachespeed;/* secondary cache speed in MHz */
601} klcpu_t ;
602
603#define CPU_STRUCT_VERSION 2
604
605typedef struct klhub_s { /* HUB */
606 klinfo_t hub_info;
607 unsigned int hub_flags; /* PCFG_HUB_xxx flags */
608 klport_t hub_port; /* hub is connected to this */
609 nic_t hub_box_nic; /* nic of containing box */
610 klconf_off_t hub_mfg_nic; /* MFG NIC string */
611 u64 hub_speed; /* Speed of hub in HZ */
612} klhub_t ;
613
614typedef struct klhub_uart_s { /* HUB */
615 klinfo_t hubuart_info;
616 unsigned int hubuart_flags; /* PCFG_HUB_xxx flags */
617 nic_t hubuart_box_nic; /* nic of containing box */
618} klhub_uart_t ;
619
620#define MEMORY_STRUCT_VERSION 2
621
622typedef struct klmembnk_s { /* MEMORY BANK */
623 klinfo_t membnk_info;
624 short membnk_memsz; /* Total memory in megabytes */
625 short membnk_dimm_select; /* bank to physical addr mapping*/
626 short membnk_bnksz[MD_MEM_BANKS]; /* Memory bank sizes */
627 short membnk_attr;
628} klmembnk_t ;
629
630#define KLCONFIG_MEMBNK_SIZE(_info, _bank) \
631 ((_info)->membnk_bnksz[(_bank)])
632
633
634#define MEMBNK_PREMIUM 1
635#define KLCONFIG_MEMBNK_PREMIUM(_info, _bank) \
636 ((_info)->membnk_attr & (MEMBNK_PREMIUM << (_bank)))
637
638#define MAX_SERIAL_NUM_SIZE 10
639
640typedef struct klmod_serial_num_s {
641 klinfo_t snum_info;
642 union {
643 char snum_str[MAX_SERIAL_NUM_SIZE];
644 unsigned long long snum_int;
645 } snum;
646} klmod_serial_num_t;
647
648/* Macros needed to access serial number structure in lboard_t.
649 Hard coded values are necessary since we cannot treat
650 serial number struct as a component without losing compatibility
651 between prom versions. */
652
653#define GET_SNUM_COMP(_l) ((klmod_serial_num_t *)\
654 KLCF_COMP(_l, _l->brd_numcompts))
655
656#define MAX_XBOW_LINKS 16
657
658typedef struct klxbow_s { /* XBOW */
659 klinfo_t xbow_info ;
660 klport_t xbow_port_info[MAX_XBOW_LINKS] ; /* Module number */
661 int xbow_master_hub_link;
662 /* type of brd connected+component struct ptr+flags */
663} klxbow_t ;
664
665#define MAX_PCI_SLOTS 8
666
667typedef struct klpci_device_s {
668 s32 pci_device_id; /* 32 bits of vendor/device ID. */
669 s32 pci_device_pad; /* 32 bits of padding. */
670} klpci_device_t;
671
672#define BRIDGE_STRUCT_VERSION 2
673
674typedef struct klbri_s { /* BRIDGE */
675 klinfo_t bri_info ;
676 unsigned char bri_eprominfo ; /* IO6prom connected to bridge */
677 unsigned char bri_bustype ; /* PCI/VME BUS bridge/GIO */
678 pci_t pci_specific ; /* PCI Board config info */
679 klpci_device_t bri_devices[MAX_PCI_DEVS] ; /* PCI IDs */
680 klconf_off_t bri_mfg_nic ;
681} klbri_t ;
682
683#define MAX_IOC3_TTY 2
684
685typedef struct klioc3_s { /* IOC3 */
686 klinfo_t ioc3_info ;
687 unsigned char ioc3_ssram ; /* Info about ssram */
688 unsigned char ioc3_nvram ; /* Info about nvram */
689 klinfo_t ioc3_superio ; /* Info about superio */
690 klconf_off_t ioc3_tty_off ;
691 klinfo_t ioc3_enet ;
692 klconf_off_t ioc3_enet_off ;
693 klconf_off_t ioc3_kbd_off ;
694} klioc3_t ;
695
696#define MAX_VME_SLOTS 8
697
698typedef struct klvmeb_s { /* VME BRIDGE - PCI CTLR */
699 klinfo_t vmeb_info ;
700 vmeb_t vmeb_specific ;
701 klconf_off_t vmeb_brdinfo[MAX_VME_SLOTS] ; /* VME Board config info */
702} klvmeb_t ;
703
704typedef struct klvmed_s { /* VME DEVICE - VME BOARD */
705 klinfo_t vmed_info ;
706 vmed_t vmed_specific ;
707 klconf_off_t vmed_brdinfo[MAX_VME_SLOTS] ; /* VME Board config info */
708} klvmed_t ;
709
710#define ROUTER_VECTOR_VERS 2
711
712/* XXX - Don't we need the number of ports here?!? */
713typedef struct klrou_s { /* ROUTER */
714 klinfo_t rou_info ;
715 unsigned int rou_flags ; /* PCFG_ROUTER_xxx flags */
716 nic_t rou_box_nic ; /* nic of the containing module */
717 klport_t rou_port[MAX_ROUTER_PORTS + 1] ; /* array index 1 to 6 */
718 klconf_off_t rou_mfg_nic ; /* MFG NIC string */
719 u64 rou_vector; /* vector from master node */
720} klrou_t ;
721
722/*
723 * Graphics Controller/Device
724 *
725 * (IP27/IO6) Prom versions 6.13 (and 6.5.1 kernels) and earlier
726 * used a couple different structures to store graphics information.
727 * For compatibility reasons, the newer data structure preserves some
728 * of the layout so that fields that are used in the old versions remain
729 * in the same place (with the same info). Determination of what version
730 * of this structure we have is done by checking the cookie field.
731 */
732#define KLGFX_COOKIE 0x0c0de000
733
734typedef struct klgfx_s { /* GRAPHICS Device */
735 klinfo_t gfx_info;
736 klconf_off_t old_gndevs; /* for compatibility with older proms */
737 klconf_off_t old_gdoff0; /* for compatibility with older proms */
738 unsigned int cookie; /* for compatibility with older proms */
739 unsigned int moduleslot;
740 struct klgfx_s *gfx_next_pipe;
741 graphics_t gfx_specific;
742 klconf_off_t pad0; /* for compatibility with older proms */
743 klconf_off_t gfx_mfg_nic;
744} klgfx_t;
745
746typedef struct klxthd_s {
747 klinfo_t xthd_info ;
748 klconf_off_t xthd_mfg_nic ; /* MFG NIC string */
749} klxthd_t ;
750
751typedef struct kltpu_s { /* TPU board */
752 klinfo_t tpu_info ;
753 klconf_off_t tpu_mfg_nic ; /* MFG NIC string */
754} kltpu_t ;
755
756typedef struct klgsn_s { /* GSN board */
757 klinfo_t gsn_info ;
758 klconf_off_t gsn_mfg_nic ; /* MFG NIC string */
759} klgsn_t ;
760
761#define MAX_SCSI_DEVS 16
762
763/*
764 * NOTE: THis is the max sized kl* structure and is used in klmalloc.c
765 * to allocate space of type COMPONENT. Make sure that if the size of
766 * any other component struct becomes more than this, then redefine
767 * that as the size to be klmalloced.
768 */
769
770typedef struct klscsi_s { /* SCSI Controller */
771 klinfo_t scsi_info ;
772 scsi_t scsi_specific ;
773 unsigned char scsi_numdevs ;
774 klconf_off_t scsi_devinfo[MAX_SCSI_DEVS] ;
775} klscsi_t ;
776
777typedef struct klscdev_s { /* SCSI device */
778 klinfo_t scdev_info ;
779 struct scsidisk_data *scdev_cfg ; /* driver fills up this */
780} klscdev_t ;
781
782typedef struct klttydev_s { /* TTY device */
783 klinfo_t ttydev_info ;
784 struct terminal_data *ttydev_cfg ; /* driver fills up this */
785} klttydev_t ;
786
787typedef struct klenetdev_s { /* ENET device */
788 klinfo_t enetdev_info ;
789 struct net_data *enetdev_cfg ; /* driver fills up this */
790} klenetdev_t ;
791
792typedef struct klkbddev_s { /* KBD device */
793 klinfo_t kbddev_info ;
794 struct keyboard_data *kbddev_cfg ; /* driver fills up this */
795} klkbddev_t ;
796
797typedef struct klmsdev_s { /* mouse device */
798 klinfo_t msdev_info ;
799 void *msdev_cfg ;
800} klmsdev_t ;
801
802#define MAX_FDDI_DEVS 10 /* XXX Is this true */
803
804typedef struct klfddi_s { /* FDDI */
805 klinfo_t fddi_info ;
806 fddi_t fddi_specific ;
807 klconf_off_t fddi_devinfo[MAX_FDDI_DEVS] ;
808} klfddi_t ;
809
810typedef struct klmio_s { /* MIO */
811 klinfo_t mio_info ;
812 mio_t mio_specific ;
813} klmio_t ;
814
815
816typedef union klcomp_s {
817 klcpu_t kc_cpu;
818 klhub_t kc_hub;
819 klmembnk_t kc_mem;
820 klxbow_t kc_xbow;
821 klbri_t kc_bri;
822 klioc3_t kc_ioc3;
823 klvmeb_t kc_vmeb;
824 klvmed_t kc_vmed;
825 klrou_t kc_rou;
826 klgfx_t kc_gfx;
827 klscsi_t kc_scsi;
828 klscdev_t kc_scsi_dev;
829 klfddi_t kc_fddi;
830 klmio_t kc_mio;
831 klmod_serial_num_t kc_snum ;
832} klcomp_t;
833
834typedef union kldev_s { /* for device structure allocation */
835 klscdev_t kc_scsi_dev ;
836 klttydev_t kc_tty_dev ;
837 klenetdev_t kc_enet_dev ;
838 klkbddev_t kc_kbd_dev ;
839} kldev_t ;
840
841/* Data structure interface routines. TBD */
842
843/* Include launch info in this file itself? TBD */
844
845/*
846 * TBD - Can the ARCS and device driver related info also be included in the
847 * KLCONFIG area. On the IO4PROM, prom device driver info is part of cfgnode_t
848 * structure, viz private to the IO4prom.
849 */
850
851/*
852 * TBD - Allocation issues.
853 *
854 * Do we need to Mark off sepatate heaps for lboard_t, rboard_t, component,
855 * errinfo and allocate from them, or have a single heap and allocate all
856 * structures from it. Debug is easier in the former method since we can
857 * dump all similar structs in one command, but there will be lots of holes,
858 * in memory and max limits are needed for number of structures.
859 * Another way to make it organized, is to have a union of all components
860 * and allocate a aligned chunk of memory greater than the biggest
861 * component.
862 */
863
864typedef union {
865 lboard_t *lbinfo ;
866} biptr_t ;
867
868
869#define BRI_PER_XBOW 6
870#define PCI_PER_BRI 8
871#define DEV_PER_PCI 16
872
873
874/* Virtual dipswitch values (starting from switch "7"): */
875
876#define VDS_NOGFX 0x8000 /* Don't enable gfx and autoboot */
877#define VDS_NOMP 0x100 /* Don't start slave processors */
878#define VDS_MANUMODE 0x80 /* Manufacturing mode */
879#define VDS_NOARB 0x40 /* No bootmaster arbitration */
880#define VDS_PODMODE 0x20 /* Go straight to POD mode */
881#define VDS_NO_DIAGS 0x10 /* Don't run any diags after BM arb */
882#define VDS_DEFAULTS 0x08 /* Use default environment values */
883#define VDS_NOMEMCLEAR 0x04 /* Don't run mem cfg code */
884#define VDS_2ND_IO4 0x02 /* Boot from the second IO4 */
885#define VDS_DEBUG_PROM 0x01 /* Print PROM debugging messages */
886
887/* external declarations of Linux kernel functions. */
888
889extern lboard_t *find_lboard(lboard_t *start, unsigned char type);
890extern klinfo_t *find_component(lboard_t *brd, klinfo_t *kli, unsigned char type);
891extern klinfo_t *find_first_component(lboard_t *brd, unsigned char type);
892extern klcpu_t *nasid_slice_to_cpuinfo(nasid_t, int);
893extern lboard_t *find_lboard_class(lboard_t *start, unsigned char brd_class);
894
895
896extern klcpu_t *sn_get_cpuinfo(cpuid_t cpu);
897
898#endif /* _ASM_SN_KLCONFIG_H */
diff --git a/arch/mips/include/asm/sn/kldir.h b/arch/mips/include/asm/sn/kldir.h
new file mode 100644
index 000000000000..1327e12e9645
--- /dev/null
+++ b/arch/mips/include/asm/sn/kldir.h
@@ -0,0 +1,217 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Derived from IRIX <sys/SN/kldir.h>, revision 1.21.
7 *
8 * Copyright (C) 1992 - 1997, 1999, 2000 Silicon Graphics, Inc.
9 * Copyright (C) 1999, 2000 by Ralf Baechle
10 */
11#ifndef _ASM_SN_KLDIR_H
12#define _ASM_SN_KLDIR_H
13
14
15/*
16 * The kldir memory area resides at a fixed place in each node's memory and
17 * provides pointers to most other IP27 memory areas. This allows us to
18 * resize and/or relocate memory areas at a later time without breaking all
19 * firmware and kernels that use them. Indices in the array are
20 * permanently dedicated to areas listed below. Some memory areas (marked
21 * below) reside at a permanently fixed location, but are included in the
22 * directory for completeness.
23 */
24
25#define KLDIR_MAGIC 0x434d5f53505f5357
26
27/*
28 * The upper portion of the memory map applies during boot
29 * only and is overwritten by IRIX/SYMMON.
30 *
31 * MEMORY MAP PER NODE
32 *
33 * 0x2000000 (32M) +-----------------------------------------+
34 * | IO6 BUFFERS FOR FLASH ENET IOC3 |
35 * 0x1F80000 (31.5M) +-----------------------------------------+
36 * | IO6 TEXT/DATA/BSS/stack |
37 * 0x1C00000 (30M) +-----------------------------------------+
38 * | IO6 PROM DEBUG TEXT/DATA/BSS/stack |
39 * 0x0800000 (28M) +-----------------------------------------+
40 * | IP27 PROM TEXT/DATA/BSS/stack |
41 * 0x1B00000 (27M) +-----------------------------------------+
42 * | IP27 CFG |
43 * 0x1A00000 (26M) +-----------------------------------------+
44 * | Graphics PROM |
45 * 0x1800000 (24M) +-----------------------------------------+
46 * | 3rd Party PROM drivers |
47 * 0x1600000 (22M) +-----------------------------------------+
48 * | |
49 * | Free |
50 * | |
51 * +-----------------------------------------+
52 * | UNIX DEBUG Version |
53 * 0x190000 (2M--) +-----------------------------------------+
54 * | SYMMON |
55 * | (For UNIX Debug only) |
56 * 0x34000 (208K) +-----------------------------------------+
57 * | SYMMON STACK [NUM_CPU_PER_NODE] |
58 * | (For UNIX Debug only) |
59 * 0x25000 (148K) +-----------------------------------------+
60 * | KLCONFIG - II (temp) |
61 * | |
62 * | ---------------------------- |
63 * | |
64 * | UNIX NON-DEBUG Version |
65 * 0x19000 (100K) +-----------------------------------------+
66 *
67 *
68 * The lower portion of the memory map contains information that is
69 * permanent and is used by the IP27PROM, IO6PROM and IRIX.
70 *
71 * 0x19000 (100K) +-----------------------------------------+
72 * | |
73 * | PI Error Spools (32K) |
74 * | |
75 * 0x12000 (72K) +-----------------------------------------+
76 * | Unused |
77 * 0x11c00 (71K) +-----------------------------------------+
78 * | CPU 1 NMI Eframe area |
79 * 0x11a00 (70.5K) +-----------------------------------------+
80 * | CPU 0 NMI Eframe area |
81 * 0x11800 (70K) +-----------------------------------------+
82 * | CPU 1 NMI Register save area |
83 * 0x11600 (69.5K) +-----------------------------------------+
84 * | CPU 0 NMI Register save area |
85 * 0x11400 (69K) +-----------------------------------------+
86 * | GDA (1k) |
87 * 0x11000 (68K) +-----------------------------------------+
88 * | Early cache Exception stack |
89 * | and/or |
90 * | kernel/io6prom nmi registers |
91 * 0x10800 (66k) +-----------------------------------------+
92 * | cache error eframe |
93 * 0x10400 (65K) +-----------------------------------------+
94 * | Exception Handlers (UALIAS copy) |
95 * 0x10000 (64K) +-----------------------------------------+
96 * | |
97 * | |
98 * | KLCONFIG - I (permanent) (48K) |
99 * | |
100 * | |
101 * | |
102 * 0x4000 (16K) +-----------------------------------------+
103 * | NMI Handler (Protected Page) |
104 * 0x3000 (12K) +-----------------------------------------+
105 * | ARCS PVECTORS (master node only) |
106 * 0x2c00 (11K) +-----------------------------------------+
107 * | ARCS TVECTORS (master node only) |
108 * 0x2800 (10K) +-----------------------------------------+
109 * | LAUNCH [NUM_CPU] |
110 * 0x2400 (9K) +-----------------------------------------+
111 * | Low memory directory (KLDIR) |
112 * 0x2000 (8K) +-----------------------------------------+
113 * | ARCS SPB (1K) |
114 * 0x1000 (4K) +-----------------------------------------+
115 * | Early cache Exception stack |
116 * | and/or |
117 * | kernel/io6prom nmi registers |
118 * 0x800 (2k) +-----------------------------------------+
119 * | cache error eframe |
120 * 0x400 (1K) +-----------------------------------------+
121 * | Exception Handlers |
122 * 0x0 (0K) +-----------------------------------------+
123 */
124
125#ifdef __ASSEMBLY__
126#define KLDIR_OFF_MAGIC 0x00
127#define KLDIR_OFF_OFFSET 0x08
128#define KLDIR_OFF_POINTER 0x10
129#define KLDIR_OFF_SIZE 0x18
130#define KLDIR_OFF_COUNT 0x20
131#define KLDIR_OFF_STRIDE 0x28
132#endif /* __ASSEMBLY__ */
133
134/*
135 * This is defined here because IP27_SYMMON_STK_SIZE must be at least what
136 * we define here. Since it's set up in the prom. We can't redefine it later
137 * and expect more space to be allocated. The way to find out the true size
138 * of the symmon stacks is to divide SYMMON_STK_SIZE by SYMMON_STK_STRIDE
139 * for a particular node.
140 */
141#define SYMMON_STACK_SIZE 0x8000
142
143#if defined(PROM)
144
145/*
146 * These defines are prom version dependent. No code other than the IP27
147 * prom should attempt to use these values.
148 */
149#define IP27_LAUNCH_OFFSET 0x2400
150#define IP27_LAUNCH_SIZE 0x400
151#define IP27_LAUNCH_COUNT 2
152#define IP27_LAUNCH_STRIDE 0x200
153
154#define IP27_KLCONFIG_OFFSET 0x4000
155#define IP27_KLCONFIG_SIZE 0xc000
156#define IP27_KLCONFIG_COUNT 1
157#define IP27_KLCONFIG_STRIDE 0
158
159#define IP27_NMI_OFFSET 0x3000
160#define IP27_NMI_SIZE 0x40
161#define IP27_NMI_COUNT 2
162#define IP27_NMI_STRIDE 0x40
163
164#define IP27_PI_ERROR_OFFSET 0x12000
165#define IP27_PI_ERROR_SIZE 0x4000
166#define IP27_PI_ERROR_COUNT 1
167#define IP27_PI_ERROR_STRIDE 0
168
169#define IP27_SYMMON_STK_OFFSET 0x25000
170#define IP27_SYMMON_STK_SIZE 0xe000
171#define IP27_SYMMON_STK_COUNT 2
172/* IP27_SYMMON_STK_STRIDE must be >= SYMMON_STACK_SIZE */
173#define IP27_SYMMON_STK_STRIDE 0x7000
174
175#define IP27_FREEMEM_OFFSET 0x19000
176#define IP27_FREEMEM_SIZE -1
177#define IP27_FREEMEM_COUNT 1
178#define IP27_FREEMEM_STRIDE 0
179
180#endif /* PROM */
181/*
182 * There will be only one of these in a partition so the IO6 must set it up.
183 */
184#define IO6_GDA_OFFSET 0x11000
185#define IO6_GDA_SIZE 0x400
186#define IO6_GDA_COUNT 1
187#define IO6_GDA_STRIDE 0
188
189/*
190 * save area of kernel nmi regs in the prom format
191 */
192#define IP27_NMI_KREGS_OFFSET 0x11400
193#define IP27_NMI_KREGS_CPU_SIZE 0x200
194/*
195 * save area of kernel nmi regs in eframe format
196 */
197#define IP27_NMI_EFRAME_OFFSET 0x11800
198#define IP27_NMI_EFRAME_SIZE 0x200
199
200#define KLDIR_ENT_SIZE 0x40
201#define KLDIR_MAX_ENTRIES (0x400 / 0x40)
202
203#ifndef __ASSEMBLY__
204typedef struct kldir_ent_s {
205 u64 magic; /* Indicates validity of entry */
206 off_t offset; /* Offset from start of node space */
207 unsigned long pointer; /* Pointer to area in some cases */
208 size_t size; /* Size in bytes */
209 u64 count; /* Repeat count if array, 1 if not */
210 size_t stride; /* Stride if array, 0 if not */
211 char rsvd[16]; /* Pad entry to 0x40 bytes */
212 /* NOTE: These 16 bytes are used in the Partition KLDIR
213 entry to store partition info. Refer to klpart.h for this. */
214} kldir_ent_t;
215#endif /* !__ASSEMBLY__ */
216
217#endif /* _ASM_SN_KLDIR_H */
diff --git a/arch/mips/include/asm/sn/klkernvars.h b/arch/mips/include/asm/sn/klkernvars.h
new file mode 100644
index 000000000000..5de4c5e8ab30
--- /dev/null
+++ b/arch/mips/include/asm/sn/klkernvars.h
@@ -0,0 +1,29 @@
1/*
2 * File ported from IRIX to Linux by Kanoj Sarcar, 06/08/00.
3 * Copyright 2000 Silicon Graphics, Inc.
4 */
5#ifndef __ASM_SN_KLKERNVARS_H
6#define __ASM_SN_KLKERNVARS_H
7
8#define KV_MAGIC_OFFSET 0x0
9#define KV_RO_NASID_OFFSET 0x4
10#define KV_RW_NASID_OFFSET 0x6
11
12#define KV_MAGIC 0x5f4b565f
13
14#ifndef __ASSEMBLY__
15
16#include <asm/sn/types.h>
17
18typedef struct kern_vars_s {
19 int kv_magic;
20 nasid_t kv_ro_nasid;
21 nasid_t kv_rw_nasid;
22 unsigned long kv_ro_baseaddr;
23 unsigned long kv_rw_baseaddr;
24} kern_vars_t;
25
26#endif /* !__ASSEMBLY__ */
27
28#endif /* __ASM_SN_KLKERNVARS_H */
29
diff --git a/arch/mips/include/asm/sn/launch.h b/arch/mips/include/asm/sn/launch.h
new file mode 100644
index 000000000000..b7c2226312c6
--- /dev/null
+++ b/arch/mips/include/asm/sn/launch.h
@@ -0,0 +1,106 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
7 * Copyright (C) 2000 by Colin Ngam
8 */
9#ifndef _ASM_SN_LAUNCH_H
10#define _ASM_SN_LAUNCH_H
11
12#include <asm/sn/types.h>
13#include <asm/sn/addrs.h>
14
15/*
16 * The launch data structure resides at a fixed place in each node's memory
17 * and is used to communicate between the master processor and the slave
18 * processors.
19 *
20 * The master stores launch parameters in the launch structure
21 * corresponding to a target processor that is in a slave loop, then sends
22 * an interrupt to the slave processor. The slave calls the desired
23 * function, then returns to the slave loop. The master may poll or wait
24 * for the slaves to finish.
25 *
26 * There is an array of launch structures, one per CPU on the node. One
27 * interrupt level is used per local CPU.
28 */
29
30#define LAUNCH_MAGIC 0xaddbead2addbead3
31#ifdef CONFIG_SGI_IP27
32#define LAUNCH_SIZEOF 0x100
33#define LAUNCH_PADSZ 0xa0
34#endif
35
36#define LAUNCH_OFF_MAGIC 0x00 /* Struct offsets for assembly */
37#define LAUNCH_OFF_BUSY 0x08
38#define LAUNCH_OFF_CALL 0x10
39#define LAUNCH_OFF_CALLC 0x18
40#define LAUNCH_OFF_CALLPARM 0x20
41#define LAUNCH_OFF_STACK 0x28
42#define LAUNCH_OFF_GP 0x30
43#define LAUNCH_OFF_BEVUTLB 0x38
44#define LAUNCH_OFF_BEVNORMAL 0x40
45#define LAUNCH_OFF_BEVECC 0x48
46
47#define LAUNCH_STATE_DONE 0 /* Return value of LAUNCH_POLL */
48#define LAUNCH_STATE_SENT 1
49#define LAUNCH_STATE_RECD 2
50
51/*
52 * The launch routine is called only if the complement address is correct.
53 *
54 * Before control is transferred to a routine, the complement address
55 * is zeroed (invalidated) to prevent an accidental call from a spurious
56 * interrupt.
57 *
58 * The slave_launch routine turns on the BUSY flag, and the slave loop
59 * clears the BUSY flag after control is returned to it.
60 */
61
62#ifndef __ASSEMBLY__
63
64typedef int launch_state_t;
65typedef void (*launch_proc_t)(u64 call_parm);
66
67typedef struct launch_s {
68 volatile u64 magic; /* Magic number */
69 volatile u64 busy; /* Slave currently active */
70 volatile launch_proc_t call_addr; /* Func. for slave to call */
71 volatile u64 call_addr_c; /* 1's complement of call_addr*/
72 volatile u64 call_parm; /* Single parm passed to call*/
73 volatile void *stack_addr; /* Stack pointer for slave function */
74 volatile void *gp_addr; /* Global pointer for slave func. */
75 volatile char *bevutlb;/* Address of bev utlb ex handler */
76 volatile char *bevnormal;/*Address of bev normal ex handler */
77 volatile char *bevecc;/* Address of bev cache err handler */
78 volatile char pad[160]; /* Pad to LAUNCH_SIZEOF */
79} launch_t;
80
81/*
82 * PROM entry points for launch routines are determined by IPxxprom/start.s
83 */
84
85#define LAUNCH_SLAVE (*(void (*)(int nasid, int cpu, \
86 launch_proc_t call_addr, \
87 u64 call_parm, \
88 void *stack_addr, \
89 void *gp_addr)) \
90 IP27PROM_LAUNCHSLAVE)
91
92#define LAUNCH_WAIT (*(void (*)(int nasid, int cpu, int timeout_msec)) \
93 IP27PROM_WAITSLAVE)
94
95#define LAUNCH_POLL (*(launch_state_t (*)(int nasid, int cpu)) \
96 IP27PROM_POLLSLAVE)
97
98#define LAUNCH_LOOP (*(void (*)(void)) \
99 IP27PROM_SLAVELOOP)
100
101#define LAUNCH_FLASH (*(void (*)(void)) \
102 IP27PROM_FLASHLEDS)
103
104#endif /* !__ASSEMBLY__ */
105
106#endif /* _ASM_SN_LAUNCH_H */
diff --git a/arch/mips/include/asm/sn/mapped_kernel.h b/arch/mips/include/asm/sn/mapped_kernel.h
new file mode 100644
index 000000000000..721496a0bb92
--- /dev/null
+++ b/arch/mips/include/asm/sn/mapped_kernel.h
@@ -0,0 +1,54 @@
1/*
2 * File created by Kanoj Sarcar 06/06/00.
3 * Copyright 2000 Silicon Graphics, Inc.
4 */
5#ifndef __ASM_SN_MAPPED_KERNEL_H
6#define __ASM_SN_MAPPED_KERNEL_H
7
8#include <linux/mmzone.h>
9
10/*
11 * Note on how mapped kernels work: the text and data section is
12 * compiled at cksseg segment (LOADADDR = 0xc001c000), and the
13 * init/setup/data section gets a 16M virtual address bump in the
14 * ld.script file (so that tlblo0 and tlblo1 maps the sections).
15 * The vmlinux.64 section addresses are put in the xkseg range
16 * using the change-addresses makefile option. Use elfdump -of
17 * on IRIX to see where the sections go. The Origin loader loads
18 * the two sections contiguously in physical memory. The loader
19 * sets the entry point into kernel_entry using a xkphys address,
20 * but instead of using 0xa800000001160000, it uses the address
21 * 0xa800000000160000, which is where it physically loaded that
22 * code. So no jumps can be done before we have switched to using
23 * cksseg addresses.
24 */
25#include <asm/addrspace.h>
26
27#define REP_BASE CAC_BASE
28
29#ifdef CONFIG_MAPPED_KERNEL
30
31#define MAPPED_ADDR_RO_TO_PHYS(x) (x - REP_BASE)
32#define MAPPED_ADDR_RW_TO_PHYS(x) (x - REP_BASE - 16777216)
33
34#define MAPPED_KERN_RO_PHYSBASE(n) (hub_data(n)->kern_vars.kv_ro_baseaddr)
35#define MAPPED_KERN_RW_PHYSBASE(n) (hub_data(n)->kern_vars.kv_rw_baseaddr)
36
37#define MAPPED_KERN_RO_TO_PHYS(x) \
38 ((unsigned long)MAPPED_ADDR_RO_TO_PHYS(x) | \
39 MAPPED_KERN_RO_PHYSBASE(get_compact_nodeid()))
40#define MAPPED_KERN_RW_TO_PHYS(x) \
41 ((unsigned long)MAPPED_ADDR_RW_TO_PHYS(x) | \
42 MAPPED_KERN_RW_PHYSBASE(get_compact_nodeid()))
43
44#else /* CONFIG_MAPPED_KERNEL */
45
46#define MAPPED_KERN_RO_TO_PHYS(x) (x - REP_BASE)
47#define MAPPED_KERN_RW_TO_PHYS(x) (x - REP_BASE)
48
49#endif /* CONFIG_MAPPED_KERNEL */
50
51#define MAPPED_KERN_RO_TO_K0(x) PHYS_TO_K0(MAPPED_KERN_RO_TO_PHYS(x))
52#define MAPPED_KERN_RW_TO_K0(x) PHYS_TO_K0(MAPPED_KERN_RW_TO_PHYS(x))
53
54#endif /* __ASM_SN_MAPPED_KERNEL_H */
diff --git a/arch/mips/include/asm/sn/nmi.h b/arch/mips/include/asm/sn/nmi.h
new file mode 100644
index 000000000000..6b7b0b5f3729
--- /dev/null
+++ b/arch/mips/include/asm/sn/nmi.h
@@ -0,0 +1,125 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1992 - 1997 Silicon Graphics, Inc.
7 */
8#ifndef __ASM_SN_NMI_H
9#define __ASM_SN_NMI_H
10
11#ident "$Revision: 1.5 $"
12
13#include <asm/sn/addrs.h>
14
15/*
16 * The launch data structure resides at a fixed place in each node's memory
17 * and is used to communicate between the master processor and the slave
18 * processors.
19 *
20 * The master stores launch parameters in the launch structure
21 * corresponding to a target processor that is in a slave loop, then sends
22 * an interrupt to the slave processor. The slave calls the desired
23 * function, followed by an optional rendezvous function, then returns to
24 * the slave loop. The master does not wait for the slaves before
25 * returning.
26 *
27 * There is an array of launch structures, one per CPU on the node. One
28 * interrupt level is used per CPU.
29 */
30
31#define NMI_MAGIC 0x48414d4d455201
32#define NMI_SIZEOF 0x40
33
34#define NMI_OFF_MAGIC 0x00 /* Struct offsets for assembly */
35#define NMI_OFF_FLAGS 0x08
36#define NMI_OFF_CALL 0x10
37#define NMI_OFF_CALLC 0x18
38#define NMI_OFF_CALLPARM 0x20
39#define NMI_OFF_GMASTER 0x28
40
41/*
42 * The NMI routine is called only if the complement address is
43 * correct.
44 *
45 * Before control is transferred to a routine, the complement address
46 * is zeroed (invalidated) to prevent an accidental call from a spurious
47 * interrupt.
48 *
49 */
50
51#ifndef __ASSEMBLY__
52
53typedef struct nmi_s {
54 volatile unsigned long magic; /* Magic number */
55 volatile unsigned long flags; /* Combination of flags above */
56 volatile void *call_addr; /* Routine for slave to call */
57 volatile void *call_addr_c; /* 1's complement of address */
58 volatile void *call_parm; /* Single parm passed to call */
59 volatile unsigned long gmaster; /* Flag true only on global master*/
60} nmi_t;
61
62#endif /* !__ASSEMBLY__ */
63
64/* Following definitions are needed both in the prom & the kernel
65 * to identify the format of the nmi cpu register save area in the
66 * low memory on each node.
67 */
68#ifndef __ASSEMBLY__
69
70struct reg_struct {
71 unsigned long gpr[32];
72 unsigned long sr;
73 unsigned long cause;
74 unsigned long epc;
75 unsigned long badva;
76 unsigned long error_epc;
77 unsigned long cache_err;
78 unsigned long nmi_sr;
79};
80
81#endif /* !__ASSEMBLY__ */
82
83/* These are the assembly language offsets into the reg_struct structure */
84
85#define R0_OFF 0x0
86#define R1_OFF 0x8
87#define R2_OFF 0x10
88#define R3_OFF 0x18
89#define R4_OFF 0x20
90#define R5_OFF 0x28
91#define R6_OFF 0x30
92#define R7_OFF 0x38
93#define R8_OFF 0x40
94#define R9_OFF 0x48
95#define R10_OFF 0x50
96#define R11_OFF 0x58
97#define R12_OFF 0x60
98#define R13_OFF 0x68
99#define R14_OFF 0x70
100#define R15_OFF 0x78
101#define R16_OFF 0x80
102#define R17_OFF 0x88
103#define R18_OFF 0x90
104#define R19_OFF 0x98
105#define R20_OFF 0xa0
106#define R21_OFF 0xa8
107#define R22_OFF 0xb0
108#define R23_OFF 0xb8
109#define R24_OFF 0xc0
110#define R25_OFF 0xc8
111#define R26_OFF 0xd0
112#define R27_OFF 0xd8
113#define R28_OFF 0xe0
114#define R29_OFF 0xe8
115#define R30_OFF 0xf0
116#define R31_OFF 0xf8
117#define SR_OFF 0x100
118#define CAUSE_OFF 0x108
119#define EPC_OFF 0x110
120#define BADVA_OFF 0x118
121#define ERROR_EPC_OFF 0x120
122#define CACHE_ERR_OFF 0x128
123#define NMISR_OFF 0x130
124
125#endif /* __ASM_SN_NMI_H */
diff --git a/arch/mips/include/asm/sn/sn0/addrs.h b/arch/mips/include/asm/sn/sn0/addrs.h
new file mode 100644
index 000000000000..b06190093bbc
--- /dev/null
+++ b/arch/mips/include/asm/sn/sn0/addrs.h
@@ -0,0 +1,288 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Derived from IRIX <sys/SN/SN0/addrs.h>, revision 1.126.
7 *
8 * Copyright (C) 1992 - 1997, 1999 Silicon Graphics, Inc.
9 * Copyright (C) 1999 by Ralf Baechle
10 */
11#ifndef _ASM_SN_SN0_ADDRS_H
12#define _ASM_SN_SN0_ADDRS_H
13
14
15/*
16 * SN0 (on a T5) Address map
17 *
18 * This file contains a set of definitions and macros which are used
19 * to reference into the major address spaces (CAC, HSPEC, IO, MSPEC,
20 * and UNCAC) used by the SN0 architecture. It also contains addresses
21 * for "major" statically locatable PROM/Kernel data structures, such as
22 * the partition table, the configuration data structure, etc.
23 * We make an implicit assumption that the processor using this file
24 * follows the R10K's provisions for specifying uncached attributes;
25 * should this change, the base registers may very well become processor-
26 * dependent.
27 *
28 * For more information on the address spaces, see the "Local Resources"
29 * chapter of the Hub specification.
30 *
31 * NOTE: This header file is included both by C and by assembler source
32 * files. Please bracket any language-dependent definitions
33 * appropriately.
34 */
35
36/*
37 * Some of the macros here need to be casted to appropriate types when used
38 * from C. They definitely must not be casted from assembly language so we
39 * use some new ANSI preprocessor stuff to paste these on where needed.
40 */
41
42/*
43 * The following couple of definitions will eventually need to be variables,
44 * since the amount of address space assigned to each node depends on
45 * whether the system is running in N-mode (more nodes with less memory)
46 * or M-mode (fewer nodes with more memory). We expect that it will
47 * be a while before we need to make this decision dynamically, though,
48 * so for now we just use defines bracketed by an ifdef.
49 */
50
51#ifdef CONFIG_SGI_SN_N_MODE
52
53#define NODE_SIZE_BITS 31
54#define BWIN_SIZE_BITS 28
55
56#define NASID_BITS 9
57#define NASID_BITMASK (0x1ffLL)
58#define NASID_SHFT 31
59#define NASID_META_BITS 5
60#define NASID_LOCAL_BITS 4
61
62#define BDDIR_UPPER_MASK (UINT64_CAST 0x7ffff << 10)
63#define BDECC_UPPER_MASK (UINT64_CAST 0x3ffffff << 3)
64
65#else /* !defined(CONFIG_SGI_SN_N_MODE), assume that M-mode is desired */
66
67#define NODE_SIZE_BITS 32
68#define BWIN_SIZE_BITS 29
69
70#define NASID_BITMASK (0xffLL)
71#define NASID_BITS 8
72#define NASID_SHFT 32
73#define NASID_META_BITS 4
74#define NASID_LOCAL_BITS 4
75
76#define BDDIR_UPPER_MASK (UINT64_CAST 0xfffff << 10)
77#define BDECC_UPPER_MASK (UINT64_CAST 0x7ffffff << 3)
78
79#endif /* !defined(CONFIG_SGI_SN_N_MODE) */
80
81#define NODE_ADDRSPACE_SIZE (UINT64_CAST 1 << NODE_SIZE_BITS)
82
83#define NASID_MASK (UINT64_CAST NASID_BITMASK << NASID_SHFT)
84#define NASID_GET(_pa) (int) ((UINT64_CAST (_pa) >> \
85 NASID_SHFT) & NASID_BITMASK)
86
87#if !defined(__ASSEMBLY__)
88
89#define NODE_SWIN_BASE(nasid, widget) \
90 ((widget == 0) ? NODE_BWIN_BASE((nasid), SWIN0_BIGWIN) \
91 : RAW_NODE_SWIN_BASE(nasid, widget))
92#else /* __ASSEMBLY__ */
93#define NODE_SWIN_BASE(nasid, widget) \
94 (NODE_IO_BASE(nasid) + (UINT64_CAST(widget) << SWIN_SIZE_BITS))
95#endif /* __ASSEMBLY__ */
96
97/*
98 * The following definitions pertain to the IO special address
99 * space. They define the location of the big and little windows
100 * of any given node.
101 */
102
103#define BWIN_INDEX_BITS 3
104#define BWIN_SIZE (UINT64_CAST 1 << BWIN_SIZE_BITS)
105#define BWIN_SIZEMASK (BWIN_SIZE - 1)
106#define BWIN_WIDGET_MASK 0x7
107#define NODE_BWIN_BASE0(nasid) (NODE_IO_BASE(nasid) + BWIN_SIZE)
108#define NODE_BWIN_BASE(nasid, bigwin) (NODE_BWIN_BASE0(nasid) + \
109 (UINT64_CAST(bigwin) << BWIN_SIZE_BITS))
110
111#define BWIN_WIDGETADDR(addr) ((addr) & BWIN_SIZEMASK)
112#define BWIN_WINDOWNUM(addr) (((addr) >> BWIN_SIZE_BITS) & BWIN_WIDGET_MASK)
113/*
114 * Verify if addr belongs to large window address of node with "nasid"
115 *
116 *
117 * NOTE: "addr" is expected to be XKPHYS address, and NOT physical
118 * address
119 *
120 *
121 */
122
123#define NODE_BWIN_ADDR(nasid, addr) \
124 (((addr) >= NODE_BWIN_BASE0(nasid)) && \
125 ((addr) < (NODE_BWIN_BASE(nasid, HUB_NUM_BIG_WINDOW) + \
126 BWIN_SIZE)))
127
128/*
129 * The following define the major position-independent aliases used
130 * in SN0.
131 * CALIAS -- Varies in size, points to the first n bytes of memory
132 * on the reader's node.
133 */
134
135#define CALIAS_BASE CAC_BASE
136
137
138
139#define BRIDGE_REG_PTR(_base, _off) ((volatile bridgereg_t *) \
140 ((__psunsigned_t)(_base) + (__psunsigned_t)(_off)))
141
142#define SN0_WIDGET_BASE(_nasid, _wid) (NODE_SWIN_BASE((_nasid), (_wid)))
143
144/* Turn on sable logging for the processors whose bits are set. */
145#define SABLE_LOG_TRIGGER(_map)
146
147#ifndef __ASSEMBLY__
148#define KERN_NMI_ADDR(nasid, slice) \
149 TO_NODE_UNCAC((nasid), IP27_NMI_KREGS_OFFSET + \
150 (IP27_NMI_KREGS_CPU_SIZE * (slice)))
151#endif /* !__ASSEMBLY__ */
152
153#ifdef PROM
154
155#define MISC_PROM_BASE PHYS_TO_K0(0x01300000)
156#define MISC_PROM_SIZE 0x200000
157
158#define DIAG_BASE PHYS_TO_K0(0x01500000)
159#define DIAG_SIZE 0x300000
160
161#define ROUTE_BASE PHYS_TO_K0(0x01800000)
162#define ROUTE_SIZE 0x200000
163
164#define IP27PROM_FLASH_HDR PHYS_TO_K0(0x01300000)
165#define IP27PROM_FLASH_DATA PHYS_TO_K0(0x01301000)
166#define IP27PROM_CORP_MAX 32
167#define IP27PROM_CORP PHYS_TO_K0(0x01800000)
168#define IP27PROM_CORP_SIZE 0x10000
169#define IP27PROM_CORP_STK PHYS_TO_K0(0x01810000)
170#define IP27PROM_CORP_STKSIZE 0x2000
171#define IP27PROM_DECOMP_BUF PHYS_TO_K0(0x01900000)
172#define IP27PROM_DECOMP_SIZE 0xfff00
173
174#define IP27PROM_BASE PHYS_TO_K0(0x01a00000)
175#define IP27PROM_BASE_MAPPED (UNCAC_BASE | 0x1fc00000)
176#define IP27PROM_SIZE_MAX 0x100000
177
178#define IP27PROM_PCFG PHYS_TO_K0(0x01b00000)
179#define IP27PROM_PCFG_SIZE 0xd0000
180#define IP27PROM_ERRDMP PHYS_TO_K1(0x01bd0000)
181#define IP27PROM_ERRDMP_SIZE 0xf000
182
183#define IP27PROM_INIT_START PHYS_TO_K1(0x01bd0000)
184#define IP27PROM_CONSOLE PHYS_TO_K1(0x01bdf000)
185#define IP27PROM_CONSOLE_SIZE 0x200
186#define IP27PROM_NETUART PHYS_TO_K1(0x01bdf200)
187#define IP27PROM_NETUART_SIZE 0x100
188#define IP27PROM_UNUSED1 PHYS_TO_K1(0x01bdf300)
189#define IP27PROM_UNUSED1_SIZE 0x500
190#define IP27PROM_ELSC_BASE_A PHYS_TO_K0(0x01bdf800)
191#define IP27PROM_ELSC_BASE_B PHYS_TO_K0(0x01bdfc00)
192#define IP27PROM_STACK_A PHYS_TO_K0(0x01be0000)
193#define IP27PROM_STACK_B PHYS_TO_K0(0x01bf0000)
194#define IP27PROM_STACK_SHFT 16
195#define IP27PROM_STACK_SIZE (1 << IP27PROM_STACK_SHFT)
196#define IP27PROM_INIT_END PHYS_TO_K0(0x01c00000)
197
198#define SLAVESTACK_BASE PHYS_TO_K0(0x01580000)
199#define SLAVESTACK_SIZE 0x40000
200
201#define ENETBUFS_BASE PHYS_TO_K0(0x01f80000)
202#define ENETBUFS_SIZE 0x20000
203
204#define IO6PROM_BASE PHYS_TO_K0(0x01c00000)
205#define IO6PROM_SIZE 0x400000
206#define IO6PROM_BASE_MAPPED (UNCAC_BASE | 0x11c00000)
207#define IO6DPROM_BASE PHYS_TO_K0(0x01c00000)
208#define IO6DPROM_SIZE 0x200000
209
210#define NODEBUGUNIX_ADDR PHYS_TO_K0(0x00019000)
211#define DEBUGUNIX_ADDR PHYS_TO_K0(0x00100000)
212
213#define IP27PROM_INT_LAUNCH 10 /* and 11 */
214#define IP27PROM_INT_NETUART 12 /* through 17 */
215
216#endif /* PROM */
217
218/*
219 * needed by symmon so it needs to be outside #if PROM
220 */
221#define IP27PROM_ELSC_SHFT 10
222#define IP27PROM_ELSC_SIZE (1 << IP27PROM_ELSC_SHFT)
223
224/*
225 * This address is used by IO6PROM to build MemoryDescriptors of
226 * free memory. This address is important since unix gets loaded
227 * at this address, and this memory has to be FREE if unix is to
228 * be loaded.
229 */
230
231#define FREEMEM_BASE PHYS_TO_K0(0x2000000)
232
233#define IO6PROM_STACK_SHFT 14 /* stack per cpu */
234#define IO6PROM_STACK_SIZE (1 << IO6PROM_STACK_SHFT)
235
236/*
237 * IP27 PROM vectors
238 */
239
240#define IP27PROM_ENTRY PHYS_TO_COMPATK1(0x1fc00000)
241#define IP27PROM_RESTART PHYS_TO_COMPATK1(0x1fc00008)
242#define IP27PROM_SLAVELOOP PHYS_TO_COMPATK1(0x1fc00010)
243#define IP27PROM_PODMODE PHYS_TO_COMPATK1(0x1fc00018)
244#define IP27PROM_IOC3UARTPOD PHYS_TO_COMPATK1(0x1fc00020)
245#define IP27PROM_FLASHLEDS PHYS_TO_COMPATK1(0x1fc00028)
246#define IP27PROM_REPOD PHYS_TO_COMPATK1(0x1fc00030)
247#define IP27PROM_LAUNCHSLAVE PHYS_TO_COMPATK1(0x1fc00038)
248#define IP27PROM_WAITSLAVE PHYS_TO_COMPATK1(0x1fc00040)
249#define IP27PROM_POLLSLAVE PHYS_TO_COMPATK1(0x1fc00048)
250
251#define KL_UART_BASE LOCAL_HUB_ADDR(MD_UREG0_0) /* base of UART regs */
252#define KL_UART_CMD LOCAL_HUB_ADDR(MD_UREG0_0) /* UART command reg */
253#define KL_UART_DATA LOCAL_HUB_ADDR(MD_UREG0_1) /* UART data reg */
254#define KL_I2C_REG MD_UREG0_0 /* I2C reg */
255
256#ifndef __ASSEMBLY__
257
258/* Address 0x400 to 0x1000 ualias points to cache error eframe + misc
259 * CACHE_ERR_SP_PTR could either contain an address to the stack, or
260 * the stack could start at CACHE_ERR_SP_PTR
261 */
262#if defined(HUB_ERR_STS_WAR)
263#define CACHE_ERR_EFRAME 0x480
264#else /* HUB_ERR_STS_WAR */
265#define CACHE_ERR_EFRAME 0x400
266#endif /* HUB_ERR_STS_WAR */
267
268#define CACHE_ERR_ECCFRAME (CACHE_ERR_EFRAME + EF_SIZE)
269#define CACHE_ERR_SP_PTR (0x1000 - 32) /* why -32? TBD */
270#define CACHE_ERR_IBASE_PTR (0x1000 - 40)
271#define CACHE_ERR_SP (CACHE_ERR_SP_PTR - 16)
272#define CACHE_ERR_AREA_SIZE (ARCS_SPB_OFFSET - CACHE_ERR_EFRAME)
273
274#endif /* !__ASSEMBLY__ */
275
276#define _ARCSPROM
277
278#if defined(HUB_ERR_STS_WAR)
279
280#define ERR_STS_WAR_REGISTER IIO_IIBUSERR
281#define ERR_STS_WAR_ADDR LOCAL_HUB_ADDR(IIO_IIBUSERR)
282#define ERR_STS_WAR_PHYSADDR TO_PHYS((__psunsigned_t)ERR_STS_WAR_ADDR)
283 /* Used to match addr in error reg. */
284#define OLD_ERR_STS_WAR_OFFSET ((MD_MEM_BANKS * MD_BANK_SIZE) - 0x100)
285
286#endif /* HUB_ERR_STS_WAR */
287
288#endif /* _ASM_SN_SN0_ADDRS_H */
diff --git a/arch/mips/include/asm/sn/sn0/arch.h b/arch/mips/include/asm/sn/sn0/arch.h
new file mode 100644
index 000000000000..f734f2007f24
--- /dev/null
+++ b/arch/mips/include/asm/sn/sn0/arch.h
@@ -0,0 +1,72 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * SGI IP27 specific setup.
7 *
8 * Copyright (C) 1995 - 1997, 1999 Silcon Graphics, Inc.
9 * Copyright (C) 1999 Ralf Baechle (ralf@gnu.org)
10 */
11#ifndef _ASM_SN_SN0_ARCH_H
12#define _ASM_SN_SN0_ARCH_H
13
14
15#ifndef SN0XXL /* 128 cpu SMP max */
16/*
17 * This is the maximum number of nodes that can be part of a kernel.
18 * Effectively, it's the maximum number of compact node ids (cnodeid_t).
19 */
20#define MAX_COMPACT_NODES 64
21
22/*
23 * MAXCPUS refers to the maximum number of CPUs in a single kernel.
24 * This is not necessarily the same as MAXNODES * CPUS_PER_NODE
25 */
26#define MAXCPUS 128
27
28#else /* SN0XXL system */
29
30#define MAX_COMPACT_NODES 128
31#define MAXCPUS 256
32
33#endif /* SN0XXL */
34
35/*
36 * This is the maximum number of NASIDS that can be present in a system.
37 * (Highest NASID plus one.)
38 */
39#define MAX_NASIDS 256
40
41/*
42 * MAX_REGIONS refers to the maximum number of hardware partitioned regions.
43 */
44#define MAX_REGIONS 64
45#define MAX_NONPREMIUM_REGIONS 16
46#define MAX_PREMIUM_REGIONS MAX_REGIONS
47
48/*
49 * MAX_PARITIONS refers to the maximum number of logically defined
50 * partitions the system can support.
51 */
52#define MAX_PARTITIONS MAX_REGIONS
53
54#define NASID_MASK_BYTES ((MAX_NASIDS + 7) / 8)
55
56/*
57 * Slot constants for SN0
58 */
59#ifdef CONFIG_SGI_SN_N_MODE
60#define MAX_MEM_SLOTS 16 /* max slots per node */
61#else /* !CONFIG_SGI_SN_N_MODE, assume CONFIG_SGI_SN_M_MODE */
62#define MAX_MEM_SLOTS 32 /* max slots per node */
63#endif /* CONFIG_SGI_SN_M_MODE */
64
65#define SLOT_SHIFT (27)
66#define SLOT_MIN_MEM_SIZE (32*1024*1024)
67
68#define CPUS_PER_NODE 2 /* CPUs on a single hub */
69#define CPUS_PER_NODE_SHFT 1 /* Bits to shift in the node number */
70#define CPUS_PER_SUBNODE 2 /* CPUs on a single hub PI */
71
72#endif /* _ASM_SN_SN0_ARCH_H */
diff --git a/arch/mips/include/asm/sn/sn0/hub.h b/arch/mips/include/asm/sn/sn0/hub.h
new file mode 100644
index 000000000000..3e228f8e7969
--- /dev/null
+++ b/arch/mips/include/asm/sn/sn0/hub.h
@@ -0,0 +1,40 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1992 - 1997, 1999 Silicon Graphics, Inc.
7 * Copyright (C) 1999 by Ralf Baechle
8 */
9#ifndef _ASM_SN_SN0_HUB_H
10#define _ASM_SN_SN0_HUB_H
11
12/* The secret password; used to release protection */
13#define HUB_PASSWORD 0x53474972756c6573ull
14
15#define CHIPID_HUB 0
16#define CHIPID_ROUTER 1
17
18#define HUB_REV_1_0 1
19#define HUB_REV_2_0 2
20#define HUB_REV_2_1 3
21#define HUB_REV_2_2 4
22#define HUB_REV_2_3 5
23#define HUB_REV_2_4 6
24
25#define MAX_HUB_PATH 80
26
27#include <asm/sn/sn0/addrs.h>
28#include <asm/sn/sn0/hubpi.h>
29#include <asm/sn/sn0/hubmd.h>
30#include <asm/sn/sn0/hubio.h>
31#include <asm/sn/sn0/hubni.h>
32//#include <asm/sn/sn0/hubcore.h>
33
34/* Translation of uncached attributes */
35#define UATTR_HSPEC 0
36#define UATTR_IO 1
37#define UATTR_MSPEC 2
38#define UATTR_UNCAC 3
39
40#endif /* _ASM_SN_SN0_HUB_H */
diff --git a/arch/mips/include/asm/sn/sn0/hubio.h b/arch/mips/include/asm/sn/sn0/hubio.h
new file mode 100644
index 000000000000..d0c29d4de084
--- /dev/null
+++ b/arch/mips/include/asm/sn/sn0/hubio.h
@@ -0,0 +1,972 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Derived from IRIX <sys/SN/SN0/hubio.h>, Revision 1.80.
7 *
8 * Copyright (C) 1992 - 1997, 1999 Silicon Graphics, Inc.
9 * Copyright (C) 1999 by Ralf Baechle
10 */
11#ifndef _ASM_SGI_SN_SN0_HUBIO_H
12#define _ASM_SGI_SN_SN0_HUBIO_H
13
14/*
15 * Hub I/O interface registers
16 *
17 * All registers in this file are subject to change until Hub chip tapeout.
18 * In general, the longer software name should be used when available.
19 */
20
21/*
22 * Slightly friendlier names for some common registers.
23 * The hardware definitions follow.
24 */
25#define IIO_WIDGET IIO_WID /* Widget identification */
26#define IIO_WIDGET_STAT IIO_WSTAT /* Widget status register */
27#define IIO_WIDGET_CTRL IIO_WCR /* Widget control register */
28#define IIO_WIDGET_TOUT IIO_WRTO /* Widget request timeout */
29#define IIO_WIDGET_FLUSH IIO_WTFR /* Widget target flush */
30#define IIO_PROTECT IIO_ILAPR /* IO interface protection */
31#define IIO_PROTECT_OVRRD IIO_ILAPO /* IO protect override */
32#define IIO_OUTWIDGET_ACCESS IIO_IOWA /* Outbound widget access */
33#define IIO_INWIDGET_ACCESS IIO_IIWA /* Inbound widget access */
34#define IIO_INDEV_ERR_MASK IIO_IIDEM /* Inbound device error mask */
35#define IIO_LLP_CSR IIO_ILCSR /* LLP control and status */
36#define IIO_LLP_LOG IIO_ILLR /* LLP log */
37#define IIO_XTALKCC_TOUT IIO_IXCC /* Xtalk credit count timeout*/
38#define IIO_XTALKTT_TOUT IIO_IXTT /* Xtalk tail timeout */
39#define IIO_IO_ERR_CLR IIO_IECLR /* IO error clear */
40#define IIO_BTE_CRB_CNT IIO_IBCN /* IO BTE CRB count */
41
42#define IIO_LLP_CSR_IS_UP 0x00002000
43#define IIO_LLP_CSR_LLP_STAT_MASK 0x00003000
44#define IIO_LLP_CSR_LLP_STAT_SHFT 12
45
46/* key to IIO_PROTECT_OVRRD */
47#define IIO_PROTECT_OVRRD_KEY 0x53474972756c6573ull /* "SGIrules" */
48
49/* BTE register names */
50#define IIO_BTE_STAT_0 IIO_IBLS_0 /* Also BTE length/status 0 */
51#define IIO_BTE_SRC_0 IIO_IBSA_0 /* Also BTE source address 0 */
52#define IIO_BTE_DEST_0 IIO_IBDA_0 /* Also BTE dest. address 0 */
53#define IIO_BTE_CTRL_0 IIO_IBCT_0 /* Also BTE control/terminate 0 */
54#define IIO_BTE_NOTIFY_0 IIO_IBNA_0 /* Also BTE notification 0 */
55#define IIO_BTE_INT_0 IIO_IBIA_0 /* Also BTE interrupt 0 */
56#define IIO_BTE_OFF_0 0 /* Base offset from BTE 0 regs. */
57#define IIO_BTE_OFF_1 IIO_IBLS_1 - IIO_IBLS_0 /* Offset from base to BTE 1 */
58
59/* BTE register offsets from base */
60#define BTEOFF_STAT 0
61#define BTEOFF_SRC (IIO_BTE_SRC_0 - IIO_BTE_STAT_0)
62#define BTEOFF_DEST (IIO_BTE_DEST_0 - IIO_BTE_STAT_0)
63#define BTEOFF_CTRL (IIO_BTE_CTRL_0 - IIO_BTE_STAT_0)
64#define BTEOFF_NOTIFY (IIO_BTE_NOTIFY_0 - IIO_BTE_STAT_0)
65#define BTEOFF_INT (IIO_BTE_INT_0 - IIO_BTE_STAT_0)
66
67
68/*
69 * The following definitions use the names defined in the IO interface
70 * document for ease of reference. When possible, software should
71 * generally use the longer but clearer names defined above.
72 */
73
74#define IIO_BASE 0x400000
75#define IIO_BASE_BTE0 0x410000
76#define IIO_BASE_BTE1 0x420000
77#define IIO_BASE_PERF 0x430000
78#define IIO_PERF_CNT 0x430008
79
80#define IO_PERF_SETS 32
81
82#define IIO_WID 0x400000 /* Widget identification */
83#define IIO_WSTAT 0x400008 /* Widget status */
84#define IIO_WCR 0x400020 /* Widget control */
85
86#define IIO_WSTAT_ECRAZY (1ULL << 32) /* Hub gone crazy */
87#define IIO_WSTAT_TXRETRY (1ULL << 9) /* Hub Tx Retry timeout */
88#define IIO_WSTAT_TXRETRY_MASK (0x7F)
89#define IIO_WSTAT_TXRETRY_SHFT (16)
90#define IIO_WSTAT_TXRETRY_CNT(w) (((w) >> IIO_WSTAT_TXRETRY_SHFT) & \
91 IIO_WSTAT_TXRETRY_MASK)
92
93#define IIO_ILAPR 0x400100 /* Local Access Protection */
94#define IIO_ILAPO 0x400108 /* Protection override */
95#define IIO_IOWA 0x400110 /* outbound widget access */
96#define IIO_IIWA 0x400118 /* inbound widget access */
97#define IIO_IIDEM 0x400120 /* Inbound Device Error Mask */
98#define IIO_ILCSR 0x400128 /* LLP control and status */
99#define IIO_ILLR 0x400130 /* LLP Log */
100#define IIO_IIDSR 0x400138 /* Interrupt destination */
101
102#define IIO_IIBUSERR 0x1400208 /* Reads here cause a bus error. */
103
104/* IO Interrupt Destination Register */
105#define IIO_IIDSR_SENT_SHIFT 28
106#define IIO_IIDSR_SENT_MASK 0x10000000
107#define IIO_IIDSR_ENB_SHIFT 24
108#define IIO_IIDSR_ENB_MASK 0x01000000
109#define IIO_IIDSR_NODE_SHIFT 8
110#define IIO_IIDSR_NODE_MASK 0x0000ff00
111#define IIO_IIDSR_LVL_SHIFT 0
112#define IIO_IIDSR_LVL_MASK 0x0000003f
113
114
115/* GFX Flow Control Node/Widget Register */
116#define IIO_IGFX_0 0x400140 /* gfx node/widget register 0 */
117#define IIO_IGFX_1 0x400148 /* gfx node/widget register 1 */
118#define IIO_IGFX_W_NUM_BITS 4 /* size of widget num field */
119#define IIO_IGFX_W_NUM_MASK ((1<<IIO_IGFX_W_NUM_BITS)-1)
120#define IIO_IGFX_W_NUM_SHIFT 0
121#define IIO_IGFX_N_NUM_BITS 9 /* size of node num field */
122#define IIO_IGFX_N_NUM_MASK ((1<<IIO_IGFX_N_NUM_BITS)-1)
123#define IIO_IGFX_N_NUM_SHIFT 4
124#define IIO_IGFX_P_NUM_BITS 1 /* size of processor num field */
125#define IIO_IGFX_P_NUM_MASK ((1<<IIO_IGFX_P_NUM_BITS)-1)
126#define IIO_IGFX_P_NUM_SHIFT 16
127#define IIO_IGFX_VLD_BITS 1 /* size of valid field */
128#define IIO_IGFX_VLD_MASK ((1<<IIO_IGFX_VLD_BITS)-1)
129#define IIO_IGFX_VLD_SHIFT 20
130#define IIO_IGFX_INIT(widget, node, cpu, valid) (\
131 (((widget) & IIO_IGFX_W_NUM_MASK) << IIO_IGFX_W_NUM_SHIFT) | \
132 (((node) & IIO_IGFX_N_NUM_MASK) << IIO_IGFX_N_NUM_SHIFT) | \
133 (((cpu) & IIO_IGFX_P_NUM_MASK) << IIO_IGFX_P_NUM_SHIFT) | \
134 (((valid) & IIO_IGFX_VLD_MASK) << IIO_IGFX_VLD_SHIFT) )
135
136/* Scratch registers (not all bits available) */
137#define IIO_SCRATCH_REG0 0x400150
138#define IIO_SCRATCH_REG1 0x400158
139#define IIO_SCRATCH_MASK 0x0000000f00f11fff
140
141#define IIO_SCRATCH_BIT0_0 0x0000000800000000
142#define IIO_SCRATCH_BIT0_1 0x0000000400000000
143#define IIO_SCRATCH_BIT0_2 0x0000000200000000
144#define IIO_SCRATCH_BIT0_3 0x0000000100000000
145#define IIO_SCRATCH_BIT0_4 0x0000000000800000
146#define IIO_SCRATCH_BIT0_5 0x0000000000400000
147#define IIO_SCRATCH_BIT0_6 0x0000000000200000
148#define IIO_SCRATCH_BIT0_7 0x0000000000100000
149#define IIO_SCRATCH_BIT0_8 0x0000000000010000
150#define IIO_SCRATCH_BIT0_9 0x0000000000001000
151#define IIO_SCRATCH_BIT0_R 0x0000000000000fff
152
153/* IO Translation Table Entries */
154#define IIO_NUM_ITTES 7 /* ITTEs numbered 0..6 */
155 /* Hw manuals number them 1..7! */
156
157/*
158 * As a permanent workaround for a bug in the PI side of the hub, we've
159 * redefined big window 7 as small window 0.
160 */
161#define HUB_NUM_BIG_WINDOW IIO_NUM_ITTES - 1
162
163/*
164 * Use the top big window as a surrogate for the first small window
165 */
166#define SWIN0_BIGWIN HUB_NUM_BIG_WINDOW
167
168#define ILCSR_WARM_RESET 0x100
169/*
170 * The IO LLP control status register and widget control register
171 */
172#ifndef __ASSEMBLY__
173
174typedef union hubii_wid_u {
175 u64 wid_reg_value;
176 struct {
177 u64 wid_rsvd: 32, /* unused */
178 wid_rev_num: 4, /* revision number */
179 wid_part_num: 16, /* the widget type: hub=c101 */
180 wid_mfg_num: 11, /* Manufacturer id (IBM) */
181 wid_rsvd1: 1; /* Reserved */
182 } wid_fields_s;
183} hubii_wid_t;
184
185
186typedef union hubii_wcr_u {
187 u64 wcr_reg_value;
188 struct {
189 u64 wcr_rsvd: 41, /* unused */
190 wcr_e_thresh: 5, /* elasticity threshold */
191 wcr_dir_con: 1, /* widget direct connect */
192 wcr_f_bad_pkt: 1, /* Force bad llp pkt enable */
193 wcr_xbar_crd: 3, /* LLP crossbar credit */
194 wcr_rsvd1: 8, /* Reserved */
195 wcr_tag_mode: 1, /* Tag mode */
196 wcr_widget_id: 4; /* LLP crossbar credit */
197 } wcr_fields_s;
198} hubii_wcr_t;
199
200#define iwcr_dir_con wcr_fields_s.wcr_dir_con
201
202typedef union hubii_wstat_u {
203 u64 reg_value;
204 struct {
205 u64 rsvd1: 31,
206 crazy: 1, /* Crazy bit */
207 rsvd2: 8,
208 llp_tx_cnt: 8, /* LLP Xmit retry counter */
209 rsvd3: 6,
210 tx_max_rtry: 1, /* LLP Retry Timeout Signal */
211 rsvd4: 2,
212 xt_tail_to: 1, /* Xtalk Tail Timeout */
213 xt_crd_to: 1, /* Xtalk Credit Timeout */
214 pending: 4; /* Pending Requests */
215 } wstat_fields_s;
216} hubii_wstat_t;
217
218
219typedef union hubii_ilcsr_u {
220 u64 icsr_reg_value;
221 struct {
222 u64 icsr_rsvd: 22, /* unused */
223 icsr_max_burst: 10, /* max burst */
224 icsr_rsvd4: 6, /* reserved */
225 icsr_max_retry: 10, /* max retry */
226 icsr_rsvd3: 2, /* reserved */
227 icsr_lnk_stat: 2, /* link status */
228 icsr_bm8: 1, /* Bit mode 8 */
229 icsr_llp_en: 1, /* LLP enable bit */
230 icsr_rsvd2: 1, /* reserver */
231 icsr_wrm_reset: 1, /* Warm reset bit */
232 icsr_rsvd1: 2, /* Data ready offset */
233 icsr_null_to: 6; /* Null timeout */
234
235 } icsr_fields_s;
236} hubii_ilcsr_t;
237
238
239typedef union hubii_iowa_u {
240 u64 iowa_reg_value;
241 struct {
242 u64 iowa_rsvd: 48, /* unused */
243 iowa_wxoac: 8, /* xtalk widget access bits */
244 iowa_rsvd1: 7, /* xtalk widget access bits */
245 iowa_w0oac: 1; /* xtalk widget access bits */
246 } iowa_fields_s;
247} hubii_iowa_t;
248
249typedef union hubii_iiwa_u {
250 u64 iiwa_reg_value;
251 struct {
252 u64 iiwa_rsvd: 48, /* unused */
253 iiwa_wxiac: 8, /* hub wid access bits */
254 iiwa_rsvd1: 7, /* reserved */
255 iiwa_w0iac: 1; /* hub wid0 access */
256 } iiwa_fields_s;
257} hubii_iiwa_t;
258
259typedef union hubii_illr_u {
260 u64 illr_reg_value;
261 struct {
262 u64 illr_rsvd: 32, /* unused */
263 illr_cb_cnt: 16, /* checkbit error count */
264 illr_sn_cnt: 16; /* sequence number count */
265 } illr_fields_s;
266} hubii_illr_t;
267
268/* The structures below are defined to extract and modify the ii
269performance registers */
270
271/* io_perf_sel allows the caller to specify what tests will be
272 performed */
273typedef union io_perf_sel {
274 u64 perf_sel_reg;
275 struct {
276 u64 perf_rsvd : 48,
277 perf_icct : 8,
278 perf_ippr1 : 4,
279 perf_ippr0 : 4;
280 } perf_sel_bits;
281} io_perf_sel_t;
282
283/* io_perf_cnt is to extract the count from the hub registers. Due to
284 hardware problems there is only one counter, not two. */
285
286typedef union io_perf_cnt {
287 u64 perf_cnt;
288 struct {
289 u64 perf_rsvd1 : 32,
290 perf_rsvd2 : 12,
291 perf_cnt : 20;
292 } perf_cnt_bits;
293} io_perf_cnt_t;
294
295#endif /* !__ASSEMBLY__ */
296
297
298#define LNK_STAT_WORKING 0x2
299
300#define IIO_LLP_CB_MAX 0xffff
301#define IIO_LLP_SN_MAX 0xffff
302
303/* IO PRB Entries */
304#define IIO_NUM_IPRBS (9)
305#define IIO_IOPRB_0 0x400198 /* PRB entry 0 */
306#define IIO_IOPRB_8 0x4001a0 /* PRB entry 8 */
307#define IIO_IOPRB_9 0x4001a8 /* PRB entry 9 */
308#define IIO_IOPRB_A 0x4001b0 /* PRB entry a */
309#define IIO_IOPRB_B 0x4001b8 /* PRB entry b */
310#define IIO_IOPRB_C 0x4001c0 /* PRB entry c */
311#define IIO_IOPRB_D 0x4001c8 /* PRB entry d */
312#define IIO_IOPRB_E 0x4001d0 /* PRB entry e */
313#define IIO_IOPRB_F 0x4001d8 /* PRB entry f */
314
315
316#define IIO_IXCC 0x4001e0 /* Crosstalk credit count timeout */
317#define IIO_IXTCC IIO_IXCC
318#define IIO_IMEM 0x4001e8 /* Miscellaneous Enable Mask */
319#define IIO_IXTT 0x4001f0 /* Crosstalk tail timeout */
320#define IIO_IECLR 0x4001f8 /* IO error clear */
321#define IIO_IBCN 0x400200 /* IO BTE CRB count */
322
323/*
324 * IIO_IMEM Register fields.
325 */
326#define IIO_IMEM_W0ESD 0x1 /* Widget 0 shut down due to error */
327#define IIO_IMEM_B0ESD (1 << 4) /* BTE 0 shut down due to error */
328#define IIO_IMEM_B1ESD (1 << 8) /* BTE 1 Shut down due to error */
329
330/* PIO Read address Table Entries */
331#define IIO_IPCA 0x400300 /* PRB Counter adjust */
332#define IIO_NUM_PRTES 8 /* Total number of PRB table entries */
333#define IIO_PRTE_0 0x400308 /* PIO Read address table entry 0 */
334#define IIO_PRTE(_x) (IIO_PRTE_0 + (8 * (_x)))
335#define IIO_WIDPRTE(x) IIO_PRTE(((x) - 8)) /* widget ID to its PRTE num */
336#define IIO_IPDR 0x400388 /* PIO table entry deallocation */
337#define IIO_ICDR 0x400390 /* CRB Entry Deallocation */
338#define IIO_IFDR 0x400398 /* IOQ FIFO Depth */
339#define IIO_IIAP 0x4003a0 /* IIQ Arbitration Parameters */
340#define IIO_IMMR IIO_IIAP
341#define IIO_ICMR 0x4003a8 /* CRB Management Register */
342#define IIO_ICCR 0x4003b0 /* CRB Control Register */
343#define IIO_ICTO 0x4003b8 /* CRB Time Out Register */
344#define IIO_ICTP 0x4003c0 /* CRB Time Out Prescalar */
345
346
347/*
348 * ICMR register fields
349 */
350#define IIO_ICMR_PC_VLD_SHFT 36
351#define IIO_ICMR_PC_VLD_MASK (0x7fffUL << IIO_ICMR_PC_VLD_SHFT)
352
353#define IIO_ICMR_CRB_VLD_SHFT 20
354#define IIO_ICMR_CRB_VLD_MASK (0x7fffUL << IIO_ICMR_CRB_VLD_SHFT)
355
356#define IIO_ICMR_FC_CNT_SHFT 16
357#define IIO_ICMR_FC_CNT_MASK (0xf << IIO_ICMR_FC_CNT_SHFT)
358
359#define IIO_ICMR_C_CNT_SHFT 4
360#define IIO_ICMR_C_CNT_MASK (0xf << IIO_ICMR_C_CNT_SHFT)
361
362#define IIO_ICMR_P_CNT_SHFT 0
363#define IIO_ICMR_P_CNT_MASK (0xf << IIO_ICMR_P_CNT_SHFT)
364
365#define IIO_ICMR_PRECISE (1UL << 52)
366#define IIO_ICMR_CLR_RPPD (1UL << 13)
367#define IIO_ICMR_CLR_RQPD (1UL << 12)
368
369/*
370 * IIO PIO Deallocation register field masks : (IIO_IPDR)
371 */
372#define IIO_IPDR_PND (1 << 4)
373
374/*
375 * IIO CRB deallocation register field masks: (IIO_ICDR)
376 */
377#define IIO_ICDR_PND (1 << 4)
378
379/*
380 * IIO CRB control register Fields: IIO_ICCR
381 */
382#define IIO_ICCR_PENDING (0x10000)
383#define IIO_ICCR_CMD_MASK (0xFF)
384#define IIO_ICCR_CMD_SHFT (7)
385#define IIO_ICCR_CMD_NOP (0x0) /* No Op */
386#define IIO_ICCR_CMD_WAKE (0x100) /* Reactivate CRB entry and process */
387#define IIO_ICCR_CMD_TIMEOUT (0x200) /* Make CRB timeout & mark invalid */
388#define IIO_ICCR_CMD_EJECT (0x400) /* Contents of entry written to memory
389 * via a WB
390 */
391#define IIO_ICCR_CMD_FLUSH (0x800)
392
393/*
394 * CRB manipulation macros
395 * The CRB macros are slightly complicated, since there are up to
396 * four registers associated with each CRB entry.
397 */
398#define IIO_NUM_CRBS 15 /* Number of CRBs */
399#define IIO_NUM_NORMAL_CRBS 12 /* Number of regular CRB entries */
400#define IIO_NUM_PC_CRBS 4 /* Number of partial cache CRBs */
401#define IIO_ICRB_OFFSET 8
402#define IIO_ICRB_0 0x400400
403/* XXX - This is now tuneable:
404 #define IIO_FIRST_PC_ENTRY 12
405 */
406
407#define IIO_ICRB_A(_x) (IIO_ICRB_0 + (4 * IIO_ICRB_OFFSET * (_x)))
408#define IIO_ICRB_B(_x) (IIO_ICRB_A(_x) + 1*IIO_ICRB_OFFSET)
409#define IIO_ICRB_C(_x) (IIO_ICRB_A(_x) + 2*IIO_ICRB_OFFSET)
410#define IIO_ICRB_D(_x) (IIO_ICRB_A(_x) + 3*IIO_ICRB_OFFSET)
411
412/* XXX - IBUE register coming for Hub 2 */
413
414/*
415 *
416 * CRB Register description.
417 *
418 * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
419 * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
420 * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
421 * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
422 * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
423 *
424 * Many of the fields in CRB are status bits used by hardware
425 * for implementation of the protocol. It's very dangerous to
426 * mess around with the CRB registers.
427 *
428 * It's OK to read the CRB registers and try to make sense out of the
429 * fields in CRB.
430 *
431 * Updating CRB requires all activities in Hub IIO to be quiesced.
432 * otherwise, a write to CRB could corrupt other CRB entries.
433 * CRBs are here only as a back door peek to hub IIO's status.
434 * Quiescing implies no dmas no PIOs
435 * either directly from the cpu or from sn0net.
436 * this is not something that can be done easily. So, AVOID updating
437 * CRBs.
438 */
439
440/*
441 * Fields in CRB Register A
442 */
443#ifndef __ASSEMBLY__
444typedef union icrba_u {
445 u64 reg_value;
446 struct {
447 u64 resvd: 6,
448 stall_bte0: 1, /* Stall BTE 0 */
449 stall_bte1: 1, /* Stall BTE 1 */
450 error: 1, /* CRB has an error */
451 ecode: 3, /* Error Code */
452 lnetuce: 1, /* SN0net Uncorrectable error */
453 mark: 1, /* CRB Has been marked */
454 xerr: 1, /* Error bit set in xtalk header */
455 sidn: 4, /* SIDN field from xtalk */
456 tnum: 5, /* TNUM field in xtalk */
457 addr: 38, /* Address of request */
458 valid: 1, /* Valid status */
459 iow: 1; /* IO Write operation */
460 } icrba_fields_s;
461} icrba_t;
462
463/* This is an alternate typedef for the HUB1 CRB A in order to allow
464 runtime selection of the format based on the REV_ID field of the
465 NI_STATUS_REV_ID register. */
466typedef union h1_icrba_u {
467 u64 reg_value;
468
469 struct {
470 u64 resvd: 6,
471 unused: 1, /* Unused but RW!! */
472 error: 1, /* CRB has an error */
473 ecode: 4, /* Error Code */
474 lnetuce: 1, /* SN0net Uncorrectable error */
475 mark: 1, /* CRB Has been marked */
476 xerr: 1, /* Error bit set in xtalk header */
477 sidn: 4, /* SIDN field from xtalk */
478 tnum: 5, /* TNUM field in xtalk */
479 addr: 38, /* Address of request */
480 valid: 1, /* Valid status */
481 iow: 1; /* IO Write operation */
482 } h1_icrba_fields_s;
483} h1_icrba_t;
484
485/* XXX - Is this still right? Check the spec. */
486#define ICRBN_A_CERR_SHFT 54
487#define ICRBN_A_ERR_MASK 0x3ff
488
489#endif /* !__ASSEMBLY__ */
490
491#define IIO_ICRB_ADDR_SHFT 2 /* Shift to get proper address */
492
493/*
494 * values for "ecode" field
495 */
496#define IIO_ICRB_ECODE_DERR 0 /* Directory error due to IIO access */
497#define IIO_ICRB_ECODE_PERR 1 /* Poison error on IO access */
498#define IIO_ICRB_ECODE_WERR 2 /* Write error by IIO access
499 * e.g. WINV to a Read only line.
500 */
501#define IIO_ICRB_ECODE_AERR 3 /* Access error caused by IIO access */
502#define IIO_ICRB_ECODE_PWERR 4 /* Error on partial write */
503#define IIO_ICRB_ECODE_PRERR 5 /* Error on partial read */
504#define IIO_ICRB_ECODE_TOUT 6 /* CRB timeout before deallocating */
505#define IIO_ICRB_ECODE_XTERR 7 /* Incoming xtalk pkt had error bit */
506
507
508
509/*
510 * Fields in CRB Register B
511 */
512#ifndef __ASSEMBLY__
513typedef union icrbb_u {
514 u64 reg_value;
515 struct {
516 u64 rsvd1: 5,
517 btenum: 1, /* BTE to which entry belongs to */
518 cohtrans: 1, /* Coherent transaction */
519 xtsize: 2, /* Xtalk operation size
520 * 0: Double Word
521 * 1: 32 Bytes.
522 * 2: 128 Bytes,
523 * 3: Reserved.
524 */
525 srcnode: 9, /* Source Node ID */
526 srcinit: 2, /* Source Initiator:
527 * See below for field values.
528 */
529 useold: 1, /* Use OLD command for processing */
530 imsgtype: 2, /* Incoming message type
531 * see below for field values
532 */
533 imsg: 8, /* Incoming message */
534 initator: 3, /* Initiator of original request
535 * See below for field values.
536 */
537 reqtype: 5, /* Identifies type of request
538 * See below for field values.
539 */
540 rsvd2: 7,
541 ackcnt: 11, /* Invalidate ack count */
542 resp: 1, /* data response given to processor */
543 ack: 1, /* indicates data ack received */
544 hold: 1, /* entry is gathering inval acks */
545 wb_pend:1, /* waiting for writeback to complete */
546 intvn: 1, /* Intervention */
547 stall_ib: 1, /* Stall Ibuf (from crosstalk) */
548 stall_intr: 1; /* Stall internal interrupts */
549 } icrbb_field_s;
550} icrbb_t;
551
552/* This is an alternate typedef for the HUB1 CRB B in order to allow
553 runtime selection of the format based on the REV_ID field of the
554 NI_STATUS_REV_ID register. */
555typedef union h1_icrbb_u {
556 u64 reg_value;
557 struct {
558 u64 rsvd1: 5,
559 btenum: 1, /* BTE to which entry belongs to */
560 cohtrans: 1, /* Coherent transaction */
561 xtsize: 2, /* Xtalk operation size
562 * 0: Double Word
563 * 1: 32 Bytes.
564 * 2: 128 Bytes,
565 * 3: Reserved.
566 */
567 srcnode: 9, /* Source Node ID */
568 srcinit: 2, /* Source Initiator:
569 * See below for field values.
570 */
571 useold: 1, /* Use OLD command for processing */
572 imsgtype: 2, /* Incoming message type
573 * see below for field values
574 */
575 imsg: 8, /* Incoming message */
576 initator: 3, /* Initiator of original request
577 * See below for field values.
578 */
579 rsvd2: 1,
580 pcache: 1, /* entry belongs to partial cache */
581 reqtype: 5, /* Identifies type of request
582 * See below for field values.
583 */
584 stl_ib: 1, /* stall Ibus coming from xtalk */
585 stl_intr: 1, /* Stall internal interrupts */
586 stl_bte0: 1, /* Stall BTE 0 */
587 stl_bte1: 1, /* Stall BTE 1 */
588 intrvn: 1, /* Req was target of intervention */
589 ackcnt: 11, /* Invalidate ack count */
590 resp: 1, /* data response given to processor */
591 ack: 1, /* indicates data ack received */
592 hold: 1, /* entry is gathering inval acks */
593 wb_pend:1, /* waiting for writeback to complete */
594 sleep: 1, /* xtalk req sleeping till IO-sync */
595 pnd_reply: 1, /* replies not issed due to IOQ full */
596 pnd_req: 1; /* reqs not issued due to IOQ full */
597 } h1_icrbb_field_s;
598} h1_icrbb_t;
599
600
601#define b_imsgtype icrbb_field_s.imsgtype
602#define b_btenum icrbb_field_s.btenum
603#define b_cohtrans icrbb_field_s.cohtrans
604#define b_xtsize icrbb_field_s.xtsize
605#define b_srcnode icrbb_field_s.srcnode
606#define b_srcinit icrbb_field_s.srcinit
607#define b_imsgtype icrbb_field_s.imsgtype
608#define b_imsg icrbb_field_s.imsg
609#define b_initiator icrbb_field_s.initiator
610
611#endif /* !__ASSEMBLY__ */
612
613/*
614 * values for field xtsize
615 */
616#define IIO_ICRB_XTSIZE_DW 0 /* Xtalk operation size is 8 bytes */
617#define IIO_ICRB_XTSIZE_32 1 /* Xtalk operation size is 32 bytes */
618#define IIO_ICRB_XTSIZE_128 2 /* Xtalk operation size is 128 bytes */
619
620/*
621 * values for field srcinit
622 */
623#define IIO_ICRB_PROC0 0 /* Source of request is Proc 0 */
624#define IIO_ICRB_PROC1 1 /* Source of request is Proc 1 */
625#define IIO_ICRB_GB_REQ 2 /* Source is Guranteed BW request */
626#define IIO_ICRB_IO_REQ 3 /* Source is Normal IO request */
627
628/*
629 * Values for field imsgtype
630 */
631#define IIO_ICRB_IMSGT_XTALK 0 /* Incoming Meessage from Xtalk */
632#define IIO_ICRB_IMSGT_BTE 1 /* Incoming message from BTE */
633#define IIO_ICRB_IMSGT_SN0NET 2 /* Incoming message from SN0 net */
634#define IIO_ICRB_IMSGT_CRB 3 /* Incoming message from CRB ??? */
635
636/*
637 * values for field initiator.
638 */
639#define IIO_ICRB_INIT_XTALK 0 /* Message originated in xtalk */
640#define IIO_ICRB_INIT_BTE0 0x1 /* Message originated in BTE 0 */
641#define IIO_ICRB_INIT_SN0NET 0x2 /* Message originated in SN0net */
642#define IIO_ICRB_INIT_CRB 0x3 /* Message originated in CRB ? */
643#define IIO_ICRB_INIT_BTE1 0x5 /* MEssage originated in BTE 1 */
644
645/*
646 * Values for field reqtype.
647 */
648/* XXX - Need to fix this for Hub 2 */
649#define IIO_ICRB_REQ_DWRD 0 /* Request type double word */
650#define IIO_ICRB_REQ_QCLRD 1 /* Request is Qrtr Caceh line Rd */
651#define IIO_ICRB_REQ_BLKRD 2 /* Request is block read */
652#define IIO_ICRB_REQ_RSHU 6 /* Request is BTE block read */
653#define IIO_ICRB_REQ_REXU 7 /* request is BTE Excl Read */
654#define IIO_ICRB_REQ_RDEX 8 /* Request is Read Exclusive */
655#define IIO_ICRB_REQ_WINC 9 /* Request is Write Invalidate */
656#define IIO_ICRB_REQ_BWINV 10 /* Request is BTE Winv */
657#define IIO_ICRB_REQ_PIORD 11 /* Request is PIO read */
658#define IIO_ICRB_REQ_PIOWR 12 /* Request is PIO Write */
659#define IIO_ICRB_REQ_PRDM 13 /* Request is Fetch&Op */
660#define IIO_ICRB_REQ_PWRM 14 /* Request is Store &Op */
661#define IIO_ICRB_REQ_PTPWR 15 /* Request is Peer to peer */
662#define IIO_ICRB_REQ_WB 16 /* Request is Write back */
663#define IIO_ICRB_REQ_DEX 17 /* Retained DEX Cache line */
664
665/*
666 * Fields in CRB Register C
667 */
668
669#ifndef __ASSEMBLY__
670
671typedef union icrbc_s {
672 u64 reg_value;
673 struct {
674 u64 rsvd: 6,
675 sleep: 1,
676 pricnt: 4, /* Priority count sent with Read req */
677 pripsc: 4, /* Priority Pre scalar */
678 bteop: 1, /* BTE Operation */
679 push_be: 34, /* Push address Byte enable
680 * Holds push addr, if CRB is for BTE
681 * If CRB belongs to Partial cache,
682 * this contains byte enables bits
683 * ([47:46] = 0)
684 */
685 suppl: 11, /* Supplemental field */
686 barrop: 1, /* Barrier Op bit set in xtalk req */
687 doresp: 1, /* Xtalk req needs a response */
688 gbr: 1; /* GBR bit set in xtalk packet */
689 } icrbc_field_s;
690} icrbc_t;
691
692#define c_pricnt icrbc_field_s.pricnt
693#define c_pripsc icrbc_field_s.pripsc
694#define c_bteop icrbc_field_s.bteop
695#define c_bteaddr icrbc_field_s.push_be /* push_be field has 2 names */
696#define c_benable icrbc_field_s.push_be /* push_be field has 2 names */
697#define c_suppl icrbc_field_s.suppl
698#define c_barrop icrbc_field_s.barrop
699#define c_doresp icrbc_field_s.doresp
700#define c_gbr icrbc_field_s.gbr
701#endif /* !__ASSEMBLY__ */
702
703/*
704 * Fields in CRB Register D
705 */
706
707#ifndef __ASSEMBLY__
708typedef union icrbd_s {
709 u64 reg_value;
710 struct {
711 u64 rsvd: 38,
712 toutvld: 1, /* Timeout in progress for this CRB */
713 ctxtvld: 1, /* Context field below is valid */
714 rsvd2: 1,
715 context: 15, /* Bit vector:
716 * Has a bit set for each CRB entry
717 * which needs to be deallocated
718 * before this CRB entry is processed.
719 * Set only for barrier operations.
720 */
721 timeout: 8; /* Timeout Upper 8 bits */
722 } icrbd_field_s;
723} icrbd_t;
724
725#define icrbd_toutvld icrbd_field_s.toutvld
726#define icrbd_ctxtvld icrbd_field_s.ctxtvld
727#define icrbd_context icrbd_field_s.context
728
729
730typedef union hubii_ifdr_u {
731 u64 hi_ifdr_value;
732 struct {
733 u64 ifdr_rsvd: 49,
734 ifdr_maxrp: 7,
735 ifdr_rsvd1: 1,
736 ifdr_maxrq: 7;
737 } hi_ifdr_fields;
738} hubii_ifdr_t;
739
740#endif /* !__ASSEMBLY__ */
741
742/*
743 * Hardware designed names for the BTE control registers.
744 */
745#define IIO_IBLS_0 0x410000 /* BTE length/status 0 */
746#define IIO_IBSA_0 0x410008 /* BTE source address 0 */
747#define IIO_IBDA_0 0x410010 /* BTE destination address 0 */
748#define IIO_IBCT_0 0x410018 /* BTE control/terminate 0 */
749#define IIO_IBNA_0 0x410020 /* BTE notification address 0 */
750#define IIO_IBNR_0 IIO_IBNA_0
751#define IIO_IBIA_0 0x410028 /* BTE interrupt address 0 */
752
753#define IIO_IBLS_1 0x420000 /* BTE length/status 1 */
754#define IIO_IBSA_1 0x420008 /* BTE source address 1 */
755#define IIO_IBDA_1 0x420010 /* BTE destination address 1 */
756#define IIO_IBCT_1 0x420018 /* BTE control/terminate 1 */
757#define IIO_IBNA_1 0x420020 /* BTE notification address 1 */
758#define IIO_IBNR_1 IIO_IBNA_1
759#define IIO_IBIA_1 0x420028 /* BTE interrupt address 1 */
760
761/*
762 * More miscellaneous registers
763 */
764#define IIO_IPCR 0x430000 /* Performance Control */
765#define IIO_IPPR 0x430008 /* Performance Profiling */
766
767/*
768 * IO Error Clear register bit field definitions
769 */
770#define IECLR_BTE1 (1 << 18) /* clear bte error 1 ??? */
771#define IECLR_BTE0 (1 << 17) /* clear bte error 0 ??? */
772#define IECLR_CRAZY (1 << 16) /* clear crazy bit in wstat reg */
773#define IECLR_PRB_F (1 << 15) /* clear err bit in PRB_F reg */
774#define IECLR_PRB_E (1 << 14) /* clear err bit in PRB_E reg */
775#define IECLR_PRB_D (1 << 13) /* clear err bit in PRB_D reg */
776#define IECLR_PRB_C (1 << 12) /* clear err bit in PRB_C reg */
777#define IECLR_PRB_B (1 << 11) /* clear err bit in PRB_B reg */
778#define IECLR_PRB_A (1 << 10) /* clear err bit in PRB_A reg */
779#define IECLR_PRB_9 (1 << 9) /* clear err bit in PRB_9 reg */
780#define IECLR_PRB_8 (1 << 8) /* clear err bit in PRB_8 reg */
781#define IECLR_PRB_0 (1 << 0) /* clear err bit in PRB_0 reg */
782
783/*
784 * IO PIO Read Table Entry format
785 */
786
787#ifndef __ASSEMBLY__
788
789typedef union iprte_a {
790 u64 entry;
791 struct {
792 u64 rsvd1 : 7, /* Reserved field */
793 valid : 1, /* Maps to a timeout entry */
794 rsvd2 : 1,
795 srcnode : 9, /* Node which did this PIO */
796 initiator : 2, /* If T5A or T5B or IO */
797 rsvd3 : 3,
798 addr : 38, /* Physical address of PIO */
799 rsvd4 : 3;
800 } iprte_fields;
801} iprte_a_t;
802
803#define iprte_valid iprte_fields.valid
804#define iprte_timeout iprte_fields.timeout
805#define iprte_srcnode iprte_fields.srcnode
806#define iprte_init iprte_fields.initiator
807#define iprte_addr iprte_fields.addr
808
809#endif /* !__ASSEMBLY__ */
810
811#define IPRTE_ADDRSHFT 3
812
813/*
814 * Hub IIO PRB Register format.
815 */
816
817#ifndef __ASSEMBLY__
818/*
819 * Note: Fields bnakctr, anakctr, xtalkctrmode, ovflow fields are
820 * "Status" fields, and should only be used in case of clean up after errors.
821 */
822
823typedef union iprb_u {
824 u64 reg_value;
825 struct {
826 u64 rsvd1: 15,
827 error: 1, /* Widget rcvd wr resp pkt w/ error */
828 ovflow: 5, /* Over flow count. perf measurement */
829 fire_and_forget: 1, /* Launch Write without response */
830 mode: 2, /* Widget operation Mode */
831 rsvd2: 2,
832 bnakctr: 14,
833 rsvd3: 2,
834 anakctr: 14,
835 xtalkctr: 8;
836 } iprb_fields_s;
837} iprb_t;
838
839#define iprb_regval reg_value
840
841#define iprb_error iprb_fields_s.error
842#define iprb_ovflow iprb_fields_s.ovflow
843#define iprb_ff iprb_fields_s.fire_and_forget
844#define iprb_mode iprb_fields_s.mode
845#define iprb_bnakctr iprb_fields_s.bnakctr
846#define iprb_anakctr iprb_fields_s.anakctr
847#define iprb_xtalkctr iprb_fields_s.xtalkctr
848
849#endif /* !__ASSEMBLY__ */
850
851/*
852 * values for mode field in iprb_t.
853 * For details of the meanings of NAK and Accept, refer the PIO flow
854 * document
855 */
856#define IPRB_MODE_NORMAL (0)
857#define IPRB_MODE_COLLECT_A (1) /* PRB in collect A mode */
858#define IPRB_MODE_SERVICE_A (2) /* NAK B and Accept A */
859#define IPRB_MODE_SERVICE_B (3) /* NAK A and Accept B */
860
861/*
862 * IO CRB entry C_A to E_A : Partial (cache) CRBS
863 */
864#ifndef __ASSEMBLY__
865typedef union icrbp_a {
866 u64 ip_reg; /* the entire register value */
867 struct {
868 u64 error: 1, /* 63, error occurred */
869 ln_uce: 1, /* 62: uncorrectable memory */
870 ln_ae: 1, /* 61: protection violation */
871 ln_werr:1, /* 60: write access error */
872 ln_aerr:1, /* 59: sn0net: Address error */
873 ln_perr:1, /* 58: sn0net: poison error */
874 timeout:1, /* 57: CRB timed out */
875 l_bdpkt:1, /* 56: truncated pkt on sn0net */
876 c_bdpkt:1, /* 55: truncated pkt on xtalk */
877 c_err: 1, /* 54: incoming xtalk req, err set*/
878 rsvd1: 12, /* 53-42: reserved */
879 valid: 1, /* 41: Valid status */
880 sidn: 4, /* 40-37: SIDN field of xtalk rqst */
881 tnum: 5, /* 36-32: TNUM of xtalk request */
882 bo: 1, /* 31: barrier op set in xtalk rqst*/
883 resprqd:1, /* 30: xtalk rqst requires response*/
884 gbr: 1, /* 29: gbr bit set in xtalk rqst */
885 size: 2, /* 28-27: size of xtalk request */
886 excl: 4, /* 26-23: exclusive bit(s) */
887 stall: 3, /* 22-20: stall (xtalk, bte 0/1) */
888 intvn: 1, /* 19: rqst target of intervention*/
889 resp: 1, /* 18: Data response given to t5 */
890 ack: 1, /* 17: Data ack received. */
891 hold: 1, /* 16: crb gathering invalidate acks*/
892 wb: 1, /* 15: writeback pending. */
893 ack_cnt:11, /* 14-04: counter of invalidate acks*/
894 tscaler:4; /* 03-00: Timeout prescaler */
895 } ip_fmt;
896} icrbp_a_t;
897
898#endif /* !__ASSEMBLY__ */
899
900/*
901 * A couple of defines to go with the above structure.
902 */
903#define ICRBP_A_CERR_SHFT 54
904#define ICRBP_A_ERR_MASK 0x3ff
905
906#ifndef __ASSEMBLY__
907typedef union hubii_idsr {
908 u64 iin_reg;
909 struct {
910 u64 rsvd1 : 35,
911 isent : 1,
912 rsvd2 : 3,
913 ienable: 1,
914 rsvd : 7,
915 node : 9,
916 rsvd4 : 1,
917 level : 7;
918 } iin_fmt;
919} hubii_idsr_t;
920#endif /* !__ASSEMBLY__ */
921
922/*
923 * IO BTE Length/Status (IIO_IBLS) register bit field definitions
924 */
925#define IBLS_BUSY (0x1 << 20)
926#define IBLS_ERROR_SHFT 16
927#define IBLS_ERROR (0x1 << IBLS_ERROR_SHFT)
928#define IBLS_LENGTH_MASK 0xffff
929
930/*
931 * IO BTE Control/Terminate register (IBCT) register bit field definitions
932 */
933#define IBCT_POISON (0x1 << 8)
934#define IBCT_NOTIFY (0x1 << 4)
935#define IBCT_ZFIL_MODE (0x1 << 0)
936
937/*
938 * IO BTE Interrupt Address Register (IBIA) register bit field definitions
939 */
940#define IBIA_LEVEL_SHFT 16
941#define IBIA_LEVEL_MASK (0x7f << IBIA_LEVEL_SHFT)
942#define IBIA_NODE_ID_SHFT 0
943#define IBIA_NODE_ID_MASK (0x1ff)
944
945/*
946 * Miscellaneous hub constants
947 */
948
949/* Number of widgets supported by hub */
950#define HUB_NUM_WIDGET 9
951#define HUB_WIDGET_ID_MIN 0x8
952#define HUB_WIDGET_ID_MAX 0xf
953
954#define HUB_WIDGET_PART_NUM 0xc101
955#define MAX_HUBS_PER_XBOW 2
956
957/*
958 * Get a hub's widget id from widget control register
959 */
960#define IIO_WCR_WID_GET(nasid) (REMOTE_HUB_L(nasid, III_WCR) & 0xf)
961#define IIO_WST_ERROR_MASK (UINT64_CAST 1 << 32) /* Widget status error */
962
963/*
964 * Number of credits Hub widget has while sending req/response to
965 * xbow.
966 * Value of 3 is required by Xbow 1.1
967 * We may be able to increase this to 4 with Xbow 1.2.
968 */
969#define HUBII_XBOW_CREDIT 3
970#define HUBII_XBOW_REV2_CREDIT 4
971
972#endif /* _ASM_SGI_SN_SN0_HUBIO_H */
diff --git a/arch/mips/include/asm/sn/sn0/hubmd.h b/arch/mips/include/asm/sn/sn0/hubmd.h
new file mode 100644
index 000000000000..14c225d80664
--- /dev/null
+++ b/arch/mips/include/asm/sn/sn0/hubmd.h
@@ -0,0 +1,789 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Derived from IRIX <sys/SN/SN0/hubmd.h>, revision 1.59.
7 *
8 * Copyright (C) 1992 - 1997, 1999 Silicon Graphics, Inc.
9 * Copyright (C) 1999 by Ralf Baechle
10 */
11#ifndef _ASM_SN_SN0_HUBMD_H
12#define _ASM_SN_SN0_HUBMD_H
13
14
15/*
16 * Hub Memory/Directory interface registers
17 */
18#define CACHE_SLINE_SIZE 128 /* Secondary cache line size on SN0 */
19
20#define MAX_REGIONS 64
21
22/* Hardware page size and shift */
23
24#define MD_PAGE_SIZE 4096 /* Page size in bytes */
25#define MD_PAGE_NUM_SHFT 12 /* Address to page number shift */
26
27/* Register offsets from LOCAL_HUB or REMOTE_HUB */
28
29#define MD_BASE 0x200000
30#define MD_BASE_PERF 0x210000
31#define MD_BASE_JUNK 0x220000
32
33#define MD_IO_PROTECT 0x200000 /* MD and core register protection */
34#define MD_IO_PROT_OVRRD 0x200008 /* Clear my bit in MD_IO_PROTECT */
35#define MD_HSPEC_PROTECT 0x200010 /* BDDIR, LBOOT, RBOOT protection */
36#define MD_MEMORY_CONFIG 0x200018 /* Memory/Directory DIMM control */
37#define MD_REFRESH_CONTROL 0x200020 /* Memory/Directory refresh ctrl */
38#define MD_FANDOP_CAC_STAT 0x200028 /* Fetch-and-op cache status */
39#define MD_MIG_DIFF_THRESH 0x200030 /* Page migr. count diff thresh. */
40#define MD_MIG_VALUE_THRESH 0x200038 /* Page migr. count abs. thresh. */
41#define MD_MIG_CANDIDATE 0x200040 /* Latest page migration candidate */
42#define MD_MIG_CANDIDATE_CLR 0x200048 /* Clear page migration candidate */
43#define MD_DIR_ERROR 0x200050 /* Directory DIMM error */
44#define MD_DIR_ERROR_CLR 0x200058 /* Directory DIMM error clear */
45#define MD_PROTOCOL_ERROR 0x200060 /* Directory protocol error */
46#define MD_PROTOCOL_ERROR_CLR 0x200068 /* Directory protocol error clear */
47#define MD_MEM_ERROR 0x200070 /* Memory DIMM error */
48#define MD_MEM_ERROR_CLR 0x200078 /* Memory DIMM error clear */
49#define MD_MISC_ERROR 0x200080 /* Miscellaneous MD error */
50#define MD_MISC_ERROR_CLR 0x200088 /* Miscellaneous MD error clear */
51#define MD_MEM_DIMM_INIT 0x200090 /* Memory DIMM mode initization. */
52#define MD_DIR_DIMM_INIT 0x200098 /* Directory DIMM mode init. */
53#define MD_MOQ_SIZE 0x2000a0 /* MD outgoing queue size */
54#define MD_MLAN_CTL 0x2000a8 /* NIC (Microlan) control register */
55
56#define MD_PERF_SEL 0x210000 /* Select perf monitor events */
57#define MD_PERF_CNT0 0x210010 /* Performance counter 0 */
58#define MD_PERF_CNT1 0x210018 /* Performance counter 1 */
59#define MD_PERF_CNT2 0x210020 /* Performance counter 2 */
60#define MD_PERF_CNT3 0x210028 /* Performance counter 3 */
61#define MD_PERF_CNT4 0x210030 /* Performance counter 4 */
62#define MD_PERF_CNT5 0x210038 /* Performance counter 5 */
63
64#define MD_UREG0_0 0x220000 /* uController/UART 0 register */
65#define MD_UREG0_1 0x220008 /* uController/UART 0 register */
66#define MD_UREG0_2 0x220010 /* uController/UART 0 register */
67#define MD_UREG0_3 0x220018 /* uController/UART 0 register */
68#define MD_UREG0_4 0x220020 /* uController/UART 0 register */
69#define MD_UREG0_5 0x220028 /* uController/UART 0 register */
70#define MD_UREG0_6 0x220030 /* uController/UART 0 register */
71#define MD_UREG0_7 0x220038 /* uController/UART 0 register */
72
73#define MD_SLOTID_USTAT 0x220048 /* Hub slot ID & UART/uCtlr status */
74#define MD_LED0 0x220050 /* Eight-bit LED for CPU A */
75#define MD_LED1 0x220058 /* Eight-bit LED for CPU B */
76
77#define MD_UREG1_0 0x220080 /* uController/UART 1 register */
78#define MD_UREG1_1 0x220088 /* uController/UART 1 register */
79#define MD_UREG1_2 0x220090 /* uController/UART 1 register */
80#define MD_UREG1_3 0x220098 /* uController/UART 1 register */
81#define MD_UREG1_4 0x2200a0 /* uController/UART 1 register */
82#define MD_UREG1_5 0x2200a8 /* uController/UART 1 register */
83#define MD_UREG1_6 0x2200b0 /* uController/UART 1 register */
84#define MD_UREG1_7 0x2200b8 /* uController/UART 1 register */
85#define MD_UREG1_8 0x2200c0 /* uController/UART 1 register */
86#define MD_UREG1_9 0x2200c8 /* uController/UART 1 register */
87#define MD_UREG1_10 0x2200d0 /* uController/UART 1 register */
88#define MD_UREG1_11 0x2200d8 /* uController/UART 1 register */
89#define MD_UREG1_12 0x2200e0 /* uController/UART 1 register */
90#define MD_UREG1_13 0x2200e8 /* uController/UART 1 register */
91#define MD_UREG1_14 0x2200f0 /* uController/UART 1 register */
92#define MD_UREG1_15 0x2200f8 /* uController/UART 1 register */
93
94#ifdef CONFIG_SGI_SN_N_MODE
95#define MD_MEM_BANKS 4 /* 4 banks of memory max in N mode */
96#else
97#define MD_MEM_BANKS 8 /* 8 banks of memory max in M mode */
98#endif
99
100/*
101 * MD_MEMORY_CONFIG fields
102 *
103 * MD_SIZE_xxx are useful for representing the size of a SIMM or bank
104 * (SIMM pair). They correspond to the values needed for the bit
105 * triplets (MMC_BANK_MASK) in the MD_MEMORY_CONFIG register for bank size.
106 * Bits not used by the MD are used by software.
107 */
108
109#define MD_SIZE_EMPTY 0 /* Valid in MEMORY_CONFIG */
110#define MD_SIZE_8MB 1
111#define MD_SIZE_16MB 2
112#define MD_SIZE_32MB 3 /* Broken in Hub 1 */
113#define MD_SIZE_64MB 4 /* Valid in MEMORY_CONFIG */
114#define MD_SIZE_128MB 5 /* Valid in MEMORY_CONFIG */
115#define MD_SIZE_256MB 6
116#define MD_SIZE_512MB 7 /* Valid in MEMORY_CONFIG */
117#define MD_SIZE_1GB 8
118#define MD_SIZE_2GB 9
119#define MD_SIZE_4GB 10
120
121#define MD_SIZE_BYTES(size) ((size) == 0 ? 0 : 0x400000L << (size))
122#define MD_SIZE_MBYTES(size) ((size) == 0 ? 0 : 4 << (size))
123
124#define MMC_FPROM_CYC_SHFT 49 /* Have to use UINT64_CAST, instead */
125#define MMC_FPROM_CYC_MASK (UINT64_CAST 31 << 49) /* of 'L' suffix, */
126#define MMC_FPROM_WR_SHFT 44 /* for assembler */
127#define MMC_FPROM_WR_MASK (UINT64_CAST 31 << 44)
128#define MMC_UCTLR_CYC_SHFT 39
129#define MMC_UCTLR_CYC_MASK (UINT64_CAST 31 << 39)
130#define MMC_UCTLR_WR_SHFT 34
131#define MMC_UCTLR_WR_MASK (UINT64_CAST 31 << 34)
132#define MMC_DIMM0_SEL_SHFT 32
133#define MMC_DIMM0_SEL_MASK (UINT64_CAST 3 << 32)
134#define MMC_IO_PROT_EN_SHFT 31
135#define MMC_IO_PROT_EN_MASK (UINT64_CAST 1 << 31)
136#define MMC_IO_PROT (UINT64_CAST 1 << 31)
137#define MMC_ARB_MLSS_SHFT 30
138#define MMC_ARB_MLSS_MASK (UINT64_CAST 1 << 30)
139#define MMC_ARB_MLSS (UINT64_CAST 1 << 30)
140#define MMC_IGNORE_ECC_SHFT 29
141#define MMC_IGNORE_ECC_MASK (UINT64_CAST 1 << 29)
142#define MMC_IGNORE_ECC (UINT64_CAST 1 << 29)
143#define MMC_DIR_PREMIUM_SHFT 28
144#define MMC_DIR_PREMIUM_MASK (UINT64_CAST 1 << 28)
145#define MMC_DIR_PREMIUM (UINT64_CAST 1 << 28)
146#define MMC_REPLY_GUAR_SHFT 24
147#define MMC_REPLY_GUAR_MASK (UINT64_CAST 15 << 24)
148#define MMC_BANK_SHFT(_b) ((_b) * 3)
149#define MMC_BANK_MASK(_b) (UINT64_CAST 7 << MMC_BANK_SHFT(_b))
150#define MMC_BANK_ALL_MASK 0xffffff
151#define MMC_RESET_DEFAULTS (UINT64_CAST 0x0f << MMC_FPROM_CYC_SHFT | \
152 UINT64_CAST 0x07 << MMC_FPROM_WR_SHFT | \
153 UINT64_CAST 0x1f << MMC_UCTLR_CYC_SHFT | \
154 UINT64_CAST 0x0f << MMC_UCTLR_WR_SHFT | \
155 MMC_IGNORE_ECC | MMC_DIR_PREMIUM | \
156 UINT64_CAST 0x0f << MMC_REPLY_GUAR_SHFT | \
157 MMC_BANK_ALL_MASK)
158
159/* MD_REFRESH_CONTROL fields */
160
161#define MRC_ENABLE_SHFT 63
162#define MRC_ENABLE_MASK (UINT64_CAST 1 << 63)
163#define MRC_ENABLE (UINT64_CAST 1 << 63)
164#define MRC_COUNTER_SHFT 12
165#define MRC_COUNTER_MASK (UINT64_CAST 0xfff << 12)
166#define MRC_CNT_THRESH_MASK 0xfff
167#define MRC_RESET_DEFAULTS (UINT64_CAST 0x400)
168
169/* MD_MEM_DIMM_INIT and MD_DIR_DIMM_INIT fields */
170
171#define MDI_SELECT_SHFT 32
172#define MDI_SELECT_MASK (UINT64_CAST 0x0f << 32)
173#define MDI_DIMM_MODE_MASK (UINT64_CAST 0xfff)
174
175/* MD_MOQ_SIZE fields */
176
177#define MMS_RP_SIZE_SHFT 8
178#define MMS_RP_SIZE_MASK (UINT64_CAST 0x3f << 8)
179#define MMS_RQ_SIZE_SHFT 0
180#define MMS_RQ_SIZE_MASK (UINT64_CAST 0x1f)
181#define MMS_RESET_DEFAULTS (0x32 << 8 | 0x12)
182
183/* MD_FANDOP_CAC_STAT fields */
184
185#define MFC_VALID_SHFT 63
186#define MFC_VALID_MASK (UINT64_CAST 1 << 63)
187#define MFC_VALID (UINT64_CAST 1 << 63)
188#define MFC_ADDR_SHFT 6
189#define MFC_ADDR_MASK (UINT64_CAST 0x3ffffff)
190
191/* MD_MLAN_CTL fields */
192
193#define MLAN_PHI1_SHFT 27
194#define MLAN_PHI1_MASK (UINT64_CAST 0x7f << 27)
195#define MLAN_PHI0_SHFT 20
196#define MLAN_PHI0_MASK (UINT64_CAST 0x7f << 27)
197#define MLAN_PULSE_SHFT 10
198#define MLAN_PULSE_MASK (UINT64_CAST 0x3ff << 10)
199#define MLAN_SAMPLE_SHFT 2
200#define MLAN_SAMPLE_MASK (UINT64_CAST 0xff << 2)
201#define MLAN_DONE_SHFT 1
202#define MLAN_DONE_MASK 2
203#define MLAN_DONE (UINT64_CAST 0x02)
204#define MLAN_RD_DATA (UINT64_CAST 0x01)
205#define MLAN_RESET_DEFAULTS (UINT64_CAST 0x31 << MLAN_PHI1_SHFT | \
206 UINT64_CAST 0x31 << MLAN_PHI0_SHFT)
207
208/* MD_SLOTID_USTAT bit definitions */
209
210#define MSU_CORECLK_TST_SHFT 7 /* You don't wanna know */
211#define MSU_CORECLK_TST_MASK (UINT64_CAST 1 << 7)
212#define MSU_CORECLK_TST (UINT64_CAST 1 << 7)
213#define MSU_CORECLK_SHFT 6 /* You don't wanna know */
214#define MSU_CORECLK_MASK (UINT64_CAST 1 << 6)
215#define MSU_CORECLK (UINT64_CAST 1 << 6)
216#define MSU_NETSYNC_SHFT 5 /* You don't wanna know */
217#define MSU_NETSYNC_MASK (UINT64_CAST 1 << 5)
218#define MSU_NETSYNC (UINT64_CAST 1 << 5)
219#define MSU_FPROMRDY_SHFT 4 /* Flash PROM ready bit */
220#define MSU_FPROMRDY_MASK (UINT64_CAST 1 << 4)
221#define MSU_FPROMRDY (UINT64_CAST 1 << 4)
222#define MSU_I2CINTR_SHFT 3 /* I2C interrupt bit */
223#define MSU_I2CINTR_MASK (UINT64_CAST 1 << 3)
224#define MSU_I2CINTR (UINT64_CAST 1 << 3)
225#define MSU_SLOTID_MASK 0xff
226#define MSU_SN0_SLOTID_SHFT 0 /* Slot ID */
227#define MSU_SN0_SLOTID_MASK (UINT64_CAST 7)
228#define MSU_SN00_SLOTID_SHFT 7
229#define MSU_SN00_SLOTID_MASK (UINT64_CAST 0x80)
230
231#define MSU_PIMM_PSC_SHFT 4
232#define MSU_PIMM_PSC_MASK (0xf << MSU_PIMM_PSC_SHFT)
233
234/* MD_MIG_DIFF_THRESH bit definitions */
235
236#define MD_MIG_DIFF_THRES_VALID_MASK (UINT64_CAST 0x1 << 63)
237#define MD_MIG_DIFF_THRES_VALID_SHFT 63
238#define MD_MIG_DIFF_THRES_VALUE_MASK (UINT64_CAST 0xfffff)
239
240/* MD_MIG_VALUE_THRESH bit definitions */
241
242#define MD_MIG_VALUE_THRES_VALID_MASK (UINT64_CAST 0x1 << 63)
243#define MD_MIG_VALUE_THRES_VALID_SHFT 63
244#define MD_MIG_VALUE_THRES_VALUE_MASK (UINT64_CAST 0xfffff)
245
246/* MD_MIG_CANDIDATE bit definitions */
247
248#define MD_MIG_CANDIDATE_VALID_MASK (UINT64_CAST 0x1 << 63)
249#define MD_MIG_CANDIDATE_VALID_SHFT 63
250#define MD_MIG_CANDIDATE_TYPE_MASK (UINT64_CAST 0x1 << 30)
251#define MD_MIG_CANDIDATE_TYPE_SHFT 30
252#define MD_MIG_CANDIDATE_OVERRUN_MASK (UINT64_CAST 0x1 << 29)
253#define MD_MIG_CANDIDATE_OVERRUN_SHFT 29
254#define MD_MIG_CANDIDATE_INITIATOR_MASK (UINT64_CAST 0x7ff << 18)
255#define MD_MIG_CANDIDATE_INITIATOR_SHFT 18
256#define MD_MIG_CANDIDATE_NODEID_MASK (UINT64_CAST 0x1ff << 20)
257#define MD_MIG_CANDIDATE_NODEID_SHFT 20
258#define MD_MIG_CANDIDATE_ADDR_MASK (UINT64_CAST 0x3ffff)
259#define MD_MIG_CANDIDATE_ADDR_SHFT 14 /* The address starts at bit 14 */
260
261/* Other MD definitions */
262
263#define MD_BANK_SHFT 29 /* log2(512 MB) */
264#define MD_BANK_MASK (UINT64_CAST 7 << 29)
265#define MD_BANK_SIZE (UINT64_CAST 1 << MD_BANK_SHFT) /* 512 MB */
266#define MD_BANK_OFFSET(_b) (UINT64_CAST (_b) << MD_BANK_SHFT)
267
268/*
269 * The following definitions cover the bit field definitions for the
270 * various MD registers. For multi-bit registers, we define both
271 * a shift amount and a mask value. By convention, if you want to
272 * isolate a field, you should mask the field and then shift it down,
273 * since this makes the masks useful without a shift.
274 */
275
276/* Directory entry states for both premium and standard SIMMs. */
277
278#define MD_DIR_SHARED (UINT64_CAST 0x0) /* 000 */
279#define MD_DIR_POISONED (UINT64_CAST 0x1) /* 001 */
280#define MD_DIR_EXCLUSIVE (UINT64_CAST 0x2) /* 010 */
281#define MD_DIR_BUSY_SHARED (UINT64_CAST 0x3) /* 011 */
282#define MD_DIR_BUSY_EXCL (UINT64_CAST 0x4) /* 100 */
283#define MD_DIR_WAIT (UINT64_CAST 0x5) /* 101 */
284#define MD_DIR_UNOWNED (UINT64_CAST 0x7) /* 111 */
285
286/*
287 * The MD_DIR_FORCE_ECC bit can be added directory entry write data
288 * to forcing the ECC to be written as-is instead of recalculated.
289 */
290
291#define MD_DIR_FORCE_ECC (UINT64_CAST 1 << 63)
292
293/*
294 * Premium SIMM directory entry shifts and masks. Each is valid only in the
295 * context(s) indicated, where A, B, and C indicate the directory entry format
296 * as shown, and low and/or high indicates which double-word of the entry.
297 *
298 * Format A: STATE = shared, FINE = 1
299 * Format B: STATE = shared, FINE = 0
300 * Format C: STATE != shared (FINE must be 0)
301 */
302
303#define MD_PDIR_MASK 0xffffffffffff /* Whole entry */
304#define MD_PDIR_ECC_SHFT 0 /* ABC low or high */
305#define MD_PDIR_ECC_MASK 0x7f
306#define MD_PDIR_PRIO_SHFT 8 /* ABC low */
307#define MD_PDIR_PRIO_MASK (0xf << 8)
308#define MD_PDIR_AX_SHFT 7 /* ABC low */
309#define MD_PDIR_AX_MASK (1 << 7)
310#define MD_PDIR_AX (1 << 7)
311#define MD_PDIR_FINE_SHFT 12 /* ABC low */
312#define MD_PDIR_FINE_MASK (1 << 12)
313#define MD_PDIR_FINE (1 << 12)
314#define MD_PDIR_OCT_SHFT 13 /* A low */
315#define MD_PDIR_OCT_MASK (7 << 13)
316#define MD_PDIR_STATE_SHFT 13 /* BC low */
317#define MD_PDIR_STATE_MASK (7 << 13)
318#define MD_PDIR_ONECNT_SHFT 16 /* BC low */
319#define MD_PDIR_ONECNT_MASK (0x3f << 16)
320#define MD_PDIR_PTR_SHFT 22 /* C low */
321#define MD_PDIR_PTR_MASK (UINT64_CAST 0x7ff << 22)
322#define MD_PDIR_VECMSB_SHFT 22 /* AB low */
323#define MD_PDIR_VECMSB_BITMASK 0x3ffffff
324#define MD_PDIR_VECMSB_BITSHFT 27
325#define MD_PDIR_VECMSB_MASK (UINT64_CAST MD_PDIR_VECMSB_BITMASK << 22)
326#define MD_PDIR_CWOFF_SHFT 7 /* C high */
327#define MD_PDIR_CWOFF_MASK (7 << 7)
328#define MD_PDIR_VECLSB_SHFT 10 /* AB high */
329#define MD_PDIR_VECLSB_BITMASK (UINT64_CAST 0x3fffffffff)
330#define MD_PDIR_VECLSB_BITSHFT 0
331#define MD_PDIR_VECLSB_MASK (MD_PDIR_VECLSB_BITMASK << 10)
332
333/*
334 * Directory initialization values
335 */
336
337#define MD_PDIR_INIT_LO (MD_DIR_UNOWNED << MD_PDIR_STATE_SHFT | \
338 MD_PDIR_AX)
339#define MD_PDIR_INIT_HI 0
340#define MD_PDIR_INIT_PROT (MD_PROT_RW << MD_PPROT_IO_SHFT | \
341 MD_PROT_RW << MD_PPROT_SHFT)
342
343/*
344 * Standard SIMM directory entry shifts and masks. Each is valid only in the
345 * context(s) indicated, where A and C indicate the directory entry format
346 * as shown, and low and/or high indicates which double-word of the entry.
347 *
348 * Format A: STATE == shared
349 * Format C: STATE != shared
350 */
351
352#define MD_SDIR_MASK 0xffff /* Whole entry */
353#define MD_SDIR_ECC_SHFT 0 /* AC low or high */
354#define MD_SDIR_ECC_MASK 0x1f
355#define MD_SDIR_PRIO_SHFT 6 /* AC low */
356#define MD_SDIR_PRIO_MASK (1 << 6)
357#define MD_SDIR_AX_SHFT 5 /* AC low */
358#define MD_SDIR_AX_MASK (1 << 5)
359#define MD_SDIR_AX (1 << 5)
360#define MD_SDIR_STATE_SHFT 7 /* AC low */
361#define MD_SDIR_STATE_MASK (7 << 7)
362#define MD_SDIR_PTR_SHFT 10 /* C low */
363#define MD_SDIR_PTR_MASK (0x3f << 10)
364#define MD_SDIR_CWOFF_SHFT 5 /* C high */
365#define MD_SDIR_CWOFF_MASK (7 << 5)
366#define MD_SDIR_VECMSB_SHFT 11 /* A low */
367#define MD_SDIR_VECMSB_BITMASK 0x1f
368#define MD_SDIR_VECMSB_BITSHFT 7
369#define MD_SDIR_VECMSB_MASK (MD_SDIR_VECMSB_BITMASK << 11)
370#define MD_SDIR_VECLSB_SHFT 5 /* A high */
371#define MD_SDIR_VECLSB_BITMASK 0x7ff
372#define MD_SDIR_VECLSB_BITSHFT 0
373#define MD_SDIR_VECLSB_MASK (MD_SDIR_VECLSB_BITMASK << 5)
374
375/*
376 * Directory initialization values
377 */
378
379#define MD_SDIR_INIT_LO (MD_DIR_UNOWNED << MD_SDIR_STATE_SHFT | \
380 MD_SDIR_AX)
381#define MD_SDIR_INIT_HI 0
382#define MD_SDIR_INIT_PROT (MD_PROT_RW << MD_SPROT_SHFT)
383
384/* Protection and migration field values */
385
386#define MD_PROT_RW (UINT64_CAST 0x6)
387#define MD_PROT_RO (UINT64_CAST 0x3)
388#define MD_PROT_NO (UINT64_CAST 0x0)
389#define MD_PROT_BAD (UINT64_CAST 0x5)
390
391/* Premium SIMM protection entry shifts and masks. */
392
393#define MD_PPROT_SHFT 0 /* Prot. field */
394#define MD_PPROT_MASK 7
395#define MD_PPROT_MIGMD_SHFT 3 /* Migration mode */
396#define MD_PPROT_MIGMD_MASK (3 << 3)
397#define MD_PPROT_REFCNT_SHFT 5 /* Reference count */
398#define MD_PPROT_REFCNT_WIDTH 0x7ffff
399#define MD_PPROT_REFCNT_MASK (MD_PPROT_REFCNT_WIDTH << 5)
400
401#define MD_PPROT_IO_SHFT 45 /* I/O Prot field */
402#define MD_PPROT_IO_MASK (UINT64_CAST 7 << 45)
403
404/* Standard SIMM protection entry shifts and masks. */
405
406#define MD_SPROT_SHFT 0 /* Prot. field */
407#define MD_SPROT_MASK 7
408#define MD_SPROT_MIGMD_SHFT 3 /* Migration mode */
409#define MD_SPROT_MIGMD_MASK (3 << 3)
410#define MD_SPROT_REFCNT_SHFT 5 /* Reference count */
411#define MD_SPROT_REFCNT_WIDTH 0x7ff
412#define MD_SPROT_REFCNT_MASK (MD_SPROT_REFCNT_WIDTH << 5)
413
414/* Migration modes used in protection entries */
415
416#define MD_PROT_MIGMD_IREL (UINT64_CAST 0x3 << 3)
417#define MD_PROT_MIGMD_IABS (UINT64_CAST 0x2 << 3)
418#define MD_PROT_MIGMD_PREL (UINT64_CAST 0x1 << 3)
419#define MD_PROT_MIGMD_OFF (UINT64_CAST 0x0 << 3)
420
421
422/*
423 * Operations on page migration threshold register
424 */
425
426#ifndef __ASSEMBLY__
427
428/*
429 * LED register macros
430 */
431
432#define CPU_LED_ADDR(_nasid, _slice) \
433 (private.p_sn00 ? \
434 REMOTE_HUB_ADDR((_nasid), MD_UREG1_0 + ((_slice) << 5)) : \
435 REMOTE_HUB_ADDR((_nasid), MD_LED0 + ((_slice) << 3)))
436
437#define SET_CPU_LEDS(_nasid, _slice, _val) \
438 (HUB_S(CPU_LED_ADDR(_nasid, _slice), (_val)))
439
440#define SET_MY_LEDS(_v) \
441 SET_CPU_LEDS(get_nasid(), get_slice(), (_v))
442
443/*
444 * Operations on Memory/Directory DIMM control register
445 */
446
447#define DIRTYPE_PREMIUM 1
448#define DIRTYPE_STANDARD 0
449#define MD_MEMORY_CONFIG_DIR_TYPE_GET(region) (\
450 (REMOTE_HUB_L(region, MD_MEMORY_CONFIG) & MMC_DIR_PREMIUM_MASK) >> \
451 MMC_DIR_PREMIUM_SHFT)
452
453
454/*
455 * Operations on page migration count difference and absolute threshold
456 * registers
457 */
458
459#define MD_MIG_DIFF_THRESH_GET(region) ( \
460 REMOTE_HUB_L((region), MD_MIG_DIFF_THRESH) & \
461 MD_MIG_DIFF_THRES_VALUE_MASK)
462
463#define MD_MIG_DIFF_THRESH_SET(region, value) ( \
464 REMOTE_HUB_S((region), MD_MIG_DIFF_THRESH, \
465 MD_MIG_DIFF_THRES_VALID_MASK | (value)))
466
467#define MD_MIG_DIFF_THRESH_DISABLE(region) ( \
468 REMOTE_HUB_S((region), MD_MIG_DIFF_THRESH, \
469 REMOTE_HUB_L((region), MD_MIG_DIFF_THRESH) \
470 & ~MD_MIG_DIFF_THRES_VALID_MASK))
471
472#define MD_MIG_DIFF_THRESH_ENABLE(region) ( \
473 REMOTE_HUB_S((region), MD_MIG_DIFF_THRESH, \
474 REMOTE_HUB_L((region), MD_MIG_DIFF_THRESH) \
475 | MD_MIG_DIFF_THRES_VALID_MASK))
476
477#define MD_MIG_DIFF_THRESH_IS_ENABLED(region) ( \
478 REMOTE_HUB_L((region), MD_MIG_DIFF_THRESH) & \
479 MD_MIG_DIFF_THRES_VALID_MASK)
480
481#define MD_MIG_VALUE_THRESH_GET(region) ( \
482 REMOTE_HUB_L((region), MD_MIG_VALUE_THRESH) & \
483 MD_MIG_VALUE_THRES_VALUE_MASK)
484
485#define MD_MIG_VALUE_THRESH_SET(region, value) ( \
486 REMOTE_HUB_S((region), MD_MIG_VALUE_THRESH, \
487 MD_MIG_VALUE_THRES_VALID_MASK | (value)))
488
489#define MD_MIG_VALUE_THRESH_DISABLE(region) ( \
490 REMOTE_HUB_S((region), MD_MIG_VALUE_THRESH, \
491 REMOTE_HUB_L(region, MD_MIG_VALUE_THRESH) \
492 & ~MD_MIG_VALUE_THRES_VALID_MASK))
493
494#define MD_MIG_VALUE_THRESH_ENABLE(region) ( \
495 REMOTE_HUB_S((region), MD_MIG_VALUE_THRESH, \
496 REMOTE_HUB_L((region), MD_MIG_VALUE_THRESH) \
497 | MD_MIG_VALUE_THRES_VALID_MASK))
498
499#define MD_MIG_VALUE_THRESH_IS_ENABLED(region) ( \
500 REMOTE_HUB_L((region), MD_MIG_VALUE_THRESH) & \
501 MD_MIG_VALUE_THRES_VALID_MASK)
502
503/*
504 * Operations on page migration candidate register
505 */
506
507#define MD_MIG_CANDIDATE_GET(my_region_id) ( \
508 REMOTE_HUB_L((my_region_id), MD_MIG_CANDIDATE_CLR))
509
510#define MD_MIG_CANDIDATE_HWPFN(value) ((value) & MD_MIG_CANDIDATE_ADDR_MASK)
511
512#define MD_MIG_CANDIDATE_NODEID(value) ( \
513 ((value) & MD_MIG_CANDIDATE_NODEID_MASK) >> MD_MIG_CANDIDATE_NODEID_SHFT)
514
515#define MD_MIG_CANDIDATE_TYPE(value) ( \
516 ((value) & MD_MIG_CANDIDATE_TYPE_MASK) >> MD_MIG_CANDIDATE_TYPE_SHFT)
517
518#define MD_MIG_CANDIDATE_VALID(value) ( \
519 ((value) & MD_MIG_CANDIDATE_VALID_MASK) >> MD_MIG_CANDIDATE_VALID_SHFT)
520
521/*
522 * Macros to retrieve fields in the protection entry
523 */
524
525/* for Premium SIMM */
526#define MD_PPROT_REFCNT_GET(value) ( \
527 ((value) & MD_PPROT_REFCNT_MASK) >> MD_PPROT_REFCNT_SHFT)
528
529#define MD_PPROT_MIGMD_GET(value) ( \
530 ((value) & MD_PPROT_MIGMD_MASK) >> MD_PPROT_MIGMD_SHFT)
531
532/* for Standard SIMM */
533#define MD_SPROT_REFCNT_GET(value) ( \
534 ((value) & MD_SPROT_REFCNT_MASK) >> MD_SPROT_REFCNT_SHFT)
535
536#define MD_SPROT_MIGMD_GET(value) ( \
537 ((value) & MD_SPROT_MIGMD_MASK) >> MD_SPROT_MIGMD_SHFT)
538
539/*
540 * Format of dir_error, mem_error, protocol_error and misc_error registers
541 */
542
543struct dir_error_reg {
544 u64 uce_vld: 1, /* 63: valid directory uce */
545 ae_vld: 1, /* 62: valid dir prot ecc error */
546 ce_vld: 1, /* 61: valid correctable ECC err*/
547 rsvd1: 19, /* 60-42: reserved */
548 bad_prot: 3, /* 41-39: encoding, bad access rights*/
549 bad_syn: 7, /* 38-32: bad dir syndrome */
550 rsvd2: 2, /* 31-30: reserved */
551 hspec_addr:27, /* 29-03: bddir space bad entry */
552 uce_ovr: 1, /* 2: multiple dir uce's */
553 ae_ovr: 1, /* 1: multiple prot ecc errs*/
554 ce_ovr: 1; /* 0: multiple correctable errs */
555};
556
557typedef union md_dir_error {
558 u64 derr_reg; /* the entire register */
559 struct dir_error_reg derr_fmt; /* the register format */
560} md_dir_error_t;
561
562
563struct mem_error_reg {
564 u64 uce_vld: 1, /* 63: valid memory uce */
565 ce_vld: 1, /* 62: valid correctable ECC err*/
566 rsvd1: 22, /* 61-40: reserved */
567 bad_syn: 8, /* 39-32: bad mem ecc syndrome */
568 address: 29, /* 31-03: bad entry pointer */
569 rsvd2: 1, /* 2: reserved */
570 uce_ovr: 1, /* 1: multiple mem uce's */
571 ce_ovr: 1; /* 0: multiple correctable errs */
572};
573
574
575typedef union md_mem_error {
576 u64 merr_reg; /* the entire register */
577 struct mem_error_reg merr_fmt; /* format of the mem_error reg */
578} md_mem_error_t;
579
580
581struct proto_error_reg {
582 u64 valid: 1, /* 63: valid protocol error */
583 rsvd1: 2, /* 62-61: reserved */
584 initiator:11, /* 60-50: id of request initiator*/
585 backoff: 2, /* 49-48: backoff control */
586 msg_type: 8, /* 47-40: type of request */
587 access: 2, /* 39-38: access rights of initiator*/
588 priority: 1, /* 37: priority level of requestor*/
589 dir_state: 4, /* 36-33: state of directory */
590 pointer_me:1, /* 32: initiator same as dir ptr */
591 address: 29, /* 31-03: request address */
592 rsvd2: 2, /* 02-01: reserved */
593 overrun: 1; /* 0: multiple protocol errs */
594};
595
596typedef union md_proto_error {
597 u64 perr_reg; /* the entire register */
598 struct proto_error_reg perr_fmt; /* format of the register */
599} md_proto_error_t;
600
601
602struct md_sdir_high_fmt {
603 unsigned short sd_hi_bvec : 11,
604 sd_hi_ecc : 5;
605};
606
607
608typedef union md_sdir_high {
609 /* The 16 bits of standard directory, upper word */
610 unsigned short sd_hi_val;
611 struct md_sdir_high_fmt sd_hi_fmt;
612}md_sdir_high_t;
613
614
615struct md_sdir_low_shared_fmt {
616 /* The meaning of lower directory, shared */
617 unsigned short sds_lo_bvec : 5,
618 sds_lo_unused: 1,
619 sds_lo_state : 3,
620 sds_lo_prio : 1,
621 sds_lo_ax : 1,
622 sds_lo_ecc : 5;
623};
624
625struct md_sdir_low_exclusive_fmt {
626 /* The meaning of lower directory, exclusive */
627 unsigned short sde_lo_ptr : 6,
628 sde_lo_state : 3,
629 sde_lo_prio : 1,
630 sde_lo_ax : 1,
631 sde_lo_ecc : 5;
632};
633
634
635typedef union md_sdir_low {
636 /* The 16 bits of standard directory, lower word */
637 unsigned short sd_lo_val;
638 struct md_sdir_low_exclusive_fmt sde_lo_fmt;
639 struct md_sdir_low_shared_fmt sds_lo_fmt;
640}md_sdir_low_t;
641
642
643
644struct md_pdir_high_fmt {
645 u64 pd_hi_unused : 16,
646 pd_hi_bvec : 38,
647 pd_hi_unused1 : 3,
648 pd_hi_ecc : 7;
649};
650
651
652typedef union md_pdir_high {
653 /* The 48 bits of standard directory, upper word */
654 u64 pd_hi_val;
655 struct md_pdir_high_fmt pd_hi_fmt;
656}md_pdir_high_t;
657
658
659struct md_pdir_low_shared_fmt {
660 /* The meaning of lower directory, shared */
661 u64 pds_lo_unused : 16,
662 pds_lo_bvec : 26,
663 pds_lo_cnt : 6,
664 pds_lo_state : 3,
665 pds_lo_ste : 1,
666 pds_lo_prio : 4,
667 pds_lo_ax : 1,
668 pds_lo_ecc : 7;
669};
670
671struct md_pdir_low_exclusive_fmt {
672 /* The meaning of lower directory, exclusive */
673 u64 pde_lo_unused : 31,
674 pde_lo_ptr : 11,
675 pde_lo_unused1 : 6,
676 pde_lo_state : 3,
677 pde_lo_ste : 1,
678 pde_lo_prio : 4,
679 pde_lo_ax : 1,
680 pde_lo_ecc : 7;
681};
682
683
684typedef union md_pdir_loent {
685 /* The 48 bits of premium directory, lower word */
686 u64 pd_lo_val;
687 struct md_pdir_low_exclusive_fmt pde_lo_fmt;
688 struct md_pdir_low_shared_fmt pds_lo_fmt;
689}md_pdir_low_t;
690
691
692/*
693 * the following two "union" definitions and two
694 * "struct" definitions are used in vmdump.c to
695 * represent directory memory information.
696 */
697
698typedef union md_dir_high {
699 md_sdir_high_t md_sdir_high;
700 md_pdir_high_t md_pdir_high;
701} md_dir_high_t;
702
703typedef union md_dir_low {
704 md_sdir_low_t md_sdir_low;
705 md_pdir_low_t md_pdir_low;
706} md_dir_low_t;
707
708typedef struct bddir_entry {
709 md_dir_low_t md_dir_low;
710 md_dir_high_t md_dir_high;
711} bddir_entry_t;
712
713typedef struct dir_mem_entry {
714 u64 prcpf[MAX_REGIONS];
715 bddir_entry_t directory_words[MD_PAGE_SIZE/CACHE_SLINE_SIZE];
716} dir_mem_entry_t;
717
718
719
720typedef union md_perf_sel {
721 u64 perf_sel_reg;
722 struct {
723 u64 perf_rsvd : 60,
724 perf_en : 1,
725 perf_sel : 3;
726 } perf_sel_bits;
727} md_perf_sel_t;
728
729typedef union md_perf_cnt {
730 u64 perf_cnt;
731 struct {
732 u64 perf_rsvd : 44,
733 perf_cnt : 20;
734 } perf_cnt_bits;
735} md_perf_cnt_t;
736
737
738#endif /* !__ASSEMBLY__ */
739
740
741#define DIR_ERROR_VALID_MASK 0xe000000000000000
742#define DIR_ERROR_VALID_SHFT 61
743#define DIR_ERROR_VALID_UCE 0x8000000000000000
744#define DIR_ERROR_VALID_AE 0x4000000000000000
745#define DIR_ERROR_VALID_CE 0x2000000000000000
746
747#define MEM_ERROR_VALID_MASK 0xc000000000000000
748#define MEM_ERROR_VALID_SHFT 62
749#define MEM_ERROR_VALID_UCE 0x8000000000000000
750#define MEM_ERROR_VALID_CE 0x4000000000000000
751
752#define PROTO_ERROR_VALID_MASK 0x8000000000000000
753
754#define MISC_ERROR_VALID_MASK 0x3ff
755
756/*
757 * Mask for hspec address that is stored in the dir error register.
758 * This represents bits 29 through 3.
759 */
760#define DIR_ERR_HSPEC_MASK 0x3ffffff8
761#define ERROR_HSPEC_MASK 0x3ffffff8
762#define ERROR_HSPEC_SHFT 3
763#define ERROR_ADDR_MASK 0xfffffff8
764#define ERROR_ADDR_SHFT 3
765
766/*
767 * MD_MISC_ERROR register defines.
768 */
769
770#define MMCE_VALID_MASK 0x3ff
771#define MMCE_ILL_MSG_SHFT 8
772#define MMCE_ILL_MSG_MASK (UINT64_CAST 0x03 << MMCE_ILL_MSG_SHFT)
773#define MMCE_ILL_REV_SHFT 6
774#define MMCE_ILL_REV_MASK (UINT64_CAST 0x03 << MMCE_ILL_REV_SHFT)
775#define MMCE_LONG_PACK_SHFT 4
776#define MMCE_LONG_PACK_MASK (UINT64_CAST 0x03 << MMCE_lONG_PACK_SHFT)
777#define MMCE_SHORT_PACK_SHFT 2
778#define MMCE_SHORT_PACK_MASK (UINT64_CAST 0x03 << MMCE_SHORT_PACK_SHFT)
779#define MMCE_BAD_DATA_SHFT 0
780#define MMCE_BAD_DATA_MASK (UINT64_CAST 0x03 << MMCE_BAD_DATA_SHFT)
781
782
783#define MD_PERF_COUNTERS 6
784#define MD_PERF_SETS 6
785
786#define MEM_DIMM_MASK 0xe0000000
787#define MEM_DIMM_SHFT 29
788
789#endif /* _ASM_SN_SN0_HUBMD_H */
diff --git a/arch/mips/include/asm/sn/sn0/hubni.h b/arch/mips/include/asm/sn/sn0/hubni.h
new file mode 100644
index 000000000000..b40d3ef97a12
--- /dev/null
+++ b/arch/mips/include/asm/sn/sn0/hubni.h
@@ -0,0 +1,255 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Derived from IRIX <sys/SN/SN0/hubni.h>, Revision 1.27.
7 *
8 * Copyright (C) 1992-1997, 1999 Silicon Graphics, Inc.
9 * Copyright (C) 1999 by Ralf Baechle
10 */
11#ifndef _ASM_SGI_SN0_HUBNI_H
12#define _ASM_SGI_SN0_HUBNI_H
13
14#ifndef __ASSEMBLY__
15#include <linux/types.h>
16#endif
17
18/*
19 * Hub Network Interface registers
20 *
21 * All registers in this file are subject to change until Hub chip tapeout.
22 */
23
24#define NI_BASE 0x600000
25#define NI_BASE_TABLES 0x630000
26
27#define NI_STATUS_REV_ID 0x600000 /* Hub network status, rev, and ID */
28#define NI_PORT_RESET 0x600008 /* Reset the network interface */
29#define NI_PROTECTION 0x600010 /* NI register access permissions */
30#define NI_GLOBAL_PARMS 0x600018 /* LLP parameters */
31#define NI_SCRATCH_REG0 0x600100 /* Scratch register 0 (64 bits) */
32#define NI_SCRATCH_REG1 0x600108 /* Scratch register 1 (64 bits) */
33#define NI_DIAG_PARMS 0x600110 /* Parameters for diags */
34
35#define NI_VECTOR_PARMS 0x600200 /* Vector PIO routing parameters */
36#define NI_VECTOR 0x600208 /* Vector PIO route */
37#define NI_VECTOR_DATA 0x600210 /* Vector PIO data */
38#define NI_VECTOR_STATUS 0x600300 /* Vector PIO return status */
39#define NI_RETURN_VECTOR 0x600308 /* Vector PIO return vector */
40#define NI_VECTOR_READ_DATA 0x600310 /* Vector PIO read data */
41#define NI_VECTOR_CLEAR 0x600380 /* Vector PIO read & clear status */
42
43#define NI_IO_PROTECT 0x600400 /* PIO protection bits */
44#define NI_IO_PROT_OVRRD 0x600408 /* PIO protection bit override */
45
46#define NI_AGE_CPU0_MEMORY 0x600500 /* CPU 0 memory age control */
47#define NI_AGE_CPU0_PIO 0x600508 /* CPU 0 PIO age control */
48#define NI_AGE_CPU1_MEMORY 0x600510 /* CPU 1 memory age control */
49#define NI_AGE_CPU1_PIO 0x600518 /* CPU 1 PIO age control */
50#define NI_AGE_GBR_MEMORY 0x600520 /* GBR memory age control */
51#define NI_AGE_GBR_PIO 0x600528 /* GBR PIO age control */
52#define NI_AGE_IO_MEMORY 0x600530 /* IO memory age control */
53#define NI_AGE_IO_PIO 0x600538 /* IO PIO age control */
54#define NI_AGE_REG_MIN NI_AGE_CPU0_MEMORY
55#define NI_AGE_REG_MAX NI_AGE_IO_PIO
56
57#define NI_PORT_PARMS 0x608000 /* LLP Parameters */
58#define NI_PORT_ERROR 0x608008 /* LLP Errors */
59#define NI_PORT_ERROR_CLEAR 0x608088 /* Clear the error bits */
60
61#define NI_META_TABLE0 0x638000 /* First meta routing table entry */
62#define NI_META_TABLE(_x) (NI_META_TABLE0 + (8 * (_x)))
63#define NI_META_ENTRIES 32
64
65#define NI_LOCAL_TABLE0 0x638100 /* First local routing table entry */
66#define NI_LOCAL_TABLE(_x) (NI_LOCAL_TABLE0 + (8 * (_x)))
67#define NI_LOCAL_ENTRIES 16
68
69/*
70 * NI_STATUS_REV_ID mask and shift definitions
71 * Have to use UINT64_CAST instead of 'L' suffix, for assembler.
72 */
73
74#define NSRI_8BITMODE_SHFT 30
75#define NSRI_8BITMODE_MASK (UINT64_CAST 0x1 << 30)
76#define NSRI_LINKUP_SHFT 29
77#define NSRI_LINKUP_MASK (UINT64_CAST 0x1 << 29)
78#define NSRI_DOWNREASON_SHFT 28 /* 0=failed, 1=never came */
79#define NSRI_DOWNREASON_MASK (UINT64_CAST 0x1 << 28) /* out of reset. */
80#define NSRI_MORENODES_SHFT 18
81#define NSRI_MORENODES_MASK (UINT64_CAST 1 << 18) /* Max. # of nodes */
82#define MORE_MEMORY 0
83#define MORE_NODES 1
84#define NSRI_REGIONSIZE_SHFT 17
85#define NSRI_REGIONSIZE_MASK (UINT64_CAST 1 << 17) /* Granularity */
86#define REGIONSIZE_FINE 1
87#define REGIONSIZE_COARSE 0
88#define NSRI_NODEID_SHFT 8
89#define NSRI_NODEID_MASK (UINT64_CAST 0x1ff << 8)/* Node (Hub) ID */
90#define NSRI_REV_SHFT 4
91#define NSRI_REV_MASK (UINT64_CAST 0xf << 4) /* Chip Revision */
92#define NSRI_CHIPID_SHFT 0
93#define NSRI_CHIPID_MASK (UINT64_CAST 0xf) /* Chip type ID */
94
95/*
96 * In fine mode, each node is a region. In coarse mode, there are
97 * eight nodes per region.
98 */
99#define NASID_TO_FINEREG_SHFT 0
100#define NASID_TO_COARSEREG_SHFT 3
101
102/* NI_PORT_RESET mask definitions */
103
104#define NPR_PORTRESET (UINT64_CAST 1 << 7) /* Send warm reset */
105#define NPR_LINKRESET (UINT64_CAST 1 << 1) /* Send link reset */
106#define NPR_LOCALRESET (UINT64_CAST 1) /* Reset entire hub */
107
108/* NI_PROTECTION mask and shift definitions */
109
110#define NPROT_RESETOK (UINT64_CAST 1)
111
112/* NI_GLOBAL_PARMS mask and shift definitions */
113
114#define NGP_MAXRETRY_SHFT 48 /* Maximum retries */
115#define NGP_MAXRETRY_MASK (UINT64_CAST 0x3ff << 48)
116#define NGP_TAILTOWRAP_SHFT 32 /* Tail timeout wrap */
117#define NGP_TAILTOWRAP_MASK (UINT64_CAST 0xffff << 32)
118
119#define NGP_CREDITTOVAL_SHFT 16 /* Tail timeout wrap */
120#define NGP_CREDITTOVAL_MASK (UINT64_CAST 0xf << 16)
121#define NGP_TAILTOVAL_SHFT 4 /* Tail timeout value */
122#define NGP_TAILTOVAL_MASK (UINT64_CAST 0xf << 4)
123
124/* NI_DIAG_PARMS mask and shift definitions */
125
126#define NDP_PORTTORESET (UINT64_CAST 1 << 18) /* Port tmout reset */
127#define NDP_LLP8BITMODE (UINT64_CAST 1 << 12) /* LLP 8-bit mode */
128#define NDP_PORTDISABLE (UINT64_CAST 1 << 6) /* Port disable */
129#define NDP_SENDERROR (UINT64_CAST 1) /* Send data error */
130
131/*
132 * NI_VECTOR_PARMS mask and shift definitions.
133 * TYPE may be any of the first four PIOTYPEs defined under NI_VECTOR_STATUS.
134 */
135
136#define NVP_PIOID_SHFT 40
137#define NVP_PIOID_MASK (UINT64_CAST 0x3ff << 40)
138#define NVP_WRITEID_SHFT 32
139#define NVP_WRITEID_MASK (UINT64_CAST 0xff << 32)
140#define NVP_ADDRESS_MASK (UINT64_CAST 0xffff8) /* Bits 19:3 */
141#define NVP_TYPE_SHFT 0
142#define NVP_TYPE_MASK (UINT64_CAST 0x3)
143
144/* NI_VECTOR_STATUS mask and shift definitions */
145
146#define NVS_VALID (UINT64_CAST 1 << 63)
147#define NVS_OVERRUN (UINT64_CAST 1 << 62)
148#define NVS_TARGET_SHFT 51
149#define NVS_TARGET_MASK (UINT64_CAST 0x3ff << 51)
150#define NVS_PIOID_SHFT 40
151#define NVS_PIOID_MASK (UINT64_CAST 0x3ff << 40)
152#define NVS_WRITEID_SHFT 32
153#define NVS_WRITEID_MASK (UINT64_CAST 0xff << 32)
154#define NVS_ADDRESS_MASK (UINT64_CAST 0xfffffff8) /* Bits 31:3 */
155#define NVS_TYPE_SHFT 0
156#define NVS_TYPE_MASK (UINT64_CAST 0x7)
157#define NVS_ERROR_MASK (UINT64_CAST 0x4) /* bit set means error */
158
159
160#define PIOTYPE_READ 0 /* VECTOR_PARMS and VECTOR_STATUS */
161#define PIOTYPE_WRITE 1 /* VECTOR_PARMS and VECTOR_STATUS */
162#define PIOTYPE_UNDEFINED 2 /* VECTOR_PARMS and VECTOR_STATUS */
163#define PIOTYPE_EXCHANGE 3 /* VECTOR_PARMS and VECTOR_STATUS */
164#define PIOTYPE_ADDR_ERR 4 /* VECTOR_STATUS only */
165#define PIOTYPE_CMD_ERR 5 /* VECTOR_STATUS only */
166#define PIOTYPE_PROT_ERR 6 /* VECTOR_STATUS only */
167#define PIOTYPE_UNKNOWN 7 /* VECTOR_STATUS only */
168
169/* NI_AGE_XXX mask and shift definitions */
170
171#define NAGE_VCH_SHFT 10
172#define NAGE_VCH_MASK (UINT64_CAST 3 << 10)
173#define NAGE_CC_SHFT 8
174#define NAGE_CC_MASK (UINT64_CAST 3 << 8)
175#define NAGE_AGE_SHFT 0
176#define NAGE_AGE_MASK (UINT64_CAST 0xff)
177#define NAGE_MASK (NAGE_VCH_MASK | NAGE_CC_MASK | NAGE_AGE_MASK)
178
179#define VCHANNEL_A 0
180#define VCHANNEL_B 1
181#define VCHANNEL_ANY 2
182
183/* NI_PORT_PARMS mask and shift definitions */
184
185#define NPP_NULLTO_SHFT 10
186#define NPP_NULLTO_MASK (UINT64_CAST 0x3f << 16)
187#define NPP_MAXBURST_SHFT 0
188#define NPP_MAXBURST_MASK (UINT64_CAST 0x3ff)
189#define NPP_RESET_DFLT_HUB20 ((UINT64_CAST 1 << NPP_NULLTO_SHFT) | \
190 (UINT64_CAST 0x3f0 << NPP_MAXBURST_SHFT))
191#define NPP_RESET_DEFAULTS ((UINT64_CAST 6 << NPP_NULLTO_SHFT) | \
192 (UINT64_CAST 0x3f0 << NPP_MAXBURST_SHFT))
193
194
195/* NI_PORT_ERROR mask and shift definitions */
196
197#define NPE_LINKRESET (UINT64_CAST 1 << 37)
198#define NPE_INTERNALERROR (UINT64_CAST 1 << 36)
199#define NPE_BADMESSAGE (UINT64_CAST 1 << 35)
200#define NPE_BADDEST (UINT64_CAST 1 << 34)
201#define NPE_FIFOOVERFLOW (UINT64_CAST 1 << 33)
202#define NPE_CREDITTO_SHFT 28
203#define NPE_CREDITTO_MASK (UINT64_CAST 0xf << 28)
204#define NPE_TAILTO_SHFT 24
205#define NPE_TAILTO_MASK (UINT64_CAST 0xf << 24)
206#define NPE_RETRYCOUNT_SHFT 16
207#define NPE_RETRYCOUNT_MASK (UINT64_CAST 0xff << 16)
208#define NPE_CBERRCOUNT_SHFT 8
209#define NPE_CBERRCOUNT_MASK (UINT64_CAST 0xff << 8)
210#define NPE_SNERRCOUNT_SHFT 0
211#define NPE_SNERRCOUNT_MASK (UINT64_CAST 0xff << 0)
212#define NPE_MASK 0x3effffffff
213
214#define NPE_COUNT_MAX 0xff
215
216#define NPE_FATAL_ERRORS (NPE_LINKRESET | NPE_INTERNALERROR | \
217 NPE_BADMESSAGE | NPE_BADDEST | \
218 NPE_FIFOOVERFLOW | NPE_CREDITTO_MASK | \
219 NPE_TAILTO_MASK)
220
221/* NI_META_TABLE mask and shift definitions */
222
223#define NMT_EXIT_PORT_MASK (UINT64_CAST 0xf)
224
225/* NI_LOCAL_TABLE mask and shift definitions */
226
227#define NLT_EXIT_PORT_MASK (UINT64_CAST 0xf)
228
229#ifndef __ASSEMBLY__
230
231typedef union hubni_port_error_u {
232 u64 nipe_reg_value;
233 struct {
234 u64 nipe_rsvd: 26, /* unused */
235 nipe_lnk_reset: 1, /* link reset */
236 nipe_intl_err: 1, /* internal error */
237 nipe_bad_msg: 1, /* bad message */
238 nipe_bad_dest: 1, /* bad dest */
239 nipe_fifo_ovfl: 1, /* fifo overflow */
240 nipe_rsvd1: 1, /* unused */
241 nipe_credit_to: 4, /* credit timeout */
242 nipe_tail_to: 4, /* tail timeout */
243 nipe_retry_cnt: 8, /* retry error count */
244 nipe_cb_cnt: 8, /* checkbit error count */
245 nipe_sn_cnt: 8; /* sequence number count */
246 } nipe_fields_s;
247} hubni_port_error_t;
248
249#define NI_LLP_RETRY_MAX 0xff
250#define NI_LLP_CB_MAX 0xff
251#define NI_LLP_SN_MAX 0xff
252
253#endif /* !__ASSEMBLY__ */
254
255#endif /* _ASM_SGI_SN0_HUBNI_H */
diff --git a/arch/mips/include/asm/sn/sn0/hubpi.h b/arch/mips/include/asm/sn/sn0/hubpi.h
new file mode 100644
index 000000000000..e39f5f9da040
--- /dev/null
+++ b/arch/mips/include/asm/sn/sn0/hubpi.h
@@ -0,0 +1,409 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Derived from IRIX <sys/SN/SN0/hubpi.h>, revision 1.28.
7 *
8 * Copyright (C) 1992 - 1997, 1999 Silicon Graphics, Inc.
9 * Copyright (C) 1999 by Ralf Baechle
10 */
11#ifndef _ASM_SN_SN0_HUBPI_H
12#define _ASM_SN_SN0_HUBPI_H
13
14#include <linux/types.h>
15
16/*
17 * Hub I/O interface registers
18 *
19 * All registers in this file are subject to change until Hub chip tapeout.
20 * All register "addresses" are actually offsets. Use the LOCAL_HUB
21 * or REMOTE_HUB macros to synthesize an actual address
22 */
23
24#define PI_BASE 0x000000
25
26/* General protection and control registers */
27
28#define PI_CPU_PROTECT 0x000000 /* CPU Protection */
29#define PI_PROT_OVERRD 0x000008 /* Clear CPU Protection bit */
30#define PI_IO_PROTECT 0x000010 /* Interrupt Pending Protection */
31#define PI_REGION_PRESENT 0x000018 /* Indicates whether region exists */
32#define PI_CPU_NUM 0x000020 /* CPU Number ID */
33#define PI_CALIAS_SIZE 0x000028 /* Cached Alias Size */
34#define PI_MAX_CRB_TIMEOUT 0x000030 /* Maximum Timeout for CRB */
35#define PI_CRB_SFACTOR 0x000038 /* Scale factor for CRB timeout */
36
37/* CALIAS values */
38#define PI_CALIAS_SIZE_0 0
39#define PI_CALIAS_SIZE_4K 1
40#define PI_CALIAS_SIZE_8K 2
41#define PI_CALIAS_SIZE_16K 3
42#define PI_CALIAS_SIZE_32K 4
43#define PI_CALIAS_SIZE_64K 5
44#define PI_CALIAS_SIZE_128K 6
45#define PI_CALIAS_SIZE_256K 7
46#define PI_CALIAS_SIZE_512K 8
47#define PI_CALIAS_SIZE_1M 9
48#define PI_CALIAS_SIZE_2M 10
49#define PI_CALIAS_SIZE_4M 11
50#define PI_CALIAS_SIZE_8M 12
51#define PI_CALIAS_SIZE_16M 13
52#define PI_CALIAS_SIZE_32M 14
53#define PI_CALIAS_SIZE_64M 15
54
55/* Processor control and status checking */
56
57#define PI_CPU_PRESENT_A 0x000040 /* CPU Present A */
58#define PI_CPU_PRESENT_B 0x000048 /* CPU Present B */
59#define PI_CPU_ENABLE_A 0x000050 /* CPU Enable A */
60#define PI_CPU_ENABLE_B 0x000058 /* CPU Enable B */
61#define PI_REPLY_LEVEL 0x000060 /* Reply Level */
62#define PI_HARDRESET_BIT 0x020068 /* Bit cleared by s/w on SR */
63#define PI_NMI_A 0x000070 /* NMI to CPU A */
64#define PI_NMI_B 0x000078 /* NMI to CPU B */
65#define PI_NMI_OFFSET (PI_NMI_B - PI_NMI_A)
66#define PI_SOFTRESET 0x000080 /* Softreset (to both CPUs) */
67
68/* Regular Interrupt register checking. */
69
70#define PI_INT_PEND_MOD 0x000090 /* Write to set pending ints */
71#define PI_INT_PEND0 0x000098 /* Read to get pending ints */
72#define PI_INT_PEND1 0x0000a0 /* Read to get pending ints */
73#define PI_INT_MASK0_A 0x0000a8 /* Interrupt Mask 0 for CPU A */
74#define PI_INT_MASK1_A 0x0000b0 /* Interrupt Mask 1 for CPU A */
75#define PI_INT_MASK0_B 0x0000b8 /* Interrupt Mask 0 for CPU B */
76#define PI_INT_MASK1_B 0x0000c0 /* Interrupt Mask 1 for CPU B */
77
78#define PI_INT_MASK_OFFSET 0x10 /* Offset from A to B */
79
80/* Crosscall interrupts */
81
82#define PI_CC_PEND_SET_A 0x0000c8 /* CC Interrupt Pending Set, CPU A */
83#define PI_CC_PEND_SET_B 0x0000d0 /* CC Interrupt Pending Set, CPU B */
84#define PI_CC_PEND_CLR_A 0x0000d8 /* CC Interrupt Pending Clr, CPU A */
85#define PI_CC_PEND_CLR_B 0x0000e0 /* CC Interrupt Pending Clr, CPU B */
86#define PI_CC_MASK 0x0000e8 /* CC Interrupt mask */
87
88#define PI_INT_SET_OFFSET 0x08 /* Offset from A to B */
89
90/* Realtime Counter and Profiler control registers */
91
92#define PI_RT_COUNT 0x030100 /* Real Time Counter */
93#define PI_RT_COMPARE_A 0x000108 /* Real Time Compare A */
94#define PI_RT_COMPARE_B 0x000110 /* Real Time Compare B */
95#define PI_PROFILE_COMPARE 0x000118 /* L5 int to both cpus when == RTC */
96#define PI_RT_PEND_A 0x000120 /* Set if RT int for A pending */
97#define PI_RT_PEND_B 0x000128 /* Set if RT int for B pending */
98#define PI_PROF_PEND_A 0x000130 /* Set if Prof int for A pending */
99#define PI_PROF_PEND_B 0x000138 /* Set if Prof int for B pending */
100#define PI_RT_EN_A 0x000140 /* RT int for CPU A enable */
101#define PI_RT_EN_B 0x000148 /* RT int for CPU B enable */
102#define PI_PROF_EN_A 0x000150 /* PROF int for CPU A enable */
103#define PI_PROF_EN_B 0x000158 /* PROF int for CPU B enable */
104#define PI_RT_LOCAL_CTRL 0x000160 /* RT control register */
105#define PI_RT_FILTER_CTRL 0x000168 /* GCLK Filter control register */
106
107#define PI_COUNT_OFFSET 0x08 /* A to B offset for all counts */
108
109/* Built-In Self Test support */
110
111#define PI_BIST_WRITE_DATA 0x000200 /* BIST write data */
112#define PI_BIST_READ_DATA 0x000208 /* BIST read data */
113#define PI_BIST_COUNT_TARG 0x000210 /* BIST Count and Target */
114#define PI_BIST_READY 0x000218 /* BIST Ready indicator */
115#define PI_BIST_SHIFT_LOAD 0x000220 /* BIST control */
116#define PI_BIST_SHIFT_UNLOAD 0x000228 /* BIST control */
117#define PI_BIST_ENTER_RUN 0x000230 /* BIST control */
118
119/* Graphics control registers */
120
121#define PI_GFX_PAGE_A 0x000300 /* Graphics page A */
122#define PI_GFX_CREDIT_CNTR_A 0x000308 /* Graphics credit counter A */
123#define PI_GFX_BIAS_A 0x000310 /* Graphics bias A */
124#define PI_GFX_INT_CNTR_A 0x000318 /* Graphics interrupt counter A */
125#define PI_GFX_INT_CMP_A 0x000320 /* Graphics interrupt comparator A */
126#define PI_GFX_PAGE_B 0x000328 /* Graphics page B */
127#define PI_GFX_CREDIT_CNTR_B 0x000330 /* Graphics credit counter B */
128#define PI_GFX_BIAS_B 0x000338 /* Graphics bias B */
129#define PI_GFX_INT_CNTR_B 0x000340 /* Graphics interrupt counter B */
130#define PI_GFX_INT_CMP_B 0x000348 /* Graphics interrupt comparator B */
131
132#define PI_GFX_OFFSET (PI_GFX_PAGE_B - PI_GFX_PAGE_A)
133#define PI_GFX_PAGE_ENABLE 0x0000010000000000LL
134
135/* Error and timeout registers */
136#define PI_ERR_INT_PEND 0x000400 /* Error Interrupt Pending */
137#define PI_ERR_INT_MASK_A 0x000408 /* Error Interrupt mask for CPU A */
138#define PI_ERR_INT_MASK_B 0x000410 /* Error Interrupt mask for CPU B */
139#define PI_ERR_STACK_ADDR_A 0x000418 /* Error stack address for CPU A */
140#define PI_ERR_STACK_ADDR_B 0x000420 /* Error stack address for CPU B */
141#define PI_ERR_STACK_SIZE 0x000428 /* Error Stack Size */
142#define PI_ERR_STATUS0_A 0x000430 /* Error Status 0A */
143#define PI_ERR_STATUS0_A_RCLR 0x000438 /* Error Status 0A clear on read */
144#define PI_ERR_STATUS1_A 0x000440 /* Error Status 1A */
145#define PI_ERR_STATUS1_A_RCLR 0x000448 /* Error Status 1A clear on read */
146#define PI_ERR_STATUS0_B 0x000450 /* Error Status 0B */
147#define PI_ERR_STATUS0_B_RCLR 0x000458 /* Error Status 0B clear on read */
148#define PI_ERR_STATUS1_B 0x000460 /* Error Status 1B */
149#define PI_ERR_STATUS1_B_RCLR 0x000468 /* Error Status 1B clear on read */
150#define PI_SPOOL_CMP_A 0x000470 /* Spool compare for CPU A */
151#define PI_SPOOL_CMP_B 0x000478 /* Spool compare for CPU B */
152#define PI_CRB_TIMEOUT_A 0x000480 /* Timed out CRB entries for A */
153#define PI_CRB_TIMEOUT_B 0x000488 /* Timed out CRB entries for B */
154#define PI_SYSAD_ERRCHK_EN 0x000490 /* Enables SYSAD error checking */
155#define PI_BAD_CHECK_BIT_A 0x000498 /* Force SYSAD check bit error */
156#define PI_BAD_CHECK_BIT_B 0x0004a0 /* Force SYSAD check bit error */
157#define PI_NACK_CNT_A 0x0004a8 /* Consecutive NACK counter */
158#define PI_NACK_CNT_B 0x0004b0 /* " " for CPU B */
159#define PI_NACK_CMP 0x0004b8 /* NACK count compare */
160#define PI_STACKADDR_OFFSET (PI_ERR_STACK_ADDR_B - PI_ERR_STACK_ADDR_A)
161#define PI_ERRSTAT_OFFSET (PI_ERR_STATUS0_B - PI_ERR_STATUS0_A)
162#define PI_RDCLR_OFFSET (PI_ERR_STATUS0_A_RCLR - PI_ERR_STATUS0_A)
163
164/* Bits in PI_ERR_INT_PEND */
165#define PI_ERR_SPOOL_CMP_B 0x00000001 /* Spool end hit high water */
166#define PI_ERR_SPOOL_CMP_A 0x00000002
167#define PI_ERR_SPUR_MSG_B 0x00000004 /* Spurious message intr. */
168#define PI_ERR_SPUR_MSG_A 0x00000008
169#define PI_ERR_WRB_TERR_B 0x00000010 /* WRB TERR */
170#define PI_ERR_WRB_TERR_A 0x00000020
171#define PI_ERR_WRB_WERR_B 0x00000040 /* WRB WERR */
172#define PI_ERR_WRB_WERR_A 0x00000080
173#define PI_ERR_SYSSTATE_B 0x00000100 /* SysState parity error */
174#define PI_ERR_SYSSTATE_A 0x00000200
175#define PI_ERR_SYSAD_DATA_B 0x00000400 /* SysAD data parity error */
176#define PI_ERR_SYSAD_DATA_A 0x00000800
177#define PI_ERR_SYSAD_ADDR_B 0x00001000 /* SysAD addr parity error */
178#define PI_ERR_SYSAD_ADDR_A 0x00002000
179#define PI_ERR_SYSCMD_DATA_B 0x00004000 /* SysCmd data parity error */
180#define PI_ERR_SYSCMD_DATA_A 0x00008000
181#define PI_ERR_SYSCMD_ADDR_B 0x00010000 /* SysCmd addr parity error */
182#define PI_ERR_SYSCMD_ADDR_A 0x00020000
183#define PI_ERR_BAD_SPOOL_B 0x00040000 /* Error spooling to memory */
184#define PI_ERR_BAD_SPOOL_A 0x00080000
185#define PI_ERR_UNCAC_UNCORR_B 0x00100000 /* Uncached uncorrectable */
186#define PI_ERR_UNCAC_UNCORR_A 0x00200000
187#define PI_ERR_SYSSTATE_TAG_B 0x00400000 /* SysState tag parity error */
188#define PI_ERR_SYSSTATE_TAG_A 0x00800000
189#define PI_ERR_MD_UNCORR 0x01000000 /* Must be cleared in MD */
190
191#define PI_ERR_CLEAR_ALL_A 0x00aaaaaa
192#define PI_ERR_CLEAR_ALL_B 0x00555555
193
194
195/*
196 * The following three macros define all possible error int pends.
197 */
198
199#define PI_FATAL_ERR_CPU_A (PI_ERR_SYSSTATE_TAG_A | \
200 PI_ERR_BAD_SPOOL_A | \
201 PI_ERR_SYSCMD_ADDR_A | \
202 PI_ERR_SYSCMD_DATA_A | \
203 PI_ERR_SYSAD_ADDR_A | \
204 PI_ERR_SYSAD_DATA_A | \
205 PI_ERR_SYSSTATE_A)
206
207#define PI_MISC_ERR_CPU_A (PI_ERR_UNCAC_UNCORR_A | \
208 PI_ERR_WRB_WERR_A | \
209 PI_ERR_WRB_TERR_A | \
210 PI_ERR_SPUR_MSG_A | \
211 PI_ERR_SPOOL_CMP_A)
212
213#define PI_FATAL_ERR_CPU_B (PI_ERR_SYSSTATE_TAG_B | \
214 PI_ERR_BAD_SPOOL_B | \
215 PI_ERR_SYSCMD_ADDR_B | \
216 PI_ERR_SYSCMD_DATA_B | \
217 PI_ERR_SYSAD_ADDR_B | \
218 PI_ERR_SYSAD_DATA_B | \
219 PI_ERR_SYSSTATE_B)
220
221#define PI_MISC_ERR_CPU_B (PI_ERR_UNCAC_UNCORR_B | \
222 PI_ERR_WRB_WERR_B | \
223 PI_ERR_WRB_TERR_B | \
224 PI_ERR_SPUR_MSG_B | \
225 PI_ERR_SPOOL_CMP_B)
226
227#define PI_ERR_GENERIC (PI_ERR_MD_UNCORR)
228
229/*
230 * Error types for PI_ERR_STATUS0_[AB] and error stack:
231 * Use the write types if WRBRRB is 1 else use the read types
232 */
233
234/* Fields in PI_ERR_STATUS0_[AB] */
235#define PI_ERR_ST0_TYPE_MASK 0x0000000000000007
236#define PI_ERR_ST0_TYPE_SHFT 0
237#define PI_ERR_ST0_REQNUM_MASK 0x0000000000000038
238#define PI_ERR_ST0_REQNUM_SHFT 3
239#define PI_ERR_ST0_SUPPL_MASK 0x000000000001ffc0
240#define PI_ERR_ST0_SUPPL_SHFT 6
241#define PI_ERR_ST0_CMD_MASK 0x0000000001fe0000
242#define PI_ERR_ST0_CMD_SHFT 17
243#define PI_ERR_ST0_ADDR_MASK 0x3ffffffffe000000
244#define PI_ERR_ST0_ADDR_SHFT 25
245#define PI_ERR_ST0_OVERRUN_MASK 0x4000000000000000
246#define PI_ERR_ST0_OVERRUN_SHFT 62
247#define PI_ERR_ST0_VALID_MASK 0x8000000000000000
248#define PI_ERR_ST0_VALID_SHFT 63
249
250/* Fields in PI_ERR_STATUS1_[AB] */
251#define PI_ERR_ST1_SPOOL_MASK 0x00000000001fffff
252#define PI_ERR_ST1_SPOOL_SHFT 0
253#define PI_ERR_ST1_TOUTCNT_MASK 0x000000001fe00000
254#define PI_ERR_ST1_TOUTCNT_SHFT 21
255#define PI_ERR_ST1_INVCNT_MASK 0x0000007fe0000000
256#define PI_ERR_ST1_INVCNT_SHFT 29
257#define PI_ERR_ST1_CRBNUM_MASK 0x0000038000000000
258#define PI_ERR_ST1_CRBNUM_SHFT 39
259#define PI_ERR_ST1_WRBRRB_MASK 0x0000040000000000
260#define PI_ERR_ST1_WRBRRB_SHFT 42
261#define PI_ERR_ST1_CRBSTAT_MASK 0x001ff80000000000
262#define PI_ERR_ST1_CRBSTAT_SHFT 43
263#define PI_ERR_ST1_MSGSRC_MASK 0xffe0000000000000
264#define PI_ERR_ST1_MSGSRC_SHFT 53
265
266/* Fields in the error stack */
267#define PI_ERR_STK_TYPE_MASK 0x0000000000000003
268#define PI_ERR_STK_TYPE_SHFT 0
269#define PI_ERR_STK_SUPPL_MASK 0x0000000000000038
270#define PI_ERR_STK_SUPPL_SHFT 3
271#define PI_ERR_STK_REQNUM_MASK 0x00000000000001c0
272#define PI_ERR_STK_REQNUM_SHFT 6
273#define PI_ERR_STK_CRBNUM_MASK 0x0000000000000e00
274#define PI_ERR_STK_CRBNUM_SHFT 9
275#define PI_ERR_STK_WRBRRB_MASK 0x0000000000001000
276#define PI_ERR_STK_WRBRRB_SHFT 12
277#define PI_ERR_STK_CRBSTAT_MASK 0x00000000007fe000
278#define PI_ERR_STK_CRBSTAT_SHFT 13
279#define PI_ERR_STK_CMD_MASK 0x000000007f800000
280#define PI_ERR_STK_CMD_SHFT 23
281#define PI_ERR_STK_ADDR_MASK 0xffffffff80000000
282#define PI_ERR_STK_ADDR_SHFT 31
283
284/* Error type in the error status or stack on Read CRBs */
285#define PI_ERR_RD_PRERR 1
286#define PI_ERR_RD_DERR 2
287#define PI_ERR_RD_TERR 3
288
289/* Error type in the error status or stack on Write CRBs */
290#define PI_ERR_WR_WERR 0
291#define PI_ERR_WR_PWERR 1
292#define PI_ERR_WR_TERR 3
293
294/* Read or Write CRB in error status or stack */
295#define PI_ERR_RRB 0
296#define PI_ERR_WRB 1
297#define PI_ERR_ANY_CRB 2
298
299/* Address masks in the error status and error stack are not the same */
300#define ERR_STK_ADDR_SHFT 7
301#define ERR_STAT0_ADDR_SHFT 3
302
303#define PI_MIN_STACK_SIZE 4096 /* For figuring out the size to set */
304#define PI_STACK_SIZE_SHFT 12 /* 4k */
305
306#define ERR_STACK_SIZE_BYTES(_sz) \
307 ((_sz) ? (PI_MIN_STACK_SIZE << ((_sz) - 1)) : 0)
308
309#ifndef __ASSEMBLY__
310/*
311 * format of error stack and error status registers.
312 */
313
314struct err_stack_format {
315 u64 sk_addr : 33, /* address */
316 sk_cmd : 8, /* message command */
317 sk_crb_sts : 10, /* status from RRB or WRB */
318 sk_rw_rb : 1, /* RRB == 0, WRB == 1 */
319 sk_crb_num : 3, /* WRB (0 to 7) or RRB (0 to 4) */
320 sk_t5_req : 3, /* RRB T5 request number */
321 sk_suppl : 3, /* lowest 3 bit of supplemental */
322 sk_err_type: 3; /* error type */
323};
324
325typedef union pi_err_stack {
326 u64 pi_stk_word;
327 struct err_stack_format pi_stk_fmt;
328} pi_err_stack_t;
329
330struct err_status0_format {
331 u64 s0_valid : 1, /* Valid */
332 s0_ovr_run : 1, /* Overrun, spooled to memory */
333 s0_addr : 37, /* address */
334 s0_cmd : 8, /* message command */
335 s0_supl : 11, /* message supplemental field */
336 s0_t5_req : 3, /* RRB T5 request number */
337 s0_err_type: 3; /* error type */
338};
339
340typedef union pi_err_stat0 {
341 u64 pi_stat0_word;
342 struct err_status0_format pi_stat0_fmt;
343} pi_err_stat0_t;
344
345struct err_status1_format {
346 u64 s1_src : 11, /* message source */
347 s1_crb_sts : 10, /* status from RRB or WRB */
348 s1_rw_rb : 1, /* RRB == 0, WRB == 1 */
349 s1_crb_num : 3, /* WRB (0 to 7) or RRB (0 to 4) */
350 s1_inval_cnt:10, /* signed invalidate counter RRB */
351 s1_to_cnt : 8, /* crb timeout counter */
352 s1_spl_cnt : 21; /* number spooled to memory */
353};
354
355typedef union pi_err_stat1 {
356 u64 pi_stat1_word;
357 struct err_status1_format pi_stat1_fmt;
358} pi_err_stat1_t;
359
360typedef u64 rtc_time_t;
361
362#endif /* !__ASSEMBLY__ */
363
364
365/* Bits in PI_SYSAD_ERRCHK_EN */
366#define PI_SYSAD_ERRCHK_ECCGEN 0x01 /* Enable ECC generation */
367#define PI_SYSAD_ERRCHK_QUALGEN 0x02 /* Enable data quality signal gen. */
368#define PI_SYSAD_ERRCHK_SADP 0x04 /* Enable SysAD parity checking */
369#define PI_SYSAD_ERRCHK_CMDP 0x08 /* Enable SysCmd parity checking */
370#define PI_SYSAD_ERRCHK_STATE 0x10 /* Enable SysState parity checking */
371#define PI_SYSAD_ERRCHK_QUAL 0x20 /* Enable data quality checking */
372#define PI_SYSAD_CHECK_ALL 0x3f /* Generate and check all signals. */
373
374/* Interrupt pending bits on R10000 */
375
376#define HUB_IP_PEND0 0x0400
377#define HUB_IP_PEND1_CC 0x0800
378#define HUB_IP_RT 0x1000
379#define HUB_IP_PROF 0x2000
380#define HUB_IP_ERROR 0x4000
381#define HUB_IP_MASK 0x7c00
382
383/* PI_RT_LOCAL_CTRL mask and shift definitions */
384
385#define PRLC_USE_INT_SHFT 16
386#define PRLC_USE_INT_MASK (UINT64_CAST 1 << 16)
387#define PRLC_USE_INT (UINT64_CAST 1 << 16)
388#define PRLC_GCLK_SHFT 15
389#define PRLC_GCLK_MASK (UINT64_CAST 1 << 15)
390#define PRLC_GCLK (UINT64_CAST 1 << 15)
391#define PRLC_GCLK_COUNT_SHFT 8
392#define PRLC_GCLK_COUNT_MASK (UINT64_CAST 0x7f << 8)
393#define PRLC_MAX_COUNT_SHFT 1
394#define PRLC_MAX_COUNT_MASK (UINT64_CAST 0x7f << 1)
395#define PRLC_GCLK_EN_SHFT 0
396#define PRLC_GCLK_EN_MASK (UINT64_CAST 1)
397#define PRLC_GCLK_EN (UINT64_CAST 1)
398
399/* PI_RT_FILTER_CTRL mask and shift definitions */
400
401/*
402 * Bits for NACK_CNT_A/B and NACK_CMP
403 */
404#define PI_NACK_CNT_EN_SHFT 20
405#define PI_NACK_CNT_EN_MASK 0x100000
406#define PI_NACK_CNT_MASK 0x0fffff
407#define PI_NACK_CNT_MAX 0x0fffff
408
409#endif /* _ASM_SN_SN0_HUBPI_H */
diff --git a/arch/mips/include/asm/sn/sn0/ip27.h b/arch/mips/include/asm/sn/sn0/ip27.h
new file mode 100644
index 000000000000..3c97e0855c8d
--- /dev/null
+++ b/arch/mips/include/asm/sn/sn0/ip27.h
@@ -0,0 +1,85 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Derived from IRIX <sys/SN/SN0/IP27.h>.
7 *
8 * Copyright (C) 1992 - 1997, 1999 Silicon Graphics, Inc.
9 * Copyright (C) 1999, 2006 by Ralf Baechle
10 */
11#ifndef _ASM_SN_SN0_IP27_H
12#define _ASM_SN_SN0_IP27_H
13
14#include <asm/mipsregs.h>
15
16/*
17 * Simple definitions for the masks which remove SW bits from pte.
18 */
19
20#define TLBLO_HWBITSHIFT 0 /* Shift value, for masking */
21
22#ifndef __ASSEMBLY__
23
24#define CAUSE_BERRINTR IE_IRQ5
25
26#define ECCF_CACHE_ERR 0
27#define ECCF_TAGLO 1
28#define ECCF_ECC 2
29#define ECCF_ERROREPC 3
30#define ECCF_PADDR 4
31#define ECCF_SIZE (5 * sizeof(long))
32
33#endif /* !__ASSEMBLY__ */
34
35#ifdef __ASSEMBLY__
36
37/*
38 * KL_GET_CPUNUM (similar to EV_GET_SPNUM for EVEREST platform) reads
39 * the processor number of the calling processor. The proc parameters
40 * must be a register.
41 */
42#define KL_GET_CPUNUM(proc) \
43 dli proc, LOCAL_HUB(0); \
44 ld proc, PI_CPU_NUM(proc)
45
46#endif /* __ASSEMBLY__ */
47
48/*
49 * R10000 status register interrupt bit mask usage for IP27.
50 */
51#define SRB_SWTIMO IE_SW0 /* 0x0100 */
52#define SRB_NET IE_SW1 /* 0x0200 */
53#define SRB_DEV0 IE_IRQ0 /* 0x0400 */
54#define SRB_DEV1 IE_IRQ1 /* 0x0800 */
55#define SRB_TIMOCLK IE_IRQ2 /* 0x1000 */
56#define SRB_PROFCLK IE_IRQ3 /* 0x2000 */
57#define SRB_ERR IE_IRQ4 /* 0x4000 */
58#define SRB_SCHEDCLK IE_IRQ5 /* 0x8000 */
59
60#define SR_IBIT_HI SRB_DEV0
61#define SR_IBIT_PROF SRB_PROFCLK
62
63#define SRB_SWTIMO_IDX 0
64#define SRB_NET_IDX 1
65#define SRB_DEV0_IDX 2
66#define SRB_DEV1_IDX 3
67#define SRB_TIMOCLK_IDX 4
68#define SRB_PROFCLK_IDX 5
69#define SRB_ERR_IDX 6
70#define SRB_SCHEDCLK_IDX 7
71
72#define NUM_CAUSE_INTRS 8
73
74#define SCACHE_LINESIZE 128
75#define SCACHE_LINEMASK (SCACHE_LINESIZE - 1)
76
77#include <asm/sn/addrs.h>
78
79#define LED_CYCLE_MASK 0x0f
80#define LED_CYCLE_SHFT 4
81
82#define SEND_NMI(_nasid, _slice) \
83 REMOTE_HUB_S((_nasid), (PI_NMI_A + ((_slice) * PI_NMI_OFFSET)), 1)
84
85#endif /* _ASM_SN_SN0_IP27_H */
diff --git a/arch/mips/include/asm/sn/sn_private.h b/arch/mips/include/asm/sn/sn_private.h
new file mode 100644
index 000000000000..1a2c3025bf28
--- /dev/null
+++ b/arch/mips/include/asm/sn/sn_private.h
@@ -0,0 +1,19 @@
1#ifndef __ASM_SN_SN_PRIVATE_H
2#define __ASM_SN_SN_PRIVATE_H
3
4#include <asm/sn/types.h>
5
6extern nasid_t master_nasid;
7
8extern void cpu_node_probe(void);
9extern cnodeid_t get_compact_nodeid(void);
10extern void hub_rtc_init(cnodeid_t);
11extern void cpu_time_init(void);
12extern void per_cpu_init(void);
13extern void install_cpu_nmi_handler(int slice);
14extern void install_ipi(void);
15extern void setup_replication_mask(void);
16extern void replicate_kernel_text(void);
17extern pfn_t node_getfirstfree(cnodeid_t);
18
19#endif /* __ASM_SN_SN_PRIVATE_H */
diff --git a/arch/mips/include/asm/sn/types.h b/arch/mips/include/asm/sn/types.h
new file mode 100644
index 000000000000..74d0bb260b86
--- /dev/null
+++ b/arch/mips/include/asm/sn/types.h
@@ -0,0 +1,26 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1999 Silicon Graphics, Inc.
7 * Copyright (C) 1999 by Ralf Baechle
8 */
9#ifndef _ASM_SN_TYPES_H
10#define _ASM_SN_TYPES_H
11
12#include <linux/types.h>
13
14typedef unsigned long cpuid_t;
15typedef unsigned long cnodemask_t;
16typedef signed short nasid_t; /* node id in numa-as-id space */
17typedef signed short cnodeid_t; /* node id in compact-id space */
18typedef signed char partid_t; /* partition ID type */
19typedef signed short moduleid_t; /* user-visible module number type */
20typedef signed short cmoduleid_t; /* kernel compact module id type */
21typedef unsigned char clusterid_t; /* Clusterid of the cell */
22typedef unsigned long pfn_t;
23
24typedef dev_t vertex_hdl_t; /* hardware graph vertex handle */
25
26#endif /* _ASM_SN_TYPES_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-24 19:52:40 -0500