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-rw-r--r--arch/mips/include/asm/sgi/gio.h86
-rw-r--r--arch/mips/include/asm/sgi/hpc3.h317
-rw-r--r--arch/mips/include/asm/sgi/ioc.h200
-rw-r--r--arch/mips/include/asm/sgi/ip22.h78
-rw-r--r--arch/mips/include/asm/sgi/mc.h231
-rw-r--r--arch/mips/include/asm/sgi/pi1.h71
-rw-r--r--arch/mips/include/asm/sgi/seeq.h21
-rw-r--r--arch/mips/include/asm/sgi/sgi.h47
-rw-r--r--arch/mips/include/asm/sgi/wd.h20
9 files changed, 1071 insertions, 0 deletions
diff --git a/arch/mips/include/asm/sgi/gio.h b/arch/mips/include/asm/sgi/gio.h
new file mode 100644
index 000000000000..889cf028c95d
--- /dev/null
+++ b/arch/mips/include/asm/sgi/gio.h
@@ -0,0 +1,86 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * gio.h: Definitions for SGI GIO bus
7 *
8 * Copyright (C) 2002 Ladislav Michl
9 */
10
11#ifndef _SGI_GIO_H
12#define _SGI_GIO_H
13
14/*
15 * GIO bus addresses
16 *
17 * The Indigo and Indy have two GIO bus connectors. Indigo2 (all models) have
18 * three physical connectors, but only two slots, GFX and EXP0.
19 *
20 * There is 10MB of GIO address space for GIO64 slot devices
21 * slot# slot type address range size
22 * ----- --------- ----------------------- -----
23 * 0 GFX 0x1f000000 - 0x1f3fffff 4MB
24 * 1 EXP0 0x1f400000 - 0x1f5fffff 2MB
25 * 2 EXP1 0x1f600000 - 0x1f9fffff 4MB
26 *
27 * There are un-slotted devices, HPC, I/O and misc devices, which are grouped
28 * into the HPC address space.
29 * - MISC 0x1fb00000 - 0x1fbfffff 1MB
30 *
31 * Following space is reserved and unused
32 * - RESERVED 0x18000000 - 0x1effffff 112MB
33 *
34 * GIO bus IDs
35 *
36 * Each GIO bus device identifies itself to the system by answering a
37 * read with an "ID" value. IDs are either 8 or 32 bits long. IDs less
38 * than 128 are 8 bits long, with the most significant 24 bits read from
39 * the slot undefined.
40 *
41 * 32-bit IDs are divided into
42 * bits 0:6 the product ID; ranges from 0x00 to 0x7F.
43 * bit 7 0=GIO Product ID is 8 bits wide
44 * 1=GIO Product ID is 32 bits wide.
45 * bits 8:15 manufacturer version for the product.
46 * bit 16 0=GIO32 and GIO32-bis, 1=GIO64.
47 * bit 17 0=no ROM present
48 * 1=ROM present on this board AND next three words
49 * space define the ROM.
50 * bits 18:31 up to manufacturer.
51 *
52 * IDs above 0x50/0xd0 are of 3rd party boards.
53 *
54 * 8-bit IDs
55 * 0x01 XPI low cost FDDI
56 * 0x02 GTR TokenRing
57 * 0x04 Synchronous ISDN
58 * 0x05 ATM board [*]
59 * 0x06 Canon Interface
60 * 0x07 16 bit SCSI Card [*]
61 * 0x08 JPEG (Double Wide)
62 * 0x09 JPEG (Single Wide)
63 * 0x0a XPI mez. FDDI device 0
64 * 0x0b XPI mez. FDDI device 1
65 * 0x0c SMPTE 259M Video [*]
66 * 0x0d Babblefish Compression [*]
67 * 0x0e E-Plex 8-port Ethernet
68 * 0x30 Lyon Lamb IVAS
69 * 0xb8 GIO 100BaseTX Fast Ethernet (gfe)
70 *
71 * [*] Device provide 32-bit ID.
72 *
73 */
74
75#define GIO_ID(x) (x & 0x7f)
76#define GIO_32BIT_ID 0x80
77#define GIO_REV(x) ((x >> 8) & 0xff)
78#define GIO_64BIT_IFACE 0x10000
79#define GIO_ROM_PRESENT 0x20000
80#define GIO_VENDOR_CODE(x) ((x >> 18) & 0x3fff)
81
82#define GIO_SLOT_GFX_BASE 0x1f000000
83#define GIO_SLOT_EXP0_BASE 0x1f400000
84#define GIO_SLOT_EXP1_BASE 0x1f600000
85
86#endif /* _SGI_GIO_H */
diff --git a/arch/mips/include/asm/sgi/hpc3.h b/arch/mips/include/asm/sgi/hpc3.h
new file mode 100644
index 000000000000..c4729f531919
--- /dev/null
+++ b/arch/mips/include/asm/sgi/hpc3.h
@@ -0,0 +1,317 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * hpc3.h: Definitions for SGI HPC3 controller
7 *
8 * Copyright (C) 1996 David S. Miller
9 * Copyright (C) 1998 Ralf Baechle
10 */
11
12#ifndef _SGI_HPC3_H
13#define _SGI_HPC3_H
14
15#include <linux/types.h>
16#include <asm/page.h>
17
18/* An HPC DMA descriptor. */
19struct hpc_dma_desc {
20 u32 pbuf; /* physical address of data buffer */
21 u32 cntinfo; /* counter and info bits */
22#define HPCDMA_EOX 0x80000000 /* last desc in chain for tx */
23#define HPCDMA_EOR 0x80000000 /* last desc in chain for rx */
24#define HPCDMA_EOXP 0x40000000 /* end of packet for tx */
25#define HPCDMA_EORP 0x40000000 /* end of packet for rx */
26#define HPCDMA_XIE 0x20000000 /* irq generated when at end of this desc */
27#define HPCDMA_XIU 0x01000000 /* Tx buffer in use by CPU. */
28#define HPCDMA_EIPC 0x00ff0000 /* SEEQ ethernet special xternal bytecount */
29#define HPCDMA_ETXD 0x00008000 /* set to one by HPC when packet tx'd */
30#define HPCDMA_OWN 0x00004000 /* Denotes ring buffer ownership on rx */
31#define HPCDMA_BCNT 0x00003fff /* size in bytes of this dma buffer */
32
33 u32 pnext; /* paddr of next hpc_dma_desc if any */
34};
35
36/* The set of regs for each HPC3 PBUS DMA channel. */
37struct hpc3_pbus_dmacregs {
38 volatile u32 pbdma_bptr; /* pbus dma channel buffer ptr */
39 volatile u32 pbdma_dptr; /* pbus dma channel desc ptr */
40 u32 _unused0[0x1000/4 - 2]; /* padding */
41 volatile u32 pbdma_ctrl; /* pbus dma channel control register has
42 * copletely different meaning for read
43 * compared with write */
44 /* read */
45#define HPC3_PDMACTRL_INT 0x00000001 /* interrupt (cleared after read) */
46#define HPC3_PDMACTRL_ISACT 0x00000002 /* channel active */
47 /* write */
48#define HPC3_PDMACTRL_SEL 0x00000002 /* little endian transfer */
49#define HPC3_PDMACTRL_RCV 0x00000004 /* direction is receive */
50#define HPC3_PDMACTRL_FLSH 0x00000008 /* enable flush for receive DMA */
51#define HPC3_PDMACTRL_ACT 0x00000010 /* start dma transfer */
52#define HPC3_PDMACTRL_LD 0x00000020 /* load enable for ACT */
53#define HPC3_PDMACTRL_RT 0x00000040 /* Use realtime GIO bus servicing */
54#define HPC3_PDMACTRL_HW 0x0000ff00 /* DMA High-water mark */
55#define HPC3_PDMACTRL_FB 0x003f0000 /* Ptr to beginning of fifo */
56#define HPC3_PDMACTRL_FE 0x3f000000 /* Ptr to end of fifo */
57
58 u32 _unused1[0x1000/4 - 1]; /* padding */
59};
60
61/* The HPC3 SCSI registers, this does not include external ones. */
62struct hpc3_scsiregs {
63 volatile u32 cbptr; /* current dma buffer ptr, diagnostic use only */
64 volatile u32 ndptr; /* next dma descriptor ptr */
65 u32 _unused0[0x1000/4 - 2]; /* padding */
66 volatile u32 bcd; /* byte count info */
67#define HPC3_SBCD_BCNTMSK 0x00003fff /* bytes to transfer from/to memory */
68#define HPC3_SBCD_XIE 0x00004000 /* Send IRQ when done with cur buf */
69#define HPC3_SBCD_EOX 0x00008000 /* Indicates this is last buf in chain */
70
71 volatile u32 ctrl; /* control register */
72#define HPC3_SCTRL_IRQ 0x01 /* IRQ asserted, either dma done or parity */
73#define HPC3_SCTRL_ENDIAN 0x02 /* DMA endian mode, 0=big 1=little */
74#define HPC3_SCTRL_DIR 0x04 /* DMA direction, 1=dev2mem 0=mem2dev */
75#define HPC3_SCTRL_FLUSH 0x08 /* Tells HPC3 to flush scsi fifos */
76#define HPC3_SCTRL_ACTIVE 0x10 /* SCSI DMA channel is active */
77#define HPC3_SCTRL_AMASK 0x20 /* DMA active inhibits PIO */
78#define HPC3_SCTRL_CRESET 0x40 /* Resets dma channel and external controller */
79#define HPC3_SCTRL_PERR 0x80 /* Bad parity on HPC3 iface to scsi controller */
80
81 volatile u32 gfptr; /* current GIO fifo ptr */
82 volatile u32 dfptr; /* current device fifo ptr */
83 volatile u32 dconfig; /* DMA configuration register */
84#define HPC3_SDCFG_HCLK 0x00001 /* Enable DMA half clock mode */
85#define HPC3_SDCFG_D1 0x00006 /* Cycles to spend in D1 state */
86#define HPC3_SDCFG_D2 0x00038 /* Cycles to spend in D2 state */
87#define HPC3_SDCFG_D3 0x001c0 /* Cycles to spend in D3 state */
88#define HPC3_SDCFG_HWAT 0x00e00 /* DMA high water mark */
89#define HPC3_SDCFG_HW 0x01000 /* Enable 16-bit halfword DMA accesses to scsi */
90#define HPC3_SDCFG_SWAP 0x02000 /* Byte swap all DMA accesses */
91#define HPC3_SDCFG_EPAR 0x04000 /* Enable parity checking for DMA */
92#define HPC3_SDCFG_POLL 0x08000 /* hd_dreq polarity control */
93#define HPC3_SDCFG_ERLY 0x30000 /* hd_dreq behavior control bits */
94
95 volatile u32 pconfig; /* PIO configuration register */
96#define HPC3_SPCFG_P3 0x0003 /* Cycles to spend in P3 state */
97#define HPC3_SPCFG_P2W 0x001c /* Cycles to spend in P2 state for writes */
98#define HPC3_SPCFG_P2R 0x01e0 /* Cycles to spend in P2 state for reads */
99#define HPC3_SPCFG_P1 0x0e00 /* Cycles to spend in P1 state */
100#define HPC3_SPCFG_HW 0x1000 /* Enable 16-bit halfword PIO accesses to scsi */
101#define HPC3_SPCFG_SWAP 0x2000 /* Byte swap all PIO accesses */
102#define HPC3_SPCFG_EPAR 0x4000 /* Enable parity checking for PIO */
103#define HPC3_SPCFG_FUJI 0x8000 /* Fujitsu scsi controller mode for faster dma/pio */
104
105 u32 _unused1[0x1000/4 - 6]; /* padding */
106};
107
108/* SEEQ ethernet HPC3 registers, only one seeq per HPC3. */
109struct hpc3_ethregs {
110 /* Receiver registers. */
111 volatile u32 rx_cbptr; /* current dma buffer ptr, diagnostic use only */
112 volatile u32 rx_ndptr; /* next dma descriptor ptr */
113 u32 _unused0[0x1000/4 - 2]; /* padding */
114 volatile u32 rx_bcd; /* byte count info */
115#define HPC3_ERXBCD_BCNTMSK 0x00003fff /* bytes to be sent to memory */
116#define HPC3_ERXBCD_XIE 0x20000000 /* HPC3 interrupts cpu at end of this buf */
117#define HPC3_ERXBCD_EOX 0x80000000 /* flags this as end of descriptor chain */
118
119 volatile u32 rx_ctrl; /* control register */
120#define HPC3_ERXCTRL_STAT50 0x0000003f /* Receive status reg bits of Seeq8003 */
121#define HPC3_ERXCTRL_STAT6 0x00000040 /* Rdonly irq status */
122#define HPC3_ERXCTRL_STAT7 0x00000080 /* Rdonlt old/new status bit from Seeq */
123#define HPC3_ERXCTRL_ENDIAN 0x00000100 /* Endian for dma channel, little=1 big=0 */
124#define HPC3_ERXCTRL_ACTIVE 0x00000200 /* Tells if DMA transfer is in progress */
125#define HPC3_ERXCTRL_AMASK 0x00000400 /* Tells if ACTIVE inhibits PIO's to hpc3 */
126#define HPC3_ERXCTRL_RBO 0x00000800 /* Receive buffer overflow if set to 1 */
127
128 volatile u32 rx_gfptr; /* current GIO fifo ptr */
129 volatile u32 rx_dfptr; /* current device fifo ptr */
130 u32 _unused1; /* padding */
131 volatile u32 reset; /* reset register */
132#define HPC3_ERST_CRESET 0x1 /* Reset dma channel and external controller */
133#define HPC3_ERST_CLRIRQ 0x2 /* Clear channel interrupt */
134#define HPC3_ERST_LBACK 0x4 /* Enable diagnostic loopback mode of Seeq8003 */
135
136 volatile u32 dconfig; /* DMA configuration register */
137#define HPC3_EDCFG_D1 0x0000f /* Cycles to spend in D1 state for PIO */
138#define HPC3_EDCFG_D2 0x000f0 /* Cycles to spend in D2 state for PIO */
139#define HPC3_EDCFG_D3 0x00f00 /* Cycles to spend in D3 state for PIO */
140#define HPC3_EDCFG_WCTRL 0x01000 /* Enable writes of desc into ex ctrl port */
141#define HPC3_EDCFG_FRXDC 0x02000 /* Clear eop stat bits upon rxdc, hw seeq fix */
142#define HPC3_EDCFG_FEOP 0x04000 /* Bad packet marker timeout enable */
143#define HPC3_EDCFG_FIRQ 0x08000 /* Another bad packet timeout enable */
144#define HPC3_EDCFG_PTO 0x30000 /* Programmed timeout value for above two */
145
146 volatile u32 pconfig; /* PIO configuration register */
147#define HPC3_EPCFG_P1 0x000f /* Cycles to spend in P1 state for PIO */
148#define HPC3_EPCFG_P2 0x00f0 /* Cycles to spend in P2 state for PIO */
149#define HPC3_EPCFG_P3 0x0f00 /* Cycles to spend in P3 state for PIO */
150#define HPC3_EPCFG_TST 0x1000 /* Diagnistic ram test feature bit */
151
152 u32 _unused2[0x1000/4 - 8]; /* padding */
153
154 /* Transmitter registers. */
155 volatile u32 tx_cbptr; /* current dma buffer ptr, diagnostic use only */
156 volatile u32 tx_ndptr; /* next dma descriptor ptr */
157 u32 _unused3[0x1000/4 - 2]; /* padding */
158 volatile u32 tx_bcd; /* byte count info */
159#define HPC3_ETXBCD_BCNTMSK 0x00003fff /* bytes to be read from memory */
160#define HPC3_ETXBCD_ESAMP 0x10000000 /* if set, too late to add descriptor */
161#define HPC3_ETXBCD_XIE 0x20000000 /* Interrupt cpu at end of cur desc */
162#define HPC3_ETXBCD_EOP 0x40000000 /* Last byte of cur buf is end of packet */
163#define HPC3_ETXBCD_EOX 0x80000000 /* This buf is the end of desc chain */
164
165 volatile u32 tx_ctrl; /* control register */
166#define HPC3_ETXCTRL_STAT30 0x0000000f /* Rdonly copy of seeq tx stat reg */
167#define HPC3_ETXCTRL_STAT4 0x00000010 /* Indicate late collision occurred */
168#define HPC3_ETXCTRL_STAT75 0x000000e0 /* Rdonly irq status from seeq */
169#define HPC3_ETXCTRL_ENDIAN 0x00000100 /* DMA channel endian mode, 1=little 0=big */
170#define HPC3_ETXCTRL_ACTIVE 0x00000200 /* DMA tx channel is active */
171#define HPC3_ETXCTRL_AMASK 0x00000400 /* Indicates ACTIVE inhibits PIO's */
172
173 volatile u32 tx_gfptr; /* current GIO fifo ptr */
174 volatile u32 tx_dfptr; /* current device fifo ptr */
175 u32 _unused4[0x1000/4 - 4]; /* padding */
176};
177
178struct hpc3_regs {
179 /* First regs for the PBUS 8 dma channels. */
180 struct hpc3_pbus_dmacregs pbdma[8];
181
182 /* Now the HPC scsi registers, we get two scsi reg sets. */
183 struct hpc3_scsiregs scsi_chan0, scsi_chan1;
184
185 /* The SEEQ hpc3 ethernet dma/control registers. */
186 struct hpc3_ethregs ethregs;
187
188 /* Here are where the hpc3 fifo's can be directly accessed
189 * via PIO accesses. Under normal operation we never stick
190 * our grubby paws in here so it's just padding. */
191 u32 _unused0[0x18000/4];
192
193 /* HPC3 irq status regs. Due to a peculiar bug you need to
194 * look at two different register addresses to get at all of
195 * the status bits. The first reg can only reliably report
196 * bits 4:0 of the status, and the second reg can only
197 * reliably report bits 9:5 of the hpc3 irq status. I told
198 * you it was a peculiar bug. ;-)
199 */
200 volatile u32 istat0; /* Irq status, only bits <4:0> reliable. */
201#define HPC3_ISTAT_PBIMASK 0x0ff /* irq bits for pbus devs 0 --> 7 */
202#define HPC3_ISTAT_SC0MASK 0x100 /* irq bit for scsi channel 0 */
203#define HPC3_ISTAT_SC1MASK 0x200 /* irq bit for scsi channel 1 */
204
205 volatile u32 gio_misc; /* GIO misc control bits. */
206#define HPC3_GIOMISC_ERTIME 0x1 /* Enable external timer real time. */
207#define HPC3_GIOMISC_DENDIAN 0x2 /* dma descriptor endian, 1=lit 0=big */
208
209 u32 eeprom; /* EEPROM data reg. */
210#define HPC3_EEPROM_EPROT 0x01 /* Protect register enable */
211#define HPC3_EEPROM_CSEL 0x02 /* Chip select */
212#define HPC3_EEPROM_ECLK 0x04 /* EEPROM clock */
213#define HPC3_EEPROM_DATO 0x08 /* Data out */
214#define HPC3_EEPROM_DATI 0x10 /* Data in */
215
216 volatile u32 istat1; /* Irq status, only bits <9:5> reliable. */
217 volatile u32 bestat; /* Bus error interrupt status reg. */
218#define HPC3_BESTAT_BLMASK 0x000ff /* Bus lane where bad parity occurred */
219#define HPC3_BESTAT_CTYPE 0x00100 /* Bus cycle type, 0=PIO 1=DMA */
220#define HPC3_BESTAT_PIDSHIFT 9
221#define HPC3_BESTAT_PIDMASK 0x3f700 /* DMA channel parity identifier */
222
223 u32 _unused1[0x14000/4 - 5]; /* padding */
224
225 /* Now direct PIO per-HPC3 peripheral access to external regs. */
226 volatile u32 scsi0_ext[256]; /* SCSI channel 0 external regs */
227 u32 _unused2[0x7c00/4];
228 volatile u32 scsi1_ext[256]; /* SCSI channel 1 external regs */
229 u32 _unused3[0x7c00/4];
230 volatile u32 eth_ext[320]; /* Ethernet external registers */
231 u32 _unused4[0x3b00/4];
232
233 /* Per-peripheral device external registers and DMA/PIO control. */
234 volatile u32 pbus_extregs[16][256];
235 volatile u32 pbus_dmacfg[8][128];
236 /* Cycles to spend in D3 for reads */
237#define HPC3_DMACFG_D3R_MASK 0x00000001
238#define HPC3_DMACFG_D3R_SHIFT 0
239 /* Cycles to spend in D4 for reads */
240#define HPC3_DMACFG_D4R_MASK 0x0000001e
241#define HPC3_DMACFG_D4R_SHIFT 1
242 /* Cycles to spend in D5 for reads */
243#define HPC3_DMACFG_D5R_MASK 0x000001e0
244#define HPC3_DMACFG_D5R_SHIFT 5
245 /* Cycles to spend in D3 for writes */
246#define HPC3_DMACFG_D3W_MASK 0x00000200
247#define HPC3_DMACFG_D3W_SHIFT 9
248 /* Cycles to spend in D4 for writes */
249#define HPC3_DMACFG_D4W_MASK 0x00003c00
250#define HPC3_DMACFG_D4W_SHIFT 10
251 /* Cycles to spend in D5 for writes */
252#define HPC3_DMACFG_D5W_MASK 0x0003c000
253#define HPC3_DMACFG_D5W_SHIFT 14
254 /* Enable 16-bit DMA access mode */
255#define HPC3_DMACFG_DS16 0x00040000
256 /* Places halfwords on high 16 bits of bus */
257#define HPC3_DMACFG_EVENHI 0x00080000
258 /* Make this device real time */
259#define HPC3_DMACFG_RTIME 0x00200000
260 /* 5 bit burst count for DMA device */
261#define HPC3_DMACFG_BURST_MASK 0x07c00000
262#define HPC3_DMACFG_BURST_SHIFT 22
263 /* Use live pbus_dreq unsynchronized signal */
264#define HPC3_DMACFG_DRQLIVE 0x08000000
265 volatile u32 pbus_piocfg[16][64];
266 /* Cycles to spend in P2 state for reads */
267#define HPC3_PIOCFG_P2R_MASK 0x00001
268#define HPC3_PIOCFG_P2R_SHIFT 0
269 /* Cycles to spend in P3 state for reads */
270#define HPC3_PIOCFG_P3R_MASK 0x0001e
271#define HPC3_PIOCFG_P3R_SHIFT 1
272 /* Cycles to spend in P4 state for reads */
273#define HPC3_PIOCFG_P4R_MASK 0x001e0
274#define HPC3_PIOCFG_P4R_SHIFT 5
275 /* Cycles to spend in P2 state for writes */
276#define HPC3_PIOCFG_P2W_MASK 0x00200
277#define HPC3_PIOCFG_P2W_SHIFT 9
278 /* Cycles to spend in P3 state for writes */
279#define HPC3_PIOCFG_P3W_MASK 0x03c00
280#define HPC3_PIOCFG_P3W_SHIFT 10
281 /* Cycles to spend in P4 state for writes */
282#define HPC3_PIOCFG_P4W_MASK 0x3c000
283#define HPC3_PIOCFG_P4W_SHIFT 14
284 /* Enable 16-bit PIO accesses */
285#define HPC3_PIOCFG_DS16 0x40000
286 /* Place even address bits in bits <15:8> */
287#define HPC3_PIOCFG_EVENHI 0x80000
288
289 /* PBUS PROM control regs. */
290 volatile u32 pbus_promwe; /* PROM write enable register */
291#define HPC3_PROM_WENAB 0x1 /* Enable writes to the PROM */
292
293 u32 _unused5[0x0800/4 - 1];
294 volatile u32 pbus_promswap; /* Chip select swap reg */
295#define HPC3_PROM_SWAP 0x1 /* invert GIO addr bit to select prom0 or prom1 */
296
297 u32 _unused6[0x0800/4 - 1];
298 volatile u32 pbus_gout; /* PROM general purpose output reg */
299#define HPC3_PROM_STAT 0x1 /* General purpose status bit in gout */
300
301 u32 _unused7[0x1000/4 - 1];
302 volatile u32 rtcregs[14]; /* Dallas clock registers */
303 u32 _unused8[50];
304 volatile u32 bbram[8192-50-14]; /* Battery backed ram */
305};
306
307/*
308 * It is possible to have two HPC3's within the address space on
309 * one machine, though only having one is more likely on an Indy.
310 */
311extern struct hpc3_regs *hpc3c0, *hpc3c1;
312#define HPC3_CHIP0_BASE 0x1fb80000 /* physical */
313#define HPC3_CHIP1_BASE 0x1fb00000 /* physical */
314
315extern void sgihpc_init(void);
316
317#endif /* _SGI_HPC3_H */
diff --git a/arch/mips/include/asm/sgi/ioc.h b/arch/mips/include/asm/sgi/ioc.h
new file mode 100644
index 000000000000..343ed15f8dc4
--- /dev/null
+++ b/arch/mips/include/asm/sgi/ioc.h
@@ -0,0 +1,200 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * ioc.h: Definitions for SGI I/O Controller
7 *
8 * Copyright (C) 1996 David S. Miller
9 * Copyright (C) 1997, 1998, 1999, 2000 Ralf Baechle
10 * Copyright (C) 2001, 2003 Ladislav Michl
11 */
12
13#ifndef _SGI_IOC_H
14#define _SGI_IOC_H
15
16#include <linux/types.h>
17#include <asm/sgi/pi1.h>
18
19/*
20 * All registers are 8-bit wide alligned on 32-bit boundary. Bad things
21 * happen if you try word access them. You have been warned.
22 */
23
24struct sgioc_uart_regs {
25 u8 _ctrl1[3];
26 volatile u8 ctrl1;
27 u8 _data1[3];
28 volatile u8 data1;
29 u8 _ctrl2[3];
30 volatile u8 ctrl2;
31 u8 _data2[3];
32 volatile u8 data2;
33};
34
35struct sgioc_keyb_regs {
36 u8 _data[3];
37 volatile u8 data;
38 u8 _command[3];
39 volatile u8 command;
40};
41
42struct sgint_regs {
43 u8 _istat0[3];
44 volatile u8 istat0; /* Interrupt status zero */
45#define SGINT_ISTAT0_FFULL 0x01
46#define SGINT_ISTAT0_SCSI0 0x02
47#define SGINT_ISTAT0_SCSI1 0x04
48#define SGINT_ISTAT0_ENET 0x08
49#define SGINT_ISTAT0_GFXDMA 0x10
50#define SGINT_ISTAT0_PPORT 0x20
51#define SGINT_ISTAT0_HPC2 0x40
52#define SGINT_ISTAT0_LIO2 0x80
53 u8 _imask0[3];
54 volatile u8 imask0; /* Interrupt mask zero */
55 u8 _istat1[3];
56 volatile u8 istat1; /* Interrupt status one */
57#define SGINT_ISTAT1_ISDNI 0x01
58#define SGINT_ISTAT1_PWR 0x02
59#define SGINT_ISTAT1_ISDNH 0x04
60#define SGINT_ISTAT1_LIO3 0x08
61#define SGINT_ISTAT1_HPC3 0x10
62#define SGINT_ISTAT1_AFAIL 0x20
63#define SGINT_ISTAT1_VIDEO 0x40
64#define SGINT_ISTAT1_GIO2 0x80
65 u8 _imask1[3];
66 volatile u8 imask1; /* Interrupt mask one */
67 u8 _vmeistat[3];
68 volatile u8 vmeistat; /* VME interrupt status */
69 u8 _cmeimask0[3];
70 volatile u8 cmeimask0; /* VME interrupt mask zero */
71 u8 _cmeimask1[3];
72 volatile u8 cmeimask1; /* VME interrupt mask one */
73 u8 _cmepol[3];
74 volatile u8 cmepol; /* VME polarity */
75 u8 _tclear[3];
76 volatile u8 tclear;
77 u8 _errstat[3];
78 volatile u8 errstat; /* Error status reg, reserved on INT2 */
79 u32 _unused0[2];
80 u8 _tcnt0[3];
81 volatile u8 tcnt0; /* counter 0 */
82 u8 _tcnt1[3];
83 volatile u8 tcnt1; /* counter 1 */
84 u8 _tcnt2[3];
85 volatile u8 tcnt2; /* counter 2 */
86 u8 _tcword[3];
87 volatile u8 tcword; /* control word */
88#define SGINT_TCWORD_BCD 0x01 /* Use BCD mode for counters */
89#define SGINT_TCWORD_MMASK 0x0e /* Mode bitmask. */
90#define SGINT_TCWORD_MITC 0x00 /* IRQ on terminal count (doesn't work) */
91#define SGINT_TCWORD_MOS 0x02 /* One-shot IRQ mode. */
92#define SGINT_TCWORD_MRGEN 0x04 /* Normal rate generation */
93#define SGINT_TCWORD_MSWGEN 0x06 /* Square wave generator mode */
94#define SGINT_TCWORD_MSWST 0x08 /* Software strobe */
95#define SGINT_TCWORD_MHWST 0x0a /* Hardware strobe */
96#define SGINT_TCWORD_CMASK 0x30 /* Command mask */
97#define SGINT_TCWORD_CLAT 0x00 /* Latch command */
98#define SGINT_TCWORD_CLSB 0x10 /* LSB read/write */
99#define SGINT_TCWORD_CMSB 0x20 /* MSB read/write */
100#define SGINT_TCWORD_CALL 0x30 /* Full counter read/write */
101#define SGINT_TCWORD_CNT0 0x00 /* Select counter zero */
102#define SGINT_TCWORD_CNT1 0x40 /* Select counter one */
103#define SGINT_TCWORD_CNT2 0x80 /* Select counter two */
104#define SGINT_TCWORD_CRBCK 0xc0 /* Readback command */
105};
106
107/*
108 * The timer is the good old 8254. Unlike in PCs it's clocked at exactly 1MHz
109 */
110#define SGINT_TIMER_CLOCK 1000000
111
112/*
113 * This is the constant we're using for calibrating the counter.
114 */
115#define SGINT_TCSAMP_COUNTER ((SGINT_TIMER_CLOCK / HZ) + 255)
116
117/* We need software copies of these because they are write only. */
118extern u8 sgi_ioc_reset, sgi_ioc_write;
119
120struct sgioc_regs {
121 struct pi1_regs pport;
122 u32 _unused0[2];
123 struct sgioc_uart_regs uart;
124 struct sgioc_keyb_regs kbdmouse;
125 u8 _gcsel[3];
126 volatile u8 gcsel;
127 u8 _genctrl[3];
128 volatile u8 genctrl;
129 u8 _panel[3];
130 volatile u8 panel;
131#define SGIOC_PANEL_POWERON 0x01
132#define SGIOC_PANEL_POWERINTR 0x02
133#define SGIOC_PANEL_VOLDNINTR 0x10
134#define SGIOC_PANEL_VOLDNHOLD 0x20
135#define SGIOC_PANEL_VOLUPINTR 0x40
136#define SGIOC_PANEL_VOLUPHOLD 0x80
137 u32 _unused1;
138 u8 _sysid[3];
139 volatile u8 sysid;
140#define SGIOC_SYSID_FULLHOUSE 0x01
141#define SGIOC_SYSID_BOARDREV(x) (((x) & 0x1e) >> 1)
142#define SGIOC_SYSID_CHIPREV(x) (((x) & 0xe0) >> 5)
143 u32 _unused2;
144 u8 _read[3];
145 volatile u8 read;
146 u32 _unused3;
147 u8 _dmasel[3];
148 volatile u8 dmasel;
149#define SGIOC_DMASEL_SCLK10MHZ 0x00 /* use 10MHZ serial clock */
150#define SGIOC_DMASEL_ISDNB 0x01 /* enable isdn B */
151#define SGIOC_DMASEL_ISDNA 0x02 /* enable isdn A */
152#define SGIOC_DMASEL_PPORT 0x04 /* use parallel DMA */
153#define SGIOC_DMASEL_SCLK667MHZ 0x10 /* use 6.67MHZ serial clock */
154#define SGIOC_DMASEL_SCLKEXT 0x20 /* use external serial clock */
155 u32 _unused4;
156 u8 _reset[3];
157 volatile u8 reset;
158#define SGIOC_RESET_PPORT 0x01 /* 0=parport reset, 1=nornal */
159#define SGIOC_RESET_KBDMOUSE 0x02 /* 0=kbdmouse reset, 1=normal */
160#define SGIOC_RESET_EISA 0x04 /* 0=eisa reset, 1=normal */
161#define SGIOC_RESET_ISDN 0x08 /* 0=isdn reset, 1=normal */
162#define SGIOC_RESET_LC0OFF 0x10 /* guiness: turn led off (red, else green) */
163#define SGIOC_RESET_LC1OFF 0x20 /* guiness: turn led off (green, else amber) */
164 u32 _unused5;
165 u8 _write[3];
166 volatile u8 write;
167#define SGIOC_WRITE_NTHRESH 0x01 /* use 4.5db threshhold */
168#define SGIOC_WRITE_TPSPEED 0x02 /* use 100ohm TP speed */
169#define SGIOC_WRITE_EPSEL 0x04 /* force cable mode: 1=AUI 0=TP */
170#define SGIOC_WRITE_EASEL 0x08 /* 1=autoselect 0=manual cable selection */
171#define SGIOC_WRITE_U1AMODE 0x10 /* 1=PC 0=MAC UART mode */
172#define SGIOC_WRITE_U0AMODE 0x20 /* 1=PC 0=MAC UART mode */
173#define SGIOC_WRITE_MLO 0x40 /* 1=4.75V 0=+5V */
174#define SGIOC_WRITE_MHI 0x80 /* 1=5.25V 0=+5V */
175 u32 _unused6;
176 struct sgint_regs int3;
177 u32 _unused7[16];
178 volatile u32 extio; /* FullHouse only */
179#define EXTIO_S0_IRQ_3 0x8000 /* S0: vid.vsync */
180#define EXTIO_S0_IRQ_2 0x4000 /* S0: gfx.fifofull */
181#define EXTIO_S0_IRQ_1 0x2000 /* S0: gfx.int */
182#define EXTIO_S0_RETRACE 0x1000
183#define EXTIO_SG_IRQ_3 0x0800 /* SG: vid.vsync */
184#define EXTIO_SG_IRQ_2 0x0400 /* SG: gfx.fifofull */
185#define EXTIO_SG_IRQ_1 0x0200 /* SG: gfx.int */
186#define EXTIO_SG_RETRACE 0x0100
187#define EXTIO_GIO_33MHZ 0x0080
188#define EXTIO_EISA_BUSERR 0x0040
189#define EXTIO_MC_BUSERR 0x0020
190#define EXTIO_HPC3_BUSERR 0x0010
191#define EXTIO_S0_STAT_1 0x0008
192#define EXTIO_S0_STAT_0 0x0004
193#define EXTIO_SG_STAT_1 0x0002
194#define EXTIO_SG_STAT_0 0x0001
195};
196
197extern struct sgioc_regs *sgioc;
198extern struct sgint_regs *sgint;
199
200#endif
diff --git a/arch/mips/include/asm/sgi/ip22.h b/arch/mips/include/asm/sgi/ip22.h
new file mode 100644
index 000000000000..c0501f91719b
--- /dev/null
+++ b/arch/mips/include/asm/sgi/ip22.h
@@ -0,0 +1,78 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * ip22.h: Definitions for SGI IP22 machines
7 *
8 * Copyright (C) 1996 David S. Miller
9 * Copyright (C) 1997, 1998, 1999, 2000 Ralf Baechle
10 */
11
12#ifndef _SGI_IP22_H
13#define _SGI_IP22_H
14
15/*
16 * These are the virtual IRQ numbers, we divide all IRQ's into
17 * 'spaces', the 'space' determines where and how to enable/disable
18 * that particular IRQ on an SGI machine. HPC DMA and MC DMA interrupts
19 * are not supported this way. Driver is supposed to allocate HPC/MC
20 * interrupt as shareable and then look to proper status bit (see
21 * HAL2 driver). This will prevent many complications, trust me ;-)
22 */
23
24#include <irq.h>
25#include <asm/sgi/ioc.h>
26
27#define SGINT_EISA 0 /* 16 EISA irq levels (Indigo2) */
28#define SGINT_CPU MIPS_CPU_IRQ_BASE /* MIPS CPU define 8 interrupt sources */
29#define SGINT_LOCAL0 (SGINT_CPU+8) /* 8 local0 irq levels */
30#define SGINT_LOCAL1 (SGINT_CPU+16) /* 8 local1 irq levels */
31#define SGINT_LOCAL2 (SGINT_CPU+24) /* 8 local2 vectored irq levels */
32#define SGINT_LOCAL3 (SGINT_CPU+32) /* 8 local3 vectored irq levels */
33#define SGINT_END (SGINT_CPU+40) /* End of 'spaces' */
34
35/*
36 * Individual interrupt definitions for the Indy and Indigo2
37 */
38
39#define SGI_SOFT_0_IRQ SGINT_CPU + 0
40#define SGI_SOFT_1_IRQ SGINT_CPU + 1
41#define SGI_LOCAL_0_IRQ SGINT_CPU + 2
42#define SGI_LOCAL_1_IRQ SGINT_CPU + 3
43#define SGI_8254_0_IRQ SGINT_CPU + 4
44#define SGI_8254_1_IRQ SGINT_CPU + 5
45#define SGI_BUSERR_IRQ SGINT_CPU + 6
46#define SGI_TIMER_IRQ SGINT_CPU + 7
47
48#define SGI_FIFO_IRQ SGINT_LOCAL0 + 0 /* FIFO full */
49#define SGI_GIO_0_IRQ SGI_FIFO_IRQ /* GIO-0 */
50#define SGI_WD93_0_IRQ SGINT_LOCAL0 + 1 /* 1st onboard WD93 */
51#define SGI_WD93_1_IRQ SGINT_LOCAL0 + 2 /* 2nd onboard WD93 */
52#define SGI_ENET_IRQ SGINT_LOCAL0 + 3 /* onboard ethernet */
53#define SGI_MCDMA_IRQ SGINT_LOCAL0 + 4 /* MC DMA done */
54#define SGI_PARPORT_IRQ SGINT_LOCAL0 + 5 /* Parallel port */
55#define SGI_GIO_1_IRQ SGINT_LOCAL0 + 6 /* GE / GIO-1 / 2nd-HPC */
56#define SGI_MAP_0_IRQ SGINT_LOCAL0 + 7 /* Mappable interrupt 0 */
57
58#define SGI_GPL0_IRQ SGINT_LOCAL1 + 0 /* General Purpose LOCAL1_N<0> */
59#define SGI_PANEL_IRQ SGINT_LOCAL1 + 1 /* front panel */
60#define SGI_GPL2_IRQ SGINT_LOCAL1 + 2 /* General Purpose LOCAL1_N<2> */
61#define SGI_MAP_1_IRQ SGINT_LOCAL1 + 3 /* Mappable interrupt 1 */
62#define SGI_HPCDMA_IRQ SGINT_LOCAL1 + 4 /* HPC DMA done */
63#define SGI_ACFAIL_IRQ SGINT_LOCAL1 + 5 /* AC fail */
64#define SGI_VINO_IRQ SGINT_LOCAL1 + 6 /* Indy VINO */
65#define SGI_GIO_2_IRQ SGINT_LOCAL1 + 7 /* Vert retrace / GIO-2 */
66
67/* Mapped interrupts. These interrupts may be mapped to either 0, or 1 */
68#define SGI_VERT_IRQ SGINT_LOCAL2 + 0 /* INT3: newport vertical status */
69#define SGI_EISA_IRQ SGINT_LOCAL2 + 3 /* EISA interrupts */
70#define SGI_KEYBD_IRQ SGINT_LOCAL2 + 4 /* keyboard */
71#define SGI_SERIAL_IRQ SGINT_LOCAL2 + 5 /* onboard serial */
72
73#define ip22_is_fullhouse() (sgioc->sysid & SGIOC_SYSID_FULLHOUSE)
74
75extern unsigned short ip22_eeprom_read(unsigned int *ctrl, int reg);
76extern unsigned short ip22_nvram_read(int reg);
77
78#endif
diff --git a/arch/mips/include/asm/sgi/mc.h b/arch/mips/include/asm/sgi/mc.h
new file mode 100644
index 000000000000..1576c2394de8
--- /dev/null
+++ b/arch/mips/include/asm/sgi/mc.h
@@ -0,0 +1,231 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * mc.h: Definitions for SGI Memory Controller
7 *
8 * Copyright (C) 1996 David S. Miller
9 * Copyright (C) 1999 Ralf Baechle
10 * Copyright (C) 1999 Silicon Graphics, Inc.
11 */
12
13#ifndef _SGI_MC_H
14#define _SGI_MC_H
15
16struct sgimc_regs {
17 u32 _unused0;
18 volatile u32 cpuctrl0; /* CPU control register 0, readwrite */
19#define SGIMC_CCTRL0_REFS 0x0000000f /* REFS mask */
20#define SGIMC_CCTRL0_EREFRESH 0x00000010 /* Memory refresh enable */
21#define SGIMC_CCTRL0_EPERRGIO 0x00000020 /* GIO parity error enable */
22#define SGIMC_CCTRL0_EPERRMEM 0x00000040 /* Main mem parity error enable */
23#define SGIMC_CCTRL0_EPERRCPU 0x00000080 /* CPU bus parity error enable */
24#define SGIMC_CCTRL0_WDOG 0x00000100 /* Watchdog timer enable */
25#define SGIMC_CCTRL0_SYSINIT 0x00000200 /* System init bit */
26#define SGIMC_CCTRL0_GFXRESET 0x00000400 /* Graphics interface reset */
27#define SGIMC_CCTRL0_EISALOCK 0x00000800 /* Lock CPU from memory for EISA */
28#define SGIMC_CCTRL0_EPERRSCMD 0x00001000 /* SysCMD bus parity error enable */
29#define SGIMC_CCTRL0_IENAB 0x00002000 /* Allow interrupts from MC */
30#define SGIMC_CCTRL0_ESNOOP 0x00004000 /* Snooping I/O enable */
31#define SGIMC_CCTRL0_EPROMWR 0x00008000 /* Prom writes from cpu enable */
32#define SGIMC_CCTRL0_WRESETPMEM 0x00010000 /* Perform warm reset, preserves mem */
33#define SGIMC_CCTRL0_LENDIAN 0x00020000 /* Put MC in little-endian mode */
34#define SGIMC_CCTRL0_WRESETDMEM 0x00040000 /* Warm reset, destroys mem contents */
35#define SGIMC_CCTRL0_CMEMBADPAR 0x02000000 /* Generate bad perr from cpu to mem */
36#define SGIMC_CCTRL0_R4KNOCHKPARR 0x04000000 /* Don't chk parity on mem data reads */
37#define SGIMC_CCTRL0_GIOBTOB 0x08000000 /* Allow GIO back to back writes */
38 u32 _unused1;
39 volatile u32 cpuctrl1; /* CPU control register 1, readwrite */
40#define SGIMC_CCTRL1_EGIOTIMEO 0x00000010 /* GIO bus timeout enable */
41#define SGIMC_CCTRL1_FIXEDEHPC 0x00001000 /* Fixed HPC endianness */
42#define SGIMC_CCTRL1_LITTLEHPC 0x00002000 /* Little endian HPC */
43#define SGIMC_CCTRL1_FIXEDEEXP0 0x00004000 /* Fixed EXP0 endianness */
44#define SGIMC_CCTRL1_LITTLEEXP0 0x00008000 /* Little endian EXP0 */
45#define SGIMC_CCTRL1_FIXEDEEXP1 0x00010000 /* Fixed EXP1 endianness */
46#define SGIMC_CCTRL1_LITTLEEXP1 0x00020000 /* Little endian EXP1 */
47
48 u32 _unused2;
49 volatile u32 watchdogt; /* Watchdog reg rdonly, write clears */
50
51 u32 _unused3;
52 volatile u32 systemid; /* MC system ID register, readonly */
53#define SGIMC_SYSID_MASKREV 0x0000000f /* Revision of MC controller */
54#define SGIMC_SYSID_EPRESENT 0x00000010 /* Indicates presence of EISA bus */
55
56 u32 _unused4[3];
57 volatile u32 divider; /* Divider reg for RPSS */
58
59 u32 _unused5;
60 u32 eeprom; /* EEPROM byte reg for r4k */
61#define SGIMC_EEPROM_PRE 0x00000001 /* eeprom chip PRE pin assertion */
62#define SGIMC_EEPROM_CSEL 0x00000002 /* Active high, eeprom chip select */
63#define SGIMC_EEPROM_SECLOCK 0x00000004 /* EEPROM serial clock */
64#define SGIMC_EEPROM_SDATAO 0x00000008 /* Serial EEPROM data-out */
65#define SGIMC_EEPROM_SDATAI 0x00000010 /* Serial EEPROM data-in */
66
67 u32 _unused6[3];
68 volatile u32 rcntpre; /* Preload refresh counter */
69
70 u32 _unused7;
71 volatile u32 rcounter; /* Readonly refresh counter */
72
73 u32 _unused8[13];
74 volatile u32 giopar; /* Parameter word for GIO64 */
75#define SGIMC_GIOPAR_HPC64 0x00000001 /* HPC talks to GIO using 64-bits */
76#define SGIMC_GIOPAR_GFX64 0x00000002 /* GFX talks to GIO using 64-bits */
77#define SGIMC_GIOPAR_EXP064 0x00000004 /* EXP(slot0) talks using 64-bits */
78#define SGIMC_GIOPAR_EXP164 0x00000008 /* EXP(slot1) talks using 64-bits */
79#define SGIMC_GIOPAR_EISA64 0x00000010 /* EISA bus talks 64-bits to GIO */
80#define SGIMC_GIOPAR_HPC264 0x00000020 /* 2nd HPX talks 64-bits to GIO */
81#define SGIMC_GIOPAR_RTIMEGFX 0x00000040 /* GFX device has realtime attr */
82#define SGIMC_GIOPAR_RTIMEEXP0 0x00000080 /* EXP(slot0) has realtime attr */
83#define SGIMC_GIOPAR_RTIMEEXP1 0x00000100 /* EXP(slot1) has realtime attr */
84#define SGIMC_GIOPAR_MASTEREISA 0x00000200 /* EISA bus can act as bus master */
85#define SGIMC_GIOPAR_ONEBUS 0x00000400 /* Exists one GIO64 pipelined bus */
86#define SGIMC_GIOPAR_MASTERGFX 0x00000800 /* GFX can act as a bus master */
87#define SGIMC_GIOPAR_MASTEREXP0 0x00001000 /* EXP(slot0) can bus master */
88#define SGIMC_GIOPAR_MASTEREXP1 0x00002000 /* EXP(slot1) can bus master */
89#define SGIMC_GIOPAR_PLINEEXP0 0x00004000 /* EXP(slot0) has pipeline attr */
90#define SGIMC_GIOPAR_PLINEEXP1 0x00008000 /* EXP(slot1) has pipeline attr */
91
92 u32 _unused9;
93 volatile u32 cputp; /* CPU bus arb time period */
94
95 u32 _unused10[3];
96 volatile u32 lbursttp; /* Time period for long bursts */
97
98 /* MC chip can drive up to 4 bank 4 SIMMs each. All SIMMs in bank must
99 * be the same size. The size encoding for supported SIMMs is bellow */
100 u32 _unused11[9];
101 volatile u32 mconfig0; /* Memory config register zero */
102 u32 _unused12;
103 volatile u32 mconfig1; /* Memory config register one */
104#define SGIMC_MCONFIG_BASEADDR 0x000000ff /* Base address of bank*/
105#define SGIMC_MCONFIG_RMASK 0x00001f00 /* Ram config bitmask */
106#define SGIMC_MCONFIG_BVALID 0x00002000 /* Bank is valid */
107#define SGIMC_MCONFIG_SBANKS 0x00004000 /* Number of subbanks */
108
109 u32 _unused13;
110 volatile u32 cmacc; /* Mem access config for CPU */
111 u32 _unused14;
112 volatile u32 gmacc; /* Mem access config for GIO */
113
114 /* This define applies to both cmacc and gmacc registers above. */
115#define SGIMC_MACC_ALIASBIG 0x20000000 /* 512MB home for alias */
116
117 /* Error address/status regs from GIO and CPU perspectives. */
118 u32 _unused15;
119 volatile u32 cerr; /* Error address reg for CPU */
120 u32 _unused16;
121 volatile u32 cstat; /* Status reg for CPU */
122#define SGIMC_CSTAT_RD 0x00000100 /* read parity error */
123#define SGIMC_CSTAT_PAR 0x00000200 /* CPU parity error */
124#define SGIMC_CSTAT_ADDR 0x00000400 /* memory bus error bad addr */
125#define SGIMC_CSTAT_SYSAD_PAR 0x00000800 /* sysad parity error */
126#define SGIMC_CSTAT_SYSCMD_PAR 0x00001000 /* syscmd parity error */
127#define SGIMC_CSTAT_BAD_DATA 0x00002000 /* bad data identifier */
128#define SGIMC_CSTAT_PAR_MASK 0x00001f00 /* parity error mask */
129#define SGIMC_CSTAT_RD_PAR (SGIMC_CSTAT_RD | SGIMC_CSTAT_PAR)
130
131 u32 _unused17;
132 volatile u32 gerr; /* Error address reg for GIO */
133 u32 _unused18;
134 volatile u32 gstat; /* Status reg for GIO */
135#define SGIMC_GSTAT_RD 0x00000100 /* read parity error */
136#define SGIMC_GSTAT_WR 0x00000200 /* write parity error */
137#define SGIMC_GSTAT_TIME 0x00000400 /* GIO bus timed out */
138#define SGIMC_GSTAT_PROM 0x00000800 /* write to PROM when PROM_EN not set */
139#define SGIMC_GSTAT_ADDR 0x00001000 /* parity error on addr cycle */
140#define SGIMC_GSTAT_BC 0x00002000 /* parity error on byte count cycle */
141#define SGIMC_GSTAT_PIO_RD 0x00004000 /* read data parity on pio */
142#define SGIMC_GSTAT_PIO_WR 0x00008000 /* write data parity on pio */
143
144 /* Special hard bus locking registers. */
145 u32 _unused19;
146 volatile u32 syssembit; /* Uni-bit system semaphore */
147 u32 _unused20;
148 volatile u32 mlock; /* Global GIO memory access lock */
149 u32 _unused21;
150 volatile u32 elock; /* Locks EISA from GIO accesses */
151
152 /* GIO dma control registers. */
153 u32 _unused22[15];
154 volatile u32 gio_dma_trans; /* DMA mask to translation GIO addrs */
155 u32 _unused23;
156 volatile u32 gio_dma_sbits; /* DMA GIO addr substitution bits */
157 u32 _unused24;
158 volatile u32 dma_intr_cause; /* DMA IRQ cause indicator bits */
159 u32 _unused25;
160 volatile u32 dma_ctrl; /* Main DMA control reg */
161
162 /* DMA TLB entry 0 */
163 u32 _unused26[5];
164 volatile u32 dtlb_hi0;
165 u32 _unused27;
166 volatile u32 dtlb_lo0;
167
168 /* DMA TLB entry 1 */
169 u32 _unused28;
170 volatile u32 dtlb_hi1;
171 u32 _unused29;
172 volatile u32 dtlb_lo1;
173
174 /* DMA TLB entry 2 */
175 u32 _unused30;
176 volatile u32 dtlb_hi2;
177 u32 _unused31;
178 volatile u32 dtlb_lo2;
179
180 /* DMA TLB entry 3 */
181 u32 _unused32;
182 volatile u32 dtlb_hi3;
183 u32 _unused33;
184 volatile u32 dtlb_lo3;
185
186 u32 _unused34[0x0392];
187
188 u32 _unused35;
189 volatile u32 rpsscounter; /* Chirps at 100ns */
190
191 u32 _unused36[0x1000/4-2*4];
192
193 u32 _unused37;
194 volatile u32 maddronly; /* Address DMA goes at */
195 u32 _unused38;
196 volatile u32 maddrpdeflts; /* Same as above, plus set defaults */
197 u32 _unused39;
198 volatile u32 dmasz; /* DMA count */
199 u32 _unused40;
200 volatile u32 ssize; /* DMA stride size */
201 u32 _unused41;
202 volatile u32 gmaddronly; /* Set GIO DMA but don't start trans */
203 u32 _unused42;
204 volatile u32 dmaddnpgo; /* Set GIO DMA addr + start transfer */
205 u32 _unused43;
206 volatile u32 dmamode; /* DMA mode config bit settings */
207 u32 _unused44;
208 volatile u32 dmaccount; /* Zoom and byte count for DMA */
209 u32 _unused45;
210 volatile u32 dmastart; /* Pedal to the metal. */
211 u32 _unused46;
212 volatile u32 dmarunning; /* DMA op is in progress */
213 u32 _unused47;
214 volatile u32 maddrdefstart; /* Set dma addr, defaults, and kick it */
215};
216
217extern struct sgimc_regs *sgimc;
218#define SGIMC_BASE 0x1fa00000 /* physical */
219
220/* Base location of the two ram banks found in IP2[0268] machines. */
221#define SGIMC_SEG0_BADDR 0x08000000
222#define SGIMC_SEG1_BADDR 0x20000000
223
224/* Maximum size of the above banks are per machine. */
225#define SGIMC_SEG0_SIZE_ALL 0x10000000 /* 256MB */
226#define SGIMC_SEG1_SIZE_IP20_IP22 0x08000000 /* 128MB */
227#define SGIMC_SEG1_SIZE_IP26_IP28 0x20000000 /* 512MB */
228
229extern void sgimc_init(void);
230
231#endif /* _SGI_MC_H */
diff --git a/arch/mips/include/asm/sgi/pi1.h b/arch/mips/include/asm/sgi/pi1.h
new file mode 100644
index 000000000000..c9506915dc5c
--- /dev/null
+++ b/arch/mips/include/asm/sgi/pi1.h
@@ -0,0 +1,71 @@
1/*
2 * pi1.h: Definitions for SGI PI1 parallel port
3 */
4
5#ifndef _SGI_PI1_H
6#define _SGI_PI1_H
7
8struct pi1_regs {
9 u8 _data[3];
10 volatile u8 data;
11 u8 _ctrl[3];
12 volatile u8 ctrl;
13#define PI1_CTRL_STROBE_N 0x01
14#define PI1_CTRL_AFD_N 0x02
15#define PI1_CTRL_INIT_N 0x04
16#define PI1_CTRL_SLIN_N 0x08
17#define PI1_CTRL_IRQ_ENA 0x10
18#define PI1_CTRL_DIR 0x20
19#define PI1_CTRL_SEL 0x40
20 u8 _status[3];
21 volatile u8 status;
22#define PI1_STAT_DEVID 0x03 /* bits 0-1 */
23#define PI1_STAT_NOINK 0x04 /* SGI MODE only */
24#define PI1_STAT_ERROR 0x08
25#define PI1_STAT_ONLINE 0x10
26#define PI1_STAT_PE 0x20
27#define PI1_STAT_ACK 0x40
28#define PI1_STAT_BUSY 0x80
29 u8 _dmactrl[3];
30 volatile u8 dmactrl;
31#define PI1_DMACTRL_FIFO_EMPTY 0x01 /* fifo empty R/O */
32#define PI1_DMACTRL_ABORT 0x02 /* reset DMA and internal fifo W/O */
33#define PI1_DMACTRL_STDMODE 0x00 /* bits 2-3 */
34#define PI1_DMACTRL_SGIMODE 0x04 /* bits 2-3 */
35#define PI1_DMACTRL_RICOHMODE 0x08 /* bits 2-3 */
36#define PI1_DMACTRL_HPMODE 0x0c /* bits 2-3 */
37#define PI1_DMACTRL_BLKMODE 0x10 /* block mode */
38#define PI1_DMACTRL_FIFO_CLEAR 0x20 /* clear fifo W/O */
39#define PI1_DMACTRL_READ 0x40 /* read */
40#define PI1_DMACTRL_RUN 0x80 /* pedal to the metal */
41 u8 _intstat[3];
42 volatile u8 intstat;
43#define PI1_INTSTAT_ACK 0x04
44#define PI1_INTSTAT_FEMPTY 0x08
45#define PI1_INTSTAT_NOINK 0x10
46#define PI1_INTSTAT_ONLINE 0x20
47#define PI1_INTSTAT_ERR 0x40
48#define PI1_INTSTAT_PE 0x80
49 u8 _intmask[3];
50 volatile u8 intmask; /* enabled low, reset high*/
51#define PI1_INTMASK_ACK 0x04
52#define PI1_INTMASK_FIFO_EMPTY 0x08
53#define PI1_INTMASK_NOINK 0x10
54#define PI1_INTMASK_ONLINE 0x20
55#define PI1_INTMASK_ERR 0x40
56#define PI1_INTMASK_PE 0x80
57 u8 _timer1[3];
58 volatile u8 timer1;
59#define PI1_TIME1 0x27
60 u8 _timer2[3];
61 volatile u8 timer2;
62#define PI1_TIME2 0x13
63 u8 _timer3[3];
64 volatile u8 timer3;
65#define PI1_TIME3 0x10
66 u8 _timer4[3];
67 volatile u8 timer4;
68#define PI1_TIME4 0x00
69};
70
71#endif
diff --git a/arch/mips/include/asm/sgi/seeq.h b/arch/mips/include/asm/sgi/seeq.h
new file mode 100644
index 000000000000..af0ffd76899d
--- /dev/null
+++ b/arch/mips/include/asm/sgi/seeq.h
@@ -0,0 +1,21 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2007 by Ralf Baechle
7 */
8#ifndef __ASM_SGI_SEEQ_H
9#define __ASM_SGI_SEEQ_H
10
11#include <linux/if_ether.h>
12
13#include <asm/sgi/hpc3.h>
14
15struct sgiseeq_platform_data {
16 struct hpc3_regs *hpc;
17 unsigned int irq;
18 unsigned char mac[ETH_ALEN];
19};
20
21#endif /* __ASM_SGI_SEEQ_H */
diff --git a/arch/mips/include/asm/sgi/sgi.h b/arch/mips/include/asm/sgi/sgi.h
new file mode 100644
index 000000000000..645cea7c0f8e
--- /dev/null
+++ b/arch/mips/include/asm/sgi/sgi.h
@@ -0,0 +1,47 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * sgi.h: Definitions specific to SGI machines.
7 *
8 * Copyright (C) 1996 David S. Miller (dm@sgi.com)
9 */
10#ifndef _ASM_SGI_SGI_H
11#define _ASM_SGI_SGI_H
12
13/* UP=UniProcessor MP=MultiProcessor(capable) */
14enum sgi_mach {
15 ip4, /* R2k UP */
16 ip5, /* R2k MP */
17 ip6, /* R3k UP */
18 ip7, /* R3k MP */
19 ip9, /* R3k UP */
20 ip12, /* R3kA UP, Indigo */
21 ip15, /* R3kA MP */
22 ip17, /* R4K UP */
23 ip19, /* R4K MP */
24 ip20, /* R4K UP, Indigo */
25 ip21, /* TFP MP */
26 ip22, /* R4x00 UP, Indigo2 */
27 ip25, /* R10k MP */
28 ip26, /* TFP UP, Indigo2 */
29 ip27, /* R10k MP, R12k MP, Origin */
30 ip28, /* R10k UP, Indigo2 */
31 ip30, /* Octane */
32 ip32, /* O2 */
33};
34
35extern enum sgi_mach sgimach;
36extern void sgi_sysinit(void);
37
38/* Many I/O space registers are byte sized and are contained within
39 * one byte per word, specifically the MSB, this macro helps out.
40 */
41#ifdef __MIPSEL__
42#define SGI_MSB(regaddr) (regaddr)
43#else
44#define SGI_MSB(regaddr) ((regaddr) | 0x3)
45#endif
46
47#endif /* _ASM_SGI_SGI_H */
diff --git a/arch/mips/include/asm/sgi/wd.h b/arch/mips/include/asm/sgi/wd.h
new file mode 100644
index 000000000000..0d6c3a4da891
--- /dev/null
+++ b/arch/mips/include/asm/sgi/wd.h
@@ -0,0 +1,20 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2007 by Ralf Baechle
7 */
8#ifndef __ASM_SGI_WD_H
9#define __ASM_SGI_WD_H
10
11#include <asm/sgi/hpc3.h>
12
13struct sgiwd93_platform_data {
14 unsigned int unit;
15 unsigned int irq;
16 struct hpc3_scsiregs *hregs;
17 unsigned char *wdregs;
18};
19
20#endif /* __ASM_SGI_WD_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-07 10:49:22 -0500