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-rw-r--r--arch/mips/include/asm/pgtable-bits.h42
1 files changed, 21 insertions, 21 deletions
diff --git a/arch/mips/include/asm/pgtable-bits.h b/arch/mips/include/asm/pgtable-bits.h
index f6a0439a4085..32aea4852fb0 100644
--- a/arch/mips/include/asm/pgtable-bits.h
+++ b/arch/mips/include/asm/pgtable-bits.h
@@ -21,7 +21,7 @@
21 * Similar to the Alpha port, we need to keep track of the ref 21 * Similar to the Alpha port, we need to keep track of the ref
22 * and mod bits in software. We have a software "yeah you can read 22 * and mod bits in software. We have a software "yeah you can read
23 * from this page" bit, and a hardware one which actually lets the 23 * from this page" bit, and a hardware one which actually lets the
24 * process read from the page. On the same token we have a software 24 * process read from the page. On the same token we have a software
25 * writable bit and the real hardware one which actually lets the 25 * writable bit and the real hardware one which actually lets the
26 * process write to the page, this keeps a mod bit via the hardware 26 * process write to the page, this keeps a mod bit via the hardware
27 * dirty bit. 27 * dirty bit.
@@ -41,9 +41,9 @@
41#define _PAGE_GLOBAL (1 << 0) 41#define _PAGE_GLOBAL (1 << 0)
42#define _PAGE_VALID_SHIFT 1 42#define _PAGE_VALID_SHIFT 1
43#define _PAGE_VALID (1 << _PAGE_VALID_SHIFT) 43#define _PAGE_VALID (1 << _PAGE_VALID_SHIFT)
44#define _PAGE_SILENT_READ (1 << 1) /* synonym */ 44#define _PAGE_SILENT_READ (1 << 1) /* synonym */
45#define _PAGE_DIRTY_SHIFT 2 45#define _PAGE_DIRTY_SHIFT 2
46#define _PAGE_DIRTY (1 << _PAGE_DIRTY_SHIFT) /* The MIPS dirty bit */ 46#define _PAGE_DIRTY (1 << _PAGE_DIRTY_SHIFT) /* The MIPS dirty bit */
47#define _PAGE_SILENT_WRITE (1 << 2) 47#define _PAGE_SILENT_WRITE (1 << 2)
48#define _CACHE_SHIFT 3 48#define _CACHE_SHIFT 3
49#define _CACHE_MASK (7 << 3) 49#define _CACHE_MASK (7 << 3)
@@ -52,7 +52,7 @@
52 * The following bits are implemented in software 52 * The following bits are implemented in software
53 * 53 *
54 * _PAGE_FILE semantics: set:pagecache unset:swap 54 * _PAGE_FILE semantics: set:pagecache unset:swap
55 */ 55 */
56#define _PAGE_PRESENT_SHIFT 6 56#define _PAGE_PRESENT_SHIFT 6
57#define _PAGE_PRESENT (1 << _PAGE_PRESENT_SHIFT) 57#define _PAGE_PRESENT (1 << _PAGE_PRESENT_SHIFT)
58#define _PAGE_READ_SHIFT 7 58#define _PAGE_READ_SHIFT 7
@@ -134,7 +134,7 @@
134#define _PAGE_HUGE (1 << _PAGE_HUGE_SHIFT) 134#define _PAGE_HUGE (1 << _PAGE_HUGE_SHIFT)
135#else 135#else
136#define _PAGE_HUGE_SHIFT (_PAGE_MODIFIED_SHIFT) 136#define _PAGE_HUGE_SHIFT (_PAGE_MODIFIED_SHIFT)
137#define _PAGE_HUGE ({BUG(); 1; }) /* Dummy value */ 137#define _PAGE_HUGE ({BUG(); 1; }) /* Dummy value */
138#endif 138#endif
139 139
140#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 140#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
@@ -143,7 +143,7 @@
143#define _PAGE_SPLITTING (1 << _PAGE_SPLITTING_SHIFT) 143#define _PAGE_SPLITTING (1 << _PAGE_SPLITTING_SHIFT)
144#else 144#else
145#define _PAGE_SPLITTING_SHIFT (_PAGE_HUGE_SHIFT) 145#define _PAGE_SPLITTING_SHIFT (_PAGE_HUGE_SHIFT)
146#define _PAGE_SPLITTING ({BUG(); 1; }) /* Dummy value */ 146#define _PAGE_SPLITTING ({BUG(); 1; }) /* Dummy value */
147#endif 147#endif
148 148
149/* Page cannot be executed */ 149/* Page cannot be executed */
@@ -159,10 +159,10 @@
159 159
160#define _PAGE_VALID_SHIFT (_PAGE_GLOBAL_SHIFT + 1) 160#define _PAGE_VALID_SHIFT (_PAGE_GLOBAL_SHIFT + 1)
161#define _PAGE_VALID (1 << _PAGE_VALID_SHIFT) 161#define _PAGE_VALID (1 << _PAGE_VALID_SHIFT)
162/* synonym */ 162/* synonym */
163#define _PAGE_SILENT_READ (_PAGE_VALID) 163#define _PAGE_SILENT_READ (_PAGE_VALID)
164 164
165/* The MIPS dirty bit */ 165/* The MIPS dirty bit */
166#define _PAGE_DIRTY_SHIFT (_PAGE_VALID_SHIFT + 1) 166#define _PAGE_DIRTY_SHIFT (_PAGE_VALID_SHIFT + 1)
167#define _PAGE_DIRTY (1 << _PAGE_DIRTY_SHIFT) 167#define _PAGE_DIRTY (1 << _PAGE_DIRTY_SHIFT)
168#define _PAGE_SILENT_WRITE (_PAGE_DIRTY) 168#define _PAGE_SILENT_WRITE (_PAGE_DIRTY)
@@ -175,7 +175,7 @@
175#endif /* defined(CONFIG_64BIT_PHYS_ADDR && defined(CONFIG_CPU_MIPS32) */ 175#endif /* defined(CONFIG_64BIT_PHYS_ADDR && defined(CONFIG_CPU_MIPS32) */
176 176
177#ifndef _PFN_SHIFT 177#ifndef _PFN_SHIFT
178#define _PFN_SHIFT PAGE_SHIFT 178#define _PFN_SHIFT PAGE_SHIFT
179#endif 179#endif
180#define _PFN_MASK (~((1 << (_PFN_SHIFT)) - 1)) 180#define _PFN_MASK (~((1 << (_PFN_SHIFT)) - 1))
181 181
@@ -230,28 +230,28 @@ static inline uint64_t pte_to_entrylo(unsigned long pte_val)
230/* No penalty for being coherent on the SB1, so just 230/* No penalty for being coherent on the SB1, so just
231 use it for "noncoherent" spaces, too. Shouldn't hurt. */ 231 use it for "noncoherent" spaces, too. Shouldn't hurt. */
232 232
233#define _CACHE_UNCACHED (2<<_CACHE_SHIFT) 233#define _CACHE_UNCACHED (2<<_CACHE_SHIFT)
234#define _CACHE_CACHABLE_COW (5<<_CACHE_SHIFT) 234#define _CACHE_CACHABLE_COW (5<<_CACHE_SHIFT)
235#define _CACHE_CACHABLE_NONCOHERENT (5<<_CACHE_SHIFT) 235#define _CACHE_CACHABLE_NONCOHERENT (5<<_CACHE_SHIFT)
236#define _CACHE_UNCACHED_ACCELERATED (7<<_CACHE_SHIFT) 236#define _CACHE_UNCACHED_ACCELERATED (7<<_CACHE_SHIFT)
237 237
238#else 238#else
239 239
240#define _CACHE_CACHABLE_NO_WA (0<<_CACHE_SHIFT) /* R4600 only */ 240#define _CACHE_CACHABLE_NO_WA (0<<_CACHE_SHIFT) /* R4600 only */
241#define _CACHE_CACHABLE_WA (1<<_CACHE_SHIFT) /* R4600 only */ 241#define _CACHE_CACHABLE_WA (1<<_CACHE_SHIFT) /* R4600 only */
242#define _CACHE_UNCACHED (2<<_CACHE_SHIFT) /* R4[0246]00 */ 242#define _CACHE_UNCACHED (2<<_CACHE_SHIFT) /* R4[0246]00 */
243#define _CACHE_CACHABLE_NONCOHERENT (3<<_CACHE_SHIFT) /* R4[0246]00 */ 243#define _CACHE_CACHABLE_NONCOHERENT (3<<_CACHE_SHIFT) /* R4[0246]00 */
244#define _CACHE_CACHABLE_CE (4<<_CACHE_SHIFT) /* R4[04]00MC only */ 244#define _CACHE_CACHABLE_CE (4<<_CACHE_SHIFT) /* R4[04]00MC only */
245#define _CACHE_CACHABLE_COW (5<<_CACHE_SHIFT) /* R4[04]00MC only */ 245#define _CACHE_CACHABLE_COW (5<<_CACHE_SHIFT) /* R4[04]00MC only */
246#define _CACHE_CACHABLE_COHERENT (5<<_CACHE_SHIFT) /* MIPS32R2 CMP */ 246#define _CACHE_CACHABLE_COHERENT (5<<_CACHE_SHIFT) /* MIPS32R2 CMP */
247#define _CACHE_CACHABLE_CUW (6<<_CACHE_SHIFT) /* R4[04]00MC only */ 247#define _CACHE_CACHABLE_CUW (6<<_CACHE_SHIFT) /* R4[04]00MC only */
248#define _CACHE_UNCACHED_ACCELERATED (7<<_CACHE_SHIFT) /* R10000 only */ 248#define _CACHE_UNCACHED_ACCELERATED (7<<_CACHE_SHIFT) /* R10000 only */
249 249
250#endif 250#endif
251 251
252#define __READABLE (_PAGE_SILENT_READ | _PAGE_ACCESSED | (cpu_has_rixi ? 0 : _PAGE_READ)) 252#define __READABLE (_PAGE_SILENT_READ | _PAGE_ACCESSED | (cpu_has_rixi ? 0 : _PAGE_READ))
253#define __WRITEABLE (_PAGE_WRITE | _PAGE_SILENT_WRITE | _PAGE_MODIFIED) 253#define __WRITEABLE (_PAGE_WRITE | _PAGE_SILENT_WRITE | _PAGE_MODIFIED)
254 254
255#define _PAGE_CHG_MASK (_PFN_MASK | _PAGE_ACCESSED | _PAGE_MODIFIED | _CACHE_MASK) 255#define _PAGE_CHG_MASK (_PFN_MASK | _PAGE_ACCESSED | _PAGE_MODIFIED | _CACHE_MASK)
256 256
257#endif /* _ASM_PGTABLE_BITS_H */ 257#endif /* _ASM_PGTABLE_BITS_H */