diff options
Diffstat (limited to 'arch/mips/include/asm/octeon/cvmx.h')
-rw-r--r-- | arch/mips/include/asm/octeon/cvmx.h | 48 |
1 files changed, 24 insertions, 24 deletions
diff --git a/arch/mips/include/asm/octeon/cvmx.h b/arch/mips/include/asm/octeon/cvmx.h index db58beab6cb2..f991e7701d3d 100644 --- a/arch/mips/include/asm/octeon/cvmx.h +++ b/arch/mips/include/asm/octeon/cvmx.h | |||
@@ -76,14 +76,14 @@ enum cvmx_mips_space { | |||
76 | #endif | 76 | #endif |
77 | 77 | ||
78 | #if CVMX_ENABLE_DEBUG_PRINTS | 78 | #if CVMX_ENABLE_DEBUG_PRINTS |
79 | #define cvmx_dprintf printk | 79 | #define cvmx_dprintf printk |
80 | #else | 80 | #else |
81 | #define cvmx_dprintf(...) {} | 81 | #define cvmx_dprintf(...) {} |
82 | #endif | 82 | #endif |
83 | 83 | ||
84 | #define CVMX_MAX_CORES (16) | 84 | #define CVMX_MAX_CORES (16) |
85 | #define CVMX_CACHE_LINE_SIZE (128) /* In bytes */ | 85 | #define CVMX_CACHE_LINE_SIZE (128) /* In bytes */ |
86 | #define CVMX_CACHE_LINE_MASK (CVMX_CACHE_LINE_SIZE - 1) /* In bytes */ | 86 | #define CVMX_CACHE_LINE_MASK (CVMX_CACHE_LINE_SIZE - 1) /* In bytes */ |
87 | #define CVMX_CACHE_LINE_ALIGNED __attribute__ ((aligned(CVMX_CACHE_LINE_SIZE))) | 87 | #define CVMX_CACHE_LINE_ALIGNED __attribute__ ((aligned(CVMX_CACHE_LINE_SIZE))) |
88 | #define CAST64(v) ((long long)(long)(v)) | 88 | #define CAST64(v) ((long long)(long)(v)) |
89 | #define CASTPTR(type, v) ((type *)(long)(v)) | 89 | #define CASTPTR(type, v) ((type *)(long)(v)) |
@@ -133,8 +133,8 @@ static inline uint64_t cvmx_build_io_address(uint64_t major_did, | |||
133 | * | 133 | * |
134 | * Example: cvmx_build_bits(39,24,value) | 134 | * Example: cvmx_build_bits(39,24,value) |
135 | * <pre> | 135 | * <pre> |
136 | * 6 5 4 3 3 2 1 | 136 | * 6 5 4 3 3 2 1 |
137 | * 3 5 7 9 1 3 5 7 0 | 137 | * 3 5 7 9 1 3 5 7 0 |
138 | * +-------+-------+-------+-------+-------+-------+-------+------+ | 138 | * +-------+-------+-------+-------+-------+-------+-------+------+ |
139 | * 000000000000000000000000___________value000000000000000000000000 | 139 | * 000000000000000000000000___________value000000000000000000000000 |
140 | * </pre> | 140 | * </pre> |
@@ -183,7 +183,7 @@ static inline uint64_t cvmx_ptr_to_phys(void *ptr) | |||
183 | * memory pointer (void *). | 183 | * memory pointer (void *). |
184 | * | 184 | * |
185 | * @physical_address: | 185 | * @physical_address: |
186 | * Hardware physical address to memory | 186 | * Hardware physical address to memory |
187 | * Returns Pointer to memory | 187 | * Returns Pointer to memory |
188 | */ | 188 | */ |
189 | static inline void *cvmx_phys_to_ptr(uint64_t physical_address) | 189 | static inline void *cvmx_phys_to_ptr(uint64_t physical_address) |
@@ -207,10 +207,10 @@ static inline void *cvmx_phys_to_ptr(uint64_t physical_address) | |||
207 | 207 | ||
208 | /* We have a full 64bit ABI. Writing to a 64bit address can be done with | 208 | /* We have a full 64bit ABI. Writing to a 64bit address can be done with |
209 | a simple volatile pointer */ | 209 | a simple volatile pointer */ |
210 | #define CVMX_BUILD_WRITE64(TYPE, ST) \ | 210 | #define CVMX_BUILD_WRITE64(TYPE, ST) \ |
211 | static inline void cvmx_write64_##TYPE(uint64_t addr, TYPE##_t val) \ | 211 | static inline void cvmx_write64_##TYPE(uint64_t addr, TYPE##_t val) \ |
212 | { \ | 212 | { \ |
213 | *CASTPTR(volatile TYPE##_t, addr) = val; \ | 213 | *CASTPTR(volatile TYPE##_t, addr) = val; \ |
214 | } | 214 | } |
215 | 215 | ||
216 | 216 | ||
@@ -221,19 +221,19 @@ static inline void cvmx_write64_##TYPE(uint64_t addr, TYPE##_t val) \ | |||
221 | 221 | ||
222 | /* We have a full 64bit ABI. Writing to a 64bit address can be done with | 222 | /* We have a full 64bit ABI. Writing to a 64bit address can be done with |
223 | a simple volatile pointer */ | 223 | a simple volatile pointer */ |
224 | #define CVMX_BUILD_READ64(TYPE, LT) \ | 224 | #define CVMX_BUILD_READ64(TYPE, LT) \ |
225 | static inline TYPE##_t cvmx_read64_##TYPE(uint64_t addr) \ | 225 | static inline TYPE##_t cvmx_read64_##TYPE(uint64_t addr) \ |
226 | { \ | 226 | { \ |
227 | return *CASTPTR(volatile TYPE##_t, addr); \ | 227 | return *CASTPTR(volatile TYPE##_t, addr); \ |
228 | } | 228 | } |
229 | 229 | ||
230 | 230 | ||
231 | /* The following defines 8 functions for writing to a 64bit address. Each | 231 | /* The following defines 8 functions for writing to a 64bit address. Each |
232 | takes two arguments, the address and the value to write. | 232 | takes two arguments, the address and the value to write. |
233 | cvmx_write64_int64 cvmx_write64_uint64 | 233 | cvmx_write64_int64 cvmx_write64_uint64 |
234 | cvmx_write64_int32 cvmx_write64_uint32 | 234 | cvmx_write64_int32 cvmx_write64_uint32 |
235 | cvmx_write64_int16 cvmx_write64_uint16 | 235 | cvmx_write64_int16 cvmx_write64_uint16 |
236 | cvmx_write64_int8 cvmx_write64_uint8 */ | 236 | cvmx_write64_int8 cvmx_write64_uint8 */ |
237 | CVMX_BUILD_WRITE64(int64, "sd"); | 237 | CVMX_BUILD_WRITE64(int64, "sd"); |
238 | CVMX_BUILD_WRITE64(int32, "sw"); | 238 | CVMX_BUILD_WRITE64(int32, "sw"); |
239 | CVMX_BUILD_WRITE64(int16, "sh"); | 239 | CVMX_BUILD_WRITE64(int16, "sh"); |
@@ -246,10 +246,10 @@ CVMX_BUILD_WRITE64(uint8, "sb"); | |||
246 | 246 | ||
247 | /* The following defines 8 functions for reading from a 64bit address. Each | 247 | /* The following defines 8 functions for reading from a 64bit address. Each |
248 | takes the address as the only argument | 248 | takes the address as the only argument |
249 | cvmx_read64_int64 cvmx_read64_uint64 | 249 | cvmx_read64_int64 cvmx_read64_uint64 |
250 | cvmx_read64_int32 cvmx_read64_uint32 | 250 | cvmx_read64_int32 cvmx_read64_uint32 |
251 | cvmx_read64_int16 cvmx_read64_uint16 | 251 | cvmx_read64_int16 cvmx_read64_uint16 |
252 | cvmx_read64_int8 cvmx_read64_uint8 */ | 252 | cvmx_read64_int8 cvmx_read64_uint8 */ |
253 | CVMX_BUILD_READ64(int64, "ld"); | 253 | CVMX_BUILD_READ64(int64, "ld"); |
254 | CVMX_BUILD_READ64(int32, "lw"); | 254 | CVMX_BUILD_READ64(int32, "lw"); |
255 | CVMX_BUILD_READ64(int16, "lh"); | 255 | CVMX_BUILD_READ64(int16, "lh"); |
@@ -389,7 +389,7 @@ static inline void cvmx_wait(uint64_t cycles) | |||
389 | 389 | ||
390 | /** | 390 | /** |
391 | * Reads a chip global cycle counter. This counts CPU cycles since | 391 | * Reads a chip global cycle counter. This counts CPU cycles since |
392 | * chip reset. The counter is 64 bit. | 392 | * chip reset. The counter is 64 bit. |
393 | * This register does not exist on CN38XX pass 1 silicion | 393 | * This register does not exist on CN38XX pass 1 silicion |
394 | * | 394 | * |
395 | * Returns Global chip cycle count since chip reset. | 395 | * Returns Global chip cycle count since chip reset. |
@@ -453,7 +453,7 @@ static inline uint32_t cvmx_octeon_num_cores(void) | |||
453 | 453 | ||
454 | /** | 454 | /** |
455 | * Read a byte of fuse data | 455 | * Read a byte of fuse data |
456 | * @byte_addr: address to read | 456 | * @byte_addr: address to read |
457 | * | 457 | * |
458 | * Returns fuse value: 0 or 1 | 458 | * Returns fuse value: 0 or 1 |
459 | */ | 459 | */ |