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-rw-r--r--arch/mips/include/asm/octeon/cvmx-spxx-defs.h225
1 files changed, 192 insertions, 33 deletions
diff --git a/arch/mips/include/asm/octeon/cvmx-spxx-defs.h b/arch/mips/include/asm/octeon/cvmx-spxx-defs.h
index b16940e32c83..c7d601d9446e 100644
--- a/arch/mips/include/asm/octeon/cvmx-spxx-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-spxx-defs.h
@@ -4,7 +4,7 @@
4 * Contact: support@caviumnetworks.com 4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK 5 * This file is part of the OCTEON SDK
6 * 6 *
7 * Copyright (c) 2003-2008 Cavium Networks 7 * Copyright (c) 2003-2012 Cavium Networks
8 * 8 *
9 * This file is free software; you can redistribute it and/or modify 9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as 10 * it under the terms of the GNU General Public License, Version 2, as
@@ -28,44 +28,33 @@
28#ifndef __CVMX_SPXX_DEFS_H__ 28#ifndef __CVMX_SPXX_DEFS_H__
29#define __CVMX_SPXX_DEFS_H__ 29#define __CVMX_SPXX_DEFS_H__
30 30
31#define CVMX_SPXX_BCKPRS_CNT(block_id) \ 31#define CVMX_SPXX_BCKPRS_CNT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000340ull) + ((block_id) & 1) * 0x8000000ull)
32 CVMX_ADD_IO_SEG(0x0001180090000340ull + (((block_id) & 1) * 0x8000000ull)) 32#define CVMX_SPXX_BIST_STAT(block_id) (CVMX_ADD_IO_SEG(0x00011800900007F8ull) + ((block_id) & 1) * 0x8000000ull)
33#define CVMX_SPXX_BIST_STAT(block_id) \ 33#define CVMX_SPXX_CLK_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000348ull) + ((block_id) & 1) * 0x8000000ull)
34 CVMX_ADD_IO_SEG(0x00011800900007F8ull + (((block_id) & 1) * 0x8000000ull)) 34#define CVMX_SPXX_CLK_STAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000350ull) + ((block_id) & 1) * 0x8000000ull)
35#define CVMX_SPXX_CLK_CTL(block_id) \ 35#define CVMX_SPXX_DBG_DESKEW_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000368ull) + ((block_id) & 1) * 0x8000000ull)
36 CVMX_ADD_IO_SEG(0x0001180090000348ull + (((block_id) & 1) * 0x8000000ull)) 36#define CVMX_SPXX_DBG_DESKEW_STATE(block_id) (CVMX_ADD_IO_SEG(0x0001180090000370ull) + ((block_id) & 1) * 0x8000000ull)
37#define CVMX_SPXX_CLK_STAT(block_id) \ 37#define CVMX_SPXX_DRV_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000358ull) + ((block_id) & 1) * 0x8000000ull)
38 CVMX_ADD_IO_SEG(0x0001180090000350ull + (((block_id) & 1) * 0x8000000ull)) 38#define CVMX_SPXX_ERR_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000320ull) + ((block_id) & 1) * 0x8000000ull)
39#define CVMX_SPXX_DBG_DESKEW_CTL(block_id) \ 39#define CVMX_SPXX_INT_DAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000318ull) + ((block_id) & 1) * 0x8000000ull)
40 CVMX_ADD_IO_SEG(0x0001180090000368ull + (((block_id) & 1) * 0x8000000ull)) 40#define CVMX_SPXX_INT_MSK(block_id) (CVMX_ADD_IO_SEG(0x0001180090000308ull) + ((block_id) & 1) * 0x8000000ull)
41#define CVMX_SPXX_DBG_DESKEW_STATE(block_id) \ 41#define CVMX_SPXX_INT_REG(block_id) (CVMX_ADD_IO_SEG(0x0001180090000300ull) + ((block_id) & 1) * 0x8000000ull)
42 CVMX_ADD_IO_SEG(0x0001180090000370ull + (((block_id) & 1) * 0x8000000ull)) 42#define CVMX_SPXX_INT_SYNC(block_id) (CVMX_ADD_IO_SEG(0x0001180090000310ull) + ((block_id) & 1) * 0x8000000ull)
43#define CVMX_SPXX_DRV_CTL(block_id) \ 43#define CVMX_SPXX_TPA_ACC(block_id) (CVMX_ADD_IO_SEG(0x0001180090000338ull) + ((block_id) & 1) * 0x8000000ull)
44 CVMX_ADD_IO_SEG(0x0001180090000358ull + (((block_id) & 1) * 0x8000000ull)) 44#define CVMX_SPXX_TPA_MAX(block_id) (CVMX_ADD_IO_SEG(0x0001180090000330ull) + ((block_id) & 1) * 0x8000000ull)
45#define CVMX_SPXX_ERR_CTL(block_id) \ 45#define CVMX_SPXX_TPA_SEL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000328ull) + ((block_id) & 1) * 0x8000000ull)
46 CVMX_ADD_IO_SEG(0x0001180090000320ull + (((block_id) & 1) * 0x8000000ull)) 46#define CVMX_SPXX_TRN4_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000360ull) + ((block_id) & 1) * 0x8000000ull)
47#define CVMX_SPXX_INT_DAT(block_id) \
48 CVMX_ADD_IO_SEG(0x0001180090000318ull + (((block_id) & 1) * 0x8000000ull))
49#define CVMX_SPXX_INT_MSK(block_id) \
50 CVMX_ADD_IO_SEG(0x0001180090000308ull + (((block_id) & 1) * 0x8000000ull))
51#define CVMX_SPXX_INT_REG(block_id) \
52 CVMX_ADD_IO_SEG(0x0001180090000300ull + (((block_id) & 1) * 0x8000000ull))
53#define CVMX_SPXX_INT_SYNC(block_id) \
54 CVMX_ADD_IO_SEG(0x0001180090000310ull + (((block_id) & 1) * 0x8000000ull))
55#define CVMX_SPXX_TPA_ACC(block_id) \
56 CVMX_ADD_IO_SEG(0x0001180090000338ull + (((block_id) & 1) * 0x8000000ull))
57#define CVMX_SPXX_TPA_MAX(block_id) \
58 CVMX_ADD_IO_SEG(0x0001180090000330ull + (((block_id) & 1) * 0x8000000ull))
59#define CVMX_SPXX_TPA_SEL(block_id) \
60 CVMX_ADD_IO_SEG(0x0001180090000328ull + (((block_id) & 1) * 0x8000000ull))
61#define CVMX_SPXX_TRN4_CTL(block_id) \
62 CVMX_ADD_IO_SEG(0x0001180090000360ull + (((block_id) & 1) * 0x8000000ull))
63 47
64union cvmx_spxx_bckprs_cnt { 48union cvmx_spxx_bckprs_cnt {
65 uint64_t u64; 49 uint64_t u64;
66 struct cvmx_spxx_bckprs_cnt_s { 50 struct cvmx_spxx_bckprs_cnt_s {
51#ifdef __BIG_ENDIAN_BITFIELD
67 uint64_t reserved_32_63:32; 52 uint64_t reserved_32_63:32;
68 uint64_t cnt:32; 53 uint64_t cnt:32;
54#else
55 uint64_t cnt:32;
56 uint64_t reserved_32_63:32;
57#endif
69 } s; 58 } s;
70 struct cvmx_spxx_bckprs_cnt_s cn38xx; 59 struct cvmx_spxx_bckprs_cnt_s cn38xx;
71 struct cvmx_spxx_bckprs_cnt_s cn38xxp2; 60 struct cvmx_spxx_bckprs_cnt_s cn38xxp2;
@@ -76,10 +65,17 @@ union cvmx_spxx_bckprs_cnt {
76union cvmx_spxx_bist_stat { 65union cvmx_spxx_bist_stat {
77 uint64_t u64; 66 uint64_t u64;
78 struct cvmx_spxx_bist_stat_s { 67 struct cvmx_spxx_bist_stat_s {
68#ifdef __BIG_ENDIAN_BITFIELD
79 uint64_t reserved_3_63:61; 69 uint64_t reserved_3_63:61;
80 uint64_t stat2:1; 70 uint64_t stat2:1;
81 uint64_t stat1:1; 71 uint64_t stat1:1;
82 uint64_t stat0:1; 72 uint64_t stat0:1;
73#else
74 uint64_t stat0:1;
75 uint64_t stat1:1;
76 uint64_t stat2:1;
77 uint64_t reserved_3_63:61;
78#endif
83 } s; 79 } s;
84 struct cvmx_spxx_bist_stat_s cn38xx; 80 struct cvmx_spxx_bist_stat_s cn38xx;
85 struct cvmx_spxx_bist_stat_s cn38xxp2; 81 struct cvmx_spxx_bist_stat_s cn38xxp2;
@@ -90,6 +86,7 @@ union cvmx_spxx_bist_stat {
90union cvmx_spxx_clk_ctl { 86union cvmx_spxx_clk_ctl {
91 uint64_t u64; 87 uint64_t u64;
92 struct cvmx_spxx_clk_ctl_s { 88 struct cvmx_spxx_clk_ctl_s {
89#ifdef __BIG_ENDIAN_BITFIELD
93 uint64_t reserved_17_63:47; 90 uint64_t reserved_17_63:47;
94 uint64_t seetrn:1; 91 uint64_t seetrn:1;
95 uint64_t reserved_12_15:4; 92 uint64_t reserved_12_15:4;
@@ -101,6 +98,19 @@ union cvmx_spxx_clk_ctl {
101 uint64_t drptrn:1; 98 uint64_t drptrn:1;
102 uint64_t rcvtrn:1; 99 uint64_t rcvtrn:1;
103 uint64_t srxdlck:1; 100 uint64_t srxdlck:1;
101#else
102 uint64_t srxdlck:1;
103 uint64_t rcvtrn:1;
104 uint64_t drptrn:1;
105 uint64_t sndtrn:1;
106 uint64_t statrcv:1;
107 uint64_t statdrv:1;
108 uint64_t runbist:1;
109 uint64_t clkdly:5;
110 uint64_t reserved_12_15:4;
111 uint64_t seetrn:1;
112 uint64_t reserved_17_63:47;
113#endif
104 } s; 114 } s;
105 struct cvmx_spxx_clk_ctl_s cn38xx; 115 struct cvmx_spxx_clk_ctl_s cn38xx;
106 struct cvmx_spxx_clk_ctl_s cn38xxp2; 116 struct cvmx_spxx_clk_ctl_s cn38xxp2;
@@ -111,6 +121,7 @@ union cvmx_spxx_clk_ctl {
111union cvmx_spxx_clk_stat { 121union cvmx_spxx_clk_stat {
112 uint64_t u64; 122 uint64_t u64;
113 struct cvmx_spxx_clk_stat_s { 123 struct cvmx_spxx_clk_stat_s {
124#ifdef __BIG_ENDIAN_BITFIELD
114 uint64_t reserved_11_63:53; 125 uint64_t reserved_11_63:53;
115 uint64_t stxcal:1; 126 uint64_t stxcal:1;
116 uint64_t reserved_9_9:1; 127 uint64_t reserved_9_9:1;
@@ -120,6 +131,17 @@ union cvmx_spxx_clk_stat {
120 uint64_t d4clk1:1; 131 uint64_t d4clk1:1;
121 uint64_t d4clk0:1; 132 uint64_t d4clk0:1;
122 uint64_t reserved_0_3:4; 133 uint64_t reserved_0_3:4;
134#else
135 uint64_t reserved_0_3:4;
136 uint64_t d4clk0:1;
137 uint64_t d4clk1:1;
138 uint64_t s4clk0:1;
139 uint64_t s4clk1:1;
140 uint64_t srxtrn:1;
141 uint64_t reserved_9_9:1;
142 uint64_t stxcal:1;
143 uint64_t reserved_11_63:53;
144#endif
123 } s; 145 } s;
124 struct cvmx_spxx_clk_stat_s cn38xx; 146 struct cvmx_spxx_clk_stat_s cn38xx;
125 struct cvmx_spxx_clk_stat_s cn38xxp2; 147 struct cvmx_spxx_clk_stat_s cn38xxp2;
@@ -130,6 +152,7 @@ union cvmx_spxx_clk_stat {
130union cvmx_spxx_dbg_deskew_ctl { 152union cvmx_spxx_dbg_deskew_ctl {
131 uint64_t u64; 153 uint64_t u64;
132 struct cvmx_spxx_dbg_deskew_ctl_s { 154 struct cvmx_spxx_dbg_deskew_ctl_s {
155#ifdef __BIG_ENDIAN_BITFIELD
133 uint64_t reserved_30_63:34; 156 uint64_t reserved_30_63:34;
134 uint64_t fallnop:1; 157 uint64_t fallnop:1;
135 uint64_t fall8:1; 158 uint64_t fall8:1;
@@ -146,6 +169,24 @@ union cvmx_spxx_dbg_deskew_ctl {
146 uint64_t offdly:6; 169 uint64_t offdly:6;
147 uint64_t dllfrc:1; 170 uint64_t dllfrc:1;
148 uint64_t dlldis:1; 171 uint64_t dlldis:1;
172#else
173 uint64_t dlldis:1;
174 uint64_t dllfrc:1;
175 uint64_t offdly:6;
176 uint64_t bitsel:5;
177 uint64_t offset:5;
178 uint64_t mux:1;
179 uint64_t inc:1;
180 uint64_t dec:1;
181 uint64_t clrdly:1;
182 uint64_t reserved_22_23:2;
183 uint64_t sstep:1;
184 uint64_t sstep_go:1;
185 uint64_t reserved_26_27:2;
186 uint64_t fall8:1;
187 uint64_t fallnop:1;
188 uint64_t reserved_30_63:34;
189#endif
149 } s; 190 } s;
150 struct cvmx_spxx_dbg_deskew_ctl_s cn38xx; 191 struct cvmx_spxx_dbg_deskew_ctl_s cn38xx;
151 struct cvmx_spxx_dbg_deskew_ctl_s cn38xxp2; 192 struct cvmx_spxx_dbg_deskew_ctl_s cn38xxp2;
@@ -156,11 +197,19 @@ union cvmx_spxx_dbg_deskew_ctl {
156union cvmx_spxx_dbg_deskew_state { 197union cvmx_spxx_dbg_deskew_state {
157 uint64_t u64; 198 uint64_t u64;
158 struct cvmx_spxx_dbg_deskew_state_s { 199 struct cvmx_spxx_dbg_deskew_state_s {
200#ifdef __BIG_ENDIAN_BITFIELD
159 uint64_t reserved_9_63:55; 201 uint64_t reserved_9_63:55;
160 uint64_t testres:1; 202 uint64_t testres:1;
161 uint64_t unxterm:1; 203 uint64_t unxterm:1;
162 uint64_t muxsel:2; 204 uint64_t muxsel:2;
163 uint64_t offset:5; 205 uint64_t offset:5;
206#else
207 uint64_t offset:5;
208 uint64_t muxsel:2;
209 uint64_t unxterm:1;
210 uint64_t testres:1;
211 uint64_t reserved_9_63:55;
212#endif
164 } s; 213 } s;
165 struct cvmx_spxx_dbg_deskew_state_s cn38xx; 214 struct cvmx_spxx_dbg_deskew_state_s cn38xx;
166 struct cvmx_spxx_dbg_deskew_state_s cn38xxp2; 215 struct cvmx_spxx_dbg_deskew_state_s cn38xxp2;
@@ -171,21 +220,40 @@ union cvmx_spxx_dbg_deskew_state {
171union cvmx_spxx_drv_ctl { 220union cvmx_spxx_drv_ctl {
172 uint64_t u64; 221 uint64_t u64;
173 struct cvmx_spxx_drv_ctl_s { 222 struct cvmx_spxx_drv_ctl_s {
223#ifdef __BIG_ENDIAN_BITFIELD
174 uint64_t reserved_0_63:64; 224 uint64_t reserved_0_63:64;
225#else
226 uint64_t reserved_0_63:64;
227#endif
175 } s; 228 } s;
176 struct cvmx_spxx_drv_ctl_cn38xx { 229 struct cvmx_spxx_drv_ctl_cn38xx {
230#ifdef __BIG_ENDIAN_BITFIELD
177 uint64_t reserved_16_63:48; 231 uint64_t reserved_16_63:48;
178 uint64_t stx4ncmp:4; 232 uint64_t stx4ncmp:4;
179 uint64_t stx4pcmp:4; 233 uint64_t stx4pcmp:4;
180 uint64_t srx4cmp:8; 234 uint64_t srx4cmp:8;
235#else
236 uint64_t srx4cmp:8;
237 uint64_t stx4pcmp:4;
238 uint64_t stx4ncmp:4;
239 uint64_t reserved_16_63:48;
240#endif
181 } cn38xx; 241 } cn38xx;
182 struct cvmx_spxx_drv_ctl_cn38xx cn38xxp2; 242 struct cvmx_spxx_drv_ctl_cn38xx cn38xxp2;
183 struct cvmx_spxx_drv_ctl_cn58xx { 243 struct cvmx_spxx_drv_ctl_cn58xx {
244#ifdef __BIG_ENDIAN_BITFIELD
184 uint64_t reserved_24_63:40; 245 uint64_t reserved_24_63:40;
185 uint64_t stx4ncmp:4; 246 uint64_t stx4ncmp:4;
186 uint64_t stx4pcmp:4; 247 uint64_t stx4pcmp:4;
187 uint64_t reserved_10_15:6; 248 uint64_t reserved_10_15:6;
188 uint64_t srx4cmp:10; 249 uint64_t srx4cmp:10;
250#else
251 uint64_t srx4cmp:10;
252 uint64_t reserved_10_15:6;
253 uint64_t stx4pcmp:4;
254 uint64_t stx4ncmp:4;
255 uint64_t reserved_24_63:40;
256#endif
189 } cn58xx; 257 } cn58xx;
190 struct cvmx_spxx_drv_ctl_cn58xx cn58xxp1; 258 struct cvmx_spxx_drv_ctl_cn58xx cn58xxp1;
191}; 259};
@@ -193,12 +261,21 @@ union cvmx_spxx_drv_ctl {
193union cvmx_spxx_err_ctl { 261union cvmx_spxx_err_ctl {
194 uint64_t u64; 262 uint64_t u64;
195 struct cvmx_spxx_err_ctl_s { 263 struct cvmx_spxx_err_ctl_s {
264#ifdef __BIG_ENDIAN_BITFIELD
196 uint64_t reserved_9_63:55; 265 uint64_t reserved_9_63:55;
197 uint64_t prtnxa:1; 266 uint64_t prtnxa:1;
198 uint64_t dipcls:1; 267 uint64_t dipcls:1;
199 uint64_t dippay:1; 268 uint64_t dippay:1;
200 uint64_t reserved_4_5:2; 269 uint64_t reserved_4_5:2;
201 uint64_t errcnt:4; 270 uint64_t errcnt:4;
271#else
272 uint64_t errcnt:4;
273 uint64_t reserved_4_5:2;
274 uint64_t dippay:1;
275 uint64_t dipcls:1;
276 uint64_t prtnxa:1;
277 uint64_t reserved_9_63:55;
278#endif
202 } s; 279 } s;
203 struct cvmx_spxx_err_ctl_s cn38xx; 280 struct cvmx_spxx_err_ctl_s cn38xx;
204 struct cvmx_spxx_err_ctl_s cn38xxp2; 281 struct cvmx_spxx_err_ctl_s cn38xxp2;
@@ -209,12 +286,21 @@ union cvmx_spxx_err_ctl {
209union cvmx_spxx_int_dat { 286union cvmx_spxx_int_dat {
210 uint64_t u64; 287 uint64_t u64;
211 struct cvmx_spxx_int_dat_s { 288 struct cvmx_spxx_int_dat_s {
289#ifdef __BIG_ENDIAN_BITFIELD
212 uint64_t reserved_32_63:32; 290 uint64_t reserved_32_63:32;
213 uint64_t mul:1; 291 uint64_t mul:1;
214 uint64_t reserved_14_30:17; 292 uint64_t reserved_14_30:17;
215 uint64_t calbnk:2; 293 uint64_t calbnk:2;
216 uint64_t rsvop:4; 294 uint64_t rsvop:4;
217 uint64_t prt:8; 295 uint64_t prt:8;
296#else
297 uint64_t prt:8;
298 uint64_t rsvop:4;
299 uint64_t calbnk:2;
300 uint64_t reserved_14_30:17;
301 uint64_t mul:1;
302 uint64_t reserved_32_63:32;
303#endif
218 } s; 304 } s;
219 struct cvmx_spxx_int_dat_s cn38xx; 305 struct cvmx_spxx_int_dat_s cn38xx;
220 struct cvmx_spxx_int_dat_s cn38xxp2; 306 struct cvmx_spxx_int_dat_s cn38xxp2;
@@ -225,6 +311,7 @@ union cvmx_spxx_int_dat {
225union cvmx_spxx_int_msk { 311union cvmx_spxx_int_msk {
226 uint64_t u64; 312 uint64_t u64;
227 struct cvmx_spxx_int_msk_s { 313 struct cvmx_spxx_int_msk_s {
314#ifdef __BIG_ENDIAN_BITFIELD
228 uint64_t reserved_12_63:52; 315 uint64_t reserved_12_63:52;
229 uint64_t calerr:1; 316 uint64_t calerr:1;
230 uint64_t syncerr:1; 317 uint64_t syncerr:1;
@@ -237,6 +324,20 @@ union cvmx_spxx_int_msk {
237 uint64_t reserved_2_3:2; 324 uint64_t reserved_2_3:2;
238 uint64_t abnorm:1; 325 uint64_t abnorm:1;
239 uint64_t prtnxa:1; 326 uint64_t prtnxa:1;
327#else
328 uint64_t prtnxa:1;
329 uint64_t abnorm:1;
330 uint64_t reserved_2_3:2;
331 uint64_t spiovr:1;
332 uint64_t clserr:1;
333 uint64_t drwnng:1;
334 uint64_t rsverr:1;
335 uint64_t tpaovr:1;
336 uint64_t diperr:1;
337 uint64_t syncerr:1;
338 uint64_t calerr:1;
339 uint64_t reserved_12_63:52;
340#endif
240 } s; 341 } s;
241 struct cvmx_spxx_int_msk_s cn38xx; 342 struct cvmx_spxx_int_msk_s cn38xx;
242 struct cvmx_spxx_int_msk_s cn38xxp2; 343 struct cvmx_spxx_int_msk_s cn38xxp2;
@@ -247,6 +348,7 @@ union cvmx_spxx_int_msk {
247union cvmx_spxx_int_reg { 348union cvmx_spxx_int_reg {
248 uint64_t u64; 349 uint64_t u64;
249 struct cvmx_spxx_int_reg_s { 350 struct cvmx_spxx_int_reg_s {
351#ifdef __BIG_ENDIAN_BITFIELD
250 uint64_t reserved_32_63:32; 352 uint64_t reserved_32_63:32;
251 uint64_t spf:1; 353 uint64_t spf:1;
252 uint64_t reserved_12_30:19; 354 uint64_t reserved_12_30:19;
@@ -261,6 +363,22 @@ union cvmx_spxx_int_reg {
261 uint64_t reserved_2_3:2; 363 uint64_t reserved_2_3:2;
262 uint64_t abnorm:1; 364 uint64_t abnorm:1;
263 uint64_t prtnxa:1; 365 uint64_t prtnxa:1;
366#else
367 uint64_t prtnxa:1;
368 uint64_t abnorm:1;
369 uint64_t reserved_2_3:2;
370 uint64_t spiovr:1;
371 uint64_t clserr:1;
372 uint64_t drwnng:1;
373 uint64_t rsverr:1;
374 uint64_t tpaovr:1;
375 uint64_t diperr:1;
376 uint64_t syncerr:1;
377 uint64_t calerr:1;
378 uint64_t reserved_12_30:19;
379 uint64_t spf:1;
380 uint64_t reserved_32_63:32;
381#endif
264 } s; 382 } s;
265 struct cvmx_spxx_int_reg_s cn38xx; 383 struct cvmx_spxx_int_reg_s cn38xx;
266 struct cvmx_spxx_int_reg_s cn38xxp2; 384 struct cvmx_spxx_int_reg_s cn38xxp2;
@@ -271,6 +389,7 @@ union cvmx_spxx_int_reg {
271union cvmx_spxx_int_sync { 389union cvmx_spxx_int_sync {
272 uint64_t u64; 390 uint64_t u64;
273 struct cvmx_spxx_int_sync_s { 391 struct cvmx_spxx_int_sync_s {
392#ifdef __BIG_ENDIAN_BITFIELD
274 uint64_t reserved_12_63:52; 393 uint64_t reserved_12_63:52;
275 uint64_t calerr:1; 394 uint64_t calerr:1;
276 uint64_t syncerr:1; 395 uint64_t syncerr:1;
@@ -283,6 +402,20 @@ union cvmx_spxx_int_sync {
283 uint64_t reserved_2_3:2; 402 uint64_t reserved_2_3:2;
284 uint64_t abnorm:1; 403 uint64_t abnorm:1;
285 uint64_t prtnxa:1; 404 uint64_t prtnxa:1;
405#else
406 uint64_t prtnxa:1;
407 uint64_t abnorm:1;
408 uint64_t reserved_2_3:2;
409 uint64_t spiovr:1;
410 uint64_t clserr:1;
411 uint64_t drwnng:1;
412 uint64_t rsverr:1;
413 uint64_t tpaovr:1;
414 uint64_t diperr:1;
415 uint64_t syncerr:1;
416 uint64_t calerr:1;
417 uint64_t reserved_12_63:52;
418#endif
286 } s; 419 } s;
287 struct cvmx_spxx_int_sync_s cn38xx; 420 struct cvmx_spxx_int_sync_s cn38xx;
288 struct cvmx_spxx_int_sync_s cn38xxp2; 421 struct cvmx_spxx_int_sync_s cn38xxp2;
@@ -293,8 +426,13 @@ union cvmx_spxx_int_sync {
293union cvmx_spxx_tpa_acc { 426union cvmx_spxx_tpa_acc {
294 uint64_t u64; 427 uint64_t u64;
295 struct cvmx_spxx_tpa_acc_s { 428 struct cvmx_spxx_tpa_acc_s {
429#ifdef __BIG_ENDIAN_BITFIELD
296 uint64_t reserved_32_63:32; 430 uint64_t reserved_32_63:32;
297 uint64_t cnt:32; 431 uint64_t cnt:32;
432#else
433 uint64_t cnt:32;
434 uint64_t reserved_32_63:32;
435#endif
298 } s; 436 } s;
299 struct cvmx_spxx_tpa_acc_s cn38xx; 437 struct cvmx_spxx_tpa_acc_s cn38xx;
300 struct cvmx_spxx_tpa_acc_s cn38xxp2; 438 struct cvmx_spxx_tpa_acc_s cn38xxp2;
@@ -305,8 +443,13 @@ union cvmx_spxx_tpa_acc {
305union cvmx_spxx_tpa_max { 443union cvmx_spxx_tpa_max {
306 uint64_t u64; 444 uint64_t u64;
307 struct cvmx_spxx_tpa_max_s { 445 struct cvmx_spxx_tpa_max_s {
446#ifdef __BIG_ENDIAN_BITFIELD
308 uint64_t reserved_32_63:32; 447 uint64_t reserved_32_63:32;
309 uint64_t max:32; 448 uint64_t max:32;
449#else
450 uint64_t max:32;
451 uint64_t reserved_32_63:32;
452#endif
310 } s; 453 } s;
311 struct cvmx_spxx_tpa_max_s cn38xx; 454 struct cvmx_spxx_tpa_max_s cn38xx;
312 struct cvmx_spxx_tpa_max_s cn38xxp2; 455 struct cvmx_spxx_tpa_max_s cn38xxp2;
@@ -317,8 +460,13 @@ union cvmx_spxx_tpa_max {
317union cvmx_spxx_tpa_sel { 460union cvmx_spxx_tpa_sel {
318 uint64_t u64; 461 uint64_t u64;
319 struct cvmx_spxx_tpa_sel_s { 462 struct cvmx_spxx_tpa_sel_s {
463#ifdef __BIG_ENDIAN_BITFIELD
320 uint64_t reserved_4_63:60; 464 uint64_t reserved_4_63:60;
321 uint64_t prtsel:4; 465 uint64_t prtsel:4;
466#else
467 uint64_t prtsel:4;
468 uint64_t reserved_4_63:60;
469#endif
322 } s; 470 } s;
323 struct cvmx_spxx_tpa_sel_s cn38xx; 471 struct cvmx_spxx_tpa_sel_s cn38xx;
324 struct cvmx_spxx_tpa_sel_s cn38xxp2; 472 struct cvmx_spxx_tpa_sel_s cn38xxp2;
@@ -329,6 +477,7 @@ union cvmx_spxx_tpa_sel {
329union cvmx_spxx_trn4_ctl { 477union cvmx_spxx_trn4_ctl {
330 uint64_t u64; 478 uint64_t u64;
331 struct cvmx_spxx_trn4_ctl_s { 479 struct cvmx_spxx_trn4_ctl_s {
480#ifdef __BIG_ENDIAN_BITFIELD
332 uint64_t reserved_13_63:51; 481 uint64_t reserved_13_63:51;
333 uint64_t trntest:1; 482 uint64_t trntest:1;
334 uint64_t jitter:3; 483 uint64_t jitter:3;
@@ -337,6 +486,16 @@ union cvmx_spxx_trn4_ctl {
337 uint64_t maxdist:5; 486 uint64_t maxdist:5;
338 uint64_t macro_en:1; 487 uint64_t macro_en:1;
339 uint64_t mux_en:1; 488 uint64_t mux_en:1;
489#else
490 uint64_t mux_en:1;
491 uint64_t macro_en:1;
492 uint64_t maxdist:5;
493 uint64_t set_boot:1;
494 uint64_t clr_boot:1;
495 uint64_t jitter:3;
496 uint64_t trntest:1;
497 uint64_t reserved_13_63:51;
498#endif
340 } s; 499 } s;
341 struct cvmx_spxx_trn4_ctl_s cn38xx; 500 struct cvmx_spxx_trn4_ctl_s cn38xx;
342 struct cvmx_spxx_trn4_ctl_s cn38xxp2; 501 struct cvmx_spxx_trn4_ctl_s cn38xxp2;
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-13 07:25:41 -0400