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-rw-r--r--arch/mips/include/asm/octeon/cvmx-pexp-defs.h378
1 files changed, 187 insertions, 191 deletions
diff --git a/arch/mips/include/asm/octeon/cvmx-pexp-defs.h b/arch/mips/include/asm/octeon/cvmx-pexp-defs.h
index 5ea5dc571b54..5ab8679d89af 100644
--- a/arch/mips/include/asm/octeon/cvmx-pexp-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-pexp-defs.h
@@ -4,7 +4,7 @@
4 * Contact: support@caviumnetworks.com 4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK 5 * This file is part of the OCTEON SDK
6 * 6 *
7 * Copyright (c) 2003-2008 Cavium Networks 7 * Copyright (c) 2003-2010 Cavium Networks
8 * 8 *
9 * This file is free software; you can redistribute it and/or modify 9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as 10 * it under the terms of the GNU General Public License, Version 2, as
@@ -35,195 +35,191 @@
35#ifndef __CVMX_PEXP_DEFS_H__ 35#ifndef __CVMX_PEXP_DEFS_H__
36#define __CVMX_PEXP_DEFS_H__ 36#define __CVMX_PEXP_DEFS_H__
37 37
38#define CVMX_PEXP_NPEI_BAR1_INDEXX(offset) \ 38#define CVMX_PEXP_NPEI_BAR1_INDEXX(offset) (CVMX_ADD_IO_SEG(0x00011F0000008000ull) + ((offset) & 31) * 16)
39 CVMX_ADD_IO_SEG(0x00011F0000008000ull + (((offset) & 31) * 16)) 39#define CVMX_PEXP_NPEI_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011F0000008580ull))
40#define CVMX_PEXP_NPEI_BIST_STATUS \ 40#define CVMX_PEXP_NPEI_BIST_STATUS2 (CVMX_ADD_IO_SEG(0x00011F0000008680ull))
41 CVMX_ADD_IO_SEG(0x00011F0000008580ull) 41#define CVMX_PEXP_NPEI_CTL_PORT0 (CVMX_ADD_IO_SEG(0x00011F0000008250ull))
42#define CVMX_PEXP_NPEI_BIST_STATUS2 \ 42#define CVMX_PEXP_NPEI_CTL_PORT1 (CVMX_ADD_IO_SEG(0x00011F0000008260ull))
43 CVMX_ADD_IO_SEG(0x00011F0000008680ull) 43#define CVMX_PEXP_NPEI_CTL_STATUS (CVMX_ADD_IO_SEG(0x00011F0000008570ull))
44#define CVMX_PEXP_NPEI_CTL_PORT0 \ 44#define CVMX_PEXP_NPEI_CTL_STATUS2 (CVMX_ADD_IO_SEG(0x00011F000000BC00ull))
45 CVMX_ADD_IO_SEG(0x00011F0000008250ull) 45#define CVMX_PEXP_NPEI_DATA_OUT_CNT (CVMX_ADD_IO_SEG(0x00011F00000085F0ull))
46#define CVMX_PEXP_NPEI_CTL_PORT1 \ 46#define CVMX_PEXP_NPEI_DBG_DATA (CVMX_ADD_IO_SEG(0x00011F0000008510ull))
47 CVMX_ADD_IO_SEG(0x00011F0000008260ull) 47#define CVMX_PEXP_NPEI_DBG_SELECT (CVMX_ADD_IO_SEG(0x00011F0000008500ull))
48#define CVMX_PEXP_NPEI_CTL_STATUS \ 48#define CVMX_PEXP_NPEI_DMA0_INT_LEVEL (CVMX_ADD_IO_SEG(0x00011F00000085C0ull))
49 CVMX_ADD_IO_SEG(0x00011F0000008570ull) 49#define CVMX_PEXP_NPEI_DMA1_INT_LEVEL (CVMX_ADD_IO_SEG(0x00011F00000085D0ull))
50#define CVMX_PEXP_NPEI_CTL_STATUS2 \ 50#define CVMX_PEXP_NPEI_DMAX_COUNTS(offset) (CVMX_ADD_IO_SEG(0x00011F0000008450ull) + ((offset) & 7) * 16)
51 CVMX_ADD_IO_SEG(0x00011F000000BC00ull) 51#define CVMX_PEXP_NPEI_DMAX_DBELL(offset) (CVMX_ADD_IO_SEG(0x00011F00000083B0ull) + ((offset) & 7) * 16)
52#define CVMX_PEXP_NPEI_DATA_OUT_CNT \ 52#define CVMX_PEXP_NPEI_DMAX_IBUFF_SADDR(offset) (CVMX_ADD_IO_SEG(0x00011F0000008400ull) + ((offset) & 7) * 16)
53 CVMX_ADD_IO_SEG(0x00011F00000085F0ull) 53#define CVMX_PEXP_NPEI_DMAX_NADDR(offset) (CVMX_ADD_IO_SEG(0x00011F00000084A0ull) + ((offset) & 7) * 16)
54#define CVMX_PEXP_NPEI_DBG_DATA \ 54#define CVMX_PEXP_NPEI_DMA_CNTS (CVMX_ADD_IO_SEG(0x00011F00000085E0ull))
55 CVMX_ADD_IO_SEG(0x00011F0000008510ull) 55#define CVMX_PEXP_NPEI_DMA_CONTROL (CVMX_ADD_IO_SEG(0x00011F00000083A0ull))
56#define CVMX_PEXP_NPEI_DBG_SELECT \ 56#define CVMX_PEXP_NPEI_DMA_PCIE_REQ_NUM (CVMX_ADD_IO_SEG(0x00011F00000085B0ull))
57 CVMX_ADD_IO_SEG(0x00011F0000008500ull) 57#define CVMX_PEXP_NPEI_DMA_STATE1 (CVMX_ADD_IO_SEG(0x00011F00000086C0ull))
58#define CVMX_PEXP_NPEI_DMA0_INT_LEVEL \ 58#define CVMX_PEXP_NPEI_DMA_STATE1_P1 (CVMX_ADD_IO_SEG(0x00011F0000008680ull))
59 CVMX_ADD_IO_SEG(0x00011F00000085C0ull) 59#define CVMX_PEXP_NPEI_DMA_STATE2 (CVMX_ADD_IO_SEG(0x00011F00000086D0ull))
60#define CVMX_PEXP_NPEI_DMA1_INT_LEVEL \ 60#define CVMX_PEXP_NPEI_DMA_STATE2_P1 (CVMX_ADD_IO_SEG(0x00011F0000008690ull))
61 CVMX_ADD_IO_SEG(0x00011F00000085D0ull) 61#define CVMX_PEXP_NPEI_DMA_STATE3_P1 (CVMX_ADD_IO_SEG(0x00011F00000086A0ull))
62#define CVMX_PEXP_NPEI_DMAX_COUNTS(offset) \ 62#define CVMX_PEXP_NPEI_DMA_STATE4_P1 (CVMX_ADD_IO_SEG(0x00011F00000086B0ull))
63 CVMX_ADD_IO_SEG(0x00011F0000008450ull + (((offset) & 7) * 16)) 63#define CVMX_PEXP_NPEI_DMA_STATE5_P1 (CVMX_ADD_IO_SEG(0x00011F00000086C0ull))
64#define CVMX_PEXP_NPEI_DMAX_DBELL(offset) \ 64#define CVMX_PEXP_NPEI_INT_A_ENB (CVMX_ADD_IO_SEG(0x00011F0000008560ull))
65 CVMX_ADD_IO_SEG(0x00011F00000083B0ull + (((offset) & 7) * 16)) 65#define CVMX_PEXP_NPEI_INT_A_ENB2 (CVMX_ADD_IO_SEG(0x00011F000000BCE0ull))
66#define CVMX_PEXP_NPEI_DMAX_IBUFF_SADDR(offset) \ 66#define CVMX_PEXP_NPEI_INT_A_SUM (CVMX_ADD_IO_SEG(0x00011F0000008550ull))
67 CVMX_ADD_IO_SEG(0x00011F0000008400ull + (((offset) & 7) * 16)) 67#define CVMX_PEXP_NPEI_INT_ENB (CVMX_ADD_IO_SEG(0x00011F0000008540ull))
68#define CVMX_PEXP_NPEI_DMAX_NADDR(offset) \ 68#define CVMX_PEXP_NPEI_INT_ENB2 (CVMX_ADD_IO_SEG(0x00011F000000BCD0ull))
69 CVMX_ADD_IO_SEG(0x00011F00000084A0ull + (((offset) & 7) * 16)) 69#define CVMX_PEXP_NPEI_INT_INFO (CVMX_ADD_IO_SEG(0x00011F0000008590ull))
70#define CVMX_PEXP_NPEI_DMA_CNTS \ 70#define CVMX_PEXP_NPEI_INT_SUM (CVMX_ADD_IO_SEG(0x00011F0000008530ull))
71 CVMX_ADD_IO_SEG(0x00011F00000085E0ull) 71#define CVMX_PEXP_NPEI_INT_SUM2 (CVMX_ADD_IO_SEG(0x00011F000000BCC0ull))
72#define CVMX_PEXP_NPEI_DMA_CONTROL \ 72#define CVMX_PEXP_NPEI_LAST_WIN_RDATA0 (CVMX_ADD_IO_SEG(0x00011F0000008600ull))
73 CVMX_ADD_IO_SEG(0x00011F00000083A0ull) 73#define CVMX_PEXP_NPEI_LAST_WIN_RDATA1 (CVMX_ADD_IO_SEG(0x00011F0000008610ull))
74#define CVMX_PEXP_NPEI_INT_A_ENB \ 74#define CVMX_PEXP_NPEI_MEM_ACCESS_CTL (CVMX_ADD_IO_SEG(0x00011F00000084F0ull))
75 CVMX_ADD_IO_SEG(0x00011F0000008560ull) 75#define CVMX_PEXP_NPEI_MEM_ACCESS_SUBIDX(offset) (CVMX_ADD_IO_SEG(0x00011F0000008280ull) + ((offset) & 31) * 16 - 16*12)
76#define CVMX_PEXP_NPEI_INT_A_ENB2 \ 76#define CVMX_PEXP_NPEI_MSI_ENB0 (CVMX_ADD_IO_SEG(0x00011F000000BC50ull))
77 CVMX_ADD_IO_SEG(0x00011F000000BCE0ull) 77#define CVMX_PEXP_NPEI_MSI_ENB1 (CVMX_ADD_IO_SEG(0x00011F000000BC60ull))
78#define CVMX_PEXP_NPEI_INT_A_SUM \ 78#define CVMX_PEXP_NPEI_MSI_ENB2 (CVMX_ADD_IO_SEG(0x00011F000000BC70ull))
79 CVMX_ADD_IO_SEG(0x00011F0000008550ull) 79#define CVMX_PEXP_NPEI_MSI_ENB3 (CVMX_ADD_IO_SEG(0x00011F000000BC80ull))
80#define CVMX_PEXP_NPEI_INT_ENB \ 80#define CVMX_PEXP_NPEI_MSI_RCV0 (CVMX_ADD_IO_SEG(0x00011F000000BC10ull))
81 CVMX_ADD_IO_SEG(0x00011F0000008540ull) 81#define CVMX_PEXP_NPEI_MSI_RCV1 (CVMX_ADD_IO_SEG(0x00011F000000BC20ull))
82#define CVMX_PEXP_NPEI_INT_ENB2 \ 82#define CVMX_PEXP_NPEI_MSI_RCV2 (CVMX_ADD_IO_SEG(0x00011F000000BC30ull))
83 CVMX_ADD_IO_SEG(0x00011F000000BCD0ull) 83#define CVMX_PEXP_NPEI_MSI_RCV3 (CVMX_ADD_IO_SEG(0x00011F000000BC40ull))
84#define CVMX_PEXP_NPEI_INT_INFO \ 84#define CVMX_PEXP_NPEI_MSI_RD_MAP (CVMX_ADD_IO_SEG(0x00011F000000BCA0ull))
85 CVMX_ADD_IO_SEG(0x00011F0000008590ull) 85#define CVMX_PEXP_NPEI_MSI_W1C_ENB0 (CVMX_ADD_IO_SEG(0x00011F000000BCF0ull))
86#define CVMX_PEXP_NPEI_INT_SUM \ 86#define CVMX_PEXP_NPEI_MSI_W1C_ENB1 (CVMX_ADD_IO_SEG(0x00011F000000BD00ull))
87 CVMX_ADD_IO_SEG(0x00011F0000008530ull) 87#define CVMX_PEXP_NPEI_MSI_W1C_ENB2 (CVMX_ADD_IO_SEG(0x00011F000000BD10ull))
88#define CVMX_PEXP_NPEI_INT_SUM2 \ 88#define CVMX_PEXP_NPEI_MSI_W1C_ENB3 (CVMX_ADD_IO_SEG(0x00011F000000BD20ull))
89 CVMX_ADD_IO_SEG(0x00011F000000BCC0ull) 89#define CVMX_PEXP_NPEI_MSI_W1S_ENB0 (CVMX_ADD_IO_SEG(0x00011F000000BD30ull))
90#define CVMX_PEXP_NPEI_LAST_WIN_RDATA0 \ 90#define CVMX_PEXP_NPEI_MSI_W1S_ENB1 (CVMX_ADD_IO_SEG(0x00011F000000BD40ull))
91 CVMX_ADD_IO_SEG(0x00011F0000008600ull) 91#define CVMX_PEXP_NPEI_MSI_W1S_ENB2 (CVMX_ADD_IO_SEG(0x00011F000000BD50ull))
92#define CVMX_PEXP_NPEI_LAST_WIN_RDATA1 \ 92#define CVMX_PEXP_NPEI_MSI_W1S_ENB3 (CVMX_ADD_IO_SEG(0x00011F000000BD60ull))
93 CVMX_ADD_IO_SEG(0x00011F0000008610ull) 93#define CVMX_PEXP_NPEI_MSI_WR_MAP (CVMX_ADD_IO_SEG(0x00011F000000BC90ull))
94#define CVMX_PEXP_NPEI_MEM_ACCESS_CTL \ 94#define CVMX_PEXP_NPEI_PCIE_CREDIT_CNT (CVMX_ADD_IO_SEG(0x00011F000000BD70ull))
95 CVMX_ADD_IO_SEG(0x00011F00000084F0ull) 95#define CVMX_PEXP_NPEI_PCIE_MSI_RCV (CVMX_ADD_IO_SEG(0x00011F000000BCB0ull))
96#define CVMX_PEXP_NPEI_MEM_ACCESS_SUBIDX(offset) \ 96#define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B1 (CVMX_ADD_IO_SEG(0x00011F0000008650ull))
97 CVMX_ADD_IO_SEG(0x00011F0000008280ull + (((offset) & 31) * 16) - 16 * 12) 97#define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B2 (CVMX_ADD_IO_SEG(0x00011F0000008660ull))
98#define CVMX_PEXP_NPEI_MSI_ENB0 \ 98#define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B3 (CVMX_ADD_IO_SEG(0x00011F0000008670ull))
99 CVMX_ADD_IO_SEG(0x00011F000000BC50ull) 99#define CVMX_PEXP_NPEI_PKTX_CNTS(offset) (CVMX_ADD_IO_SEG(0x00011F000000A400ull) + ((offset) & 31) * 16)
100#define CVMX_PEXP_NPEI_MSI_ENB1 \ 100#define CVMX_PEXP_NPEI_PKTX_INSTR_BADDR(offset) (CVMX_ADD_IO_SEG(0x00011F000000A800ull) + ((offset) & 31) * 16)
101 CVMX_ADD_IO_SEG(0x00011F000000BC60ull) 101#define CVMX_PEXP_NPEI_PKTX_INSTR_BAOFF_DBELL(offset) (CVMX_ADD_IO_SEG(0x00011F000000AC00ull) + ((offset) & 31) * 16)
102#define CVMX_PEXP_NPEI_MSI_ENB2 \ 102#define CVMX_PEXP_NPEI_PKTX_INSTR_FIFO_RSIZE(offset) (CVMX_ADD_IO_SEG(0x00011F000000B000ull) + ((offset) & 31) * 16)
103 CVMX_ADD_IO_SEG(0x00011F000000BC70ull) 103#define CVMX_PEXP_NPEI_PKTX_INSTR_HEADER(offset) (CVMX_ADD_IO_SEG(0x00011F000000B400ull) + ((offset) & 31) * 16)
104#define CVMX_PEXP_NPEI_MSI_ENB3 \ 104#define CVMX_PEXP_NPEI_PKTX_IN_BP(offset) (CVMX_ADD_IO_SEG(0x00011F000000B800ull) + ((offset) & 31) * 16)
105 CVMX_ADD_IO_SEG(0x00011F000000BC80ull) 105#define CVMX_PEXP_NPEI_PKTX_SLIST_BADDR(offset) (CVMX_ADD_IO_SEG(0x00011F0000009400ull) + ((offset) & 31) * 16)
106#define CVMX_PEXP_NPEI_MSI_RCV0 \ 106#define CVMX_PEXP_NPEI_PKTX_SLIST_BAOFF_DBELL(offset) (CVMX_ADD_IO_SEG(0x00011F0000009800ull) + ((offset) & 31) * 16)
107 CVMX_ADD_IO_SEG(0x00011F000000BC10ull) 107#define CVMX_PEXP_NPEI_PKTX_SLIST_FIFO_RSIZE(offset) (CVMX_ADD_IO_SEG(0x00011F0000009C00ull) + ((offset) & 31) * 16)
108#define CVMX_PEXP_NPEI_MSI_RCV1 \ 108#define CVMX_PEXP_NPEI_PKT_CNT_INT (CVMX_ADD_IO_SEG(0x00011F0000009110ull))
109 CVMX_ADD_IO_SEG(0x00011F000000BC20ull) 109#define CVMX_PEXP_NPEI_PKT_CNT_INT_ENB (CVMX_ADD_IO_SEG(0x00011F0000009130ull))
110#define CVMX_PEXP_NPEI_MSI_RCV2 \ 110#define CVMX_PEXP_NPEI_PKT_DATA_OUT_ES (CVMX_ADD_IO_SEG(0x00011F00000090B0ull))
111 CVMX_ADD_IO_SEG(0x00011F000000BC30ull) 111#define CVMX_PEXP_NPEI_PKT_DATA_OUT_NS (CVMX_ADD_IO_SEG(0x00011F00000090A0ull))
112#define CVMX_PEXP_NPEI_MSI_RCV3 \ 112#define CVMX_PEXP_NPEI_PKT_DATA_OUT_ROR (CVMX_ADD_IO_SEG(0x00011F0000009090ull))
113 CVMX_ADD_IO_SEG(0x00011F000000BC40ull) 113#define CVMX_PEXP_NPEI_PKT_DPADDR (CVMX_ADD_IO_SEG(0x00011F0000009080ull))
114#define CVMX_PEXP_NPEI_MSI_RD_MAP \ 114#define CVMX_PEXP_NPEI_PKT_INPUT_CONTROL (CVMX_ADD_IO_SEG(0x00011F0000009150ull))
115 CVMX_ADD_IO_SEG(0x00011F000000BCA0ull) 115#define CVMX_PEXP_NPEI_PKT_INSTR_ENB (CVMX_ADD_IO_SEG(0x00011F0000009000ull))
116#define CVMX_PEXP_NPEI_MSI_W1C_ENB0 \ 116#define CVMX_PEXP_NPEI_PKT_INSTR_RD_SIZE (CVMX_ADD_IO_SEG(0x00011F0000009190ull))
117 CVMX_ADD_IO_SEG(0x00011F000000BCF0ull) 117#define CVMX_PEXP_NPEI_PKT_INSTR_SIZE (CVMX_ADD_IO_SEG(0x00011F0000009020ull))
118#define CVMX_PEXP_NPEI_MSI_W1C_ENB1 \ 118#define CVMX_PEXP_NPEI_PKT_INT_LEVELS (CVMX_ADD_IO_SEG(0x00011F0000009100ull))
119 CVMX_ADD_IO_SEG(0x00011F000000BD00ull) 119#define CVMX_PEXP_NPEI_PKT_IN_BP (CVMX_ADD_IO_SEG(0x00011F00000086B0ull))
120#define CVMX_PEXP_NPEI_MSI_W1C_ENB2 \ 120#define CVMX_PEXP_NPEI_PKT_IN_DONEX_CNTS(offset) (CVMX_ADD_IO_SEG(0x00011F000000A000ull) + ((offset) & 31) * 16)
121 CVMX_ADD_IO_SEG(0x00011F000000BD10ull) 121#define CVMX_PEXP_NPEI_PKT_IN_INSTR_COUNTS (CVMX_ADD_IO_SEG(0x00011F00000086A0ull))
122#define CVMX_PEXP_NPEI_MSI_W1C_ENB3 \ 122#define CVMX_PEXP_NPEI_PKT_IN_PCIE_PORT (CVMX_ADD_IO_SEG(0x00011F00000091A0ull))
123 CVMX_ADD_IO_SEG(0x00011F000000BD20ull) 123#define CVMX_PEXP_NPEI_PKT_IPTR (CVMX_ADD_IO_SEG(0x00011F0000009070ull))
124#define CVMX_PEXP_NPEI_MSI_W1S_ENB0 \ 124#define CVMX_PEXP_NPEI_PKT_OUTPUT_WMARK (CVMX_ADD_IO_SEG(0x00011F0000009160ull))
125 CVMX_ADD_IO_SEG(0x00011F000000BD30ull) 125#define CVMX_PEXP_NPEI_PKT_OUT_BMODE (CVMX_ADD_IO_SEG(0x00011F00000090D0ull))
126#define CVMX_PEXP_NPEI_MSI_W1S_ENB1 \ 126#define CVMX_PEXP_NPEI_PKT_OUT_ENB (CVMX_ADD_IO_SEG(0x00011F0000009010ull))
127 CVMX_ADD_IO_SEG(0x00011F000000BD40ull) 127#define CVMX_PEXP_NPEI_PKT_PCIE_PORT (CVMX_ADD_IO_SEG(0x00011F00000090E0ull))
128#define CVMX_PEXP_NPEI_MSI_W1S_ENB2 \ 128#define CVMX_PEXP_NPEI_PKT_PORT_IN_RST (CVMX_ADD_IO_SEG(0x00011F0000008690ull))
129 CVMX_ADD_IO_SEG(0x00011F000000BD50ull) 129#define CVMX_PEXP_NPEI_PKT_SLIST_ES (CVMX_ADD_IO_SEG(0x00011F0000009050ull))
130#define CVMX_PEXP_NPEI_MSI_W1S_ENB3 \ 130#define CVMX_PEXP_NPEI_PKT_SLIST_ID_SIZE (CVMX_ADD_IO_SEG(0x00011F0000009180ull))
131 CVMX_ADD_IO_SEG(0x00011F000000BD60ull) 131#define CVMX_PEXP_NPEI_PKT_SLIST_NS (CVMX_ADD_IO_SEG(0x00011F0000009040ull))
132#define CVMX_PEXP_NPEI_MSI_WR_MAP \ 132#define CVMX_PEXP_NPEI_PKT_SLIST_ROR (CVMX_ADD_IO_SEG(0x00011F0000009030ull))
133 CVMX_ADD_IO_SEG(0x00011F000000BC90ull) 133#define CVMX_PEXP_NPEI_PKT_TIME_INT (CVMX_ADD_IO_SEG(0x00011F0000009120ull))
134#define CVMX_PEXP_NPEI_PCIE_CREDIT_CNT \ 134#define CVMX_PEXP_NPEI_PKT_TIME_INT_ENB (CVMX_ADD_IO_SEG(0x00011F0000009140ull))
135 CVMX_ADD_IO_SEG(0x00011F000000BD70ull) 135#define CVMX_PEXP_NPEI_RSL_INT_BLOCKS (CVMX_ADD_IO_SEG(0x00011F0000008520ull))
136#define CVMX_PEXP_NPEI_PCIE_MSI_RCV \ 136#define CVMX_PEXP_NPEI_SCRATCH_1 (CVMX_ADD_IO_SEG(0x00011F0000008270ull))
137 CVMX_ADD_IO_SEG(0x00011F000000BCB0ull) 137#define CVMX_PEXP_NPEI_STATE1 (CVMX_ADD_IO_SEG(0x00011F0000008620ull))
138#define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B1 \ 138#define CVMX_PEXP_NPEI_STATE2 (CVMX_ADD_IO_SEG(0x00011F0000008630ull))
139 CVMX_ADD_IO_SEG(0x00011F0000008650ull) 139#define CVMX_PEXP_NPEI_STATE3 (CVMX_ADD_IO_SEG(0x00011F0000008640ull))
140#define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B2 \ 140#define CVMX_PEXP_NPEI_WINDOW_CTL (CVMX_ADD_IO_SEG(0x00011F0000008380ull))
141 CVMX_ADD_IO_SEG(0x00011F0000008660ull) 141#define CVMX_PEXP_SLI_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011F0000010580ull))
142#define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B3 \ 142#define CVMX_PEXP_SLI_CTL_PORTX(offset) (CVMX_ADD_IO_SEG(0x00011F0000010050ull) + ((offset) & 1) * 16)
143 CVMX_ADD_IO_SEG(0x00011F0000008670ull) 143#define CVMX_PEXP_SLI_CTL_STATUS (CVMX_ADD_IO_SEG(0x00011F0000010570ull))
144#define CVMX_PEXP_NPEI_PKTX_CNTS(offset) \ 144#define CVMX_PEXP_SLI_DATA_OUT_CNT (CVMX_ADD_IO_SEG(0x00011F00000105F0ull))
145 CVMX_ADD_IO_SEG(0x00011F000000A400ull + (((offset) & 31) * 16)) 145#define CVMX_PEXP_SLI_DBG_DATA (CVMX_ADD_IO_SEG(0x00011F0000010310ull))
146#define CVMX_PEXP_NPEI_PKTX_INSTR_BADDR(offset) \ 146#define CVMX_PEXP_SLI_DBG_SELECT (CVMX_ADD_IO_SEG(0x00011F0000010300ull))
147 CVMX_ADD_IO_SEG(0x00011F000000A800ull + (((offset) & 31) * 16)) 147#define CVMX_PEXP_SLI_DMAX_CNT(offset) (CVMX_ADD_IO_SEG(0x00011F0000010400ull) + ((offset) & 1) * 16)
148#define CVMX_PEXP_NPEI_PKTX_INSTR_BAOFF_DBELL(offset) \ 148#define CVMX_PEXP_SLI_DMAX_INT_LEVEL(offset) (CVMX_ADD_IO_SEG(0x00011F00000103E0ull) + ((offset) & 1) * 16)
149 CVMX_ADD_IO_SEG(0x00011F000000AC00ull + (((offset) & 31) * 16)) 149#define CVMX_PEXP_SLI_DMAX_TIM(offset) (CVMX_ADD_IO_SEG(0x00011F0000010420ull) + ((offset) & 1) * 16)
150#define CVMX_PEXP_NPEI_PKTX_INSTR_FIFO_RSIZE(offset) \ 150#define CVMX_PEXP_SLI_INT_ENB_CIU (CVMX_ADD_IO_SEG(0x00011F0000013CD0ull))
151 CVMX_ADD_IO_SEG(0x00011F000000B000ull + (((offset) & 31) * 16)) 151#define CVMX_PEXP_SLI_INT_ENB_PORTX(offset) (CVMX_ADD_IO_SEG(0x00011F0000010340ull) + ((offset) & 1) * 16)
152#define CVMX_PEXP_NPEI_PKTX_INSTR_HEADER(offset) \ 152#define CVMX_PEXP_SLI_INT_SUM (CVMX_ADD_IO_SEG(0x00011F0000010330ull))
153 CVMX_ADD_IO_SEG(0x00011F000000B400ull + (((offset) & 31) * 16)) 153#define CVMX_PEXP_SLI_LAST_WIN_RDATA0 (CVMX_ADD_IO_SEG(0x00011F0000010600ull))
154#define CVMX_PEXP_NPEI_PKTX_IN_BP(offset) \ 154#define CVMX_PEXP_SLI_LAST_WIN_RDATA1 (CVMX_ADD_IO_SEG(0x00011F0000010610ull))
155 CVMX_ADD_IO_SEG(0x00011F000000B800ull + (((offset) & 31) * 16)) 155#define CVMX_PEXP_SLI_MAC_CREDIT_CNT (CVMX_ADD_IO_SEG(0x00011F0000013D70ull))
156#define CVMX_PEXP_NPEI_PKTX_SLIST_BADDR(offset) \ 156#define CVMX_PEXP_SLI_MEM_ACCESS_CTL (CVMX_ADD_IO_SEG(0x00011F00000102F0ull))
157 CVMX_ADD_IO_SEG(0x00011F0000009400ull + (((offset) & 31) * 16)) 157#define CVMX_PEXP_SLI_MEM_ACCESS_SUBIDX(offset) (CVMX_ADD_IO_SEG(0x00011F00000100E0ull) + ((offset) & 31) * 16 - 16*12)
158#define CVMX_PEXP_NPEI_PKTX_SLIST_BAOFF_DBELL(offset) \ 158#define CVMX_PEXP_SLI_MSI_ENB0 (CVMX_ADD_IO_SEG(0x00011F0000013C50ull))
159 CVMX_ADD_IO_SEG(0x00011F0000009800ull + (((offset) & 31) * 16)) 159#define CVMX_PEXP_SLI_MSI_ENB1 (CVMX_ADD_IO_SEG(0x00011F0000013C60ull))
160#define CVMX_PEXP_NPEI_PKTX_SLIST_FIFO_RSIZE(offset) \ 160#define CVMX_PEXP_SLI_MSI_ENB2 (CVMX_ADD_IO_SEG(0x00011F0000013C70ull))
161 CVMX_ADD_IO_SEG(0x00011F0000009C00ull + (((offset) & 31) * 16)) 161#define CVMX_PEXP_SLI_MSI_ENB3 (CVMX_ADD_IO_SEG(0x00011F0000013C80ull))
162#define CVMX_PEXP_NPEI_PKT_CNT_INT \ 162#define CVMX_PEXP_SLI_MSI_RCV0 (CVMX_ADD_IO_SEG(0x00011F0000013C10ull))
163 CVMX_ADD_IO_SEG(0x00011F0000009110ull) 163#define CVMX_PEXP_SLI_MSI_RCV1 (CVMX_ADD_IO_SEG(0x00011F0000013C20ull))
164#define CVMX_PEXP_NPEI_PKT_CNT_INT_ENB \ 164#define CVMX_PEXP_SLI_MSI_RCV2 (CVMX_ADD_IO_SEG(0x00011F0000013C30ull))
165 CVMX_ADD_IO_SEG(0x00011F0000009130ull) 165#define CVMX_PEXP_SLI_MSI_RCV3 (CVMX_ADD_IO_SEG(0x00011F0000013C40ull))
166#define CVMX_PEXP_NPEI_PKT_DATA_OUT_ES \ 166#define CVMX_PEXP_SLI_MSI_RD_MAP (CVMX_ADD_IO_SEG(0x00011F0000013CA0ull))
167 CVMX_ADD_IO_SEG(0x00011F00000090B0ull) 167#define CVMX_PEXP_SLI_MSI_W1C_ENB0 (CVMX_ADD_IO_SEG(0x00011F0000013CF0ull))
168#define CVMX_PEXP_NPEI_PKT_DATA_OUT_NS \ 168#define CVMX_PEXP_SLI_MSI_W1C_ENB1 (CVMX_ADD_IO_SEG(0x00011F0000013D00ull))
169 CVMX_ADD_IO_SEG(0x00011F00000090A0ull) 169#define CVMX_PEXP_SLI_MSI_W1C_ENB2 (CVMX_ADD_IO_SEG(0x00011F0000013D10ull))
170#define CVMX_PEXP_NPEI_PKT_DATA_OUT_ROR \ 170#define CVMX_PEXP_SLI_MSI_W1C_ENB3 (CVMX_ADD_IO_SEG(0x00011F0000013D20ull))
171 CVMX_ADD_IO_SEG(0x00011F0000009090ull) 171#define CVMX_PEXP_SLI_MSI_W1S_ENB0 (CVMX_ADD_IO_SEG(0x00011F0000013D30ull))
172#define CVMX_PEXP_NPEI_PKT_DPADDR \ 172#define CVMX_PEXP_SLI_MSI_W1S_ENB1 (CVMX_ADD_IO_SEG(0x00011F0000013D40ull))
173 CVMX_ADD_IO_SEG(0x00011F0000009080ull) 173#define CVMX_PEXP_SLI_MSI_W1S_ENB2 (CVMX_ADD_IO_SEG(0x00011F0000013D50ull))
174#define CVMX_PEXP_NPEI_PKT_INPUT_CONTROL \ 174#define CVMX_PEXP_SLI_MSI_W1S_ENB3 (CVMX_ADD_IO_SEG(0x00011F0000013D60ull))
175 CVMX_ADD_IO_SEG(0x00011F0000009150ull) 175#define CVMX_PEXP_SLI_MSI_WR_MAP (CVMX_ADD_IO_SEG(0x00011F0000013C90ull))
176#define CVMX_PEXP_NPEI_PKT_INSTR_ENB \ 176#define CVMX_PEXP_SLI_PCIE_MSI_RCV (CVMX_ADD_IO_SEG(0x00011F0000013CB0ull))
177 CVMX_ADD_IO_SEG(0x00011F0000009000ull) 177#define CVMX_PEXP_SLI_PCIE_MSI_RCV_B1 (CVMX_ADD_IO_SEG(0x00011F0000010650ull))
178#define CVMX_PEXP_NPEI_PKT_INSTR_RD_SIZE \ 178#define CVMX_PEXP_SLI_PCIE_MSI_RCV_B2 (CVMX_ADD_IO_SEG(0x00011F0000010660ull))
179 CVMX_ADD_IO_SEG(0x00011F0000009190ull) 179#define CVMX_PEXP_SLI_PCIE_MSI_RCV_B3 (CVMX_ADD_IO_SEG(0x00011F0000010670ull))
180#define CVMX_PEXP_NPEI_PKT_INSTR_SIZE \ 180#define CVMX_PEXP_SLI_PKTX_CNTS(offset) (CVMX_ADD_IO_SEG(0x00011F0000012400ull) + ((offset) & 31) * 16)
181 CVMX_ADD_IO_SEG(0x00011F0000009020ull) 181#define CVMX_PEXP_SLI_PKTX_INSTR_BADDR(offset) (CVMX_ADD_IO_SEG(0x00011F0000012800ull) + ((offset) & 31) * 16)
182#define CVMX_PEXP_NPEI_PKT_INT_LEVELS \ 182#define CVMX_PEXP_SLI_PKTX_INSTR_BAOFF_DBELL(offset) (CVMX_ADD_IO_SEG(0x00011F0000012C00ull) + ((offset) & 31) * 16)
183 CVMX_ADD_IO_SEG(0x00011F0000009100ull) 183#define CVMX_PEXP_SLI_PKTX_INSTR_FIFO_RSIZE(offset) (CVMX_ADD_IO_SEG(0x00011F0000013000ull) + ((offset) & 31) * 16)
184#define CVMX_PEXP_NPEI_PKT_IN_BP \ 184#define CVMX_PEXP_SLI_PKTX_INSTR_HEADER(offset) (CVMX_ADD_IO_SEG(0x00011F0000013400ull) + ((offset) & 31) * 16)
185 CVMX_ADD_IO_SEG(0x00011F00000086B0ull) 185#define CVMX_PEXP_SLI_PKTX_IN_BP(offset) (CVMX_ADD_IO_SEG(0x00011F0000013800ull) + ((offset) & 31) * 16)
186#define CVMX_PEXP_NPEI_PKT_IN_DONEX_CNTS(offset) \ 186#define CVMX_PEXP_SLI_PKTX_OUT_SIZE(offset) (CVMX_ADD_IO_SEG(0x00011F0000010C00ull) + ((offset) & 31) * 16)
187 CVMX_ADD_IO_SEG(0x00011F000000A000ull + (((offset) & 31) * 16)) 187#define CVMX_PEXP_SLI_PKTX_SLIST_BADDR(offset) (CVMX_ADD_IO_SEG(0x00011F0000011400ull) + ((offset) & 31) * 16)
188#define CVMX_PEXP_NPEI_PKT_IN_INSTR_COUNTS \ 188#define CVMX_PEXP_SLI_PKTX_SLIST_BAOFF_DBELL(offset) (CVMX_ADD_IO_SEG(0x00011F0000011800ull) + ((offset) & 31) * 16)
189 CVMX_ADD_IO_SEG(0x00011F00000086A0ull) 189#define CVMX_PEXP_SLI_PKTX_SLIST_FIFO_RSIZE(offset) (CVMX_ADD_IO_SEG(0x00011F0000011C00ull) + ((offset) & 31) * 16)
190#define CVMX_PEXP_NPEI_PKT_IN_PCIE_PORT \ 190#define CVMX_PEXP_SLI_PKT_CNT_INT (CVMX_ADD_IO_SEG(0x00011F0000011130ull))
191 CVMX_ADD_IO_SEG(0x00011F00000091A0ull) 191#define CVMX_PEXP_SLI_PKT_CNT_INT_ENB (CVMX_ADD_IO_SEG(0x00011F0000011150ull))
192#define CVMX_PEXP_NPEI_PKT_IPTR \ 192#define CVMX_PEXP_SLI_PKT_CTL (CVMX_ADD_IO_SEG(0x00011F0000011220ull))
193 CVMX_ADD_IO_SEG(0x00011F0000009070ull) 193#define CVMX_PEXP_SLI_PKT_DATA_OUT_ES (CVMX_ADD_IO_SEG(0x00011F00000110B0ull))
194#define CVMX_PEXP_NPEI_PKT_OUTPUT_WMARK \ 194#define CVMX_PEXP_SLI_PKT_DATA_OUT_NS (CVMX_ADD_IO_SEG(0x00011F00000110A0ull))
195 CVMX_ADD_IO_SEG(0x00011F0000009160ull) 195#define CVMX_PEXP_SLI_PKT_DATA_OUT_ROR (CVMX_ADD_IO_SEG(0x00011F0000011090ull))
196#define CVMX_PEXP_NPEI_PKT_OUT_BMODE \ 196#define CVMX_PEXP_SLI_PKT_DPADDR (CVMX_ADD_IO_SEG(0x00011F0000011080ull))
197 CVMX_ADD_IO_SEG(0x00011F00000090D0ull) 197#define CVMX_PEXP_SLI_PKT_INPUT_CONTROL (CVMX_ADD_IO_SEG(0x00011F0000011170ull))
198#define CVMX_PEXP_NPEI_PKT_OUT_ENB \ 198#define CVMX_PEXP_SLI_PKT_INSTR_ENB (CVMX_ADD_IO_SEG(0x00011F0000011000ull))
199 CVMX_ADD_IO_SEG(0x00011F0000009010ull) 199#define CVMX_PEXP_SLI_PKT_INSTR_RD_SIZE (CVMX_ADD_IO_SEG(0x00011F00000111A0ull))
200#define CVMX_PEXP_NPEI_PKT_PCIE_PORT \ 200#define CVMX_PEXP_SLI_PKT_INSTR_SIZE (CVMX_ADD_IO_SEG(0x00011F0000011020ull))
201 CVMX_ADD_IO_SEG(0x00011F00000090E0ull) 201#define CVMX_PEXP_SLI_PKT_INT_LEVELS (CVMX_ADD_IO_SEG(0x00011F0000011120ull))
202#define CVMX_PEXP_NPEI_PKT_PORT_IN_RST \ 202#define CVMX_PEXP_SLI_PKT_IN_BP (CVMX_ADD_IO_SEG(0x00011F0000011210ull))
203 CVMX_ADD_IO_SEG(0x00011F0000008690ull) 203#define CVMX_PEXP_SLI_PKT_IN_DONEX_CNTS(offset) (CVMX_ADD_IO_SEG(0x00011F0000012000ull) + ((offset) & 31) * 16)
204#define CVMX_PEXP_NPEI_PKT_SLIST_ES \ 204#define CVMX_PEXP_SLI_PKT_IN_INSTR_COUNTS (CVMX_ADD_IO_SEG(0x00011F0000011200ull))
205 CVMX_ADD_IO_SEG(0x00011F0000009050ull) 205#define CVMX_PEXP_SLI_PKT_IN_PCIE_PORT (CVMX_ADD_IO_SEG(0x00011F00000111B0ull))
206#define CVMX_PEXP_NPEI_PKT_SLIST_ID_SIZE \ 206#define CVMX_PEXP_SLI_PKT_IPTR (CVMX_ADD_IO_SEG(0x00011F0000011070ull))
207 CVMX_ADD_IO_SEG(0x00011F0000009180ull) 207#define CVMX_PEXP_SLI_PKT_OUTPUT_WMARK (CVMX_ADD_IO_SEG(0x00011F0000011180ull))
208#define CVMX_PEXP_NPEI_PKT_SLIST_NS \ 208#define CVMX_PEXP_SLI_PKT_OUT_BMODE (CVMX_ADD_IO_SEG(0x00011F00000110D0ull))
209 CVMX_ADD_IO_SEG(0x00011F0000009040ull) 209#define CVMX_PEXP_SLI_PKT_OUT_ENB (CVMX_ADD_IO_SEG(0x00011F0000011010ull))
210#define CVMX_PEXP_NPEI_PKT_SLIST_ROR \ 210#define CVMX_PEXP_SLI_PKT_PCIE_PORT (CVMX_ADD_IO_SEG(0x00011F00000110E0ull))
211 CVMX_ADD_IO_SEG(0x00011F0000009030ull) 211#define CVMX_PEXP_SLI_PKT_PORT_IN_RST (CVMX_ADD_IO_SEG(0x00011F00000111F0ull))
212#define CVMX_PEXP_NPEI_PKT_TIME_INT \ 212#define CVMX_PEXP_SLI_PKT_SLIST_ES (CVMX_ADD_IO_SEG(0x00011F0000011050ull))
213 CVMX_ADD_IO_SEG(0x00011F0000009120ull) 213#define CVMX_PEXP_SLI_PKT_SLIST_NS (CVMX_ADD_IO_SEG(0x00011F0000011040ull))
214#define CVMX_PEXP_NPEI_PKT_TIME_INT_ENB \ 214#define CVMX_PEXP_SLI_PKT_SLIST_ROR (CVMX_ADD_IO_SEG(0x00011F0000011030ull))
215 CVMX_ADD_IO_SEG(0x00011F0000009140ull) 215#define CVMX_PEXP_SLI_PKT_TIME_INT (CVMX_ADD_IO_SEG(0x00011F0000011140ull))
216#define CVMX_PEXP_NPEI_RSL_INT_BLOCKS \ 216#define CVMX_PEXP_SLI_PKT_TIME_INT_ENB (CVMX_ADD_IO_SEG(0x00011F0000011160ull))
217 CVMX_ADD_IO_SEG(0x00011F0000008520ull) 217#define CVMX_PEXP_SLI_S2M_PORTX_CTL(offset) (CVMX_ADD_IO_SEG(0x00011F0000013D80ull) + ((offset) & 1) * 16)
218#define CVMX_PEXP_NPEI_SCRATCH_1 \ 218#define CVMX_PEXP_SLI_SCRATCH_1 (CVMX_ADD_IO_SEG(0x00011F00000103C0ull))
219 CVMX_ADD_IO_SEG(0x00011F0000008270ull) 219#define CVMX_PEXP_SLI_SCRATCH_2 (CVMX_ADD_IO_SEG(0x00011F00000103D0ull))
220#define CVMX_PEXP_NPEI_STATE1 \ 220#define CVMX_PEXP_SLI_STATE1 (CVMX_ADD_IO_SEG(0x00011F0000010620ull))
221 CVMX_ADD_IO_SEG(0x00011F0000008620ull) 221#define CVMX_PEXP_SLI_STATE2 (CVMX_ADD_IO_SEG(0x00011F0000010630ull))
222#define CVMX_PEXP_NPEI_STATE2 \ 222#define CVMX_PEXP_SLI_STATE3 (CVMX_ADD_IO_SEG(0x00011F0000010640ull))
223 CVMX_ADD_IO_SEG(0x00011F0000008630ull) 223#define CVMX_PEXP_SLI_WINDOW_CTL (CVMX_ADD_IO_SEG(0x00011F00000102E0ull))
224#define CVMX_PEXP_NPEI_STATE3 \
225 CVMX_ADD_IO_SEG(0x00011F0000008640ull)
226#define CVMX_PEXP_NPEI_WINDOW_CTL \
227 CVMX_ADD_IO_SEG(0x00011F0000008380ull)
228 224
229#endif 225#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-10 07:19:53 -0500