1 files changed, 121 insertions, 241 deletions
diff --git a/arch/mips/include/asm/octeon/cvmx-npi-defs.h b/arch/mips/include/asm/octeon/cvmx-npi-defs.h
index 4e03cd8561e3..f089c780060f 100644
--- a/arch/mips/include/asm/octeon/cvmx-npi-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-npi-defs.h
@@ -4,7 +4,7 @@
 * Contact: support@caviumnetworks.com
 * This file is part of the OCTEON SDK
 *
- * Copyright (c) 2003-2008 Cavium Networks
+ * Copyright (c) 2003-2010 Cavium Networks
 *
 * This file is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License, Version 2, as
@@ -28,246 +28,126 @@
 #ifndef __CVMX_NPI_DEFS_H__
 #define __CVMX_NPI_DEFS_H__
-#define CVMX_NPI_BASE_ADDR_INPUT0 \
+#define CVMX_NPI_BASE_ADDR_INPUT0 CVMX_NPI_BASE_ADDR_INPUTX(0)
-         CVMX_ADD_IO_SEG(0x00011F0000000070ull)
+#define CVMX_NPI_BASE_ADDR_INPUT1 CVMX_NPI_BASE_ADDR_INPUTX(1)
-#define CVMX_NPI_BASE_ADDR_INPUT1 \
+#define CVMX_NPI_BASE_ADDR_INPUT2 CVMX_NPI_BASE_ADDR_INPUTX(2)
-         CVMX_ADD_IO_SEG(0x00011F0000000080ull)
+#define CVMX_NPI_BASE_ADDR_INPUT3 CVMX_NPI_BASE_ADDR_INPUTX(3)
-#define CVMX_NPI_BASE_ADDR_INPUT2 \
+#define CVMX_NPI_BASE_ADDR_INPUTX(offset) (CVMX_ADD_IO_SEG(0x00011F0000000070ull) + ((offset) & 3) * 16)
-         CVMX_ADD_IO_SEG(0x00011F0000000090ull)
+#define CVMX_NPI_BASE_ADDR_OUTPUT0 CVMX_NPI_BASE_ADDR_OUTPUTX(0)
-#define CVMX_NPI_BASE_ADDR_INPUT3 \
+#define CVMX_NPI_BASE_ADDR_OUTPUT1 CVMX_NPI_BASE_ADDR_OUTPUTX(1)
-         CVMX_ADD_IO_SEG(0x00011F00000000A0ull)
+#define CVMX_NPI_BASE_ADDR_OUTPUT2 CVMX_NPI_BASE_ADDR_OUTPUTX(2)
-#define CVMX_NPI_BASE_ADDR_INPUTX(offset) \
+#define CVMX_NPI_BASE_ADDR_OUTPUT3 CVMX_NPI_BASE_ADDR_OUTPUTX(3)
-         CVMX_ADD_IO_SEG(0x00011F0000000070ull + (((offset) & 3) * 16))
+#define CVMX_NPI_BASE_ADDR_OUTPUTX(offset) (CVMX_ADD_IO_SEG(0x00011F00000000B8ull) + ((offset) & 3) * 8)
-#define CVMX_NPI_BASE_ADDR_OUTPUT0 \
+#define CVMX_NPI_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011F00000003F8ull))
-         CVMX_ADD_IO_SEG(0x00011F00000000B8ull)
+#define CVMX_NPI_BUFF_SIZE_OUTPUT0 CVMX_NPI_BUFF_SIZE_OUTPUTX(0)
-#define CVMX_NPI_BASE_ADDR_OUTPUT1 \
+#define CVMX_NPI_BUFF_SIZE_OUTPUT1 CVMX_NPI_BUFF_SIZE_OUTPUTX(1)
-         CVMX_ADD_IO_SEG(0x00011F00000000C0ull)
+#define CVMX_NPI_BUFF_SIZE_OUTPUT2 CVMX_NPI_BUFF_SIZE_OUTPUTX(2)
-#define CVMX_NPI_BASE_ADDR_OUTPUT2 \
+#define CVMX_NPI_BUFF_SIZE_OUTPUT3 CVMX_NPI_BUFF_SIZE_OUTPUTX(3)
-         CVMX_ADD_IO_SEG(0x00011F00000000C8ull)
+#define CVMX_NPI_BUFF_SIZE_OUTPUTX(offset) (CVMX_ADD_IO_SEG(0x00011F00000000E0ull) + ((offset) & 3) * 8)
-#define CVMX_NPI_BASE_ADDR_OUTPUT3 \
+#define CVMX_NPI_COMP_CTL (CVMX_ADD_IO_SEG(0x00011F0000000218ull))
-         CVMX_ADD_IO_SEG(0x00011F00000000D0ull)
+#define CVMX_NPI_CTL_STATUS (CVMX_ADD_IO_SEG(0x00011F0000000010ull))
-#define CVMX_NPI_BASE_ADDR_OUTPUTX(offset) \
+#define CVMX_NPI_DBG_SELECT (CVMX_ADD_IO_SEG(0x00011F0000000008ull))
-         CVMX_ADD_IO_SEG(0x00011F00000000B8ull + (((offset) & 3) * 8))
+#define CVMX_NPI_DMA_CONTROL (CVMX_ADD_IO_SEG(0x00011F0000000128ull))
-#define CVMX_NPI_BIST_STATUS \
+#define CVMX_NPI_DMA_HIGHP_COUNTS (CVMX_ADD_IO_SEG(0x00011F0000000148ull))
-         CVMX_ADD_IO_SEG(0x00011F00000003F8ull)
+#define CVMX_NPI_DMA_HIGHP_NADDR (CVMX_ADD_IO_SEG(0x00011F0000000158ull))
-#define CVMX_NPI_BUFF_SIZE_OUTPUT0 \
+#define CVMX_NPI_DMA_LOWP_COUNTS (CVMX_ADD_IO_SEG(0x00011F0000000140ull))
-         CVMX_ADD_IO_SEG(0x00011F00000000E0ull)
+#define CVMX_NPI_DMA_LOWP_NADDR (CVMX_ADD_IO_SEG(0x00011F0000000150ull))
-#define CVMX_NPI_BUFF_SIZE_OUTPUT1 \
+#define CVMX_NPI_HIGHP_DBELL (CVMX_ADD_IO_SEG(0x00011F0000000120ull))
-         CVMX_ADD_IO_SEG(0x00011F00000000E8ull)
+#define CVMX_NPI_HIGHP_IBUFF_SADDR (CVMX_ADD_IO_SEG(0x00011F0000000110ull))
-#define CVMX_NPI_BUFF_SIZE_OUTPUT2 \
+#define CVMX_NPI_INPUT_CONTROL (CVMX_ADD_IO_SEG(0x00011F0000000138ull))
-         CVMX_ADD_IO_SEG(0x00011F00000000F0ull)
+#define CVMX_NPI_INT_ENB (CVMX_ADD_IO_SEG(0x00011F0000000020ull))
-#define CVMX_NPI_BUFF_SIZE_OUTPUT3 \
+#define CVMX_NPI_INT_SUM (CVMX_ADD_IO_SEG(0x00011F0000000018ull))
-         CVMX_ADD_IO_SEG(0x00011F00000000F8ull)
+#define CVMX_NPI_LOWP_DBELL (CVMX_ADD_IO_SEG(0x00011F0000000118ull))
-#define CVMX_NPI_BUFF_SIZE_OUTPUTX(offset) \
+#define CVMX_NPI_LOWP_IBUFF_SADDR (CVMX_ADD_IO_SEG(0x00011F0000000108ull))
-         CVMX_ADD_IO_SEG(0x00011F00000000E0ull + (((offset) & 3) * 8))
+#define CVMX_NPI_MEM_ACCESS_SUBID3 CVMX_NPI_MEM_ACCESS_SUBIDX(3)
-#define CVMX_NPI_COMP_CTL \
+#define CVMX_NPI_MEM_ACCESS_SUBID4 CVMX_NPI_MEM_ACCESS_SUBIDX(4)
-         CVMX_ADD_IO_SEG(0x00011F0000000218ull)
+#define CVMX_NPI_MEM_ACCESS_SUBID5 CVMX_NPI_MEM_ACCESS_SUBIDX(5)
-#define CVMX_NPI_CTL_STATUS \
+#define CVMX_NPI_MEM_ACCESS_SUBID6 CVMX_NPI_MEM_ACCESS_SUBIDX(6)
-         CVMX_ADD_IO_SEG(0x00011F0000000010ull)
+#define CVMX_NPI_MEM_ACCESS_SUBIDX(offset) (CVMX_ADD_IO_SEG(0x00011F0000000028ull) + ((offset) & 7) * 8 - 8*3)
-#define CVMX_NPI_DBG_SELECT \
+#define CVMX_NPI_MSI_RCV (0x0000000000000190ull)
-         CVMX_ADD_IO_SEG(0x00011F0000000008ull)
+#define CVMX_NPI_NPI_MSI_RCV (CVMX_ADD_IO_SEG(0x00011F0000001190ull))
-#define CVMX_NPI_DMA_CONTROL \
+#define CVMX_NPI_NUM_DESC_OUTPUT0 CVMX_NPI_NUM_DESC_OUTPUTX(0)
-         CVMX_ADD_IO_SEG(0x00011F0000000128ull)
+#define CVMX_NPI_NUM_DESC_OUTPUT1 CVMX_NPI_NUM_DESC_OUTPUTX(1)
-#define CVMX_NPI_DMA_HIGHP_COUNTS \
+#define CVMX_NPI_NUM_DESC_OUTPUT2 CVMX_NPI_NUM_DESC_OUTPUTX(2)
-         CVMX_ADD_IO_SEG(0x00011F0000000148ull)
+#define CVMX_NPI_NUM_DESC_OUTPUT3 CVMX_NPI_NUM_DESC_OUTPUTX(3)
-#define CVMX_NPI_DMA_HIGHP_NADDR \
+#define CVMX_NPI_NUM_DESC_OUTPUTX(offset) (CVMX_ADD_IO_SEG(0x00011F0000000050ull) + ((offset) & 3) * 8)
-         CVMX_ADD_IO_SEG(0x00011F0000000158ull)
+#define CVMX_NPI_OUTPUT_CONTROL (CVMX_ADD_IO_SEG(0x00011F0000000100ull))
-#define CVMX_NPI_DMA_LOWP_COUNTS \
+#define CVMX_NPI_P0_DBPAIR_ADDR CVMX_NPI_PX_DBPAIR_ADDR(0)
-         CVMX_ADD_IO_SEG(0x00011F0000000140ull)
+#define CVMX_NPI_P0_INSTR_ADDR CVMX_NPI_PX_INSTR_ADDR(0)
-#define CVMX_NPI_DMA_LOWP_NADDR \
+#define CVMX_NPI_P0_INSTR_CNTS CVMX_NPI_PX_INSTR_CNTS(0)
-         CVMX_ADD_IO_SEG(0x00011F0000000150ull)
+#define CVMX_NPI_P0_PAIR_CNTS CVMX_NPI_PX_PAIR_CNTS(0)
-#define CVMX_NPI_HIGHP_DBELL \
+#define CVMX_NPI_P1_DBPAIR_ADDR CVMX_NPI_PX_DBPAIR_ADDR(1)
-         CVMX_ADD_IO_SEG(0x00011F0000000120ull)
+#define CVMX_NPI_P1_INSTR_ADDR CVMX_NPI_PX_INSTR_ADDR(1)
-#define CVMX_NPI_HIGHP_IBUFF_SADDR \
+#define CVMX_NPI_P1_INSTR_CNTS CVMX_NPI_PX_INSTR_CNTS(1)
-         CVMX_ADD_IO_SEG(0x00011F0000000110ull)
+#define CVMX_NPI_P1_PAIR_CNTS CVMX_NPI_PX_PAIR_CNTS(1)
-#define CVMX_NPI_INPUT_CONTROL \
+#define CVMX_NPI_P2_DBPAIR_ADDR CVMX_NPI_PX_DBPAIR_ADDR(2)
-         CVMX_ADD_IO_SEG(0x00011F0000000138ull)
+#define CVMX_NPI_P2_INSTR_ADDR CVMX_NPI_PX_INSTR_ADDR(2)
-#define CVMX_NPI_INT_ENB \
+#define CVMX_NPI_P2_INSTR_CNTS CVMX_NPI_PX_INSTR_CNTS(2)
-         CVMX_ADD_IO_SEG(0x00011F0000000020ull)
+#define CVMX_NPI_P2_PAIR_CNTS CVMX_NPI_PX_PAIR_CNTS(2)
-#define CVMX_NPI_INT_SUM \
+#define CVMX_NPI_P3_DBPAIR_ADDR CVMX_NPI_PX_DBPAIR_ADDR(3)
-         CVMX_ADD_IO_SEG(0x00011F0000000018ull)
+#define CVMX_NPI_P3_INSTR_ADDR CVMX_NPI_PX_INSTR_ADDR(3)
-#define CVMX_NPI_LOWP_DBELL \
+#define CVMX_NPI_P3_INSTR_CNTS CVMX_NPI_PX_INSTR_CNTS(3)
-         CVMX_ADD_IO_SEG(0x00011F0000000118ull)
+#define CVMX_NPI_P3_PAIR_CNTS CVMX_NPI_PX_PAIR_CNTS(3)
-#define CVMX_NPI_LOWP_IBUFF_SADDR \
+#define CVMX_NPI_PCI_BAR1_INDEXX(offset) (CVMX_ADD_IO_SEG(0x00011F0000001100ull) + ((offset) & 31) * 4)
-         CVMX_ADD_IO_SEG(0x00011F0000000108ull)
+#define CVMX_NPI_PCI_BIST_REG (CVMX_ADD_IO_SEG(0x00011F00000011C0ull))
-#define CVMX_NPI_MEM_ACCESS_SUBID3 \
+#define CVMX_NPI_PCI_BURST_SIZE (CVMX_ADD_IO_SEG(0x00011F00000000D8ull))
-         CVMX_ADD_IO_SEG(0x00011F0000000028ull)
+#define CVMX_NPI_PCI_CFG00 (CVMX_ADD_IO_SEG(0x00011F0000001800ull))
-#define CVMX_NPI_MEM_ACCESS_SUBID4 \
+#define CVMX_NPI_PCI_CFG01 (CVMX_ADD_IO_SEG(0x00011F0000001804ull))
-         CVMX_ADD_IO_SEG(0x00011F0000000030ull)
+#define CVMX_NPI_PCI_CFG02 (CVMX_ADD_IO_SEG(0x00011F0000001808ull))
-#define CVMX_NPI_MEM_ACCESS_SUBID5 \
+#define CVMX_NPI_PCI_CFG03 (CVMX_ADD_IO_SEG(0x00011F000000180Cull))
-         CVMX_ADD_IO_SEG(0x00011F0000000038ull)
+#define CVMX_NPI_PCI_CFG04 (CVMX_ADD_IO_SEG(0x00011F0000001810ull))
-#define CVMX_NPI_MEM_ACCESS_SUBID6 \
+#define CVMX_NPI_PCI_CFG05 (CVMX_ADD_IO_SEG(0x00011F0000001814ull))
-         CVMX_ADD_IO_SEG(0x00011F0000000040ull)
+#define CVMX_NPI_PCI_CFG06 (CVMX_ADD_IO_SEG(0x00011F0000001818ull))
-#define CVMX_NPI_MEM_ACCESS_SUBIDX(offset) \
+#define CVMX_NPI_PCI_CFG07 (CVMX_ADD_IO_SEG(0x00011F000000181Cull))
-         CVMX_ADD_IO_SEG(0x00011F0000000028ull + (((offset) & 7) * 8) - 8 * 3)
+#define CVMX_NPI_PCI_CFG08 (CVMX_ADD_IO_SEG(0x00011F0000001820ull))
-#define CVMX_NPI_MSI_RCV \
+#define CVMX_NPI_PCI_CFG09 (CVMX_ADD_IO_SEG(0x00011F0000001824ull))
-         (0x0000000000000190ull)
+#define CVMX_NPI_PCI_CFG10 (CVMX_ADD_IO_SEG(0x00011F0000001828ull))
-#define CVMX_NPI_NPI_MSI_RCV \
+#define CVMX_NPI_PCI_CFG11 (CVMX_ADD_IO_SEG(0x00011F000000182Cull))
-         CVMX_ADD_IO_SEG(0x00011F0000001190ull)
+#define CVMX_NPI_PCI_CFG12 (CVMX_ADD_IO_SEG(0x00011F0000001830ull))
-#define CVMX_NPI_NUM_DESC_OUTPUT0 \
+#define CVMX_NPI_PCI_CFG13 (CVMX_ADD_IO_SEG(0x00011F0000001834ull))
-         CVMX_ADD_IO_SEG(0x00011F0000000050ull)
+#define CVMX_NPI_PCI_CFG15 (CVMX_ADD_IO_SEG(0x00011F000000183Cull))
-#define CVMX_NPI_NUM_DESC_OUTPUT1 \
+#define CVMX_NPI_PCI_CFG16 (CVMX_ADD_IO_SEG(0x00011F0000001840ull))
-         CVMX_ADD_IO_SEG(0x00011F0000000058ull)
+#define CVMX_NPI_PCI_CFG17 (CVMX_ADD_IO_SEG(0x00011F0000001844ull))
-#define CVMX_NPI_NUM_DESC_OUTPUT2 \
+#define CVMX_NPI_PCI_CFG18 (CVMX_ADD_IO_SEG(0x00011F0000001848ull))
-         CVMX_ADD_IO_SEG(0x00011F0000000060ull)
+#define CVMX_NPI_PCI_CFG19 (CVMX_ADD_IO_SEG(0x00011F000000184Cull))
-#define CVMX_NPI_NUM_DESC_OUTPUT3 \
+#define CVMX_NPI_PCI_CFG20 (CVMX_ADD_IO_SEG(0x00011F0000001850ull))
-         CVMX_ADD_IO_SEG(0x00011F0000000068ull)
+#define CVMX_NPI_PCI_CFG21 (CVMX_ADD_IO_SEG(0x00011F0000001854ull))
-#define CVMX_NPI_NUM_DESC_OUTPUTX(offset) \
+#define CVMX_NPI_PCI_CFG22 (CVMX_ADD_IO_SEG(0x00011F0000001858ull))
-         CVMX_ADD_IO_SEG(0x00011F0000000050ull + (((offset) & 3) * 8))
+#define CVMX_NPI_PCI_CFG56 (CVMX_ADD_IO_SEG(0x00011F00000018E0ull))
-#define CVMX_NPI_OUTPUT_CONTROL \
+#define CVMX_NPI_PCI_CFG57 (CVMX_ADD_IO_SEG(0x00011F00000018E4ull))
-         CVMX_ADD_IO_SEG(0x00011F0000000100ull)
+#define CVMX_NPI_PCI_CFG58 (CVMX_ADD_IO_SEG(0x00011F00000018E8ull))
-#define CVMX_NPI_P0_DBPAIR_ADDR \
+#define CVMX_NPI_PCI_CFG59 (CVMX_ADD_IO_SEG(0x00011F00000018ECull))
-         CVMX_ADD_IO_SEG(0x00011F0000000180ull)
+#define CVMX_NPI_PCI_CFG60 (CVMX_ADD_IO_SEG(0x00011F00000018F0ull))
-#define CVMX_NPI_P0_INSTR_ADDR \
+#define CVMX_NPI_PCI_CFG61 (CVMX_ADD_IO_SEG(0x00011F00000018F4ull))
-         CVMX_ADD_IO_SEG(0x00011F00000001C0ull)
+#define CVMX_NPI_PCI_CFG62 (CVMX_ADD_IO_SEG(0x00011F00000018F8ull))
-#define CVMX_NPI_P0_INSTR_CNTS \
+#define CVMX_NPI_PCI_CFG63 (CVMX_ADD_IO_SEG(0x00011F00000018FCull))
-         CVMX_ADD_IO_SEG(0x00011F00000001A0ull)
+#define CVMX_NPI_PCI_CNT_REG (CVMX_ADD_IO_SEG(0x00011F00000011B8ull))
-#define CVMX_NPI_P0_PAIR_CNTS \
+#define CVMX_NPI_PCI_CTL_STATUS_2 (CVMX_ADD_IO_SEG(0x00011F000000118Cull))
-         CVMX_ADD_IO_SEG(0x00011F0000000160ull)
+#define CVMX_NPI_PCI_INT_ARB_CFG (CVMX_ADD_IO_SEG(0x00011F0000000130ull))
-#define CVMX_NPI_P1_DBPAIR_ADDR \
+#define CVMX_NPI_PCI_INT_ENB2 (CVMX_ADD_IO_SEG(0x00011F00000011A0ull))
-         CVMX_ADD_IO_SEG(0x00011F0000000188ull)
+#define CVMX_NPI_PCI_INT_SUM2 (CVMX_ADD_IO_SEG(0x00011F0000001198ull))
-#define CVMX_NPI_P1_INSTR_ADDR \
+#define CVMX_NPI_PCI_READ_CMD (CVMX_ADD_IO_SEG(0x00011F0000000048ull))
-         CVMX_ADD_IO_SEG(0x00011F00000001C8ull)
+#define CVMX_NPI_PCI_READ_CMD_6 (CVMX_ADD_IO_SEG(0x00011F0000001180ull))
-#define CVMX_NPI_P1_INSTR_CNTS \
+#define CVMX_NPI_PCI_READ_CMD_C (CVMX_ADD_IO_SEG(0x00011F0000001184ull))
-         CVMX_ADD_IO_SEG(0x00011F00000001A8ull)
+#define CVMX_NPI_PCI_READ_CMD_E (CVMX_ADD_IO_SEG(0x00011F0000001188ull))
-#define CVMX_NPI_P1_PAIR_CNTS \
+#define CVMX_NPI_PCI_SCM_REG (CVMX_ADD_IO_SEG(0x00011F00000011A8ull))
-         CVMX_ADD_IO_SEG(0x00011F0000000168ull)
+#define CVMX_NPI_PCI_TSR_REG (CVMX_ADD_IO_SEG(0x00011F00000011B0ull))
-#define CVMX_NPI_P2_DBPAIR_ADDR \
+#define CVMX_NPI_PORT32_INSTR_HDR (CVMX_ADD_IO_SEG(0x00011F00000001F8ull))
-         CVMX_ADD_IO_SEG(0x00011F0000000190ull)
+#define CVMX_NPI_PORT33_INSTR_HDR (CVMX_ADD_IO_SEG(0x00011F0000000200ull))
-#define CVMX_NPI_P2_INSTR_ADDR \
+#define CVMX_NPI_PORT34_INSTR_HDR (CVMX_ADD_IO_SEG(0x00011F0000000208ull))
-         CVMX_ADD_IO_SEG(0x00011F00000001D0ull)
+#define CVMX_NPI_PORT35_INSTR_HDR (CVMX_ADD_IO_SEG(0x00011F0000000210ull))
-#define CVMX_NPI_P2_INSTR_CNTS \
+#define CVMX_NPI_PORT_BP_CONTROL (CVMX_ADD_IO_SEG(0x00011F00000001F0ull))
-         CVMX_ADD_IO_SEG(0x00011F00000001B0ull)
+#define CVMX_NPI_PX_DBPAIR_ADDR(offset) (CVMX_ADD_IO_SEG(0x00011F0000000180ull) + ((offset) & 3) * 8)
-#define CVMX_NPI_P2_PAIR_CNTS \
+#define CVMX_NPI_PX_INSTR_ADDR(offset) (CVMX_ADD_IO_SEG(0x00011F00000001C0ull) + ((offset) & 3) * 8)
-         CVMX_ADD_IO_SEG(0x00011F0000000170ull)
+#define CVMX_NPI_PX_INSTR_CNTS(offset) (CVMX_ADD_IO_SEG(0x00011F00000001A0ull) + ((offset) & 3) * 8)
-#define CVMX_NPI_P3_DBPAIR_ADDR \
+#define CVMX_NPI_PX_PAIR_CNTS(offset) (CVMX_ADD_IO_SEG(0x00011F0000000160ull) + ((offset) & 3) * 8)
-         CVMX_ADD_IO_SEG(0x00011F0000000198ull)
+#define CVMX_NPI_RSL_INT_BLOCKS (CVMX_ADD_IO_SEG(0x00011F0000000000ull))
-#define CVMX_NPI_P3_INSTR_ADDR \
+#define CVMX_NPI_SIZE_INPUT0 CVMX_NPI_SIZE_INPUTX(0)
-         CVMX_ADD_IO_SEG(0x00011F00000001D8ull)
+#define CVMX_NPI_SIZE_INPUT1 CVMX_NPI_SIZE_INPUTX(1)
-#define CVMX_NPI_P3_INSTR_CNTS \
+#define CVMX_NPI_SIZE_INPUT2 CVMX_NPI_SIZE_INPUTX(2)
-         CVMX_ADD_IO_SEG(0x00011F00000001B8ull)
+#define CVMX_NPI_SIZE_INPUT3 CVMX_NPI_SIZE_INPUTX(3)
-#define CVMX_NPI_P3_PAIR_CNTS \
+#define CVMX_NPI_SIZE_INPUTX(offset) (CVMX_ADD_IO_SEG(0x00011F0000000078ull) + ((offset) & 3) * 16)
-         CVMX_ADD_IO_SEG(0x00011F0000000178ull)
+#define CVMX_NPI_WIN_READ_TO (CVMX_ADD_IO_SEG(0x00011F00000001E0ull))
-#define CVMX_NPI_PCI_BAR1_INDEXX(offset) \
-         CVMX_ADD_IO_SEG(0x00011F0000001100ull + (((offset) & 31) * 4))
-#define CVMX_NPI_PCI_BIST_REG \
-         CVMX_ADD_IO_SEG(0x00011F00000011C0ull)
-#define CVMX_NPI_PCI_BURST_SIZE \
-         CVMX_ADD_IO_SEG(0x00011F00000000D8ull)
-#define CVMX_NPI_PCI_CFG00 \
-         CVMX_ADD_IO_SEG(0x00011F0000001800ull)
-#define CVMX_NPI_PCI_CFG01 \
-         CVMX_ADD_IO_SEG(0x00011F0000001804ull)
-#define CVMX_NPI_PCI_CFG02 \
-         CVMX_ADD_IO_SEG(0x00011F0000001808ull)
-#define CVMX_NPI_PCI_CFG03 \
-         CVMX_ADD_IO_SEG(0x00011F000000180Cull)
-#define CVMX_NPI_PCI_CFG04 \
-         CVMX_ADD_IO_SEG(0x00011F0000001810ull)
-#define CVMX_NPI_PCI_CFG05 \
-         CVMX_ADD_IO_SEG(0x00011F0000001814ull)
-#define CVMX_NPI_PCI_CFG06 \
-         CVMX_ADD_IO_SEG(0x00011F0000001818ull)
-#define CVMX_NPI_PCI_CFG07 \
-         CVMX_ADD_IO_SEG(0x00011F000000181Cull)
-#define CVMX_NPI_PCI_CFG08 \
-         CVMX_ADD_IO_SEG(0x00011F0000001820ull)
-#define CVMX_NPI_PCI_CFG09 \
-         CVMX_ADD_IO_SEG(0x00011F0000001824ull)
-#define CVMX_NPI_PCI_CFG10 \
-         CVMX_ADD_IO_SEG(0x00011F0000001828ull)
-#define CVMX_NPI_PCI_CFG11 \
-         CVMX_ADD_IO_SEG(0x00011F000000182Cull)
-#define CVMX_NPI_PCI_CFG12 \
-         CVMX_ADD_IO_SEG(0x00011F0000001830ull)
-#define CVMX_NPI_PCI_CFG13 \
-         CVMX_ADD_IO_SEG(0x00011F0000001834ull)
-#define CVMX_NPI_PCI_CFG15 \
-         CVMX_ADD_IO_SEG(0x00011F000000183Cull)
-#define CVMX_NPI_PCI_CFG16 \
-         CVMX_ADD_IO_SEG(0x00011F0000001840ull)
-#define CVMX_NPI_PCI_CFG17 \
-         CVMX_ADD_IO_SEG(0x00011F0000001844ull)
-#define CVMX_NPI_PCI_CFG18 \
-         CVMX_ADD_IO_SEG(0x00011F0000001848ull)
-#define CVMX_NPI_PCI_CFG19 \
-         CVMX_ADD_IO_SEG(0x00011F000000184Cull)
-#define CVMX_NPI_PCI_CFG20 \
-         CVMX_ADD_IO_SEG(0x00011F0000001850ull)
-#define CVMX_NPI_PCI_CFG21 \
-         CVMX_ADD_IO_SEG(0x00011F0000001854ull)
-#define CVMX_NPI_PCI_CFG22 \
-         CVMX_ADD_IO_SEG(0x00011F0000001858ull)
-#define CVMX_NPI_PCI_CFG56 \
-         CVMX_ADD_IO_SEG(0x00011F00000018E0ull)
-#define CVMX_NPI_PCI_CFG57 \
-         CVMX_ADD_IO_SEG(0x00011F00000018E4ull)
-#define CVMX_NPI_PCI_CFG58 \
-         CVMX_ADD_IO_SEG(0x00011F00000018E8ull)
-#define CVMX_NPI_PCI_CFG59 \
-         CVMX_ADD_IO_SEG(0x00011F00000018ECull)
-#define CVMX_NPI_PCI_CFG60 \
-         CVMX_ADD_IO_SEG(0x00011F00000018F0ull)
-#define CVMX_NPI_PCI_CFG61 \
-         CVMX_ADD_IO_SEG(0x00011F00000018F4ull)
-#define CVMX_NPI_PCI_CFG62 \
-         CVMX_ADD_IO_SEG(0x00011F00000018F8ull)
-#define CVMX_NPI_PCI_CFG63 \
-         CVMX_ADD_IO_SEG(0x00011F00000018FCull)
-#define CVMX_NPI_PCI_CNT_REG \
-         CVMX_ADD_IO_SEG(0x00011F00000011B8ull)
-#define CVMX_NPI_PCI_CTL_STATUS_2 \
-         CVMX_ADD_IO_SEG(0x00011F000000118Cull)
-#define CVMX_NPI_PCI_INT_ARB_CFG \
-         CVMX_ADD_IO_SEG(0x00011F0000000130ull)
-#define CVMX_NPI_PCI_INT_ENB2 \
-         CVMX_ADD_IO_SEG(0x00011F00000011A0ull)
-#define CVMX_NPI_PCI_INT_SUM2 \
-         CVMX_ADD_IO_SEG(0x00011F0000001198ull)
-#define CVMX_NPI_PCI_READ_CMD \
-         CVMX_ADD_IO_SEG(0x00011F0000000048ull)
-#define CVMX_NPI_PCI_READ_CMD_6 \
-         CVMX_ADD_IO_SEG(0x00011F0000001180ull)
-#define CVMX_NPI_PCI_READ_CMD_C \
-         CVMX_ADD_IO_SEG(0x00011F0000001184ull)
-#define CVMX_NPI_PCI_READ_CMD_E \
-         CVMX_ADD_IO_SEG(0x00011F0000001188ull)
-#define CVMX_NPI_PCI_SCM_REG \
-         CVMX_ADD_IO_SEG(0x00011F00000011A8ull)
-#define CVMX_NPI_PCI_TSR_REG \
-         CVMX_ADD_IO_SEG(0x00011F00000011B0ull)
-#define CVMX_NPI_PORT32_INSTR_HDR \
-         CVMX_ADD_IO_SEG(0x00011F00000001F8ull)
-#define CVMX_NPI_PORT33_INSTR_HDR \
-         CVMX_ADD_IO_SEG(0x00011F0000000200ull)
-#define CVMX_NPI_PORT34_INSTR_HDR \
-         CVMX_ADD_IO_SEG(0x00011F0000000208ull)
-#define CVMX_NPI_PORT35_INSTR_HDR \
-         CVMX_ADD_IO_SEG(0x00011F0000000210ull)
-#define CVMX_NPI_PORT_BP_CONTROL \
-         CVMX_ADD_IO_SEG(0x00011F00000001F0ull)
-#define CVMX_NPI_PX_DBPAIR_ADDR(offset) \
-         CVMX_ADD_IO_SEG(0x00011F0000000180ull + (((offset) & 3) * 8))
-#define CVMX_NPI_PX_INSTR_ADDR(offset) \
-         CVMX_ADD_IO_SEG(0x00011F00000001C0ull + (((offset) & 3) * 8))
-#define CVMX_NPI_PX_INSTR_CNTS(offset) \
-         CVMX_ADD_IO_SEG(0x00011F00000001A0ull + (((offset) & 3) * 8))
-#define CVMX_NPI_PX_PAIR_CNTS(offset) \
-         CVMX_ADD_IO_SEG(0x00011F0000000160ull + (((offset) & 3) * 8))
-#define CVMX_NPI_RSL_INT_BLOCKS \
-         CVMX_ADD_IO_SEG(0x00011F0000000000ull)
-#define CVMX_NPI_SIZE_INPUT0 \
-         CVMX_ADD_IO_SEG(0x00011F0000000078ull)
-#define CVMX_NPI_SIZE_INPUT1 \
-         CVMX_ADD_IO_SEG(0x00011F0000000088ull)
-#define CVMX_NPI_SIZE_INPUT2 \
-         CVMX_ADD_IO_SEG(0x00011F0000000098ull)
-#define CVMX_NPI_SIZE_INPUT3 \
-         CVMX_ADD_IO_SEG(0x00011F00000000A8ull)
-#define CVMX_NPI_SIZE_INPUTX(offset) \
-         CVMX_ADD_IO_SEG(0x00011F0000000078ull + (((offset) & 3) * 16))
-#define CVMX_NPI_WIN_READ_TO \
-         CVMX_ADD_IO_SEG(0x00011F00000001E0ull)
 union cvmx_npi_base_addr_inputx {
        uint64_t u64;

diff --git a/arch/mips/include/asm/octeon/cvmx-npi-defs.h b/arch/mips/include/asm/octeon/cvmx-npi-defs.h index 4e03cd8561e3..f089c780060f 100644 --- a/arch/mips/include/asm/octeon/cvmx-npi-defs.h +++ b/arch/mips/include/asm/octeon/cvmx-npi-defs.h
@@ -4,7 +4,7 @@
4	* Contact: support@caviumnetworks.com	4	* Contact: support@caviumnetworks.com
5	* This file is part of the OCTEON SDK	5	* This file is part of the OCTEON SDK
6	*	6	*
7	* Copyright (c) 2003-2008 Cavium Networks	7	* Copyright (c) 2003-2010 Cavium Networks
8	*	8	*
9	* This file is free software; you can redistribute it and/or modify	9	* This file is free software; you can redistribute it and/or modify
10	* it under the terms of the GNU General Public License, Version 2, as	10	* it under the terms of the GNU General Public License, Version 2, as
@@ -28,246 +28,126 @@
28	#ifndef __CVMX_NPI_DEFS_H__	28	#ifndef __CVMX_NPI_DEFS_H__
29	#define __CVMX_NPI_DEFS_H__	29	#define __CVMX_NPI_DEFS_H__
30		30
31	#define CVMX_NPI_BASE_ADDR_INPUT0 \	31	#define CVMX_NPI_BASE_ADDR_INPUT0 CVMX_NPI_BASE_ADDR_INPUTX(0)
32	CVMX_ADD_IO_SEG(0x00011F0000000070ull)	32	#define CVMX_NPI_BASE_ADDR_INPUT1 CVMX_NPI_BASE_ADDR_INPUTX(1)
33	#define CVMX_NPI_BASE_ADDR_INPUT1 \	33	#define CVMX_NPI_BASE_ADDR_INPUT2 CVMX_NPI_BASE_ADDR_INPUTX(2)
34	CVMX_ADD_IO_SEG(0x00011F0000000080ull)	34	#define CVMX_NPI_BASE_ADDR_INPUT3 CVMX_NPI_BASE_ADDR_INPUTX(3)
35	#define CVMX_NPI_BASE_ADDR_INPUT2 \	35	#define CVMX_NPI_BASE_ADDR_INPUTX(offset) (CVMX_ADD_IO_SEG(0x00011F0000000070ull) + ((offset) & 3) * 16)
36	CVMX_ADD_IO_SEG(0x00011F0000000090ull)	36	#define CVMX_NPI_BASE_ADDR_OUTPUT0 CVMX_NPI_BASE_ADDR_OUTPUTX(0)
37	#define CVMX_NPI_BASE_ADDR_INPUT3 \	37	#define CVMX_NPI_BASE_ADDR_OUTPUT1 CVMX_NPI_BASE_ADDR_OUTPUTX(1)
38	CVMX_ADD_IO_SEG(0x00011F00000000A0ull)	38	#define CVMX_NPI_BASE_ADDR_OUTPUT2 CVMX_NPI_BASE_ADDR_OUTPUTX(2)
39	#define CVMX_NPI_BASE_ADDR_INPUTX(offset) \	39	#define CVMX_NPI_BASE_ADDR_OUTPUT3 CVMX_NPI_BASE_ADDR_OUTPUTX(3)
40	CVMX_ADD_IO_SEG(0x00011F0000000070ull + (((offset) & 3) * 16))	40	#define CVMX_NPI_BASE_ADDR_OUTPUTX(offset) (CVMX_ADD_IO_SEG(0x00011F00000000B8ull) + ((offset) & 3) * 8)
41	#define CVMX_NPI_BASE_ADDR_OUTPUT0 \	41	#define CVMX_NPI_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011F00000003F8ull))
42	CVMX_ADD_IO_SEG(0x00011F00000000B8ull)	42	#define CVMX_NPI_BUFF_SIZE_OUTPUT0 CVMX_NPI_BUFF_SIZE_OUTPUTX(0)
43	#define CVMX_NPI_BASE_ADDR_OUTPUT1 \	43	#define CVMX_NPI_BUFF_SIZE_OUTPUT1 CVMX_NPI_BUFF_SIZE_OUTPUTX(1)
44	CVMX_ADD_IO_SEG(0x00011F00000000C0ull)	44	#define CVMX_NPI_BUFF_SIZE_OUTPUT2 CVMX_NPI_BUFF_SIZE_OUTPUTX(2)
45	#define CVMX_NPI_BASE_ADDR_OUTPUT2 \	45	#define CVMX_NPI_BUFF_SIZE_OUTPUT3 CVMX_NPI_BUFF_SIZE_OUTPUTX(3)
46	CVMX_ADD_IO_SEG(0x00011F00000000C8ull)	46	#define CVMX_NPI_BUFF_SIZE_OUTPUTX(offset) (CVMX_ADD_IO_SEG(0x00011F00000000E0ull) + ((offset) & 3) * 8)
47	#define CVMX_NPI_BASE_ADDR_OUTPUT3 \	47	#define CVMX_NPI_COMP_CTL (CVMX_ADD_IO_SEG(0x00011F0000000218ull))
48	CVMX_ADD_IO_SEG(0x00011F00000000D0ull)	48	#define CVMX_NPI_CTL_STATUS (CVMX_ADD_IO_SEG(0x00011F0000000010ull))
49	#define CVMX_NPI_BASE_ADDR_OUTPUTX(offset) \	49	#define CVMX_NPI_DBG_SELECT (CVMX_ADD_IO_SEG(0x00011F0000000008ull))
50	CVMX_ADD_IO_SEG(0x00011F00000000B8ull + (((offset) & 3) * 8))	50	#define CVMX_NPI_DMA_CONTROL (CVMX_ADD_IO_SEG(0x00011F0000000128ull))
51	#define CVMX_NPI_BIST_STATUS \	51	#define CVMX_NPI_DMA_HIGHP_COUNTS (CVMX_ADD_IO_SEG(0x00011F0000000148ull))
52	CVMX_ADD_IO_SEG(0x00011F00000003F8ull)	52	#define CVMX_NPI_DMA_HIGHP_NADDR (CVMX_ADD_IO_SEG(0x00011F0000000158ull))
53	#define CVMX_NPI_BUFF_SIZE_OUTPUT0 \	53	#define CVMX_NPI_DMA_LOWP_COUNTS (CVMX_ADD_IO_SEG(0x00011F0000000140ull))
54	CVMX_ADD_IO_SEG(0x00011F00000000E0ull)	54	#define CVMX_NPI_DMA_LOWP_NADDR (CVMX_ADD_IO_SEG(0x00011F0000000150ull))
55	#define CVMX_NPI_BUFF_SIZE_OUTPUT1 \	55	#define CVMX_NPI_HIGHP_DBELL (CVMX_ADD_IO_SEG(0x00011F0000000120ull))
56	CVMX_ADD_IO_SEG(0x00011F00000000E8ull)	56	#define CVMX_NPI_HIGHP_IBUFF_SADDR (CVMX_ADD_IO_SEG(0x00011F0000000110ull))
57	#define CVMX_NPI_BUFF_SIZE_OUTPUT2 \	57	#define CVMX_NPI_INPUT_CONTROL (CVMX_ADD_IO_SEG(0x00011F0000000138ull))
58	CVMX_ADD_IO_SEG(0x00011F00000000F0ull)	58	#define CVMX_NPI_INT_ENB (CVMX_ADD_IO_SEG(0x00011F0000000020ull))
59	#define CVMX_NPI_BUFF_SIZE_OUTPUT3 \	59	#define CVMX_NPI_INT_SUM (CVMX_ADD_IO_SEG(0x00011F0000000018ull))
60	CVMX_ADD_IO_SEG(0x00011F00000000F8ull)	60	#define CVMX_NPI_LOWP_DBELL (CVMX_ADD_IO_SEG(0x00011F0000000118ull))
61	#define CVMX_NPI_BUFF_SIZE_OUTPUTX(offset) \	61	#define CVMX_NPI_LOWP_IBUFF_SADDR (CVMX_ADD_IO_SEG(0x00011F0000000108ull))
62	CVMX_ADD_IO_SEG(0x00011F00000000E0ull + (((offset) & 3) * 8))	62	#define CVMX_NPI_MEM_ACCESS_SUBID3 CVMX_NPI_MEM_ACCESS_SUBIDX(3)
63	#define CVMX_NPI_COMP_CTL \	63	#define CVMX_NPI_MEM_ACCESS_SUBID4 CVMX_NPI_MEM_ACCESS_SUBIDX(4)
64	CVMX_ADD_IO_SEG(0x00011F0000000218ull)	64	#define CVMX_NPI_MEM_ACCESS_SUBID5 CVMX_NPI_MEM_ACCESS_SUBIDX(5)
65	#define CVMX_NPI_CTL_STATUS \	65	#define CVMX_NPI_MEM_ACCESS_SUBID6 CVMX_NPI_MEM_ACCESS_SUBIDX(6)
66	CVMX_ADD_IO_SEG(0x00011F0000000010ull)	66	#define CVMX_NPI_MEM_ACCESS_SUBIDX(offset) (CVMX_ADD_IO_SEG(0x00011F0000000028ull) + ((offset) & 7) * 8 - 8*3)
67	#define CVMX_NPI_DBG_SELECT \	67	#define CVMX_NPI_MSI_RCV (0x0000000000000190ull)
68	CVMX_ADD_IO_SEG(0x00011F0000000008ull)	68	#define CVMX_NPI_NPI_MSI_RCV (CVMX_ADD_IO_SEG(0x00011F0000001190ull))
69	#define CVMX_NPI_DMA_CONTROL \	69	#define CVMX_NPI_NUM_DESC_OUTPUT0 CVMX_NPI_NUM_DESC_OUTPUTX(0)
70	CVMX_ADD_IO_SEG(0x00011F0000000128ull)	70	#define CVMX_NPI_NUM_DESC_OUTPUT1 CVMX_NPI_NUM_DESC_OUTPUTX(1)
71	#define CVMX_NPI_DMA_HIGHP_COUNTS \	71	#define CVMX_NPI_NUM_DESC_OUTPUT2 CVMX_NPI_NUM_DESC_OUTPUTX(2)
72	CVMX_ADD_IO_SEG(0x00011F0000000148ull)	72	#define CVMX_NPI_NUM_DESC_OUTPUT3 CVMX_NPI_NUM_DESC_OUTPUTX(3)
73	#define CVMX_NPI_DMA_HIGHP_NADDR \	73	#define CVMX_NPI_NUM_DESC_OUTPUTX(offset) (CVMX_ADD_IO_SEG(0x00011F0000000050ull) + ((offset) & 3) * 8)
74	CVMX_ADD_IO_SEG(0x00011F0000000158ull)	74	#define CVMX_NPI_OUTPUT_CONTROL (CVMX_ADD_IO_SEG(0x00011F0000000100ull))
75	#define CVMX_NPI_DMA_LOWP_COUNTS \	75	#define CVMX_NPI_P0_DBPAIR_ADDR CVMX_NPI_PX_DBPAIR_ADDR(0)
76	CVMX_ADD_IO_SEG(0x00011F0000000140ull)	76	#define CVMX_NPI_P0_INSTR_ADDR CVMX_NPI_PX_INSTR_ADDR(0)
77	#define CVMX_NPI_DMA_LOWP_NADDR \	77	#define CVMX_NPI_P0_INSTR_CNTS CVMX_NPI_PX_INSTR_CNTS(0)
78	CVMX_ADD_IO_SEG(0x00011F0000000150ull)	78	#define CVMX_NPI_P0_PAIR_CNTS CVMX_NPI_PX_PAIR_CNTS(0)
79	#define CVMX_NPI_HIGHP_DBELL \	79	#define CVMX_NPI_P1_DBPAIR_ADDR CVMX_NPI_PX_DBPAIR_ADDR(1)
80	CVMX_ADD_IO_SEG(0x00011F0000000120ull)	80	#define CVMX_NPI_P1_INSTR_ADDR CVMX_NPI_PX_INSTR_ADDR(1)
81	#define CVMX_NPI_HIGHP_IBUFF_SADDR \	81	#define CVMX_NPI_P1_INSTR_CNTS CVMX_NPI_PX_INSTR_CNTS(1)
82	CVMX_ADD_IO_SEG(0x00011F0000000110ull)	82	#define CVMX_NPI_P1_PAIR_CNTS CVMX_NPI_PX_PAIR_CNTS(1)
83	#define CVMX_NPI_INPUT_CONTROL \	83	#define CVMX_NPI_P2_DBPAIR_ADDR CVMX_NPI_PX_DBPAIR_ADDR(2)
84	CVMX_ADD_IO_SEG(0x00011F0000000138ull)	84	#define CVMX_NPI_P2_INSTR_ADDR CVMX_NPI_PX_INSTR_ADDR(2)
85	#define CVMX_NPI_INT_ENB \	85	#define CVMX_NPI_P2_INSTR_CNTS CVMX_NPI_PX_INSTR_CNTS(2)
86	CVMX_ADD_IO_SEG(0x00011F0000000020ull)	86	#define CVMX_NPI_P2_PAIR_CNTS CVMX_NPI_PX_PAIR_CNTS(2)
87	#define CVMX_NPI_INT_SUM \	87	#define CVMX_NPI_P3_DBPAIR_ADDR CVMX_NPI_PX_DBPAIR_ADDR(3)
88	CVMX_ADD_IO_SEG(0x00011F0000000018ull)	88	#define CVMX_NPI_P3_INSTR_ADDR CVMX_NPI_PX_INSTR_ADDR(3)
89	#define CVMX_NPI_LOWP_DBELL \	89	#define CVMX_NPI_P3_INSTR_CNTS CVMX_NPI_PX_INSTR_CNTS(3)
90	CVMX_ADD_IO_SEG(0x00011F0000000118ull)	90	#define CVMX_NPI_P3_PAIR_CNTS CVMX_NPI_PX_PAIR_CNTS(3)
91	#define CVMX_NPI_LOWP_IBUFF_SADDR \	91	#define CVMX_NPI_PCI_BAR1_INDEXX(offset) (CVMX_ADD_IO_SEG(0x00011F0000001100ull) + ((offset) & 31) * 4)
92	CVMX_ADD_IO_SEG(0x00011F0000000108ull)	92	#define CVMX_NPI_PCI_BIST_REG (CVMX_ADD_IO_SEG(0x00011F00000011C0ull))
93	#define CVMX_NPI_MEM_ACCESS_SUBID3 \	93	#define CVMX_NPI_PCI_BURST_SIZE (CVMX_ADD_IO_SEG(0x00011F00000000D8ull))
94	CVMX_ADD_IO_SEG(0x00011F0000000028ull)	94	#define CVMX_NPI_PCI_CFG00 (CVMX_ADD_IO_SEG(0x00011F0000001800ull))
95	#define CVMX_NPI_MEM_ACCESS_SUBID4 \	95	#define CVMX_NPI_PCI_CFG01 (CVMX_ADD_IO_SEG(0x00011F0000001804ull))
96	CVMX_ADD_IO_SEG(0x00011F0000000030ull)	96	#define CVMX_NPI_PCI_CFG02 (CVMX_ADD_IO_SEG(0x00011F0000001808ull))
97	#define CVMX_NPI_MEM_ACCESS_SUBID5 \	97	#define CVMX_NPI_PCI_CFG03 (CVMX_ADD_IO_SEG(0x00011F000000180Cull))
98	CVMX_ADD_IO_SEG(0x00011F0000000038ull)	98	#define CVMX_NPI_PCI_CFG04 (CVMX_ADD_IO_SEG(0x00011F0000001810ull))
99	#define CVMX_NPI_MEM_ACCESS_SUBID6 \	99	#define CVMX_NPI_PCI_CFG05 (CVMX_ADD_IO_SEG(0x00011F0000001814ull))
100	CVMX_ADD_IO_SEG(0x00011F0000000040ull)	100	#define CVMX_NPI_PCI_CFG06 (CVMX_ADD_IO_SEG(0x00011F0000001818ull))
101	#define CVMX_NPI_MEM_ACCESS_SUBIDX(offset) \	101	#define CVMX_NPI_PCI_CFG07 (CVMX_ADD_IO_SEG(0x00011F000000181Cull))
102	CVMX_ADD_IO_SEG(0x00011F0000000028ull + (((offset) & 7) * 8) - 8 * 3)	102	#define CVMX_NPI_PCI_CFG08 (CVMX_ADD_IO_SEG(0x00011F0000001820ull))
103	#define CVMX_NPI_MSI_RCV \	103	#define CVMX_NPI_PCI_CFG09 (CVMX_ADD_IO_SEG(0x00011F0000001824ull))
104	(0x0000000000000190ull)	104	#define CVMX_NPI_PCI_CFG10 (CVMX_ADD_IO_SEG(0x00011F0000001828ull))
105	#define CVMX_NPI_NPI_MSI_RCV \	105	#define CVMX_NPI_PCI_CFG11 (CVMX_ADD_IO_SEG(0x00011F000000182Cull))
106	CVMX_ADD_IO_SEG(0x00011F0000001190ull)	106	#define CVMX_NPI_PCI_CFG12 (CVMX_ADD_IO_SEG(0x00011F0000001830ull))
107	#define CVMX_NPI_NUM_DESC_OUTPUT0 \	107	#define CVMX_NPI_PCI_CFG13 (CVMX_ADD_IO_SEG(0x00011F0000001834ull))
108	CVMX_ADD_IO_SEG(0x00011F0000000050ull)	108	#define CVMX_NPI_PCI_CFG15 (CVMX_ADD_IO_SEG(0x00011F000000183Cull))
109	#define CVMX_NPI_NUM_DESC_OUTPUT1 \	109	#define CVMX_NPI_PCI_CFG16 (CVMX_ADD_IO_SEG(0x00011F0000001840ull))
110	CVMX_ADD_IO_SEG(0x00011F0000000058ull)	110	#define CVMX_NPI_PCI_CFG17 (CVMX_ADD_IO_SEG(0x00011F0000001844ull))
111	#define CVMX_NPI_NUM_DESC_OUTPUT2 \	111	#define CVMX_NPI_PCI_CFG18 (CVMX_ADD_IO_SEG(0x00011F0000001848ull))
112	CVMX_ADD_IO_SEG(0x00011F0000000060ull)	112	#define CVMX_NPI_PCI_CFG19 (CVMX_ADD_IO_SEG(0x00011F000000184Cull))
113	#define CVMX_NPI_NUM_DESC_OUTPUT3 \	113	#define CVMX_NPI_PCI_CFG20 (CVMX_ADD_IO_SEG(0x00011F0000001850ull))
114	CVMX_ADD_IO_SEG(0x00011F0000000068ull)	114	#define CVMX_NPI_PCI_CFG21 (CVMX_ADD_IO_SEG(0x00011F0000001854ull))
115	#define CVMX_NPI_NUM_DESC_OUTPUTX(offset) \	115	#define CVMX_NPI_PCI_CFG22 (CVMX_ADD_IO_SEG(0x00011F0000001858ull))
116	CVMX_ADD_IO_SEG(0x00011F0000000050ull + (((offset) & 3) * 8))	116	#define CVMX_NPI_PCI_CFG56 (CVMX_ADD_IO_SEG(0x00011F00000018E0ull))
117	#define CVMX_NPI_OUTPUT_CONTROL \	117	#define CVMX_NPI_PCI_CFG57 (CVMX_ADD_IO_SEG(0x00011F00000018E4ull))
118	CVMX_ADD_IO_SEG(0x00011F0000000100ull)	118	#define CVMX_NPI_PCI_CFG58 (CVMX_ADD_IO_SEG(0x00011F00000018E8ull))
119	#define CVMX_NPI_P0_DBPAIR_ADDR \	119	#define CVMX_NPI_PCI_CFG59 (CVMX_ADD_IO_SEG(0x00011F00000018ECull))
120	CVMX_ADD_IO_SEG(0x00011F0000000180ull)	120	#define CVMX_NPI_PCI_CFG60 (CVMX_ADD_IO_SEG(0x00011F00000018F0ull))
121	#define CVMX_NPI_P0_INSTR_ADDR \	121	#define CVMX_NPI_PCI_CFG61 (CVMX_ADD_IO_SEG(0x00011F00000018F4ull))
122	CVMX_ADD_IO_SEG(0x00011F00000001C0ull)	122	#define CVMX_NPI_PCI_CFG62 (CVMX_ADD_IO_SEG(0x00011F00000018F8ull))
123	#define CVMX_NPI_P0_INSTR_CNTS \	123	#define CVMX_NPI_PCI_CFG63 (CVMX_ADD_IO_SEG(0x00011F00000018FCull))
124	CVMX_ADD_IO_SEG(0x00011F00000001A0ull)	124	#define CVMX_NPI_PCI_CNT_REG (CVMX_ADD_IO_SEG(0x00011F00000011B8ull))
125	#define CVMX_NPI_P0_PAIR_CNTS \	125	#define CVMX_NPI_PCI_CTL_STATUS_2 (CVMX_ADD_IO_SEG(0x00011F000000118Cull))
126	CVMX_ADD_IO_SEG(0x00011F0000000160ull)	126	#define CVMX_NPI_PCI_INT_ARB_CFG (CVMX_ADD_IO_SEG(0x00011F0000000130ull))
127	#define CVMX_NPI_P1_DBPAIR_ADDR \	127	#define CVMX_NPI_PCI_INT_ENB2 (CVMX_ADD_IO_SEG(0x00011F00000011A0ull))
128	CVMX_ADD_IO_SEG(0x00011F0000000188ull)	128	#define CVMX_NPI_PCI_INT_SUM2 (CVMX_ADD_IO_SEG(0x00011F0000001198ull))
129	#define CVMX_NPI_P1_INSTR_ADDR \	129	#define CVMX_NPI_PCI_READ_CMD (CVMX_ADD_IO_SEG(0x00011F0000000048ull))
130	CVMX_ADD_IO_SEG(0x00011F00000001C8ull)	130	#define CVMX_NPI_PCI_READ_CMD_6 (CVMX_ADD_IO_SEG(0x00011F0000001180ull))
131	#define CVMX_NPI_P1_INSTR_CNTS \	131	#define CVMX_NPI_PCI_READ_CMD_C (CVMX_ADD_IO_SEG(0x00011F0000001184ull))
132	CVMX_ADD_IO_SEG(0x00011F00000001A8ull)	132	#define CVMX_NPI_PCI_READ_CMD_E (CVMX_ADD_IO_SEG(0x00011F0000001188ull))
133	#define CVMX_NPI_P1_PAIR_CNTS \	133	#define CVMX_NPI_PCI_SCM_REG (CVMX_ADD_IO_SEG(0x00011F00000011A8ull))
134	CVMX_ADD_IO_SEG(0x00011F0000000168ull)	134	#define CVMX_NPI_PCI_TSR_REG (CVMX_ADD_IO_SEG(0x00011F00000011B0ull))
135	#define CVMX_NPI_P2_DBPAIR_ADDR \	135	#define CVMX_NPI_PORT32_INSTR_HDR (CVMX_ADD_IO_SEG(0x00011F00000001F8ull))
136	CVMX_ADD_IO_SEG(0x00011F0000000190ull)	136	#define CVMX_NPI_PORT33_INSTR_HDR (CVMX_ADD_IO_SEG(0x00011F0000000200ull))
137	#define CVMX_NPI_P2_INSTR_ADDR \	137	#define CVMX_NPI_PORT34_INSTR_HDR (CVMX_ADD_IO_SEG(0x00011F0000000208ull))
138	CVMX_ADD_IO_SEG(0x00011F00000001D0ull)	138	#define CVMX_NPI_PORT35_INSTR_HDR (CVMX_ADD_IO_SEG(0x00011F0000000210ull))
139	#define CVMX_NPI_P2_INSTR_CNTS \	139	#define CVMX_NPI_PORT_BP_CONTROL (CVMX_ADD_IO_SEG(0x00011F00000001F0ull))
140	CVMX_ADD_IO_SEG(0x00011F00000001B0ull)	140	#define CVMX_NPI_PX_DBPAIR_ADDR(offset) (CVMX_ADD_IO_SEG(0x00011F0000000180ull) + ((offset) & 3) * 8)
141	#define CVMX_NPI_P2_PAIR_CNTS \	141	#define CVMX_NPI_PX_INSTR_ADDR(offset) (CVMX_ADD_IO_SEG(0x00011F00000001C0ull) + ((offset) & 3) * 8)
142	CVMX_ADD_IO_SEG(0x00011F0000000170ull)	142	#define CVMX_NPI_PX_INSTR_CNTS(offset) (CVMX_ADD_IO_SEG(0x00011F00000001A0ull) + ((offset) & 3) * 8)
143	#define CVMX_NPI_P3_DBPAIR_ADDR \	143	#define CVMX_NPI_PX_PAIR_CNTS(offset) (CVMX_ADD_IO_SEG(0x00011F0000000160ull) + ((offset) & 3) * 8)
144	CVMX_ADD_IO_SEG(0x00011F0000000198ull)	144	#define CVMX_NPI_RSL_INT_BLOCKS (CVMX_ADD_IO_SEG(0x00011F0000000000ull))
145	#define CVMX_NPI_P3_INSTR_ADDR \	145	#define CVMX_NPI_SIZE_INPUT0 CVMX_NPI_SIZE_INPUTX(0)
146	CVMX_ADD_IO_SEG(0x00011F00000001D8ull)	146	#define CVMX_NPI_SIZE_INPUT1 CVMX_NPI_SIZE_INPUTX(1)
147	#define CVMX_NPI_P3_INSTR_CNTS \	147	#define CVMX_NPI_SIZE_INPUT2 CVMX_NPI_SIZE_INPUTX(2)
148	CVMX_ADD_IO_SEG(0x00011F00000001B8ull)	148	#define CVMX_NPI_SIZE_INPUT3 CVMX_NPI_SIZE_INPUTX(3)
149	#define CVMX_NPI_P3_PAIR_CNTS \	149	#define CVMX_NPI_SIZE_INPUTX(offset) (CVMX_ADD_IO_SEG(0x00011F0000000078ull) + ((offset) & 3) * 16)
150	CVMX_ADD_IO_SEG(0x00011F0000000178ull)	150	#define CVMX_NPI_WIN_READ_TO (CVMX_ADD_IO_SEG(0x00011F00000001E0ull))
151	#define CVMX_NPI_PCI_BAR1_INDEXX(offset) \
152	CVMX_ADD_IO_SEG(0x00011F0000001100ull + (((offset) & 31) * 4))
153	#define CVMX_NPI_PCI_BIST_REG \
154	CVMX_ADD_IO_SEG(0x00011F00000011C0ull)
155	#define CVMX_NPI_PCI_BURST_SIZE \
156	CVMX_ADD_IO_SEG(0x00011F00000000D8ull)
157	#define CVMX_NPI_PCI_CFG00 \
158	CVMX_ADD_IO_SEG(0x00011F0000001800ull)
159	#define CVMX_NPI_PCI_CFG01 \
160	CVMX_ADD_IO_SEG(0x00011F0000001804ull)
161	#define CVMX_NPI_PCI_CFG02 \
162	CVMX_ADD_IO_SEG(0x00011F0000001808ull)
163	#define CVMX_NPI_PCI_CFG03 \
164	CVMX_ADD_IO_SEG(0x00011F000000180Cull)
165	#define CVMX_NPI_PCI_CFG04 \
166	CVMX_ADD_IO_SEG(0x00011F0000001810ull)
167	#define CVMX_NPI_PCI_CFG05 \
168	CVMX_ADD_IO_SEG(0x00011F0000001814ull)
169	#define CVMX_NPI_PCI_CFG06 \
170	CVMX_ADD_IO_SEG(0x00011F0000001818ull)
171	#define CVMX_NPI_PCI_CFG07 \
172	CVMX_ADD_IO_SEG(0x00011F000000181Cull)
173	#define CVMX_NPI_PCI_CFG08 \
174	CVMX_ADD_IO_SEG(0x00011F0000001820ull)
175	#define CVMX_NPI_PCI_CFG09 \
176	CVMX_ADD_IO_SEG(0x00011F0000001824ull)
177	#define CVMX_NPI_PCI_CFG10 \
178	CVMX_ADD_IO_SEG(0x00011F0000001828ull)
179	#define CVMX_NPI_PCI_CFG11 \
180	CVMX_ADD_IO_SEG(0x00011F000000182Cull)
181	#define CVMX_NPI_PCI_CFG12 \
182	CVMX_ADD_IO_SEG(0x00011F0000001830ull)
183	#define CVMX_NPI_PCI_CFG13 \
184	CVMX_ADD_IO_SEG(0x00011F0000001834ull)
185	#define CVMX_NPI_PCI_CFG15 \
186	CVMX_ADD_IO_SEG(0x00011F000000183Cull)
187	#define CVMX_NPI_PCI_CFG16 \
188	CVMX_ADD_IO_SEG(0x00011F0000001840ull)
189	#define CVMX_NPI_PCI_CFG17 \
190	CVMX_ADD_IO_SEG(0x00011F0000001844ull)
191	#define CVMX_NPI_PCI_CFG18 \
192	CVMX_ADD_IO_SEG(0x00011F0000001848ull)
193	#define CVMX_NPI_PCI_CFG19 \
194	CVMX_ADD_IO_SEG(0x00011F000000184Cull)
195	#define CVMX_NPI_PCI_CFG20 \
196	CVMX_ADD_IO_SEG(0x00011F0000001850ull)
197	#define CVMX_NPI_PCI_CFG21 \
198	CVMX_ADD_IO_SEG(0x00011F0000001854ull)
199	#define CVMX_NPI_PCI_CFG22 \
200	CVMX_ADD_IO_SEG(0x00011F0000001858ull)
201	#define CVMX_NPI_PCI_CFG56 \
202	CVMX_ADD_IO_SEG(0x00011F00000018E0ull)
203	#define CVMX_NPI_PCI_CFG57 \
204	CVMX_ADD_IO_SEG(0x00011F00000018E4ull)
205	#define CVMX_NPI_PCI_CFG58 \
206	CVMX_ADD_IO_SEG(0x00011F00000018E8ull)
207	#define CVMX_NPI_PCI_CFG59 \
208	CVMX_ADD_IO_SEG(0x00011F00000018ECull)
209	#define CVMX_NPI_PCI_CFG60 \
210	CVMX_ADD_IO_SEG(0x00011F00000018F0ull)
211	#define CVMX_NPI_PCI_CFG61 \
212	CVMX_ADD_IO_SEG(0x00011F00000018F4ull)
213	#define CVMX_NPI_PCI_CFG62 \
214	CVMX_ADD_IO_SEG(0x00011F00000018F8ull)
215	#define CVMX_NPI_PCI_CFG63 \
216	CVMX_ADD_IO_SEG(0x00011F00000018FCull)
217	#define CVMX_NPI_PCI_CNT_REG \
218	CVMX_ADD_IO_SEG(0x00011F00000011B8ull)
219	#define CVMX_NPI_PCI_CTL_STATUS_2 \
220	CVMX_ADD_IO_SEG(0x00011F000000118Cull)
221	#define CVMX_NPI_PCI_INT_ARB_CFG \
222	CVMX_ADD_IO_SEG(0x00011F0000000130ull)
223	#define CVMX_NPI_PCI_INT_ENB2 \
224	CVMX_ADD_IO_SEG(0x00011F00000011A0ull)
225	#define CVMX_NPI_PCI_INT_SUM2 \
226	CVMX_ADD_IO_SEG(0x00011F0000001198ull)
227	#define CVMX_NPI_PCI_READ_CMD \
228	CVMX_ADD_IO_SEG(0x00011F0000000048ull)
229	#define CVMX_NPI_PCI_READ_CMD_6 \
230	CVMX_ADD_IO_SEG(0x00011F0000001180ull)
231	#define CVMX_NPI_PCI_READ_CMD_C \
232	CVMX_ADD_IO_SEG(0x00011F0000001184ull)
233	#define CVMX_NPI_PCI_READ_CMD_E \
234	CVMX_ADD_IO_SEG(0x00011F0000001188ull)
235	#define CVMX_NPI_PCI_SCM_REG \
236	CVMX_ADD_IO_SEG(0x00011F00000011A8ull)
237	#define CVMX_NPI_PCI_TSR_REG \
238	CVMX_ADD_IO_SEG(0x00011F00000011B0ull)
239	#define CVMX_NPI_PORT32_INSTR_HDR \
240	CVMX_ADD_IO_SEG(0x00011F00000001F8ull)
241	#define CVMX_NPI_PORT33_INSTR_HDR \
242	CVMX_ADD_IO_SEG(0x00011F0000000200ull)
243	#define CVMX_NPI_PORT34_INSTR_HDR \
244	CVMX_ADD_IO_SEG(0x00011F0000000208ull)
245	#define CVMX_NPI_PORT35_INSTR_HDR \
246	CVMX_ADD_IO_SEG(0x00011F0000000210ull)
247	#define CVMX_NPI_PORT_BP_CONTROL \
248	CVMX_ADD_IO_SEG(0x00011F00000001F0ull)
249	#define CVMX_NPI_PX_DBPAIR_ADDR(offset) \
250	CVMX_ADD_IO_SEG(0x00011F0000000180ull + (((offset) & 3) * 8))
251	#define CVMX_NPI_PX_INSTR_ADDR(offset) \
252	CVMX_ADD_IO_SEG(0x00011F00000001C0ull + (((offset) & 3) * 8))
253	#define CVMX_NPI_PX_INSTR_CNTS(offset) \
254	CVMX_ADD_IO_SEG(0x00011F00000001A0ull + (((offset) & 3) * 8))
255	#define CVMX_NPI_PX_PAIR_CNTS(offset) \
256	CVMX_ADD_IO_SEG(0x00011F0000000160ull + (((offset) & 3) * 8))
257	#define CVMX_NPI_RSL_INT_BLOCKS \
258	CVMX_ADD_IO_SEG(0x00011F0000000000ull)
259	#define CVMX_NPI_SIZE_INPUT0 \
260	CVMX_ADD_IO_SEG(0x00011F0000000078ull)
261	#define CVMX_NPI_SIZE_INPUT1 \
262	CVMX_ADD_IO_SEG(0x00011F0000000088ull)
263	#define CVMX_NPI_SIZE_INPUT2 \
264	CVMX_ADD_IO_SEG(0x00011F0000000098ull)
265	#define CVMX_NPI_SIZE_INPUT3 \
266	CVMX_ADD_IO_SEG(0x00011F00000000A8ull)
267	#define CVMX_NPI_SIZE_INPUTX(offset) \
268	CVMX_ADD_IO_SEG(0x00011F0000000078ull + (((offset) & 3) * 16))
269	#define CVMX_NPI_WIN_READ_TO \
270	CVMX_ADD_IO_SEG(0x00011F00000001E0ull)
271		151
272	union cvmx_npi_base_addr_inputx {	152	union cvmx_npi_base_addr_inputx {
273	uint64_t u64;	153	uint64_t u64;