10 files changed, 222 insertions, 108 deletions

diff --git a/arch/mips/include/asm/netlogic/common.h b/arch/mips/include/asm/netlogic/common.h
index bb68c3398c80..c281f03eb312 100644
--- a/arch/mips/include/asm/netlogic/common.h
+++ b/arch/mips/include/asm/netlogic/common.h
@@ -84,7 +84,6 @@ nlm_set_nmi_handler(void *handler)
  */
 void nlm_init_boot_cpu(void);
 unsigned int nlm_get_cpu_frequency(void);
-void nlm_node_init(int node);
 extern struct plat_smp_ops nlm_smp_ops;
 extern char nlm_reset_entry[], nlm_reset_entry_end[];
 
@@ -94,26 +93,16 @@ extern struct dma_map_ops nlm_swiotlb_dma_ops;
 extern unsigned int nlm_threads_per_core;
 extern cpumask_t nlm_cpumask;
 
-struct nlm_soc_info {
-        unsigned long coremask; /* cores enabled on the soc */
-        unsigned long ebase;
-        uint64_t irqmask;
-        uint64_t sysbase;       /* only for XLP */
-        uint64_t picbase;
-        spinlock_t piclock;
-};
-
-#define nlm_get_node(i)         (&nlm_nodes[i])
-#ifdef CONFIG_CPU_XLR
-#define nlm_current_node()      (&nlm_nodes[0])
-#else
-#define nlm_current_node()      (&nlm_nodes[nlm_nodeid()])
-#endif
-
 struct irq_data;
 uint64_t nlm_pci_irqmask(int node);
+void nlm_setup_pic_irq(int node, int picirq, int irq, int irt);
 void nlm_set_pic_extra_ack(int node, int irq,  void (*xack)(struct irq_data *));
 
+#ifdef CONFIG_PCI_MSI
+void nlm_dispatch_msi(int node, int lirq);
+void nlm_dispatch_msix(int node, int msixirq);
+#endif
+
 /*
  * The NR_IRQs is divided between nodes, each of them has a separate irq space
  */
@@ -122,7 +111,6 @@ static inline int nlm_irq_to_xirq(int node, int irq)
         return node * NR_IRQS / NLM_NR_NODES + irq;
 }
 
-extern struct nlm_soc_info nlm_nodes[NLM_NR_NODES];
 extern int nlm_cpu_ready[];
 #endif
 #endif /* _NETLOGIC_COMMON_H_ */
diff --git a/arch/mips/include/asm/netlogic/mips-extns.h b/arch/mips/include/asm/netlogic/mips-extns.h
index f299d31d7c1a..de9aada6f4c1 100644
--- a/arch/mips/include/asm/netlogic/mips-extns.h
+++ b/arch/mips/include/asm/netlogic/mips-extns.h
@@ -146,7 +146,12 @@ static inline int hard_smp_processor_id(void)
 
 static inline int nlm_nodeid(void)
 {
-        return (__read_32bit_c0_register($15, 1) >> 5) & 0x3;
+        uint32_t prid = read_c0_prid();
+
+        if ((prid & 0xff00) == PRID_IMP_NETLOGIC_XLP9XX)
+                return (__read_32bit_c0_register($15, 1) >> 7) & 0x7;
+        else
+                return (__read_32bit_c0_register($15, 1) >> 5) & 0x3;
 }
 
 static inline unsigned int nlm_core_id(void)
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/bridge.h b/arch/mips/include/asm/netlogic/xlp-hal/bridge.h
index 4e8eacb9588a..3067f983495d 100644
--- a/arch/mips/include/asm/netlogic/xlp-hal/bridge.h
+++ b/arch/mips/include/asm/netlogic/xlp-hal/bridge.h
@@ -69,44 +69,9 @@
 #define BRIDGE_FLASH_LIMIT3             0x13
 
 #define BRIDGE_DRAM_BAR(i)              (0x14 + (i))
-#define BRIDGE_DRAM_BAR0                0x14
-#define BRIDGE_DRAM_BAR1                0x15
-#define BRIDGE_DRAM_BAR2                0x16
-#define BRIDGE_DRAM_BAR3                0x17
-#define BRIDGE_DRAM_BAR4                0x18
-#define BRIDGE_DRAM_BAR5                0x19
-#define BRIDGE_DRAM_BAR6                0x1a
-#define BRIDGE_DRAM_BAR7                0x1b
-
 #define BRIDGE_DRAM_LIMIT(i)            (0x1c + (i))
-#define BRIDGE_DRAM_LIMIT0              0x1c
-#define BRIDGE_DRAM_LIMIT1              0x1d
-#define BRIDGE_DRAM_LIMIT2              0x1e
-#define BRIDGE_DRAM_LIMIT3              0x1f
-#define BRIDGE_DRAM_LIMIT4              0x20
-#define BRIDGE_DRAM_LIMIT5              0x21
-#define BRIDGE_DRAM_LIMIT6              0x22
-#define BRIDGE_DRAM_LIMIT7              0x23
-
 #define BRIDGE_DRAM_NODE_TRANSLN(i)     (0x24 + (i))
-#define BRIDGE_DRAM_NODE_TRANSLN0       0x24
-#define BRIDGE_DRAM_NODE_TRANSLN1       0x25
-#define BRIDGE_DRAM_NODE_TRANSLN2       0x26
-#define BRIDGE_DRAM_NODE_TRANSLN3       0x27
-#define BRIDGE_DRAM_NODE_TRANSLN4       0x28
-#define BRIDGE_DRAM_NODE_TRANSLN5       0x29
-#define BRIDGE_DRAM_NODE_TRANSLN6       0x2a
-#define BRIDGE_DRAM_NODE_TRANSLN7       0x2b
-
 #define BRIDGE_DRAM_CHNL_TRANSLN(i)     (0x2c + (i))
-#define BRIDGE_DRAM_CHNL_TRANSLN0       0x2c
-#define BRIDGE_DRAM_CHNL_TRANSLN1       0x2d
-#define BRIDGE_DRAM_CHNL_TRANSLN2       0x2e
-#define BRIDGE_DRAM_CHNL_TRANSLN3       0x2f
-#define BRIDGE_DRAM_CHNL_TRANSLN4       0x30
-#define BRIDGE_DRAM_CHNL_TRANSLN5       0x31
-#define BRIDGE_DRAM_CHNL_TRANSLN6       0x32
-#define BRIDGE_DRAM_CHNL_TRANSLN7       0x33
 
 #define BRIDGE_PCIEMEM_BASE0            0x34
 #define BRIDGE_PCIEMEM_BASE1            0x35
@@ -178,12 +143,42 @@
 #define BRIDGE_GIO_WEIGHT               0x2cb
 #define BRIDGE_FLASH_WEIGHT             0x2cc
 
+/* FIXME verify */
+#define BRIDGE_9XX_FLASH_BAR(i)         (0x11 + (i))
+#define BRIDGE_9XX_FLASH_BAR_LIMIT(i)   (0x15 + (i))
+
+#define BRIDGE_9XX_DRAM_BAR(i)          (0x19 + (i))
+#define BRIDGE_9XX_DRAM_LIMIT(i)        (0x29 + (i))
+#define BRIDGE_9XX_DRAM_NODE_TRANSLN(i) (0x39 + (i))
+#define BRIDGE_9XX_DRAM_CHNL_TRANSLN(i) (0x49 + (i))
+
+#define BRIDGE_9XX_ADDRESS_ERROR0       0x9d
+#define BRIDGE_9XX_ADDRESS_ERROR1       0x9e
+#define BRIDGE_9XX_ADDRESS_ERROR2       0x9f
+
+#define BRIDGE_9XX_PCIEMEM_BASE0        0x59
+#define BRIDGE_9XX_PCIEMEM_BASE1        0x5a
+#define BRIDGE_9XX_PCIEMEM_BASE2        0x5b
+#define BRIDGE_9XX_PCIEMEM_BASE3        0x5c
+#define BRIDGE_9XX_PCIEMEM_LIMIT0       0x5d
+#define BRIDGE_9XX_PCIEMEM_LIMIT1       0x5e
+#define BRIDGE_9XX_PCIEMEM_LIMIT2       0x5f
+#define BRIDGE_9XX_PCIEMEM_LIMIT3       0x60
+#define BRIDGE_9XX_PCIEIO_BASE0         0x61
+#define BRIDGE_9XX_PCIEIO_BASE1         0x62
+#define BRIDGE_9XX_PCIEIO_BASE2         0x63
+#define BRIDGE_9XX_PCIEIO_BASE3         0x64
+#define BRIDGE_9XX_PCIEIO_LIMIT0        0x65
+#define BRIDGE_9XX_PCIEIO_LIMIT1        0x66
+#define BRIDGE_9XX_PCIEIO_LIMIT2        0x67
+#define BRIDGE_9XX_PCIEIO_LIMIT3        0x68
+
 #ifndef __ASSEMBLY__
 
 #define nlm_read_bridge_reg(b, r)       nlm_read_reg(b, r)
 #define nlm_write_bridge_reg(b, r, v)   nlm_write_reg(b, r, v)
-#define nlm_get_bridge_pcibase(node)    \
-                        nlm_pcicfg_base(XLP_IO_BRIDGE_OFFSET(node))
+#define nlm_get_bridge_pcibase(node)    nlm_pcicfg_base(cpu_is_xlp9xx() ? \
+                XLP9XX_IO_BRIDGE_OFFSET(node) : XLP_IO_BRIDGE_OFFSET(node))
 #define nlm_get_bridge_regbase(node)    \
                         (nlm_get_bridge_pcibase(node) + XLP_IO_PCI_HDRSZ)
 
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/iomap.h b/arch/mips/include/asm/netlogic/xlp-hal/iomap.h
index 55eee77adaca..1f23dfaa7167 100644
--- a/arch/mips/include/asm/netlogic/xlp-hal/iomap.h
+++ b/arch/mips/include/asm/netlogic/xlp-hal/iomap.h
@@ -48,8 +48,10 @@
 #define XLP_IO_SIZE                     (64 << 20)      /* ECFG space size */
 #define XLP_IO_PCI_HDRSZ                0x100
 #define XLP_IO_DEV(node, dev)           ((dev) + (node) * 8)
-#define XLP_HDR_OFFSET(node, bus, dev, fn)      (((bus) << 20) | \
-                                ((XLP_IO_DEV(node, dev)) << 15) | ((fn) << 12))
+#define XLP_IO_PCI_OFFSET(b, d, f)      (((b) << 20) | ((d) << 15) | ((f) << 12))
+
+#define XLP_HDR_OFFSET(node, bus, dev, fn) \
+                XLP_IO_PCI_OFFSET(bus, XLP_IO_DEV(node, dev), fn)
 
 #define XLP_IO_BRIDGE_OFFSET(node)      XLP_HDR_OFFSET(node, 0, 0, 0)
 /* coherent inter chip */
@@ -109,6 +111,36 @@
 #define XLP_IO_MMC_OFFSET(node, slot)   \
                 ((XLP_IO_SD_OFFSET(node))+(slot*0x100)+XLP_IO_PCI_HDRSZ)
 
+/* Things have changed drastically in XLP 9XX */
+#define XLP9XX_HDR_OFFSET(n, d, f)      \
+                        XLP_IO_PCI_OFFSET(xlp9xx_get_socbus(n), d, f)
+
+#define XLP9XX_IO_BRIDGE_OFFSET(node)   XLP_IO_PCI_OFFSET(0, 0, node)
+#define XLP9XX_IO_PIC_OFFSET(node)      XLP9XX_HDR_OFFSET(node, 2, 0)
+#define XLP9XX_IO_UART_OFFSET(node)     XLP9XX_HDR_OFFSET(node, 2, 2)
+#define XLP9XX_IO_SYS_OFFSET(node)      XLP9XX_HDR_OFFSET(node, 6, 0)
+#define XLP9XX_IO_FUSE_OFFSET(node)     XLP9XX_HDR_OFFSET(node, 6, 1)
+#define XLP9XX_IO_JTAG_OFFSET(node)     XLP9XX_HDR_OFFSET(node, 6, 4)
+
+#define XLP9XX_IO_PCIE_OFFSET(node, i)  XLP9XX_HDR_OFFSET(node, 1, i)
+#define XLP9XX_IO_PCIE0_OFFSET(node)    XLP9XX_HDR_OFFSET(node, 1, 0)
+#define XLP9XX_IO_PCIE2_OFFSET(node)    XLP9XX_HDR_OFFSET(node, 1, 2)
+#define XLP9XX_IO_PCIE3_OFFSET(node)    XLP9XX_HDR_OFFSET(node, 1, 3)
+
+/* XLP9xx USB block */
+#define XLP9XX_IO_USB_OFFSET(node, i)           XLP9XX_HDR_OFFSET(node, 4, i)
+#define XLP9XX_IO_USB_XHCI0_OFFSET(node)        XLP9XX_HDR_OFFSET(node, 4, 1)
+#define XLP9XX_IO_USB_XHCI1_OFFSET(node)        XLP9XX_HDR_OFFSET(node, 4, 2)
+
+/* XLP9XX on-chip SATA controller */
+#define XLP9XX_IO_SATA_OFFSET(node)             XLP9XX_HDR_OFFSET(node, 3, 2)
+
+#define XLP9XX_IO_NOR_OFFSET(node)              XLP9XX_HDR_OFFSET(node, 7, 0)
+#define XLP9XX_IO_NAND_OFFSET(node)             XLP9XX_HDR_OFFSET(node, 7, 1)
+#define XLP9XX_IO_SPI_OFFSET(node)              XLP9XX_HDR_OFFSET(node, 7, 2)
+/* SD flash */
+#define XLP9XX_IO_MMCSD_OFFSET(node)            XLP9XX_HDR_OFFSET(node, 7, 3)
+
 /* PCI config header register id's */
 #define XLP_PCI_CFGREG0                 0x00
 #define XLP_PCI_CFGREG1                 0x01
@@ -156,11 +188,23 @@
 #define PCI_DEVICE_ID_NLM_MMC           0x1018
 #define PCI_DEVICE_ID_NLM_XHCI          0x101d
 
+#define PCI_DEVICE_ID_XLP9XX_SATA       0x901A
+#define PCI_DEVICE_ID_XLP9XX_XHCI       0x901D
+
 #ifndef __ASSEMBLY__
 
 #define nlm_read_pci_reg(b, r)          nlm_read_reg(b, r)
 #define nlm_write_pci_reg(b, r, v)      nlm_write_reg(b, r, v)
 
+static inline int xlp9xx_get_socbus(int node)
+{
+        uint64_t socbridge;
+
+        if (node == 0)
+                return 1;
+        socbridge = nlm_pcicfg_base(XLP9XX_IO_BRIDGE_OFFSET(node));
+        return (nlm_read_pci_reg(socbridge, 0x6) >> 8) & 0xff;
+}
 #endif /* !__ASSEMBLY */
 
 #endif /* __NLM_HAL_IOMAP_H__ */
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/pcibus.h b/arch/mips/include/asm/netlogic/xlp-hal/pcibus.h
index b559cb9f56ea..d4deb87ad069 100644
--- a/arch/mips/include/asm/netlogic/xlp-hal/pcibus.h
+++ b/arch/mips/include/asm/netlogic/xlp-hal/pcibus.h
@@ -52,25 +52,48 @@
 #define PCIE_BYTE_SWAP_MEM_LIM          0x248
 #define PCIE_BYTE_SWAP_IO_BASE          0x249
 #define PCIE_BYTE_SWAP_IO_LIM           0x24A
+
+#define PCIE_BRIDGE_MSIX_ADDR_BASE      0x24F
+#define PCIE_BRIDGE_MSIX_ADDR_LIMIT     0x250
 #define PCIE_MSI_STATUS                 0x25A
 #define PCIE_MSI_EN                     0x25B
+#define PCIE_MSIX_STATUS                0x25D
+#define PCIE_INT_STATUS0                0x25F
+#define PCIE_INT_STATUS1                0x260
 #define PCIE_INT_EN0                    0x261
+#define PCIE_INT_EN1                    0x262
 
-/* PCIE_MSI_EN */
-#define PCIE_MSI_VECTOR_INT_EN          0xFFFFFFFF
+/* XLP9XX has basic changes */
+#define PCIE_9XX_BYTE_SWAP_MEM_BASE     0x25c
+#define PCIE_9XX_BYTE_SWAP_MEM_LIM      0x25d
+#define PCIE_9XX_BYTE_SWAP_IO_BASE      0x25e
+#define PCIE_9XX_BYTE_SWAP_IO_LIM       0x25f
 
-/* PCIE_INT_EN0 */
-#define PCIE_MSI_INT_EN                 (1 << 9)
+/* other */
+#define PCIE_NLINKS                     4
 
+/* MSI addresses */
+#define MSI_ADDR_BASE                   0xfffee00000ULL
+#define MSI_ADDR_SZ                     0x10000
+#define MSI_LINK_ADDR(n, l)             (MSI_ADDR_BASE + \
+                                (PCIE_NLINKS * (n) + (l)) * MSI_ADDR_SZ)
+#define MSIX_ADDR_BASE                  0xfffef00000ULL
+#define MSIX_LINK_ADDR(n, l)            (MSIX_ADDR_BASE + \
+                                (PCIE_NLINKS * (n) + (l)) * MSI_ADDR_SZ)
 #ifndef __ASSEMBLY__
 
 #define nlm_read_pcie_reg(b, r)         nlm_read_reg(b, r)
 #define nlm_write_pcie_reg(b, r, v)     nlm_write_reg(b, r, v)
-#define nlm_get_pcie_base(node, inst)   \
-                        nlm_pcicfg_base(XLP_IO_PCIE_OFFSET(node, inst))
-#define nlm_get_pcie_regbase(node, inst)        \
-                        (nlm_get_pcie_base(node, inst) + XLP_IO_PCI_HDRSZ)
+#define nlm_get_pcie_base(node, inst)   nlm_pcicfg_base(cpu_is_xlp9xx() ? \
+        XLP9XX_IO_PCIE_OFFSET(node, inst) : XLP_IO_PCIE_OFFSET(node, inst))
+
+#ifdef CONFIG_PCI_MSI
+void xlp_init_node_msi_irqs(int node, int link);
+#else
+static inline void xlp_init_node_msi_irqs(int node, int link) {}
+#endif
+
+struct pci_dev *xlp_get_pcie_link(const struct pci_dev *dev);
 
-int xlp_pcie_link_irt(int link);
 #endif
 #endif /* __NLM_HAL_PCIBUS_H__ */
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/pic.h b/arch/mips/include/asm/netlogic/xlp-hal/pic.h
index 105389b79f09..f10bf3bba58f 100644
--- a/arch/mips/include/asm/netlogic/xlp-hal/pic.h
+++ b/arch/mips/include/asm/netlogic/xlp-hal/pic.h
@@ -150,12 +150,19 @@
 #define PIC_IRT0                0x74
 #define PIC_IRT(i)              (PIC_IRT0 + ((i) * 2))
 
-#define TIMER_CYCLES_MAXVAL     0xffffffffffffffffULL
+#define PIC_9XX_PENDING_0       0x6
+#define PIC_9XX_PENDING_1       0x8
+#define PIC_9XX_PENDING_2       0xa
+#define PIC_9XX_PENDING_3       0xc
+
+#define PIC_9XX_IRT0            0x1c0
+#define PIC_9XX_IRT(i)          (PIC_9XX_IRT0 + ((i) * 2))
 
 /*
  *    IRT Map
  */
 #define PIC_NUM_IRTS            160
+#define PIC_9XX_NUM_IRTS        256
 
 #define PIC_IRT_WD_0_INDEX      0
 #define PIC_IRT_WD_1_INDEX      1
@@ -193,14 +200,9 @@
 #define PIC_IRT_PCIE_LINK_INDEX(num)    ((num) + PIC_IRT_PCIE_LINK_0_INDEX)
 
 #define PIC_CLOCK_TIMER                 7
-#define PIC_IRQ_BASE                    8
 
 #if !defined(LOCORE) && !defined(__ASSEMBLY__)
 
-#define PIC_IRT_FIRST_IRQ               (PIC_IRQ_BASE)
-#define PIC_IRT_LAST_IRQ                63
-#define PIC_IRQ_IS_IRT(irq)             ((irq) >= PIC_IRT_FIRST_IRQ)
-
 /*
  *   Misc
  */
@@ -210,30 +212,26 @@
 
 #define nlm_read_pic_reg(b, r)  nlm_read_reg64(b, r)
 #define nlm_write_pic_reg(b, r, v) nlm_write_reg64(b, r, v)
-#define nlm_get_pic_pcibase(node) nlm_pcicfg_base(XLP_IO_PIC_OFFSET(node))
+#define nlm_get_pic_pcibase(node)       nlm_pcicfg_base(cpu_is_xlp9xx() ? \
+                XLP9XX_IO_PIC_OFFSET(node) : XLP_IO_PIC_OFFSET(node))
 #define nlm_get_pic_regbase(node) (nlm_get_pic_pcibase(node) + XLP_IO_PCI_HDRSZ)
 
 /* We use PIC on node 0 as a timer */
 #define pic_timer_freq()                nlm_get_pic_frequency(0)
 
 /* IRT and h/w interrupt routines */
-static inline int
-nlm_pic_read_irt(uint64_t base, int irt_index)
-{
-        return nlm_read_pic_reg(base, PIC_IRT(irt_index));
-}
-
 static inline void
-nlm_set_irt_to_cpu(uint64_t base, int irt, int cpu)
+nlm_9xx_pic_write_irt(uint64_t base, int irt_num, int en, int nmi,
+        int sch, int vec, int dt, int db, int cpu)
 {
         uint64_t val;
 
-        val = nlm_read_pic_reg(base, PIC_IRT(irt));
-        /* clear cpuset and mask */
-        val &= ~((0x7ull << 16) | 0xffff);
-        /* set DB, cpuset and cpumask */
-        val |= (1 << 19) | ((cpu >> 4) << 16) | (1 << (cpu & 0xf));
-        nlm_write_pic_reg(base, PIC_IRT(irt), val);
+        val = (((uint64_t)en & 0x1) << 22) | ((nmi & 0x1) << 23) |
+                        ((0 /*mc*/) << 20) | ((vec & 0x3f) << 24) |
+                        ((dt & 0x1) << 21) | (0 /*ptr*/ << 16) |
+                        (cpu & 0x3ff);
+
+        nlm_write_pic_reg(base, PIC_9XX_IRT(irt_num), val);
 }
 
 static inline void
@@ -254,9 +252,13 @@ static inline void
 nlm_pic_write_irt_direct(uint64_t base, int irt_num, int en, int nmi,
         int sch, int vec, int cpu)
 {
-        nlm_pic_write_irt(base, irt_num, en, nmi, sch, vec, 1,
-                (cpu >> 4),             /* thread group */
-                1 << (cpu & 0xf));      /* thread mask */
+        if (cpu_is_xlp9xx())
+                nlm_9xx_pic_write_irt(base, irt_num, en, nmi, sch, vec,
+                                                        1, 0, cpu);
+        else
+                nlm_pic_write_irt(base, irt_num, en, nmi, sch, vec, 1,
+                        (cpu >> 4),             /* thread group */
+                        1 << (cpu & 0xf));      /* thread mask */
 }
 
 static inline uint64_t
@@ -298,8 +300,13 @@ nlm_pic_enable_irt(uint64_t base, int irt)
 {
         uint64_t reg;
 
-        reg = nlm_read_pic_reg(base, PIC_IRT(irt));
-        nlm_write_pic_reg(base, PIC_IRT(irt), reg | (1u << 31));
+        if (cpu_is_xlp9xx()) {
+                reg = nlm_read_pic_reg(base, PIC_9XX_IRT(irt));
+                nlm_write_pic_reg(base, PIC_9XX_IRT(irt), reg | (1 << 22));
+        } else {
+                reg = nlm_read_pic_reg(base, PIC_IRT(irt));
+                nlm_write_pic_reg(base, PIC_IRT(irt), reg | (1u << 31));
+        }
 }
 
 static inline void
@@ -307,8 +314,15 @@ nlm_pic_disable_irt(uint64_t base, int irt)
 {
         uint64_t reg;
 
-        reg = nlm_read_pic_reg(base, PIC_IRT(irt));
-        nlm_write_pic_reg(base, PIC_IRT(irt), reg & ~((uint64_t)1 << 31));
+        if (cpu_is_xlp9xx()) {
+                reg = nlm_read_pic_reg(base, PIC_9XX_IRT(irt));
+                reg &= ~((uint64_t)1 << 22);
+                nlm_write_pic_reg(base, PIC_9XX_IRT(irt), reg);
+        } else {
+                reg = nlm_read_pic_reg(base, PIC_IRT(irt));
+                reg &= ~((uint64_t)1 << 31);
+                nlm_write_pic_reg(base, PIC_IRT(irt), reg);
+        }
 }
 
 static inline void
@@ -316,8 +330,13 @@ nlm_pic_send_ipi(uint64_t base, int hwt, int irq, int nmi)
 {
         uint64_t ipi;
 
-        ipi = ((uint64_t)nmi << 31) | (irq << 20);
-        ipi |= ((hwt >> 4) << 16) | (1 << (hwt & 0xf)); /* cpuset and mask */
+        if (cpu_is_xlp9xx())
+                ipi = (nmi << 23) | (irq << 24) |
+                        (0/*mcm*/ << 20) | (0/*ptr*/ << 16) | hwt;
+        else
+                ipi = ((uint64_t)nmi << 31) | (irq << 20) |
+                        ((hwt >> 4) << 16) | (1 << (hwt & 0xf));
+
         nlm_write_pic_reg(base, PIC_IPI_CTL, ipi);
 }
 
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/sys.h b/arch/mips/include/asm/netlogic/xlp-hal/sys.h
index fcf2833c16ca..d9b107ffca93 100644
--- a/arch/mips/include/asm/netlogic/xlp-hal/sys.h
+++ b/arch/mips/include/asm/netlogic/xlp-hal/sys.h
@@ -147,13 +147,29 @@
 #define SYS_SYS_PLL_MEM_REQ                     0x2a3
 #define SYS_PLL_MEM_STAT                        0x2a4
 
+/* Registers changed on 9XX */
+#define SYS_9XX_POWER_ON_RESET_CFG              0x00
+#define SYS_9XX_CHIP_RESET                      0x01
+#define SYS_9XX_CPU_RESET                       0x02
+#define SYS_9XX_CPU_NONCOHERENT_MODE            0x03
+
+/* XLP 9XX fuse block registers */
+#define FUSE_9XX_DEVCFG6                        0xc6
+
 #ifndef __ASSEMBLY__
 
 #define nlm_read_sys_reg(b, r)          nlm_read_reg(b, r)
 #define nlm_write_sys_reg(b, r, v)      nlm_write_reg(b, r, v)
-#define nlm_get_sys_pcibase(node) nlm_pcicfg_base(XLP_IO_SYS_OFFSET(node))
+#define nlm_get_sys_pcibase(node)       nlm_pcicfg_base(cpu_is_xlp9xx() ? \
+                XLP9XX_IO_SYS_OFFSET(node) : XLP_IO_SYS_OFFSET(node))
 #define nlm_get_sys_regbase(node) (nlm_get_sys_pcibase(node) + XLP_IO_PCI_HDRSZ)
 
+/* XLP9XX fuse block */
+#define nlm_get_fuse_pcibase(node)      \
+                        nlm_pcicfg_base(XLP9XX_IO_FUSE_OFFSET(node))
+#define nlm_get_fuse_regbase(node)      \
+                        (nlm_get_fuse_pcibase(node) + XLP_IO_PCI_HDRSZ)
+
 unsigned int nlm_get_pic_frequency(int node);
 #endif
 #endif
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/uart.h b/arch/mips/include/asm/netlogic/xlp-hal/uart.h
index 86d16e1e6072..a6c54424dd95 100644
--- a/arch/mips/include/asm/netlogic/xlp-hal/uart.h
+++ b/arch/mips/include/asm/netlogic/xlp-hal/uart.h
@@ -94,7 +94,8 @@
 #define nlm_read_uart_reg(b, r)         nlm_read_reg(b, r)
 #define nlm_write_uart_reg(b, r, v)     nlm_write_reg(b, r, v)
 #define nlm_get_uart_pcibase(node, inst)        \
-                nlm_pcicfg_base(XLP_IO_UART_OFFSET(node, inst))
+        nlm_pcicfg_base(cpu_is_xlp9xx() ?  XLP9XX_IO_UART_OFFSET(node) : \
+                                                XLP_IO_UART_OFFSET(node, inst))
 #define nlm_get_uart_regbase(node, inst)        \
                         (nlm_get_uart_pcibase(node, inst) + XLP_IO_PCI_HDRSZ)
 
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/xlp.h b/arch/mips/include/asm/netlogic/xlp-hal/xlp.h
index 470f2095b346..2b0c9599ebe5 100644
--- a/arch/mips/include/asm/netlogic/xlp-hal/xlp.h
+++ b/arch/mips/include/asm/netlogic/xlp-hal/xlp.h
@@ -37,10 +37,9 @@
 
 #define PIC_UART_0_IRQ                  17
 #define PIC_UART_1_IRQ                  18
-#define PIC_PCIE_LINK_0_IRQ             19
-#define PIC_PCIE_LINK_1_IRQ             20
-#define PIC_PCIE_LINK_2_IRQ             21
-#define PIC_PCIE_LINK_3_IRQ             22
+
+#define PIC_PCIE_LINK_LEGACY_IRQ_BASE   19
+#define PIC_PCIE_LINK_LEGACY_IRQ(i)     (19 + (i))
 
 #define PIC_EHCI_0_IRQ                  23
 #define PIC_EHCI_1_IRQ                  24
@@ -51,6 +50,8 @@
 #define PIC_2XX_XHCI_0_IRQ              23
 #define PIC_2XX_XHCI_1_IRQ              24
 #define PIC_2XX_XHCI_2_IRQ              25
+#define PIC_9XX_XHCI_0_IRQ              23
+#define PIC_9XX_XHCI_1_IRQ              24
 
 #define PIC_MMC_IRQ                     29
 #define PIC_I2C_0_IRQ                   30
@@ -58,6 +59,23 @@
 #define PIC_I2C_2_IRQ                   32
 #define PIC_I2C_3_IRQ                   33
 
+#define PIC_PCIE_LINK_MSI_IRQ_BASE      44      /* 44 - 47 MSI IRQ */
+#define PIC_PCIE_LINK_MSI_IRQ(i)        (44 + (i))
+
+/* MSI-X with second link-level dispatch */
+#define PIC_PCIE_MSIX_IRQ_BASE          48      /* 48 - 51 MSI-X IRQ */
+#define PIC_PCIE_MSIX_IRQ(i)            (48 + (i))
+
+#define NLM_MSIX_VEC_BASE               96      /* 96 - 127 - MSIX mapped */
+#define NLM_MSI_VEC_BASE                128     /* 128 -255 - MSI mapped */
+
+#define NLM_PIC_INDIRECT_VEC_BASE       512
+#define NLM_GPIO_VEC_BASE               768
+
+#define PIC_IRQ_BASE                    8
+#define PIC_IRT_FIRST_IRQ               PIC_IRQ_BASE
+#define PIC_IRT_LAST_IRQ                63
+
 #ifndef __ASSEMBLY__
 
 /* SMP support functions */
@@ -68,6 +86,9 @@ void xlp_mmu_init(void);
 void nlm_hal_init(void);
 int xlp_get_dram_map(int n, uint64_t *dram_map);
 
+struct pci_dev;
+int xlp_socdev_to_node(const struct pci_dev *dev);
+
 /* Device tree related */
 void xlp_early_init_devtree(void);
 void *xlp_dt_init(void *fdtp);
@@ -76,8 +97,15 @@ static inline int cpu_is_xlpii(void)
 {
         int chip = read_c0_prid() & 0xff00;
 
-        return chip == PRID_IMP_NETLOGIC_XLP2XX;
+        return chip == PRID_IMP_NETLOGIC_XLP2XX ||
+                chip == PRID_IMP_NETLOGIC_XLP9XX;
 }
 
+static inline int cpu_is_xlp9xx(void)
+{
+        int chip = read_c0_prid() & 0xff00;
+
+        return chip == PRID_IMP_NETLOGIC_XLP9XX;
+}
 #endif /* !__ASSEMBLY__ */
 #endif /* _ASM_NLM_XLP_H */
diff --git a/arch/mips/include/asm/netlogic/xlr/xlr.h b/arch/mips/include/asm/netlogic/xlr/xlr.h
index c1667e0c272a..ceb991ca8436 100644
--- a/arch/mips/include/asm/netlogic/xlr/xlr.h
+++ b/arch/mips/include/asm/netlogic/xlr/xlr.h
@@ -35,11 +35,6 @@
 #ifndef _ASM_NLM_XLR_H
 #define _ASM_NLM_XLR_H
 
-/* Platform UART functions */
-struct uart_port;
-unsigned int nlm_xlr_uart_in(struct uart_port *, int);
-void nlm_xlr_uart_out(struct uart_port *, int, int);
-
 /* SMP helpers */
 void xlr_wakeup_secondary_cpus(void);