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-rw-r--r--arch/mips/include/asm/mipsregs.h735
1 files changed, 339 insertions, 396 deletions
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 7e4e6f8fab37..12b70c25906a 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -123,16 +123,16 @@
123 * Status Register Values 123 * Status Register Values
124 */ 124 */
125 125
126#define FPU_CSR_FLUSH 0x01000000 /* flush denormalised results to 0 */ 126#define FPU_CSR_FLUSH 0x01000000 /* flush denormalised results to 0 */
127#define FPU_CSR_COND 0x00800000 /* $fcc0 */ 127#define FPU_CSR_COND 0x00800000 /* $fcc0 */
128#define FPU_CSR_COND0 0x00800000 /* $fcc0 */ 128#define FPU_CSR_COND0 0x00800000 /* $fcc0 */
129#define FPU_CSR_COND1 0x02000000 /* $fcc1 */ 129#define FPU_CSR_COND1 0x02000000 /* $fcc1 */
130#define FPU_CSR_COND2 0x04000000 /* $fcc2 */ 130#define FPU_CSR_COND2 0x04000000 /* $fcc2 */
131#define FPU_CSR_COND3 0x08000000 /* $fcc3 */ 131#define FPU_CSR_COND3 0x08000000 /* $fcc3 */
132#define FPU_CSR_COND4 0x10000000 /* $fcc4 */ 132#define FPU_CSR_COND4 0x10000000 /* $fcc4 */
133#define FPU_CSR_COND5 0x20000000 /* $fcc5 */ 133#define FPU_CSR_COND5 0x20000000 /* $fcc5 */
134#define FPU_CSR_COND6 0x40000000 /* $fcc6 */ 134#define FPU_CSR_COND6 0x40000000 /* $fcc6 */
135#define FPU_CSR_COND7 0x80000000 /* $fcc7 */ 135#define FPU_CSR_COND7 0x80000000 /* $fcc7 */
136 136
137/* 137/*
138 * Bits 18 - 20 of the FPU Status Register will be read as 0, 138 * Bits 18 - 20 of the FPU Status Register will be read as 0,
@@ -145,34 +145,34 @@
145 * E the exception enable 145 * E the exception enable
146 * S the sticky/flag bit 146 * S the sticky/flag bit
147*/ 147*/
148#define FPU_CSR_ALL_X 0x0003f000 148#define FPU_CSR_ALL_X 0x0003f000
149#define FPU_CSR_UNI_X 0x00020000 149#define FPU_CSR_UNI_X 0x00020000
150#define FPU_CSR_INV_X 0x00010000 150#define FPU_CSR_INV_X 0x00010000
151#define FPU_CSR_DIV_X 0x00008000 151#define FPU_CSR_DIV_X 0x00008000
152#define FPU_CSR_OVF_X 0x00004000 152#define FPU_CSR_OVF_X 0x00004000
153#define FPU_CSR_UDF_X 0x00002000 153#define FPU_CSR_UDF_X 0x00002000
154#define FPU_CSR_INE_X 0x00001000 154#define FPU_CSR_INE_X 0x00001000
155 155
156#define FPU_CSR_ALL_E 0x00000f80 156#define FPU_CSR_ALL_E 0x00000f80
157#define FPU_CSR_INV_E 0x00000800 157#define FPU_CSR_INV_E 0x00000800
158#define FPU_CSR_DIV_E 0x00000400 158#define FPU_CSR_DIV_E 0x00000400
159#define FPU_CSR_OVF_E 0x00000200 159#define FPU_CSR_OVF_E 0x00000200
160#define FPU_CSR_UDF_E 0x00000100 160#define FPU_CSR_UDF_E 0x00000100
161#define FPU_CSR_INE_E 0x00000080 161#define FPU_CSR_INE_E 0x00000080
162 162
163#define FPU_CSR_ALL_S 0x0000007c 163#define FPU_CSR_ALL_S 0x0000007c
164#define FPU_CSR_INV_S 0x00000040 164#define FPU_CSR_INV_S 0x00000040
165#define FPU_CSR_DIV_S 0x00000020 165#define FPU_CSR_DIV_S 0x00000020
166#define FPU_CSR_OVF_S 0x00000010 166#define FPU_CSR_OVF_S 0x00000010
167#define FPU_CSR_UDF_S 0x00000008 167#define FPU_CSR_UDF_S 0x00000008
168#define FPU_CSR_INE_S 0x00000004 168#define FPU_CSR_INE_S 0x00000004
169 169
170/* Bits 0 and 1 of FPU Status Register specify the rounding mode */ 170/* Bits 0 and 1 of FPU Status Register specify the rounding mode */
171#define FPU_CSR_RM 0x00000003 171#define FPU_CSR_RM 0x00000003
172#define FPU_CSR_RN 0x0 /* nearest */ 172#define FPU_CSR_RN 0x0 /* nearest */
173#define FPU_CSR_RZ 0x1 /* towards zero */ 173#define FPU_CSR_RZ 0x1 /* towards zero */
174#define FPU_CSR_RU 0x2 /* towards +Infinity */ 174#define FPU_CSR_RU 0x2 /* towards +Infinity */
175#define FPU_CSR_RD 0x3 /* towards -Infinity */ 175#define FPU_CSR_RD 0x3 /* towards -Infinity */
176 176
177 177
178/* 178/*
@@ -214,15 +214,15 @@
214 * Default page size for a given kernel configuration 214 * Default page size for a given kernel configuration
215 */ 215 */
216#ifdef CONFIG_PAGE_SIZE_4KB 216#ifdef CONFIG_PAGE_SIZE_4KB
217#define PM_DEFAULT_MASK PM_4K 217#define PM_DEFAULT_MASK PM_4K
218#elif defined(CONFIG_PAGE_SIZE_8KB) 218#elif defined(CONFIG_PAGE_SIZE_8KB)
219#define PM_DEFAULT_MASK PM_8K 219#define PM_DEFAULT_MASK PM_8K
220#elif defined(CONFIG_PAGE_SIZE_16KB) 220#elif defined(CONFIG_PAGE_SIZE_16KB)
221#define PM_DEFAULT_MASK PM_16K 221#define PM_DEFAULT_MASK PM_16K
222#elif defined(CONFIG_PAGE_SIZE_32KB) 222#elif defined(CONFIG_PAGE_SIZE_32KB)
223#define PM_DEFAULT_MASK PM_32K 223#define PM_DEFAULT_MASK PM_32K
224#elif defined(CONFIG_PAGE_SIZE_64KB) 224#elif defined(CONFIG_PAGE_SIZE_64KB)
225#define PM_DEFAULT_MASK PM_64K 225#define PM_DEFAULT_MASK PM_64K
226#else 226#else
227#error Bad page size configuration! 227#error Bad page size configuration!
228#endif 228#endif
@@ -260,34 +260,34 @@
260/* 260/*
261 * PageGrain bits 261 * PageGrain bits
262 */ 262 */
263#define PG_RIE (_ULCAST_(1) << 31) 263#define PG_RIE (_ULCAST_(1) << 31)
264#define PG_XIE (_ULCAST_(1) << 30) 264#define PG_XIE (_ULCAST_(1) << 30)
265#define PG_ELPA (_ULCAST_(1) << 29) 265#define PG_ELPA (_ULCAST_(1) << 29)
266#define PG_ESP (_ULCAST_(1) << 28) 266#define PG_ESP (_ULCAST_(1) << 28)
267 267
268/* 268/*
269 * R4x00 interrupt enable / cause bits 269 * R4x00 interrupt enable / cause bits
270 */ 270 */
271#define IE_SW0 (_ULCAST_(1) << 8) 271#define IE_SW0 (_ULCAST_(1) << 8)
272#define IE_SW1 (_ULCAST_(1) << 9) 272#define IE_SW1 (_ULCAST_(1) << 9)
273#define IE_IRQ0 (_ULCAST_(1) << 10) 273#define IE_IRQ0 (_ULCAST_(1) << 10)
274#define IE_IRQ1 (_ULCAST_(1) << 11) 274#define IE_IRQ1 (_ULCAST_(1) << 11)
275#define IE_IRQ2 (_ULCAST_(1) << 12) 275#define IE_IRQ2 (_ULCAST_(1) << 12)
276#define IE_IRQ3 (_ULCAST_(1) << 13) 276#define IE_IRQ3 (_ULCAST_(1) << 13)
277#define IE_IRQ4 (_ULCAST_(1) << 14) 277#define IE_IRQ4 (_ULCAST_(1) << 14)
278#define IE_IRQ5 (_ULCAST_(1) << 15) 278#define IE_IRQ5 (_ULCAST_(1) << 15)
279 279
280/* 280/*
281 * R4x00 interrupt cause bits 281 * R4x00 interrupt cause bits
282 */ 282 */
283#define C_SW0 (_ULCAST_(1) << 8) 283#define C_SW0 (_ULCAST_(1) << 8)
284#define C_SW1 (_ULCAST_(1) << 9) 284#define C_SW1 (_ULCAST_(1) << 9)
285#define C_IRQ0 (_ULCAST_(1) << 10) 285#define C_IRQ0 (_ULCAST_(1) << 10)
286#define C_IRQ1 (_ULCAST_(1) << 11) 286#define C_IRQ1 (_ULCAST_(1) << 11)
287#define C_IRQ2 (_ULCAST_(1) << 12) 287#define C_IRQ2 (_ULCAST_(1) << 12)
288#define C_IRQ3 (_ULCAST_(1) << 13) 288#define C_IRQ3 (_ULCAST_(1) << 13)
289#define C_IRQ4 (_ULCAST_(1) << 14) 289#define C_IRQ4 (_ULCAST_(1) << 14)
290#define C_IRQ5 (_ULCAST_(1) << 15) 290#define C_IRQ5 (_ULCAST_(1) << 15)
291 291
292/* 292/*
293 * Bitfields in the R4xx0 cp0 status register 293 * Bitfields in the R4xx0 cp0 status register
@@ -301,7 +301,7 @@
301# define KSU_KERNEL 0x00000000 301# define KSU_KERNEL 0x00000000
302#define ST0_UX 0x00000020 302#define ST0_UX 0x00000020
303#define ST0_SX 0x00000040 303#define ST0_SX 0x00000040
304#define ST0_KX 0x00000080 304#define ST0_KX 0x00000080
305#define ST0_DE 0x00010000 305#define ST0_DE 0x00010000
306#define ST0_CE 0x00020000 306#define ST0_CE 0x00020000
307 307
@@ -315,7 +315,7 @@
315/* 315/*
316 * Bitfields in the R[23]000 cp0 status register. 316 * Bitfields in the R[23]000 cp0 status register.
317 */ 317 */
318#define ST0_IEC 0x00000001 318#define ST0_IEC 0x00000001
319#define ST0_KUC 0x00000002 319#define ST0_KUC 0x00000002
320#define ST0_IEP 0x00000004 320#define ST0_IEP 0x00000004
321#define ST0_KUP 0x00000008 321#define ST0_KUP 0x00000008
@@ -329,7 +329,7 @@
329/* 329/*
330 * Bits specific to the R4640/R4650 330 * Bits specific to the R4640/R4650
331 */ 331 */
332#define ST0_UM (_ULCAST_(1) << 4) 332#define ST0_UM (_ULCAST_(1) << 4)
333#define ST0_IL (_ULCAST_(1) << 23) 333#define ST0_IL (_ULCAST_(1) << 23)
334#define ST0_DL (_ULCAST_(1) << 24) 334#define ST0_DL (_ULCAST_(1) << 24)
335 335
@@ -343,22 +343,22 @@
343 */ 343 */
344#define TX39_CONF_ICS_SHIFT 19 344#define TX39_CONF_ICS_SHIFT 19
345#define TX39_CONF_ICS_MASK 0x00380000 345#define TX39_CONF_ICS_MASK 0x00380000
346#define TX39_CONF_ICS_1KB 0x00000000 346#define TX39_CONF_ICS_1KB 0x00000000
347#define TX39_CONF_ICS_2KB 0x00080000 347#define TX39_CONF_ICS_2KB 0x00080000
348#define TX39_CONF_ICS_4KB 0x00100000 348#define TX39_CONF_ICS_4KB 0x00100000
349#define TX39_CONF_ICS_8KB 0x00180000 349#define TX39_CONF_ICS_8KB 0x00180000
350#define TX39_CONF_ICS_16KB 0x00200000 350#define TX39_CONF_ICS_16KB 0x00200000
351 351
352#define TX39_CONF_DCS_SHIFT 16 352#define TX39_CONF_DCS_SHIFT 16
353#define TX39_CONF_DCS_MASK 0x00070000 353#define TX39_CONF_DCS_MASK 0x00070000
354#define TX39_CONF_DCS_1KB 0x00000000 354#define TX39_CONF_DCS_1KB 0x00000000
355#define TX39_CONF_DCS_2KB 0x00010000 355#define TX39_CONF_DCS_2KB 0x00010000
356#define TX39_CONF_DCS_4KB 0x00020000 356#define TX39_CONF_DCS_4KB 0x00020000
357#define TX39_CONF_DCS_8KB 0x00030000 357#define TX39_CONF_DCS_8KB 0x00030000
358#define TX39_CONF_DCS_16KB 0x00040000 358#define TX39_CONF_DCS_16KB 0x00040000
359 359
360#define TX39_CONF_CWFON 0x00004000 360#define TX39_CONF_CWFON 0x00004000
361#define TX39_CONF_WBON 0x00002000 361#define TX39_CONF_WBON 0x00002000
362#define TX39_CONF_RF_SHIFT 10 362#define TX39_CONF_RF_SHIFT 10
363#define TX39_CONF_RF_MASK 0x00000c00 363#define TX39_CONF_RF_MASK 0x00000c00
364#define TX39_CONF_DOZE 0x00000200 364#define TX39_CONF_DOZE 0x00000200
@@ -375,38 +375,38 @@
375 * Status register bits available in all MIPS CPUs. 375 * Status register bits available in all MIPS CPUs.
376 */ 376 */
377#define ST0_IM 0x0000ff00 377#define ST0_IM 0x0000ff00
378#define STATUSB_IP0 8 378#define STATUSB_IP0 8
379#define STATUSF_IP0 (_ULCAST_(1) << 8) 379#define STATUSF_IP0 (_ULCAST_(1) << 8)
380#define STATUSB_IP1 9 380#define STATUSB_IP1 9
381#define STATUSF_IP1 (_ULCAST_(1) << 9) 381#define STATUSF_IP1 (_ULCAST_(1) << 9)
382#define STATUSB_IP2 10 382#define STATUSB_IP2 10
383#define STATUSF_IP2 (_ULCAST_(1) << 10) 383#define STATUSF_IP2 (_ULCAST_(1) << 10)
384#define STATUSB_IP3 11 384#define STATUSB_IP3 11
385#define STATUSF_IP3 (_ULCAST_(1) << 11) 385#define STATUSF_IP3 (_ULCAST_(1) << 11)
386#define STATUSB_IP4 12 386#define STATUSB_IP4 12
387#define STATUSF_IP4 (_ULCAST_(1) << 12) 387#define STATUSF_IP4 (_ULCAST_(1) << 12)
388#define STATUSB_IP5 13 388#define STATUSB_IP5 13
389#define STATUSF_IP5 (_ULCAST_(1) << 13) 389#define STATUSF_IP5 (_ULCAST_(1) << 13)
390#define STATUSB_IP6 14 390#define STATUSB_IP6 14
391#define STATUSF_IP6 (_ULCAST_(1) << 14) 391#define STATUSF_IP6 (_ULCAST_(1) << 14)
392#define STATUSB_IP7 15 392#define STATUSB_IP7 15
393#define STATUSF_IP7 (_ULCAST_(1) << 15) 393#define STATUSF_IP7 (_ULCAST_(1) << 15)
394#define STATUSB_IP8 0 394#define STATUSB_IP8 0
395#define STATUSF_IP8 (_ULCAST_(1) << 0) 395#define STATUSF_IP8 (_ULCAST_(1) << 0)
396#define STATUSB_IP9 1 396#define STATUSB_IP9 1
397#define STATUSF_IP9 (_ULCAST_(1) << 1) 397#define STATUSF_IP9 (_ULCAST_(1) << 1)
398#define STATUSB_IP10 2 398#define STATUSB_IP10 2
399#define STATUSF_IP10 (_ULCAST_(1) << 2) 399#define STATUSF_IP10 (_ULCAST_(1) << 2)
400#define STATUSB_IP11 3 400#define STATUSB_IP11 3
401#define STATUSF_IP11 (_ULCAST_(1) << 3) 401#define STATUSF_IP11 (_ULCAST_(1) << 3)
402#define STATUSB_IP12 4 402#define STATUSB_IP12 4
403#define STATUSF_IP12 (_ULCAST_(1) << 4) 403#define STATUSF_IP12 (_ULCAST_(1) << 4)
404#define STATUSB_IP13 5 404#define STATUSB_IP13 5
405#define STATUSF_IP13 (_ULCAST_(1) << 5) 405#define STATUSF_IP13 (_ULCAST_(1) << 5)
406#define STATUSB_IP14 6 406#define STATUSB_IP14 6
407#define STATUSF_IP14 (_ULCAST_(1) << 6) 407#define STATUSF_IP14 (_ULCAST_(1) << 6)
408#define STATUSB_IP15 7 408#define STATUSB_IP15 7
409#define STATUSF_IP15 (_ULCAST_(1) << 7) 409#define STATUSF_IP15 (_ULCAST_(1) << 7)
410#define ST0_CH 0x00040000 410#define ST0_CH 0x00040000
411#define ST0_NMI 0x00080000 411#define ST0_NMI 0x00080000
412#define ST0_SR 0x00100000 412#define ST0_SR 0x00100000
@@ -436,36 +436,36 @@
436 * 436 *
437 * Refer to your MIPS R4xx0 manual, chapter 5 for explanation. 437 * Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
438 */ 438 */
439#define CAUSEB_EXCCODE 2 439#define CAUSEB_EXCCODE 2
440#define CAUSEF_EXCCODE (_ULCAST_(31) << 2) 440#define CAUSEF_EXCCODE (_ULCAST_(31) << 2)
441#define CAUSEB_IP 8 441#define CAUSEB_IP 8
442#define CAUSEF_IP (_ULCAST_(255) << 8) 442#define CAUSEF_IP (_ULCAST_(255) << 8)
443#define CAUSEB_IP0 8 443#define CAUSEB_IP0 8
444#define CAUSEF_IP0 (_ULCAST_(1) << 8) 444#define CAUSEF_IP0 (_ULCAST_(1) << 8)
445#define CAUSEB_IP1 9 445#define CAUSEB_IP1 9
446#define CAUSEF_IP1 (_ULCAST_(1) << 9) 446#define CAUSEF_IP1 (_ULCAST_(1) << 9)
447#define CAUSEB_IP2 10 447#define CAUSEB_IP2 10
448#define CAUSEF_IP2 (_ULCAST_(1) << 10) 448#define CAUSEF_IP2 (_ULCAST_(1) << 10)
449#define CAUSEB_IP3 11 449#define CAUSEB_IP3 11
450#define CAUSEF_IP3 (_ULCAST_(1) << 11) 450#define CAUSEF_IP3 (_ULCAST_(1) << 11)
451#define CAUSEB_IP4 12 451#define CAUSEB_IP4 12
452#define CAUSEF_IP4 (_ULCAST_(1) << 12) 452#define CAUSEF_IP4 (_ULCAST_(1) << 12)
453#define CAUSEB_IP5 13 453#define CAUSEB_IP5 13
454#define CAUSEF_IP5 (_ULCAST_(1) << 13) 454#define CAUSEF_IP5 (_ULCAST_(1) << 13)
455#define CAUSEB_IP6 14 455#define CAUSEB_IP6 14
456#define CAUSEF_IP6 (_ULCAST_(1) << 14) 456#define CAUSEF_IP6 (_ULCAST_(1) << 14)
457#define CAUSEB_IP7 15 457#define CAUSEB_IP7 15
458#define CAUSEF_IP7 (_ULCAST_(1) << 15) 458#define CAUSEF_IP7 (_ULCAST_(1) << 15)
459#define CAUSEB_IV 23 459#define CAUSEB_IV 23
460#define CAUSEF_IV (_ULCAST_(1) << 23) 460#define CAUSEF_IV (_ULCAST_(1) << 23)
461#define CAUSEB_PCI 26 461#define CAUSEB_PCI 26
462#define CAUSEF_PCI (_ULCAST_(1) << 26) 462#define CAUSEF_PCI (_ULCAST_(1) << 26)
463#define CAUSEB_CE 28 463#define CAUSEB_CE 28
464#define CAUSEF_CE (_ULCAST_(3) << 28) 464#define CAUSEF_CE (_ULCAST_(3) << 28)
465#define CAUSEB_TI 30 465#define CAUSEB_TI 30
466#define CAUSEF_TI (_ULCAST_(1) << 30) 466#define CAUSEF_TI (_ULCAST_(1) << 30)
467#define CAUSEB_BD 31 467#define CAUSEB_BD 31
468#define CAUSEF_BD (_ULCAST_(1) << 31) 468#define CAUSEF_BD (_ULCAST_(1) << 31)
469 469
470/* 470/*
471 * Bits in the coprocessor 0 config register. 471 * Bits in the coprocessor 0 config register.
@@ -483,11 +483,11 @@
483#define CONF_BE (_ULCAST_(1) << 15) 483#define CONF_BE (_ULCAST_(1) << 15)
484 484
485/* Bits common to various processors. */ 485/* Bits common to various processors. */
486#define CONF_CU (_ULCAST_(1) << 3) 486#define CONF_CU (_ULCAST_(1) << 3)
487#define CONF_DB (_ULCAST_(1) << 4) 487#define CONF_DB (_ULCAST_(1) << 4)
488#define CONF_IB (_ULCAST_(1) << 5) 488#define CONF_IB (_ULCAST_(1) << 5)
489#define CONF_DC (_ULCAST_(7) << 6) 489#define CONF_DC (_ULCAST_(7) << 6)
490#define CONF_IC (_ULCAST_(7) << 9) 490#define CONF_IC (_ULCAST_(7) << 9)
491#define CONF_EB (_ULCAST_(1) << 13) 491#define CONF_EB (_ULCAST_(1) << 13)
492#define CONF_EM (_ULCAST_(1) << 14) 492#define CONF_EM (_ULCAST_(1) << 14)
493#define CONF_SM (_ULCAST_(1) << 16) 493#define CONF_SM (_ULCAST_(1) << 16)
@@ -497,29 +497,29 @@
497#define CONF_EC (_ULCAST_(7) << 28) 497#define CONF_EC (_ULCAST_(7) << 28)
498#define CONF_CM (_ULCAST_(1) << 31) 498#define CONF_CM (_ULCAST_(1) << 31)
499 499
500/* Bits specific to the R4xx0. */ 500/* Bits specific to the R4xx0. */
501#define R4K_CONF_SW (_ULCAST_(1) << 20) 501#define R4K_CONF_SW (_ULCAST_(1) << 20)
502#define R4K_CONF_SS (_ULCAST_(1) << 21) 502#define R4K_CONF_SS (_ULCAST_(1) << 21)
503#define R4K_CONF_SB (_ULCAST_(3) << 22) 503#define R4K_CONF_SB (_ULCAST_(3) << 22)
504 504
505/* Bits specific to the R5000. */ 505/* Bits specific to the R5000. */
506#define R5K_CONF_SE (_ULCAST_(1) << 12) 506#define R5K_CONF_SE (_ULCAST_(1) << 12)
507#define R5K_CONF_SS (_ULCAST_(3) << 20) 507#define R5K_CONF_SS (_ULCAST_(3) << 20)
508 508
509/* Bits specific to the RM7000. */ 509/* Bits specific to the RM7000. */
510#define RM7K_CONF_SE (_ULCAST_(1) << 3) 510#define RM7K_CONF_SE (_ULCAST_(1) << 3)
511#define RM7K_CONF_TE (_ULCAST_(1) << 12) 511#define RM7K_CONF_TE (_ULCAST_(1) << 12)
512#define RM7K_CONF_CLK (_ULCAST_(1) << 16) 512#define RM7K_CONF_CLK (_ULCAST_(1) << 16)
513#define RM7K_CONF_TC (_ULCAST_(1) << 17) 513#define RM7K_CONF_TC (_ULCAST_(1) << 17)
514#define RM7K_CONF_SI (_ULCAST_(3) << 20) 514#define RM7K_CONF_SI (_ULCAST_(3) << 20)
515#define RM7K_CONF_SC (_ULCAST_(1) << 31) 515#define RM7K_CONF_SC (_ULCAST_(1) << 31)
516 516
517/* Bits specific to the R10000. */ 517/* Bits specific to the R10000. */
518#define R10K_CONF_DN (_ULCAST_(3) << 3) 518#define R10K_CONF_DN (_ULCAST_(3) << 3)
519#define R10K_CONF_CT (_ULCAST_(1) << 5) 519#define R10K_CONF_CT (_ULCAST_(1) << 5)
520#define R10K_CONF_PE (_ULCAST_(1) << 6) 520#define R10K_CONF_PE (_ULCAST_(1) << 6)
521#define R10K_CONF_PM (_ULCAST_(3) << 7) 521#define R10K_CONF_PM (_ULCAST_(3) << 7)
522#define R10K_CONF_EC (_ULCAST_(15)<< 9) 522#define R10K_CONF_EC (_ULCAST_(15)<< 9)
523#define R10K_CONF_SB (_ULCAST_(1) << 13) 523#define R10K_CONF_SB (_ULCAST_(1) << 13)
524#define R10K_CONF_SK (_ULCAST_(1) << 14) 524#define R10K_CONF_SK (_ULCAST_(1) << 14)
525#define R10K_CONF_SS (_ULCAST_(7) << 16) 525#define R10K_CONF_SS (_ULCAST_(7) << 16)
@@ -527,14 +527,14 @@
527#define R10K_CONF_DC (_ULCAST_(7) << 26) 527#define R10K_CONF_DC (_ULCAST_(7) << 26)
528#define R10K_CONF_IC (_ULCAST_(7) << 29) 528#define R10K_CONF_IC (_ULCAST_(7) << 29)
529 529
530/* Bits specific to the VR41xx. */ 530/* Bits specific to the VR41xx. */
531#define VR41_CONF_CS (_ULCAST_(1) << 12) 531#define VR41_CONF_CS (_ULCAST_(1) << 12)
532#define VR41_CONF_P4K (_ULCAST_(1) << 13) 532#define VR41_CONF_P4K (_ULCAST_(1) << 13)
533#define VR41_CONF_BP (_ULCAST_(1) << 16) 533#define VR41_CONF_BP (_ULCAST_(1) << 16)
534#define VR41_CONF_M16 (_ULCAST_(1) << 20) 534#define VR41_CONF_M16 (_ULCAST_(1) << 20)
535#define VR41_CONF_AD (_ULCAST_(1) << 23) 535#define VR41_CONF_AD (_ULCAST_(1) << 23)
536 536
537/* Bits specific to the R30xx. */ 537/* Bits specific to the R30xx. */
538#define R30XX_CONF_FDM (_ULCAST_(1) << 19) 538#define R30XX_CONF_FDM (_ULCAST_(1) << 19)
539#define R30XX_CONF_REV (_ULCAST_(1) << 22) 539#define R30XX_CONF_REV (_ULCAST_(1) << 22)
540#define R30XX_CONF_AC (_ULCAST_(1) << 23) 540#define R30XX_CONF_AC (_ULCAST_(1) << 23)
@@ -551,8 +551,8 @@
551#define TX49_CONF_HALT (_ULCAST_(1) << 18) 551#define TX49_CONF_HALT (_ULCAST_(1) << 18)
552#define TX49_CONF_CWFON (_ULCAST_(1) << 27) 552#define TX49_CONF_CWFON (_ULCAST_(1) << 27)
553 553
554/* Bits specific to the MIPS32/64 PRA. */ 554/* Bits specific to the MIPS32/64 PRA. */
555#define MIPS_CONF_MT (_ULCAST_(7) << 7) 555#define MIPS_CONF_MT (_ULCAST_(7) << 7)
556#define MIPS_CONF_AR (_ULCAST_(7) << 10) 556#define MIPS_CONF_AR (_ULCAST_(7) << 10)
557#define MIPS_CONF_AT (_ULCAST_(3) << 13) 557#define MIPS_CONF_AT (_ULCAST_(3) << 13)
558#define MIPS_CONF_M (_ULCAST_(1) << 31) 558#define MIPS_CONF_M (_ULCAST_(1) << 31)
@@ -560,14 +560,14 @@
560/* 560/*
561 * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above. 561 * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above.
562 */ 562 */
563#define MIPS_CONF1_FP (_ULCAST_(1) << 0) 563#define MIPS_CONF1_FP (_ULCAST_(1) << 0)
564#define MIPS_CONF1_EP (_ULCAST_(1) << 1) 564#define MIPS_CONF1_EP (_ULCAST_(1) << 1)
565#define MIPS_CONF1_CA (_ULCAST_(1) << 2) 565#define MIPS_CONF1_CA (_ULCAST_(1) << 2)
566#define MIPS_CONF1_WR (_ULCAST_(1) << 3) 566#define MIPS_CONF1_WR (_ULCAST_(1) << 3)
567#define MIPS_CONF1_PC (_ULCAST_(1) << 4) 567#define MIPS_CONF1_PC (_ULCAST_(1) << 4)
568#define MIPS_CONF1_MD (_ULCAST_(1) << 5) 568#define MIPS_CONF1_MD (_ULCAST_(1) << 5)
569#define MIPS_CONF1_C2 (_ULCAST_(1) << 6) 569#define MIPS_CONF1_C2 (_ULCAST_(1) << 6)
570#define MIPS_CONF1_DA (_ULCAST_(7) << 7) 570#define MIPS_CONF1_DA (_ULCAST_(7) << 7)
571#define MIPS_CONF1_DL (_ULCAST_(7) << 10) 571#define MIPS_CONF1_DL (_ULCAST_(7) << 10)
572#define MIPS_CONF1_DS (_ULCAST_(7) << 13) 572#define MIPS_CONF1_DS (_ULCAST_(7) << 13)
573#define MIPS_CONF1_IA (_ULCAST_(7) << 16) 573#define MIPS_CONF1_IA (_ULCAST_(7) << 16)
@@ -575,26 +575,28 @@
575#define MIPS_CONF1_IS (_ULCAST_(7) << 22) 575#define MIPS_CONF1_IS (_ULCAST_(7) << 22)
576#define MIPS_CONF1_TLBS (_ULCAST_(63)<< 25) 576#define MIPS_CONF1_TLBS (_ULCAST_(63)<< 25)
577 577
578#define MIPS_CONF2_SA (_ULCAST_(15)<< 0) 578#define MIPS_CONF2_SA (_ULCAST_(15)<< 0)
579#define MIPS_CONF2_SL (_ULCAST_(15)<< 4) 579#define MIPS_CONF2_SL (_ULCAST_(15)<< 4)
580#define MIPS_CONF2_SS (_ULCAST_(15)<< 8) 580#define MIPS_CONF2_SS (_ULCAST_(15)<< 8)
581#define MIPS_CONF2_SU (_ULCAST_(15)<< 12) 581#define MIPS_CONF2_SU (_ULCAST_(15)<< 12)
582#define MIPS_CONF2_TA (_ULCAST_(15)<< 16) 582#define MIPS_CONF2_TA (_ULCAST_(15)<< 16)
583#define MIPS_CONF2_TL (_ULCAST_(15)<< 20) 583#define MIPS_CONF2_TL (_ULCAST_(15)<< 20)
584#define MIPS_CONF2_TS (_ULCAST_(15)<< 24) 584#define MIPS_CONF2_TS (_ULCAST_(15)<< 24)
585#define MIPS_CONF2_TU (_ULCAST_(7) << 28) 585#define MIPS_CONF2_TU (_ULCAST_(7) << 28)
586 586
587#define MIPS_CONF3_TL (_ULCAST_(1) << 0) 587#define MIPS_CONF3_TL (_ULCAST_(1) << 0)
588#define MIPS_CONF3_SM (_ULCAST_(1) << 1) 588#define MIPS_CONF3_SM (_ULCAST_(1) << 1)
589#define MIPS_CONF3_MT (_ULCAST_(1) << 2) 589#define MIPS_CONF3_MT (_ULCAST_(1) << 2)
590#define MIPS_CONF3_SP (_ULCAST_(1) << 4) 590#define MIPS_CONF3_SP (_ULCAST_(1) << 4)
591#define MIPS_CONF3_VINT (_ULCAST_(1) << 5) 591#define MIPS_CONF3_VINT (_ULCAST_(1) << 5)
592#define MIPS_CONF3_VEIC (_ULCAST_(1) << 6) 592#define MIPS_CONF3_VEIC (_ULCAST_(1) << 6)
593#define MIPS_CONF3_LPA (_ULCAST_(1) << 7) 593#define MIPS_CONF3_LPA (_ULCAST_(1) << 7)
594#define MIPS_CONF3_DSP (_ULCAST_(1) << 10) 594#define MIPS_CONF3_DSP (_ULCAST_(1) << 10)
595#define MIPS_CONF3_DSP2P (_ULCAST_(1) << 11) 595#define MIPS_CONF3_DSP2P (_ULCAST_(1) << 11)
596#define MIPS_CONF3_RXI (_ULCAST_(1) << 12) 596#define MIPS_CONF3_RXI (_ULCAST_(1) << 12)
597#define MIPS_CONF3_ULRI (_ULCAST_(1) << 13) 597#define MIPS_CONF3_ULRI (_ULCAST_(1) << 13)
598#define MIPS_CONF3_ISA (_ULCAST_(3) << 14)
599#define MIPS_CONF3_VZ (_ULCAST_(1) << 23)
598 600
599#define MIPS_CONF4_MMUSIZEEXT (_ULCAST_(255) << 0) 601#define MIPS_CONF4_MMUSIZEEXT (_ULCAST_(255) << 0)
600#define MIPS_CONF4_MMUEXTDEF (_ULCAST_(3) << 14) 602#define MIPS_CONF4_MMUEXTDEF (_ULCAST_(3) << 14)
@@ -621,7 +623,7 @@
621#ifndef __ASSEMBLY__ 623#ifndef __ASSEMBLY__
622 624
623/* 625/*
624 * Functions to access the R10000 performance counters. These are basically 626 * Functions to access the R10000 performance counters. These are basically
625 * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit 627 * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit
626 * performance counter number encoded into bits 1 ... 5 of the instruction. 628 * performance counter number encoded into bits 1 ... 5 of the instruction.
627 * Only performance counters 0 to 1 actually exist, so for a non-R10000 aware 629 * Only performance counters 0 to 1 actually exist, so for a non-R10000 aware
@@ -632,13 +634,13 @@
632 unsigned int __res; \ 634 unsigned int __res; \
633 __asm__ __volatile__( \ 635 __asm__ __volatile__( \
634 "mfpc\t%0, %1" \ 636 "mfpc\t%0, %1" \
635 : "=r" (__res) \ 637 : "=r" (__res) \
636 : "i" (counter)); \ 638 : "i" (counter)); \
637 \ 639 \
638 __res; \ 640 __res; \
639}) 641})
640 642
641#define write_r10k_perf_cntr(counter,val) \ 643#define write_r10k_perf_cntr(counter,val) \
642do { \ 644do { \
643 __asm__ __volatile__( \ 645 __asm__ __volatile__( \
644 "mtpc\t%0, %1" \ 646 "mtpc\t%0, %1" \
@@ -651,13 +653,13 @@ do { \
651 unsigned int __res; \ 653 unsigned int __res; \
652 __asm__ __volatile__( \ 654 __asm__ __volatile__( \
653 "mfps\t%0, %1" \ 655 "mfps\t%0, %1" \
654 : "=r" (__res) \ 656 : "=r" (__res) \
655 : "i" (counter)); \ 657 : "i" (counter)); \
656 \ 658 \
657 __res; \ 659 __res; \
658}) 660})
659 661
660#define write_r10k_perf_cntl(counter,val) \ 662#define write_r10k_perf_cntl(counter,val) \
661do { \ 663do { \
662 __asm__ __volatile__( \ 664 __asm__ __volatile__( \
663 "mtps\t%0, %1" \ 665 "mtps\t%0, %1" \
@@ -847,20 +849,20 @@ do { \
847#define write_c0_context(val) __write_ulong_c0_register($4, 0, val) 849#define write_c0_context(val) __write_ulong_c0_register($4, 0, val)
848 850
849#define read_c0_userlocal() __read_ulong_c0_register($4, 2) 851#define read_c0_userlocal() __read_ulong_c0_register($4, 2)
850#define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val) 852#define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val)
851 853
852#define read_c0_pagemask() __read_32bit_c0_register($5, 0) 854#define read_c0_pagemask() __read_32bit_c0_register($5, 0)
853#define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val) 855#define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val)
854 856
855#define read_c0_pagegrain() __read_32bit_c0_register($5, 1) 857#define read_c0_pagegrain() __read_32bit_c0_register($5, 1)
856#define write_c0_pagegrain(val) __write_32bit_c0_register($5, 1, val) 858#define write_c0_pagegrain(val) __write_32bit_c0_register($5, 1, val)
857 859
858#define read_c0_wired() __read_32bit_c0_register($6, 0) 860#define read_c0_wired() __read_32bit_c0_register($6, 0)
859#define write_c0_wired(val) __write_32bit_c0_register($6, 0, val) 861#define write_c0_wired(val) __write_32bit_c0_register($6, 0, val)
860 862
861#define read_c0_info() __read_32bit_c0_register($7, 0) 863#define read_c0_info() __read_32bit_c0_register($7, 0)
862 864
863#define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */ 865#define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */
864#define write_c0_cache(val) __write_32bit_c0_register($7, 0, val) 866#define write_c0_cache(val) __write_32bit_c0_register($7, 0, val)
865 867
866#define read_c0_badvaddr() __read_ulong_c0_register($8, 0) 868#define read_c0_badvaddr() __read_ulong_c0_register($8, 0)
@@ -975,7 +977,7 @@ do { \
975#define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val) 977#define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val)
976 978
977#define read_c0_framemask() __read_32bit_c0_register($21, 0) 979#define read_c0_framemask() __read_32bit_c0_register($21, 0)
978#define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val) 980#define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val)
979 981
980#define read_c0_diag() __read_32bit_c0_register($22, 0) 982#define read_c0_diag() __read_32bit_c0_register($22, 0)
981#define write_c0_diag(val) __write_32bit_c0_register($22, 0, val) 983#define write_c0_diag(val) __write_32bit_c0_register($22, 0, val)
@@ -1005,27 +1007,27 @@ do { \
1005 * MIPS32 / MIPS64 performance counters 1007 * MIPS32 / MIPS64 performance counters
1006 */ 1008 */
1007#define read_c0_perfctrl0() __read_32bit_c0_register($25, 0) 1009#define read_c0_perfctrl0() __read_32bit_c0_register($25, 0)
1008#define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val) 1010#define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val)
1009#define read_c0_perfcntr0() __read_32bit_c0_register($25, 1) 1011#define read_c0_perfcntr0() __read_32bit_c0_register($25, 1)
1010#define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val) 1012#define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val)
1011#define read_c0_perfcntr0_64() __read_64bit_c0_register($25, 1) 1013#define read_c0_perfcntr0_64() __read_64bit_c0_register($25, 1)
1012#define write_c0_perfcntr0_64(val) __write_64bit_c0_register($25, 1, val) 1014#define write_c0_perfcntr0_64(val) __write_64bit_c0_register($25, 1, val)
1013#define read_c0_perfctrl1() __read_32bit_c0_register($25, 2) 1015#define read_c0_perfctrl1() __read_32bit_c0_register($25, 2)
1014#define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val) 1016#define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val)
1015#define read_c0_perfcntr1() __read_32bit_c0_register($25, 3) 1017#define read_c0_perfcntr1() __read_32bit_c0_register($25, 3)
1016#define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val) 1018#define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val)
1017#define read_c0_perfcntr1_64() __read_64bit_c0_register($25, 3) 1019#define read_c0_perfcntr1_64() __read_64bit_c0_register($25, 3)
1018#define write_c0_perfcntr1_64(val) __write_64bit_c0_register($25, 3, val) 1020#define write_c0_perfcntr1_64(val) __write_64bit_c0_register($25, 3, val)
1019#define read_c0_perfctrl2() __read_32bit_c0_register($25, 4) 1021#define read_c0_perfctrl2() __read_32bit_c0_register($25, 4)
1020#define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val) 1022#define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val)
1021#define read_c0_perfcntr2() __read_32bit_c0_register($25, 5) 1023#define read_c0_perfcntr2() __read_32bit_c0_register($25, 5)
1022#define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val) 1024#define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val)
1023#define read_c0_perfcntr2_64() __read_64bit_c0_register($25, 5) 1025#define read_c0_perfcntr2_64() __read_64bit_c0_register($25, 5)
1024#define write_c0_perfcntr2_64(val) __write_64bit_c0_register($25, 5, val) 1026#define write_c0_perfcntr2_64(val) __write_64bit_c0_register($25, 5, val)
1025#define read_c0_perfctrl3() __read_32bit_c0_register($25, 6) 1027#define read_c0_perfctrl3() __read_32bit_c0_register($25, 6)
1026#define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val) 1028#define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val)
1027#define read_c0_perfcntr3() __read_32bit_c0_register($25, 7) 1029#define read_c0_perfcntr3() __read_32bit_c0_register($25, 7)
1028#define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val) 1030#define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val)
1029#define read_c0_perfcntr3_64() __read_64bit_c0_register($25, 7) 1031#define read_c0_perfcntr3_64() __read_64bit_c0_register($25, 7)
1030#define write_c0_perfcntr3_64(val) __write_64bit_c0_register($25, 7, val) 1032#define write_c0_perfcntr3_64(val) __write_64bit_c0_register($25, 7, val)
1031 1033
@@ -1033,12 +1035,12 @@ do { \
1033#define write_c0_ecc(val) __write_32bit_c0_register($26, 0, val) 1035#define write_c0_ecc(val) __write_32bit_c0_register($26, 0, val)
1034 1036
1035#define read_c0_derraddr0() __read_ulong_c0_register($26, 1) 1037#define read_c0_derraddr0() __read_ulong_c0_register($26, 1)
1036#define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val) 1038#define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val)
1037 1039
1038#define read_c0_cacheerr() __read_32bit_c0_register($27, 0) 1040#define read_c0_cacheerr() __read_32bit_c0_register($27, 0)
1039 1041
1040#define read_c0_derraddr1() __read_ulong_c0_register($27, 1) 1042#define read_c0_derraddr1() __read_ulong_c0_register($27, 1)
1041#define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val) 1043#define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val)
1042 1044
1043#define read_c0_taglo() __read_32bit_c0_register($28, 0) 1045#define read_c0_taglo() __read_32bit_c0_register($28, 0)
1044#define write_c0_taglo(val) __write_32bit_c0_register($28, 0, val) 1046#define write_c0_taglo(val) __write_32bit_c0_register($28, 0, val)
@@ -1083,9 +1085,9 @@ do { \
1083#define write_c0_cvmctl(val) __write_64bit_c0_register($9, 7, val) 1085#define write_c0_cvmctl(val) __write_64bit_c0_register($9, 7, val)
1084 1086
1085#define read_c0_cvmmemctl() __read_64bit_c0_register($11, 7) 1087#define read_c0_cvmmemctl() __read_64bit_c0_register($11, 7)
1086#define write_c0_cvmmemctl(val) __write_64bit_c0_register($11, 7, val) 1088#define write_c0_cvmmemctl(val) __write_64bit_c0_register($11, 7, val)
1087/* 1089/*
1088 * The cacheerr registers are not standardized. On OCTEON, they are 1090 * The cacheerr registers are not standardized. On OCTEON, they are
1089 * 64 bits wide. 1091 * 64 bits wide.
1090 */ 1092 */
1091#define read_octeon_c0_icacheerr() __read_64bit_c0_register($27, 0) 1093#define read_octeon_c0_icacheerr() __read_64bit_c0_register($27, 0)
@@ -1142,48 +1144,42 @@ do { \
1142/* 1144/*
1143 * Macros to access the floating point coprocessor control registers 1145 * Macros to access the floating point coprocessor control registers
1144 */ 1146 */
1145#define read_32bit_cp1_register(source) \ 1147#define read_32bit_cp1_register(source) \
1146({ int __res; \ 1148({ \
1147 __asm__ __volatile__( \ 1149 int __res; \
1148 ".set\tpush\n\t" \ 1150 \
1149 ".set\treorder\n\t" \ 1151 __asm__ __volatile__( \
1150 /* gas fails to assemble cfc1 for some archs (octeon).*/ \ 1152 " .set push \n" \
1151 ".set\tmips1\n\t" \ 1153 " .set reorder \n" \
1152 "cfc1\t%0,"STR(source)"\n\t" \ 1154 " # gas fails to assemble cfc1 for some archs, \n" \
1153 ".set\tpop" \ 1155 " # like Octeon. \n" \
1154 : "=r" (__res)); \ 1156 " .set mips1 \n" \
1155 __res;}) 1157 " cfc1 %0,"STR(source)" \n" \
1158 " .set pop \n" \
1159 : "=r" (__res)); \
1160 __res; \
1161})
1156 1162
1163#ifdef HAVE_AS_DSP
1157#define rddsp(mask) \ 1164#define rddsp(mask) \
1158({ \ 1165({ \
1159 unsigned int __res; \ 1166 unsigned int __dspctl; \
1160 \ 1167 \
1161 __asm__ __volatile__( \ 1168 __asm__ __volatile__( \
1162 " .set push \n" \ 1169 " rddsp %0, %x1 \n" \
1163 " .set noat \n" \ 1170 : "=r" (__dspctl) \
1164 " # rddsp $1, %x1 \n" \
1165 " .word 0x7c000cb8 | (%x1 << 16) \n" \
1166 " move %0, $1 \n" \
1167 " .set pop \n" \
1168 : "=r" (__res) \
1169 : "i" (mask)); \ 1171 : "i" (mask)); \
1170 __res; \ 1172 __dspctl; \
1171}) 1173})
1172 1174
1173#define wrdsp(val, mask) \ 1175#define wrdsp(val, mask) \
1174do { \ 1176do { \
1175 __asm__ __volatile__( \ 1177 __asm__ __volatile__( \
1176 " .set push \n" \ 1178 " wrdsp %0, %x1 \n" \
1177 " .set noat \n" \ 1179 : \
1178 " move $1, %0 \n" \
1179 " # wrdsp $1, %x1 \n" \
1180 " .word 0x7c2004f8 | (%x1 << 11) \n" \
1181 " .set pop \n" \
1182 : \
1183 : "r" (val), "i" (mask)); \ 1180 : "r" (val), "i" (mask)); \
1184} while (0) 1181} while (0)
1185 1182
1186#if 0 /* Need DSP ASE capable assembler ... */
1187#define mflo0() ({ long mflo0; __asm__("mflo %0, $ac0" : "=r" (mflo0)); mflo0;}) 1183#define mflo0() ({ long mflo0; __asm__("mflo %0, $ac0" : "=r" (mflo0)); mflo0;})
1188#define mflo1() ({ long mflo1; __asm__("mflo %0, $ac1" : "=r" (mflo1)); mflo1;}) 1184#define mflo1() ({ long mflo1; __asm__("mflo %0, $ac1" : "=r" (mflo1)); mflo1;})
1189#define mflo2() ({ long mflo2; __asm__("mflo %0, $ac2" : "=r" (mflo2)); mflo2;}) 1185#define mflo2() ({ long mflo2; __asm__("mflo %0, $ac2" : "=r" (mflo2)); mflo2;})
@@ -1206,230 +1202,177 @@ do { \
1206 1202
1207#else 1203#else
1208 1204
1209#define mfhi0() \ 1205#ifdef CONFIG_CPU_MICROMIPS
1210({ \ 1206#define rddsp(mask) \
1211 unsigned long __treg; \
1212 \
1213 __asm__ __volatile__( \
1214 " .set push \n" \
1215 " .set noat \n" \
1216 " # mfhi %0, $ac0 \n" \
1217 " .word 0x00000810 \n" \
1218 " move %0, $1 \n" \
1219 " .set pop \n" \
1220 : "=r" (__treg)); \
1221 __treg; \
1222})
1223
1224#define mfhi1() \
1225({ \
1226 unsigned long __treg; \
1227 \
1228 __asm__ __volatile__( \
1229 " .set push \n" \
1230 " .set noat \n" \
1231 " # mfhi %0, $ac1 \n" \
1232 " .word 0x00200810 \n" \
1233 " move %0, $1 \n" \
1234 " .set pop \n" \
1235 : "=r" (__treg)); \
1236 __treg; \
1237})
1238
1239#define mfhi2() \
1240({ \
1241 unsigned long __treg; \
1242 \
1243 __asm__ __volatile__( \
1244 " .set push \n" \
1245 " .set noat \n" \
1246 " # mfhi %0, $ac2 \n" \
1247 " .word 0x00400810 \n" \
1248 " move %0, $1 \n" \
1249 " .set pop \n" \
1250 : "=r" (__treg)); \
1251 __treg; \
1252})
1253
1254#define mfhi3() \
1255({ \
1256 unsigned long __treg; \
1257 \
1258 __asm__ __volatile__( \
1259 " .set push \n" \
1260 " .set noat \n" \
1261 " # mfhi %0, $ac3 \n" \
1262 " .word 0x00600810 \n" \
1263 " move %0, $1 \n" \
1264 " .set pop \n" \
1265 : "=r" (__treg)); \
1266 __treg; \
1267})
1268
1269#define mflo0() \
1270({ \
1271 unsigned long __treg; \
1272 \
1273 __asm__ __volatile__( \
1274 " .set push \n" \
1275 " .set noat \n" \
1276 " # mflo %0, $ac0 \n" \
1277 " .word 0x00000812 \n" \
1278 " move %0, $1 \n" \
1279 " .set pop \n" \
1280 : "=r" (__treg)); \
1281 __treg; \
1282})
1283
1284#define mflo1() \
1285({ \
1286 unsigned long __treg; \
1287 \
1288 __asm__ __volatile__( \
1289 " .set push \n" \
1290 " .set noat \n" \
1291 " # mflo %0, $ac1 \n" \
1292 " .word 0x00200812 \n" \
1293 " move %0, $1 \n" \
1294 " .set pop \n" \
1295 : "=r" (__treg)); \
1296 __treg; \
1297})
1298
1299#define mflo2() \
1300({ \
1301 unsigned long __treg; \
1302 \
1303 __asm__ __volatile__( \
1304 " .set push \n" \
1305 " .set noat \n" \
1306 " # mflo %0, $ac2 \n" \
1307 " .word 0x00400812 \n" \
1308 " move %0, $1 \n" \
1309 " .set pop \n" \
1310 : "=r" (__treg)); \
1311 __treg; \
1312})
1313
1314#define mflo3() \
1315({ \ 1207({ \
1316 unsigned long __treg; \ 1208 unsigned int __res; \
1317 \ 1209 \
1318 __asm__ __volatile__( \ 1210 __asm__ __volatile__( \
1319 " .set push \n" \
1320 " .set noat \n" \
1321 " # mflo %0, $ac3 \n" \
1322 " .word 0x00600812 \n" \
1323 " move %0, $1 \n" \
1324 " .set pop \n" \
1325 : "=r" (__treg)); \
1326 __treg; \
1327})
1328
1329#define mthi0(x) \
1330do { \
1331 __asm__ __volatile__( \
1332 " .set push \n" \ 1211 " .set push \n" \
1333 " .set noat \n" \ 1212 " .set noat \n" \
1334 " move $1, %0 \n" \ 1213 " # rddsp $1, %x1 \n" \
1335 " # mthi $1, $ac0 \n" \ 1214 " .hword ((0x0020067c | (%x1 << 14)) >> 16) \n" \
1336 " .word 0x00200011 \n" \ 1215 " .hword ((0x0020067c | (%x1 << 14)) & 0xffff) \n" \
1216 " move %0, $1 \n" \
1337 " .set pop \n" \ 1217 " .set pop \n" \
1338 : \ 1218 : "=r" (__res) \
1339 : "r" (x)); \ 1219 : "i" (mask)); \
1340} while (0) 1220 __res; \
1221})
1341 1222
1342#define mthi1(x) \ 1223#define wrdsp(val, mask) \
1343do { \ 1224do { \
1344 __asm__ __volatile__( \ 1225 __asm__ __volatile__( \
1345 " .set push \n" \ 1226 " .set push \n" \
1346 " .set noat \n" \ 1227 " .set noat \n" \
1347 " move $1, %0 \n" \ 1228 " move $1, %0 \n" \
1348 " # mthi $1, $ac1 \n" \ 1229 " # wrdsp $1, %x1 \n" \
1349 " .word 0x00200811 \n" \ 1230 " .hword ((0x0020167c | (%x1 << 14)) >> 16) \n" \
1231 " .hword ((0x0020167c | (%x1 << 14)) & 0xffff) \n" \
1350 " .set pop \n" \ 1232 " .set pop \n" \
1351 : \ 1233 : \
1352 : "r" (x)); \ 1234 : "r" (val), "i" (mask)); \
1353} while (0) 1235} while (0)
1354 1236
1355#define mthi2(x) \ 1237#define _umips_dsp_mfxxx(ins) \
1356do { \ 1238({ \
1239 unsigned long __treg; \
1240 \
1357 __asm__ __volatile__( \ 1241 __asm__ __volatile__( \
1358 " .set push \n" \ 1242 " .set push \n" \
1359 " .set noat \n" \ 1243 " .set noat \n" \
1360 " move $1, %0 \n" \ 1244 " .hword 0x0001 \n" \
1361 " # mthi $1, $ac2 \n" \ 1245 " .hword %x1 \n" \
1362 " .word 0x00201011 \n" \ 1246 " move %0, $1 \n" \
1363 " .set pop \n" \ 1247 " .set pop \n" \
1364 : \ 1248 : "=r" (__treg) \
1365 : "r" (x)); \ 1249 : "i" (ins)); \
1366} while (0) 1250 __treg; \
1251})
1367 1252
1368#define mthi3(x) \ 1253#define _umips_dsp_mtxxx(val, ins) \
1369do { \ 1254do { \
1370 __asm__ __volatile__( \ 1255 __asm__ __volatile__( \
1371 " .set push \n" \ 1256 " .set push \n" \
1372 " .set noat \n" \ 1257 " .set noat \n" \
1373 " move $1, %0 \n" \ 1258 " move $1, %0 \n" \
1374 " # mthi $1, $ac3 \n" \ 1259 " .hword 0x0001 \n" \
1375 " .word 0x00201811 \n" \ 1260 " .hword %x1 \n" \
1376 " .set pop \n" \ 1261 " .set pop \n" \
1377 : \ 1262 : \
1378 : "r" (x)); \ 1263 : "r" (val), "i" (ins)); \
1379} while (0) 1264} while (0)
1380 1265
1381#define mtlo0(x) \ 1266#define _umips_dsp_mflo(reg) _umips_dsp_mfxxx((reg << 14) | 0x107c)
1382do { \ 1267#define _umips_dsp_mfhi(reg) _umips_dsp_mfxxx((reg << 14) | 0x007c)
1268
1269#define _umips_dsp_mtlo(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x307c))
1270#define _umips_dsp_mthi(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x207c))
1271
1272#define mflo0() _umips_dsp_mflo(0)
1273#define mflo1() _umips_dsp_mflo(1)
1274#define mflo2() _umips_dsp_mflo(2)
1275#define mflo3() _umips_dsp_mflo(3)
1276
1277#define mfhi0() _umips_dsp_mfhi(0)
1278#define mfhi1() _umips_dsp_mfhi(1)
1279#define mfhi2() _umips_dsp_mfhi(2)
1280#define mfhi3() _umips_dsp_mfhi(3)
1281
1282#define mtlo0(x) _umips_dsp_mtlo(x, 0)
1283#define mtlo1(x) _umips_dsp_mtlo(x, 1)
1284#define mtlo2(x) _umips_dsp_mtlo(x, 2)
1285#define mtlo3(x) _umips_dsp_mtlo(x, 3)
1286
1287#define mthi0(x) _umips_dsp_mthi(x, 0)
1288#define mthi1(x) _umips_dsp_mthi(x, 1)
1289#define mthi2(x) _umips_dsp_mthi(x, 2)
1290#define mthi3(x) _umips_dsp_mthi(x, 3)
1291
1292#else /* !CONFIG_CPU_MICROMIPS */
1293#define rddsp(mask) \
1294({ \
1295 unsigned int __res; \
1296 \
1383 __asm__ __volatile__( \ 1297 __asm__ __volatile__( \
1384 " .set push \n" \ 1298 " .set push \n" \
1385 " .set noat \n" \ 1299 " .set noat \n" \
1386 " move $1, %0 \n" \ 1300 " # rddsp $1, %x1 \n" \
1387 " # mtlo $1, $ac0 \n" \ 1301 " .word 0x7c000cb8 | (%x1 << 16) \n" \
1388 " .word 0x00200013 \n" \ 1302 " move %0, $1 \n" \
1389 " .set pop \n" \ 1303 " .set pop \n" \
1390 : \ 1304 : "=r" (__res) \
1391 : "r" (x)); \ 1305 : "i" (mask)); \
1392} while (0) 1306 __res; \
1307})
1393 1308
1394#define mtlo1(x) \ 1309#define wrdsp(val, mask) \
1395do { \ 1310do { \
1396 __asm__ __volatile__( \ 1311 __asm__ __volatile__( \
1397 " .set push \n" \ 1312 " .set push \n" \
1398 " .set noat \n" \ 1313 " .set noat \n" \
1399 " move $1, %0 \n" \ 1314 " move $1, %0 \n" \
1400 " # mtlo $1, $ac1 \n" \ 1315 " # wrdsp $1, %x1 \n" \
1401 " .word 0x00200813 \n" \ 1316 " .word 0x7c2004f8 | (%x1 << 11) \n" \
1402 " .set pop \n" \ 1317 " .set pop \n" \
1403 : \ 1318 : \
1404 : "r" (x)); \ 1319 : "r" (val), "i" (mask)); \
1405} while (0) 1320} while (0)
1406 1321
1407#define mtlo2(x) \ 1322#define _dsp_mfxxx(ins) \
1408do { \ 1323({ \
1324 unsigned long __treg; \
1325 \
1409 __asm__ __volatile__( \ 1326 __asm__ __volatile__( \
1410 " .set push \n" \ 1327 " .set push \n" \
1411 " .set noat \n" \ 1328 " .set noat \n" \
1412 " move $1, %0 \n" \ 1329 " .word (0x00000810 | %1) \n" \
1413 " # mtlo $1, $ac2 \n" \ 1330 " move %0, $1 \n" \
1414 " .word 0x00201013 \n" \
1415 " .set pop \n" \ 1331 " .set pop \n" \
1416 : \ 1332 : "=r" (__treg) \
1417 : "r" (x)); \ 1333 : "i" (ins)); \
1418} while (0) 1334 __treg; \
1335})
1419 1336
1420#define mtlo3(x) \ 1337#define _dsp_mtxxx(val, ins) \
1421do { \ 1338do { \
1422 __asm__ __volatile__( \ 1339 __asm__ __volatile__( \
1423 " .set push \n" \ 1340 " .set push \n" \
1424 " .set noat \n" \ 1341 " .set noat \n" \
1425 " move $1, %0 \n" \ 1342 " move $1, %0 \n" \
1426 " # mtlo $1, $ac3 \n" \ 1343 " .word (0x00200011 | %1) \n" \
1427 " .word 0x00201813 \n" \
1428 " .set pop \n" \ 1344 " .set pop \n" \
1429 : \ 1345 : \
1430 : "r" (x)); \ 1346 : "r" (val), "i" (ins)); \
1431} while (0) 1347} while (0)
1432 1348
1349#define _dsp_mflo(reg) _dsp_mfxxx((reg << 21) | 0x0002)
1350#define _dsp_mfhi(reg) _dsp_mfxxx((reg << 21) | 0x0000)
1351
1352#define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0002))
1353#define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0000))
1354
1355#define mflo0() _dsp_mflo(0)
1356#define mflo1() _dsp_mflo(1)
1357#define mflo2() _dsp_mflo(2)
1358#define mflo3() _dsp_mflo(3)
1359
1360#define mfhi0() _dsp_mfhi(0)
1361#define mfhi1() _dsp_mfhi(1)
1362#define mfhi2() _dsp_mfhi(2)
1363#define mfhi3() _dsp_mfhi(3)
1364
1365#define mtlo0(x) _dsp_mtlo(x, 0)
1366#define mtlo1(x) _dsp_mtlo(x, 1)
1367#define mtlo2(x) _dsp_mtlo(x, 2)
1368#define mtlo3(x) _dsp_mtlo(x, 3)
1369
1370#define mthi0(x) _dsp_mthi(x, 0)
1371#define mthi1(x) _dsp_mthi(x, 1)
1372#define mthi2(x) _dsp_mthi(x, 2)
1373#define mthi3(x) _dsp_mthi(x, 3)
1374
1375#endif /* CONFIG_CPU_MICROMIPS */
1433#endif 1376#endif
1434 1377
1435/* 1378/*
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-24 04:49:43 -0500