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-rw-r--r--arch/mips/include/asm/mips-boards/bonito64.h106
-rw-r--r--arch/mips/include/asm/mips-boards/generic.h40
-rw-r--r--arch/mips/include/asm/mips-boards/launch.h10
-rw-r--r--arch/mips/include/asm/mips-boards/malta.h10
-rw-r--r--arch/mips/include/asm/mips-boards/maltaint.h8
-rw-r--r--arch/mips/include/asm/mips-boards/piix4.h8
-rw-r--r--arch/mips/include/asm/mips-boards/prom.h6
-rw-r--r--arch/mips/include/asm/mips-boards/sead3int.h4
-rw-r--r--arch/mips/include/asm/mips-boards/sim.h14
9 files changed, 103 insertions, 103 deletions
diff --git a/arch/mips/include/asm/mips-boards/bonito64.h b/arch/mips/include/asm/mips-boards/bonito64.h
index d14e2adc4be5..b2048d1bcc1c 100644
--- a/arch/mips/include/asm/mips-boards/bonito64.h
+++ b/arch/mips/include/asm/mips-boards/bonito64.h
@@ -41,18 +41,18 @@ extern unsigned long _pcictrl_bonito_pcicfg;
41 41
42#define BONITO_BOOT_BASE 0x1fc00000 42#define BONITO_BOOT_BASE 0x1fc00000
43#define BONITO_BOOT_SIZE 0x00100000 43#define BONITO_BOOT_SIZE 0x00100000
44#define BONITO_BOOT_TOP (BONITO_BOOT_BASE+BONITO_BOOT_SIZE-1) 44#define BONITO_BOOT_TOP (BONITO_BOOT_BASE+BONITO_BOOT_SIZE-1)
45#define BONITO_FLASH_BASE 0x1c000000 45#define BONITO_FLASH_BASE 0x1c000000
46#define BONITO_FLASH_SIZE 0x03000000 46#define BONITO_FLASH_SIZE 0x03000000
47#define BONITO_FLASH_TOP (BONITO_FLASH_BASE+BONITO_FLASH_SIZE-1) 47#define BONITO_FLASH_TOP (BONITO_FLASH_BASE+BONITO_FLASH_SIZE-1)
48#define BONITO_SOCKET_BASE 0x1f800000 48#define BONITO_SOCKET_BASE 0x1f800000
49#define BONITO_SOCKET_SIZE 0x00400000 49#define BONITO_SOCKET_SIZE 0x00400000
50#define BONITO_SOCKET_TOP (BONITO_SOCKET_BASE+BONITO_SOCKET_SIZE-1) 50#define BONITO_SOCKET_TOP (BONITO_SOCKET_BASE+BONITO_SOCKET_SIZE-1)
51#define BONITO_REG_BASE 0x1fe00000 51#define BONITO_REG_BASE 0x1fe00000
52#define BONITO_REG_SIZE 0x00040000 52#define BONITO_REG_SIZE 0x00040000
53#define BONITO_REG_TOP (BONITO_REG_BASE+BONITO_REG_SIZE-1) 53#define BONITO_REG_TOP (BONITO_REG_BASE+BONITO_REG_SIZE-1)
54#define BONITO_DEV_BASE 0x1ff00000 54#define BONITO_DEV_BASE 0x1ff00000
55#define BONITO_DEV_SIZE 0x00100000 55#define BONITO_DEV_SIZE 0x00100000
56#define BONITO_DEV_TOP (BONITO_DEV_BASE+BONITO_DEV_SIZE-1) 56#define BONITO_DEV_TOP (BONITO_DEV_BASE+BONITO_DEV_SIZE-1)
57#define BONITO_PCILO_BASE 0x10000000 57#define BONITO_PCILO_BASE 0x10000000
58#define BONITO_PCILO_SIZE 0x0c000000 58#define BONITO_PCILO_SIZE 0x0c000000
@@ -79,14 +79,14 @@ extern unsigned long _pcictrl_bonito_pcicfg;
79 79
80/* PCI Configuration Registers */ 80/* PCI Configuration Registers */
81 81
82#define BONITO_PCI_REG(x) BONITO(BONITO_PCICONFIGBASE + (x)) 82#define BONITO_PCI_REG(x) BONITO(BONITO_PCICONFIGBASE + (x))
83#define BONITO_PCIDID BONITO_PCI_REG(0x00) 83#define BONITO_PCIDID BONITO_PCI_REG(0x00)
84#define BONITO_PCICMD BONITO_PCI_REG(0x04) 84#define BONITO_PCICMD BONITO_PCI_REG(0x04)
85#define BONITO_PCICLASS BONITO_PCI_REG(0x08) 85#define BONITO_PCICLASS BONITO_PCI_REG(0x08)
86#define BONITO_PCILTIMER BONITO_PCI_REG(0x0c) 86#define BONITO_PCILTIMER BONITO_PCI_REG(0x0c)
87#define BONITO_PCIBASE0 BONITO_PCI_REG(0x10) 87#define BONITO_PCIBASE0 BONITO_PCI_REG(0x10)
88#define BONITO_PCIBASE1 BONITO_PCI_REG(0x14) 88#define BONITO_PCIBASE1 BONITO_PCI_REG(0x14)
89#define BONITO_PCIBASE2 BONITO_PCI_REG(0x18) 89#define BONITO_PCIBASE2 BONITO_PCI_REG(0x18)
90#define BONITO_PCIEXPRBASE BONITO_PCI_REG(0x30) 90#define BONITO_PCIEXPRBASE BONITO_PCI_REG(0x30)
91#define BONITO_PCIINT BONITO_PCI_REG(0x3c) 91#define BONITO_PCIINT BONITO_PCI_REG(0x3c)
92 92
@@ -95,7 +95,7 @@ extern unsigned long _pcictrl_bonito_pcicfg;
95#define BONITO_PCICMD_MABORT_CLR 0x20000000 95#define BONITO_PCICMD_MABORT_CLR 0x20000000
96#define BONITO_PCICMD_MTABORT_CLR 0x10000000 96#define BONITO_PCICMD_MTABORT_CLR 0x10000000
97#define BONITO_PCICMD_TABORT_CLR 0x08000000 97#define BONITO_PCICMD_TABORT_CLR 0x08000000
98#define BONITO_PCICMD_MPERR_CLR 0x01000000 98#define BONITO_PCICMD_MPERR_CLR 0x01000000
99#define BONITO_PCICMD_PERRRESPEN 0x00000040 99#define BONITO_PCICMD_PERRRESPEN 0x00000040
100#define BONITO_PCICMD_ASTEPEN 0x00000080 100#define BONITO_PCICMD_ASTEPEN 0x00000080
101#define BONITO_PCICMD_SERREN 0x00000100 101#define BONITO_PCICMD_SERREN 0x00000100
@@ -139,7 +139,7 @@ extern unsigned long _pcictrl_bonito_pcicfg;
139 139
140/* Other Bonito configuration */ 140/* Other Bonito configuration */
141 141
142#define BONITO_BONGENCFG_OFFSET 0x4 142#define BONITO_BONGENCFG_OFFSET 0x4
143#define BONITO_BONGENCFG BONITO(BONITO_REGBASE + BONITO_BONGENCFG_OFFSET) 143#define BONITO_BONGENCFG BONITO(BONITO_REGBASE + BONITO_BONGENCFG_OFFSET)
144 144
145#define BONITO_BONGENCFG_DEBUGMODE 0x00000001 145#define BONITO_BONGENCFG_DEBUGMODE 0x00000001
@@ -165,7 +165,7 @@ extern unsigned long _pcictrl_bonito_pcicfg;
165 165
166/* 2. IO & IDE configuration */ 166/* 2. IO & IDE configuration */
167 167
168#define BONITO_IODEVCFG BONITO(BONITO_REGBASE + 0x08) 168#define BONITO_IODEVCFG BONITO(BONITO_REGBASE + 0x08)
169 169
170/* 3. IO & IDE configuration */ 170/* 3. IO & IDE configuration */
171 171
@@ -181,33 +181,33 @@ extern unsigned long _pcictrl_bonito_pcicfg;
181 181
182/* GPIO Regs - r/w */ 182/* GPIO Regs - r/w */
183 183
184#define BONITO_GPIODATA_OFFSET 0x1c 184#define BONITO_GPIODATA_OFFSET 0x1c
185#define BONITO_GPIODATA BONITO(BONITO_REGBASE + BONITO_GPIODATA_OFFSET) 185#define BONITO_GPIODATA BONITO(BONITO_REGBASE + BONITO_GPIODATA_OFFSET)
186#define BONITO_GPIOIE BONITO(BONITO_REGBASE + 0x20) 186#define BONITO_GPIOIE BONITO(BONITO_REGBASE + 0x20)
187 187
188/* ICU Configuration Regs - r/w */ 188/* ICU Configuration Regs - r/w */
189 189
190#define BONITO_INTEDGE BONITO(BONITO_REGBASE + 0x24) 190#define BONITO_INTEDGE BONITO(BONITO_REGBASE + 0x24)
191#define BONITO_INTSTEER BONITO(BONITO_REGBASE + 0x28) 191#define BONITO_INTSTEER BONITO(BONITO_REGBASE + 0x28)
192#define BONITO_INTPOL BONITO(BONITO_REGBASE + 0x2c) 192#define BONITO_INTPOL BONITO(BONITO_REGBASE + 0x2c)
193 193
194/* ICU Enable Regs - IntEn & IntISR are r/o. */ 194/* ICU Enable Regs - IntEn & IntISR are r/o. */
195 195
196#define BONITO_INTENSET BONITO(BONITO_REGBASE + 0x30) 196#define BONITO_INTENSET BONITO(BONITO_REGBASE + 0x30)
197#define BONITO_INTENCLR BONITO(BONITO_REGBASE + 0x34) 197#define BONITO_INTENCLR BONITO(BONITO_REGBASE + 0x34)
198#define BONITO_INTEN BONITO(BONITO_REGBASE + 0x38) 198#define BONITO_INTEN BONITO(BONITO_REGBASE + 0x38)
199#define BONITO_INTISR BONITO(BONITO_REGBASE + 0x3c) 199#define BONITO_INTISR BONITO(BONITO_REGBASE + 0x3c)
200 200
201/* PCI mail boxes */ 201/* PCI mail boxes */
202 202
203#define BONITO_PCIMAIL0_OFFSET 0x40 203#define BONITO_PCIMAIL0_OFFSET 0x40
204#define BONITO_PCIMAIL1_OFFSET 0x44 204#define BONITO_PCIMAIL1_OFFSET 0x44
205#define BONITO_PCIMAIL2_OFFSET 0x48 205#define BONITO_PCIMAIL2_OFFSET 0x48
206#define BONITO_PCIMAIL3_OFFSET 0x4c 206#define BONITO_PCIMAIL3_OFFSET 0x4c
207#define BONITO_PCIMAIL0 BONITO(BONITO_REGBASE + 0x40) 207#define BONITO_PCIMAIL0 BONITO(BONITO_REGBASE + 0x40)
208#define BONITO_PCIMAIL1 BONITO(BONITO_REGBASE + 0x44) 208#define BONITO_PCIMAIL1 BONITO(BONITO_REGBASE + 0x44)
209#define BONITO_PCIMAIL2 BONITO(BONITO_REGBASE + 0x48) 209#define BONITO_PCIMAIL2 BONITO(BONITO_REGBASE + 0x48)
210#define BONITO_PCIMAIL3 BONITO(BONITO_REGBASE + 0x4c) 210#define BONITO_PCIMAIL3 BONITO(BONITO_REGBASE + 0x4c)
211 211
212 212
213/* 6. PCI cache */ 213/* 6. PCI cache */
@@ -216,7 +216,7 @@ extern unsigned long _pcictrl_bonito_pcicfg;
216#define BONITO_PCICACHETAG BONITO(BONITO_REGBASE + 0x54) 216#define BONITO_PCICACHETAG BONITO(BONITO_REGBASE + 0x54)
217 217
218#define BONITO_PCIBADADDR BONITO(BONITO_REGBASE + 0x58) 218#define BONITO_PCIBADADDR BONITO(BONITO_REGBASE + 0x58)
219#define BONITO_PCIMSTAT BONITO(BONITO_REGBASE + 0x5c) 219#define BONITO_PCIMSTAT BONITO(BONITO_REGBASE + 0x5c)
220 220
221 221
222/* 222/*
@@ -228,20 +228,20 @@ extern unsigned long _pcictrl_bonito_pcicfg;
228 228
229#define BONITO_CONFIGBASE 0x000 229#define BONITO_CONFIGBASE 0x000
230#define BONITO_BONITOBASE 0x100 230#define BONITO_BONITOBASE 0x100
231#define BONITO_LDMABASE 0x200 231#define BONITO_LDMABASE 0x200
232#define BONITO_COPBASE 0x300 232#define BONITO_COPBASE 0x300
233#define BONITO_REG_BLOCKMASK 0x300 233#define BONITO_REG_BLOCKMASK 0x300
234 234
235#define BONITO_LDMACTRL BONITO(BONITO_LDMABASE + 0x0) 235#define BONITO_LDMACTRL BONITO(BONITO_LDMABASE + 0x0)
236#define BONITO_LDMASTAT BONITO(BONITO_LDMABASE + 0x0) 236#define BONITO_LDMASTAT BONITO(BONITO_LDMABASE + 0x0)
237#define BONITO_LDMAADDR BONITO(BONITO_LDMABASE + 0x4) 237#define BONITO_LDMAADDR BONITO(BONITO_LDMABASE + 0x4)
238#define BONITO_LDMAGO BONITO(BONITO_LDMABASE + 0x8) 238#define BONITO_LDMAGO BONITO(BONITO_LDMABASE + 0x8)
239#define BONITO_LDMADATA BONITO(BONITO_LDMABASE + 0xc) 239#define BONITO_LDMADATA BONITO(BONITO_LDMABASE + 0xc)
240 240
241#define BONITO_COPCTRL BONITO(BONITO_COPBASE + 0x0) 241#define BONITO_COPCTRL BONITO(BONITO_COPBASE + 0x0)
242#define BONITO_COPSTAT BONITO(BONITO_COPBASE + 0x0) 242#define BONITO_COPSTAT BONITO(BONITO_COPBASE + 0x0)
243#define BONITO_COPPADDR BONITO(BONITO_COPBASE + 0x4) 243#define BONITO_COPPADDR BONITO(BONITO_COPBASE + 0x4)
244#define BONITO_COPDADDR BONITO(BONITO_COPBASE + 0x8) 244#define BONITO_COPDADDR BONITO(BONITO_COPBASE + 0x8)
245#define BONITO_COPGO BONITO(BONITO_COPBASE + 0xc) 245#define BONITO_COPGO BONITO(BONITO_COPBASE + 0xc)
246 246
247 247
@@ -257,7 +257,7 @@ extern unsigned long _pcictrl_bonito_pcicfg;
257#define BONITO_IDECOPGO_DMA_SIZE_SHIFT 0 257#define BONITO_IDECOPGO_DMA_SIZE_SHIFT 0
258#define BONITO_IDECOPGO_DMA_WRITE 0x00010000 258#define BONITO_IDECOPGO_DMA_WRITE 0x00010000
259#define BONITO_IDECOPGO_DMAWCOUNT 0x000f0000 259#define BONITO_IDECOPGO_DMAWCOUNT 0x000f0000
260#define BONITO_IDECOPGO_DMAWCOUNT_SHIFT 16 260#define BONITO_IDECOPGO_DMAWCOUNT_SHIFT 16
261 261
262#define BONITO_IDECOPCTRL_DMA_STARTBIT 0x80000000 262#define BONITO_IDECOPCTRL_DMA_STARTBIT 0x80000000
263#define BONITO_IDECOPCTRL_DMA_RSTBIT 0x40000000 263#define BONITO_IDECOPCTRL_DMA_RSTBIT 0x40000000
@@ -291,11 +291,11 @@ extern unsigned long _pcictrl_bonito_pcicfg;
291#define BONITO_SDCFG_DRAMMODESET 0x00200000 291#define BONITO_SDCFG_DRAMMODESET 0x00200000
292/* --- */ 292/* --- */
293#define BONITO_SDCFG_DRAMEXTREGS 0x00400000 293#define BONITO_SDCFG_DRAMEXTREGS 0x00400000
294#define BONITO_SDCFG_DRAMPARITY 0x00800000 294#define BONITO_SDCFG_DRAMPARITY 0x00800000
295/* Added by RPF 11-9-00 */ 295/* Added by RPF 11-9-00 */
296#define BONITO_SDCFG_DRAMBURSTLEN 0x03000000 296#define BONITO_SDCFG_DRAMBURSTLEN 0x03000000
297#define BONITO_SDCFG_DRAMBURSTLEN_SHIFT 24 297#define BONITO_SDCFG_DRAMBURSTLEN_SHIFT 24
298#define BONITO_SDCFG_DRAMMODESET_DONE 0x80000000 298#define BONITO_SDCFG_DRAMMODESET_DONE 0x80000000
299/* --- */ 299/* --- */
300 300
301/* PCI Cache - pciCacheCtrl */ 301/* PCI Cache - pciCacheCtrl */
@@ -308,7 +308,7 @@ extern unsigned long _pcictrl_bonito_pcicfg;
308 308
309#define BONITO_PCICACHECTRL_IOBCCOH_PRES 0x00000100 309#define BONITO_PCICACHECTRL_IOBCCOH_PRES 0x00000100
310#define BONITO_PCICACHECTRL_IOBCCOH_EN 0x00000200 310#define BONITO_PCICACHECTRL_IOBCCOH_EN 0x00000200
311#define BONITO_PCICACHECTRL_CPUCOH_PRES 0x00000400 311#define BONITO_PCICACHECTRL_CPUCOH_PRES 0x00000400
312#define BONITO_PCICACHECTRL_CPUCOH_EN 0x00000800 312#define BONITO_PCICACHECTRL_CPUCOH_EN 0x00000800
313 313
314#define BONITO_IODEVCFG_BUFFBIT_CS0 0x00000001 314#define BONITO_IODEVCFG_BUFFBIT_CS0 0x00000001
@@ -343,18 +343,18 @@ extern unsigned long _pcictrl_bonito_pcicfg;
343 343
344/* gpio */ 344/* gpio */
345#define BONITO_GPIO_GPIOW 0x000003ff 345#define BONITO_GPIO_GPIOW 0x000003ff
346#define BONITO_GPIO_GPIOW_SHIFT 0 346#define BONITO_GPIO_GPIOW_SHIFT 0
347#define BONITO_GPIO_GPIOR 0x01ff0000 347#define BONITO_GPIO_GPIOR 0x01ff0000
348#define BONITO_GPIO_GPIOR_SHIFT 16 348#define BONITO_GPIO_GPIOR_SHIFT 16
349#define BONITO_GPIO_GPINR 0xfe000000 349#define BONITO_GPIO_GPINR 0xfe000000
350#define BONITO_GPIO_GPINR_SHIFT 25 350#define BONITO_GPIO_GPINR_SHIFT 25
351#define BONITO_GPIO_IOW(N) (1<<(BONITO_GPIO_GPIOW_SHIFT+(N))) 351#define BONITO_GPIO_IOW(N) (1<<(BONITO_GPIO_GPIOW_SHIFT+(N)))
352#define BONITO_GPIO_IOR(N) (1<<(BONITO_GPIO_GPIOR_SHIFT+(N))) 352#define BONITO_GPIO_IOR(N) (1<<(BONITO_GPIO_GPIOR_SHIFT+(N)))
353#define BONITO_GPIO_INR(N) (1<<(BONITO_GPIO_GPINR_SHIFT+(N))) 353#define BONITO_GPIO_INR(N) (1<<(BONITO_GPIO_GPINR_SHIFT+(N)))
354 354
355/* ICU */ 355/* ICU */
356#define BONITO_ICU_MBOXES 0x0000000f 356#define BONITO_ICU_MBOXES 0x0000000f
357#define BONITO_ICU_MBOXES_SHIFT 0 357#define BONITO_ICU_MBOXES_SHIFT 0
358#define BONITO_ICU_DMARDY 0x00000010 358#define BONITO_ICU_DMARDY 0x00000010
359#define BONITO_ICU_DMAEMPTY 0x00000020 359#define BONITO_ICU_DMAEMPTY 0x00000020
360#define BONITO_ICU_COPYRDY 0x00000040 360#define BONITO_ICU_COPYRDY 0x00000040
@@ -384,13 +384,13 @@ extern unsigned long _pcictrl_bonito_pcicfg;
384#define BONITO_PCIMAP_PCIMAP_2 0x00040000 384#define BONITO_PCIMAP_PCIMAP_2 0x00040000
385#define BONITO_PCIMAP_WIN(WIN, ADDR) ((((ADDR)>>26) & BONITO_PCIMAP_PCIMAP_LO0) << ((WIN)*6)) 385#define BONITO_PCIMAP_WIN(WIN, ADDR) ((((ADDR)>>26) & BONITO_PCIMAP_PCIMAP_LO0) << ((WIN)*6))
386 386
387#define BONITO_PCIMAP_WINSIZE (1<<26) 387#define BONITO_PCIMAP_WINSIZE (1<<26)
388#define BONITO_PCIMAP_WINOFFSET(ADDR) ((ADDR) & (BONITO_PCIMAP_WINSIZE - 1)) 388#define BONITO_PCIMAP_WINOFFSET(ADDR) ((ADDR) & (BONITO_PCIMAP_WINSIZE - 1))
389#define BONITO_PCIMAP_WINBASE(ADDR) ((ADDR) << 26) 389#define BONITO_PCIMAP_WINBASE(ADDR) ((ADDR) << 26)
390 390
391/* pcimembaseCfg */ 391/* pcimembaseCfg */
392 392
393#define BONITO_PCIMEMBASECFG_MASK 0xf0000000 393#define BONITO_PCIMEMBASECFG_MASK 0xf0000000
394#define BONITO_PCIMEMBASECFG_MEMBASE0_MASK 0x0000001f 394#define BONITO_PCIMEMBASECFG_MEMBASE0_MASK 0x0000001f
395#define BONITO_PCIMEMBASECFG_MEMBASE0_MASK_SHIFT 0 395#define BONITO_PCIMEMBASECFG_MEMBASE0_MASK_SHIFT 0
396#define BONITO_PCIMEMBASECFG_MEMBASE0_TRANS 0x000003e0 396#define BONITO_PCIMEMBASECFG_MEMBASE0_TRANS 0x000003e0
@@ -406,21 +406,21 @@ extern unsigned long _pcictrl_bonito_pcicfg;
406#define BONITO_PCIMEMBASECFG_MEMBASE1_IO 0x00800000 406#define BONITO_PCIMEMBASECFG_MEMBASE1_IO 0x00800000
407 407
408#define BONITO_PCIMEMBASECFG_ASHIFT 23 408#define BONITO_PCIMEMBASECFG_ASHIFT 23
409#define BONITO_PCIMEMBASECFG_AMASK 0x007fffff 409#define BONITO_PCIMEMBASECFG_AMASK 0x007fffff
410#define BONITO_PCIMEMBASECFGSIZE(WIN, SIZE) (((~((SIZE)-1))>>(BONITO_PCIMEMBASECFG_ASHIFT-BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT)) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK) 410#define BONITO_PCIMEMBASECFGSIZE(WIN, SIZE) (((~((SIZE)-1))>>(BONITO_PCIMEMBASECFG_ASHIFT-BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT)) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK)
411#define BONITO_PCIMEMBASECFGBASE(WIN, BASE) (((BASE)>>(BONITO_PCIMEMBASECFG_ASHIFT-BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS_SHIFT)) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS) 411#define BONITO_PCIMEMBASECFGBASE(WIN, BASE) (((BASE)>>(BONITO_PCIMEMBASECFG_ASHIFT-BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS_SHIFT)) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS)
412 412
413#define BONITO_PCIMEMBASECFG_SIZE(WIN, CFG) (((((~(CFG)) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK)) << (BONITO_PCIMEMBASECFG_ASHIFT - BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT)) | BONITO_PCIMEMBASECFG_AMASK) 413#define BONITO_PCIMEMBASECFG_SIZE(WIN, CFG) (((((~(CFG)) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK)) << (BONITO_PCIMEMBASECFG_ASHIFT - BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT)) | BONITO_PCIMEMBASECFG_AMASK)
414 414
415 415
416#define BONITO_PCIMEMBASECFG_ADDRMASK(WIN, CFG) ((((CFG) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK) >> BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT) << BONITO_PCIMEMBASECFG_ASHIFT) 416#define BONITO_PCIMEMBASECFG_ADDRMASK(WIN, CFG) ((((CFG) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK) >> BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT) << BONITO_PCIMEMBASECFG_ASHIFT)
417#define BONITO_PCIMEMBASECFG_ADDRMASK(WIN, CFG) ((((CFG) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK) >> BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT) << BONITO_PCIMEMBASECFG_ASHIFT) 417#define BONITO_PCIMEMBASECFG_ADDRMASK(WIN, CFG) ((((CFG) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK) >> BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT) << BONITO_PCIMEMBASECFG_ASHIFT)
418#define BONITO_PCIMEMBASECFG_ADDRTRANS(WIN, CFG) ((((CFG) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS) >> BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS_SHIFT) << BONITO_PCIMEMBASECFG_ASHIFT) 418#define BONITO_PCIMEMBASECFG_ADDRTRANS(WIN, CFG) ((((CFG) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS) >> BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS_SHIFT) << BONITO_PCIMEMBASECFG_ASHIFT)
419 419
420#define BONITO_PCITOPHYS(WIN, ADDR, CFG) ( \ 420#define BONITO_PCITOPHYS(WIN, ADDR, CFG) ( \
421 (((ADDR) & (~(BONITO_PCIMEMBASECFG_MASK))) & (~(BONITO_PCIMEMBASECFG_ADDRMASK(WIN, CFG)))) | \ 421 (((ADDR) & (~(BONITO_PCIMEMBASECFG_MASK))) & (~(BONITO_PCIMEMBASECFG_ADDRMASK(WIN, CFG)))) | \
422 (BONITO_PCIMEMBASECFG_ADDRTRANS(WIN, CFG)) \ 422 (BONITO_PCIMEMBASECFG_ADDRTRANS(WIN, CFG)) \
423 ) 423 )
424 424
425/* PCICmd */ 425/* PCICmd */
426 426
diff --git a/arch/mips/include/asm/mips-boards/generic.h b/arch/mips/include/asm/mips-boards/generic.h
index c01e286394da..1465b1193b12 100644
--- a/arch/mips/include/asm/mips-boards/generic.h
+++ b/arch/mips/include/asm/mips-boards/generic.h
@@ -27,39 +27,39 @@
27/* 27/*
28 * Display register base. 28 * Display register base.
29 */ 29 */
30#define ASCII_DISPLAY_WORD_BASE 0x1f000410 30#define ASCII_DISPLAY_WORD_BASE 0x1f000410
31#define ASCII_DISPLAY_POS_BASE 0x1f000418 31#define ASCII_DISPLAY_POS_BASE 0x1f000418
32 32
33 33
34/* 34/*
35 * Yamon Prom print address. 35 * Yamon Prom print address.
36 */ 36 */
37#define YAMON_PROM_PRINT_ADDR 0x1fc00504 37#define YAMON_PROM_PRINT_ADDR 0x1fc00504
38 38
39 39
40/* 40/*
41 * Reset register. 41 * Reset register.
42 */ 42 */
43#define SOFTRES_REG 0x1f000500 43#define SOFTRES_REG 0x1f000500
44#define GORESET 0x42 44#define GORESET 0x42
45 45
46/* 46/*
47 * Revision register. 47 * Revision register.
48 */ 48 */
49#define MIPS_REVISION_REG 0x1fc00010 49#define MIPS_REVISION_REG 0x1fc00010
50#define MIPS_REVISION_CORID_QED_RM5261 0 50#define MIPS_REVISION_CORID_QED_RM5261 0
51#define MIPS_REVISION_CORID_CORE_LV 1 51#define MIPS_REVISION_CORID_CORE_LV 1
52#define MIPS_REVISION_CORID_BONITO64 2 52#define MIPS_REVISION_CORID_BONITO64 2
53#define MIPS_REVISION_CORID_CORE_20K 3 53#define MIPS_REVISION_CORID_CORE_20K 3
54#define MIPS_REVISION_CORID_CORE_FPGA 4 54#define MIPS_REVISION_CORID_CORE_FPGA 4
55#define MIPS_REVISION_CORID_CORE_MSC 5 55#define MIPS_REVISION_CORID_CORE_MSC 5
56#define MIPS_REVISION_CORID_CORE_EMUL 6 56#define MIPS_REVISION_CORID_CORE_EMUL 6
57#define MIPS_REVISION_CORID_CORE_FPGA2 7 57#define MIPS_REVISION_CORID_CORE_FPGA2 7
58#define MIPS_REVISION_CORID_CORE_FPGAR2 8 58#define MIPS_REVISION_CORID_CORE_FPGAR2 8
59#define MIPS_REVISION_CORID_CORE_FPGA3 9 59#define MIPS_REVISION_CORID_CORE_FPGA3 9
60#define MIPS_REVISION_CORID_CORE_24K 10 60#define MIPS_REVISION_CORID_CORE_24K 10
61#define MIPS_REVISION_CORID_CORE_FPGA4 11 61#define MIPS_REVISION_CORID_CORE_FPGA4 11
62#define MIPS_REVISION_CORID_CORE_FPGA5 12 62#define MIPS_REVISION_CORID_CORE_FPGA5 12
63 63
64/**** Artificial corid defines ****/ 64/**** Artificial corid defines ****/
65/* 65/*
@@ -97,4 +97,4 @@ extern void mips_pcibios_init(void);
97#define mips_pcibios_init() do { } while (0) 97#define mips_pcibios_init() do { } while (0)
98#endif 98#endif
99 99
100#endif /* __ASM_MIPS_BOARDS_GENERIC_H */ 100#endif /* __ASM_MIPS_BOARDS_GENERIC_H */
diff --git a/arch/mips/include/asm/mips-boards/launch.h b/arch/mips/include/asm/mips-boards/launch.h
index d8ae7f95a522..653477e4074d 100644
--- a/arch/mips/include/asm/mips-boards/launch.h
+++ b/arch/mips/include/asm/mips-boards/launch.h
@@ -16,11 +16,11 @@ struct cpulaunch {
16#else 16#else
17 17
18#define LOG2CPULAUNCH 5 18#define LOG2CPULAUNCH 5
19#define LAUNCH_PC 0 19#define LAUNCH_PC 0
20#define LAUNCH_GP 4 20#define LAUNCH_GP 4
21#define LAUNCH_SP 8 21#define LAUNCH_SP 8
22#define LAUNCH_A0 12 22#define LAUNCH_A0 12
23#define LAUNCH_FLAGS 28 23#define LAUNCH_FLAGS 28
24 24
25#endif 25#endif
26 26
diff --git a/arch/mips/include/asm/mips-boards/malta.h b/arch/mips/include/asm/mips-boards/malta.h
index c1891578fa65..722bc889eab5 100644
--- a/arch/mips/include/asm/mips-boards/malta.h
+++ b/arch/mips/include/asm/mips-boards/malta.h
@@ -33,9 +33,9 @@
33 * Malta I/O ports base address for the Galileo GT64120 and Algorithmics 33 * Malta I/O ports base address for the Galileo GT64120 and Algorithmics
34 * Bonito system controllers. 34 * Bonito system controllers.
35 */ 35 */
36#define MALTA_GT_PORT_BASE get_gt_port_base(GT_PCI0IOLD_OFS) 36#define MALTA_GT_PORT_BASE get_gt_port_base(GT_PCI0IOLD_OFS)
37#define MALTA_BONITO_PORT_BASE ((unsigned long)ioremap (0x1fd00000, 0x10000)) 37#define MALTA_BONITO_PORT_BASE ((unsigned long)ioremap (0x1fd00000, 0x10000))
38#define MALTA_MSC_PORT_BASE get_msc_port_base(MSC01_PCI_SC2PIOBASL) 38#define MALTA_MSC_PORT_BASE get_msc_port_base(MSC01_PCI_SC2PIOBASL)
39 39
40static inline unsigned long get_gt_port_base(unsigned long reg) 40static inline unsigned long get_gt_port_base(unsigned long reg)
41{ 41{
@@ -77,8 +77,8 @@ static inline unsigned long get_msc_port_base(unsigned long reg)
77/* 77/*
78 * Malta RTC-device indirect register access. 78 * Malta RTC-device indirect register access.
79 */ 79 */
80#define MALTA_RTC_ADR_REG 0x70 80#define MALTA_RTC_ADR_REG 0x70
81#define MALTA_RTC_DAT_REG 0x71 81#define MALTA_RTC_DAT_REG 0x71
82 82
83/* 83/*
84 * Malta SMSC FDC37M817 Super I/O Controller register. 84 * Malta SMSC FDC37M817 Super I/O Controller register.
diff --git a/arch/mips/include/asm/mips-boards/maltaint.h b/arch/mips/include/asm/mips-boards/maltaint.h
index 669244815753..e330732ddf98 100644
--- a/arch/mips/include/asm/mips-boards/maltaint.h
+++ b/arch/mips/include/asm/mips-boards/maltaint.h
@@ -4,8 +4,8 @@
4 * for more details. 4 * for more details.
5 * 5 *
6 * Copyright (C) 2000,2012 MIPS Technologies, Inc. All rights reserved. 6 * Copyright (C) 2000,2012 MIPS Technologies, Inc. All rights reserved.
7 * Carsten Langgaard <carstenl@mips.com> 7 * Carsten Langgaard <carstenl@mips.com>
8 * Steven J. Hill <sjhill@mips.com> 8 * Steven J. Hill <sjhill@mips.com>
9 */ 9 */
10#ifndef _MIPS_MALTAINT_H 10#ifndef _MIPS_MALTAINT_H
11#define _MIPS_MALTAINT_H 11#define _MIPS_MALTAINT_H
@@ -24,9 +24,9 @@
24#define MIPSCPU_INT_I8259A MIPSCPU_INT_MB0 24#define MIPSCPU_INT_I8259A MIPSCPU_INT_MB0
25#define MIPSCPU_INT_MB1 3 25#define MIPSCPU_INT_MB1 3
26#define MIPSCPU_INT_SMI MIPSCPU_INT_MB1 26#define MIPSCPU_INT_SMI MIPSCPU_INT_MB1
27#define MIPSCPU_INT_IPI0 MIPSCPU_INT_MB1 /* GIC IPI */ 27#define MIPSCPU_INT_IPI0 MIPSCPU_INT_MB1 /* GIC IPI */
28#define MIPSCPU_INT_MB2 4 28#define MIPSCPU_INT_MB2 4
29#define MIPSCPU_INT_IPI1 MIPSCPU_INT_MB2 /* GIC IPI */ 29#define MIPSCPU_INT_IPI1 MIPSCPU_INT_MB2 /* GIC IPI */
30#define MIPSCPU_INT_MB3 5 30#define MIPSCPU_INT_MB3 5
31#define MIPSCPU_INT_COREHI MIPSCPU_INT_MB3 31#define MIPSCPU_INT_COREHI MIPSCPU_INT_MB3
32#define MIPSCPU_INT_MB4 6 32#define MIPSCPU_INT_MB4 6
diff --git a/arch/mips/include/asm/mips-boards/piix4.h b/arch/mips/include/asm/mips-boards/piix4.h
index 2971d60f2e95..a02596cf1abd 100644
--- a/arch/mips/include/asm/mips-boards/piix4.h
+++ b/arch/mips/include/asm/mips-boards/piix4.h
@@ -53,7 +53,7 @@
53#define PIIX4_OCW2_SP (0x6 << 5) 53#define PIIX4_OCW2_SP (0x6 << 5)
54#define PIIX4_OCW2_NOP (0x2 << 5) 54#define PIIX4_OCW2_NOP (0x2 << 5)
55 55
56#define PIIX4_OCW2_SEL (0x0 << 3) 56#define PIIX4_OCW2_SEL (0x0 << 3)
57 57
58#define PIIX4_OCW2_ILS_0 0 58#define PIIX4_OCW2_ILS_0 0
59#define PIIX4_OCW2_ILS_1 1 59#define PIIX4_OCW2_ILS_1 1
@@ -72,9 +72,9 @@
72#define PIIX4_OCW2_ILS_14 6 72#define PIIX4_OCW2_ILS_14 6
73#define PIIX4_OCW2_ILS_15 7 73#define PIIX4_OCW2_ILS_15 7
74 74
75#define PIIX4_OCW3_SEL (0x1 << 3) 75#define PIIX4_OCW3_SEL (0x1 << 3)
76 76
77#define PIIX4_OCW3_IRR 0x2 77#define PIIX4_OCW3_IRR 0x2
78#define PIIX4_OCW3_ISR 0x3 78#define PIIX4_OCW3_ISR 0x3
79 79
80#endif /* __ASM_MIPS_BOARDS_PIIX4_H */ 80#endif /* __ASM_MIPS_BOARDS_PIIX4_H */
diff --git a/arch/mips/include/asm/mips-boards/prom.h b/arch/mips/include/asm/mips-boards/prom.h
index a9db576a9768..e7aed3e4ff58 100644
--- a/arch/mips/include/asm/mips-boards/prom.h
+++ b/arch/mips/include/asm/mips-boards/prom.h
@@ -39,9 +39,9 @@ extern int get_ethernet_addr(char *ethernet_addr);
39/* Memory descriptor management. */ 39/* Memory descriptor management. */
40#define PROM_MAX_PMEMBLOCKS 32 40#define PROM_MAX_PMEMBLOCKS 32
41struct prom_pmemblock { 41struct prom_pmemblock {
42 unsigned long base; /* Within KSEG0. */ 42 unsigned long base; /* Within KSEG0. */
43 unsigned int size; /* In bytes. */ 43 unsigned int size; /* In bytes. */
44 unsigned int type; /* free or prom memory */ 44 unsigned int type; /* free or prom memory */
45}; 45};
46 46
47#endif /* !(_MIPS_PROM_H) */ 47#endif /* !(_MIPS_PROM_H) */
diff --git a/arch/mips/include/asm/mips-boards/sead3int.h b/arch/mips/include/asm/mips-boards/sead3int.h
index d634d9a807f6..6b17aaf7d901 100644
--- a/arch/mips/include/asm/mips-boards/sead3int.h
+++ b/arch/mips/include/asm/mips-boards/sead3int.h
@@ -4,8 +4,8 @@
4 * for more details. 4 * for more details.
5 * 5 *
6 * Copyright (C) 2000,2012 MIPS Technologies, Inc. All rights reserved. 6 * Copyright (C) 2000,2012 MIPS Technologies, Inc. All rights reserved.
7 * Douglas Leung <douglas@mips.com> 7 * Douglas Leung <douglas@mips.com>
8 * Steven J. Hill <sjhill@mips.com> 8 * Steven J. Hill <sjhill@mips.com>
9 */ 9 */
10#ifndef _MIPS_SEAD3INT_H 10#ifndef _MIPS_SEAD3INT_H
11#define _MIPS_SEAD3INT_H 11#define _MIPS_SEAD3INT_H
diff --git a/arch/mips/include/asm/mips-boards/sim.h b/arch/mips/include/asm/mips-boards/sim.h
index acb7c2331d98..b112fdc9f77d 100644
--- a/arch/mips/include/asm/mips-boards/sim.h
+++ b/arch/mips/include/asm/mips-boards/sim.h
@@ -19,18 +19,18 @@
19#ifndef _ASM_MIPS_BOARDS_SIM_H 19#ifndef _ASM_MIPS_BOARDS_SIM_H
20#define _ASM_MIPS_BOARDS_SIM_H 20#define _ASM_MIPS_BOARDS_SIM_H
21 21
22#define STATS_ON 1 22#define STATS_ON 1
23#define STATS_OFF 2 23#define STATS_OFF 2
24#define STATS_CLEAR 3 24#define STATS_CLEAR 3
25#define STATS_DUMP 4 25#define STATS_DUMP 4
26#define TRACE_ON 5 26#define TRACE_ON 5
27#define TRACE_OFF 6 27#define TRACE_OFF 6
28 28
29 29
30#define simcfg(code) \ 30#define simcfg(code) \
31({ \ 31({ \
32 __asm__ __volatile__( \ 32 __asm__ __volatile__( \
33 "sltiu $0,$0, %0" \ 33 "sltiu $0,$0, %0" \
34 ::"i"(code) \ 34 ::"i"(code) \
35 ); \ 35 ); \
36}) 36})
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-15 01:54:40 -0500