diff options
Diffstat (limited to 'arch/mips/include/asm/mips-boards/sead3int.h')
-rw-r--r-- | arch/mips/include/asm/mips-boards/sead3int.h | 15 |
1 files changed, 14 insertions, 1 deletions
diff --git a/arch/mips/include/asm/mips-boards/sead3int.h b/arch/mips/include/asm/mips-boards/sead3int.h index 6b17aaf7d901..8932c7de0419 100644 --- a/arch/mips/include/asm/mips-boards/sead3int.h +++ b/arch/mips/include/asm/mips-boards/sead3int.h | |||
@@ -10,10 +10,23 @@ | |||
10 | #ifndef _MIPS_SEAD3INT_H | 10 | #ifndef _MIPS_SEAD3INT_H |
11 | #define _MIPS_SEAD3INT_H | 11 | #define _MIPS_SEAD3INT_H |
12 | 12 | ||
13 | #include <linux/irqchip/mips-gic.h> | ||
14 | |||
13 | /* SEAD-3 GIC address space definitions. */ | 15 | /* SEAD-3 GIC address space definitions. */ |
14 | #define GIC_BASE_ADDR 0x1b1c0000 | 16 | #define GIC_BASE_ADDR 0x1b1c0000 |
15 | #define GIC_ADDRSPACE_SZ (128 * 1024) | 17 | #define GIC_ADDRSPACE_SZ (128 * 1024) |
16 | 18 | ||
17 | #define MIPS_GIC_IRQ_BASE (MIPS_CPU_IRQ_BASE + 0) | 19 | /* CPU interrupt offsets */ |
20 | #define CPU_INT_GIC 2 | ||
21 | #define CPU_INT_EHCI 2 | ||
22 | #define CPU_INT_UART0 4 | ||
23 | #define CPU_INT_UART1 4 | ||
24 | #define CPU_INT_NET 6 | ||
25 | |||
26 | /* GIC interrupt offsets */ | ||
27 | #define GIC_INT_NET GIC_SHARED_TO_HWIRQ(0) | ||
28 | #define GIC_INT_UART1 GIC_SHARED_TO_HWIRQ(2) | ||
29 | #define GIC_INT_UART0 GIC_SHARED_TO_HWIRQ(3) | ||
30 | #define GIC_INT_EHCI GIC_SHARED_TO_HWIRQ(5) | ||
18 | 31 | ||
19 | #endif /* !(_MIPS_SEAD3INT_H) */ | 32 | #endif /* !(_MIPS_SEAD3INT_H) */ |